1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2021 NXP
12 #include <ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
21 #include "rte_dpaa2_mempool.h"
23 #include "dpaa2_pmd_logs.h"
24 #include <fslmc_vfio.h>
25 #include <dpaa2_hw_pvt.h>
26 #include <dpaa2_hw_mempool.h>
27 #include <dpaa2_hw_dpio.h>
28 #include <mc/fsl_dpmng.h>
29 #include "dpaa2_ethdev.h"
30 #include "dpaa2_sparser.h"
31 #include <fsl_qbman_debug.h>
33 #define DRIVER_LOOPBACK_MODE "drv_loopback"
34 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
35 #define DRIVER_TX_CONF "drv_tx_conf"
36 #define DRIVER_ERROR_QUEUE "drv_err_queue"
37 #define CHECK_INTERVAL 100 /* 100ms */
38 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
40 /* Supported Rx offloads */
41 static uint64_t dev_rx_offloads_sup =
42 RTE_ETH_RX_OFFLOAD_CHECKSUM |
43 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
44 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
45 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
46 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
47 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
48 RTE_ETH_RX_OFFLOAD_TIMESTAMP;
50 /* Rx offloads which cannot be disabled */
51 static uint64_t dev_rx_offloads_nodis =
52 RTE_ETH_RX_OFFLOAD_RSS_HASH |
53 RTE_ETH_RX_OFFLOAD_SCATTER;
55 /* Supported Tx offloads */
56 static uint64_t dev_tx_offloads_sup =
57 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
58 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
59 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
60 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
61 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
62 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
63 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
64 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
66 /* Tx offloads which cannot be disabled */
67 static uint64_t dev_tx_offloads_nodis =
68 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
70 /* enable timestamp in mbuf */
71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
72 uint64_t dpaa2_timestamp_rx_dynflag;
73 int dpaa2_timestamp_dynfield_offset = -1;
75 /* Enable error queue */
76 bool dpaa2_enable_err_queue;
78 #define MAX_NB_RX_DESC 11264
81 struct rte_dpaa2_xstats_name_off {
82 char name[RTE_ETH_XSTATS_NAME_SIZE];
83 uint8_t page_id; /* dpni statistics page id */
84 uint8_t stats_id; /* stats id in the given page */
87 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
88 {"ingress_multicast_frames", 0, 2},
89 {"ingress_multicast_bytes", 0, 3},
90 {"ingress_broadcast_frames", 0, 4},
91 {"ingress_broadcast_bytes", 0, 5},
92 {"egress_multicast_frames", 1, 2},
93 {"egress_multicast_bytes", 1, 3},
94 {"egress_broadcast_frames", 1, 4},
95 {"egress_broadcast_bytes", 1, 5},
96 {"ingress_filtered_frames", 2, 0},
97 {"ingress_discarded_frames", 2, 1},
98 {"ingress_nobuffer_discards", 2, 2},
99 {"egress_discarded_frames", 2, 3},
100 {"egress_confirmed_frames", 2, 4},
101 {"cgr_reject_frames", 4, 0},
102 {"cgr_reject_bytes", 4, 1},
105 static struct rte_dpaa2_driver rte_dpaa2_pmd;
106 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
107 int wait_to_complete);
108 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
109 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
110 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
113 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
116 struct dpaa2_dev_priv *priv = dev->data->dev_private;
117 struct fsl_mc_io *dpni = dev->process_private;
119 PMD_INIT_FUNC_TRACE();
122 DPAA2_PMD_ERR("dpni is NULL");
127 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
130 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
131 priv->token, vlan_id);
134 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
135 ret, vlan_id, priv->hw_id);
141 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
143 struct dpaa2_dev_priv *priv = dev->data->dev_private;
144 struct fsl_mc_io *dpni = dev->process_private;
147 PMD_INIT_FUNC_TRACE();
149 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
150 /* VLAN Filter not available */
151 if (!priv->max_vlan_filters) {
152 DPAA2_PMD_INFO("VLAN filter not available");
156 if (dev->data->dev_conf.rxmode.offloads &
157 RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
158 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
161 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
164 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
171 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
172 enum rte_vlan_type vlan_type __rte_unused,
175 struct dpaa2_dev_priv *priv = dev->data->dev_private;
176 struct fsl_mc_io *dpni = dev->process_private;
179 PMD_INIT_FUNC_TRACE();
181 /* nothing to be done for standard vlan tpids */
182 if (tpid == 0x8100 || tpid == 0x88A8)
185 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
188 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
189 /* if already configured tpids, remove them first */
191 struct dpni_custom_tpid_cfg tpid_list = {0};
193 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
194 priv->token, &tpid_list);
197 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
198 priv->token, tpid_list.tpid1);
201 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
209 dpaa2_fw_version_get(struct rte_eth_dev *dev,
214 struct fsl_mc_io *dpni = dev->process_private;
215 struct mc_soc_version mc_plat_info = {0};
216 struct mc_version mc_ver_info = {0};
218 PMD_INIT_FUNC_TRACE();
220 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
221 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
223 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
224 DPAA2_PMD_WARN("\tmc_get_version failed");
226 ret = snprintf(fw_version, fw_size,
231 mc_ver_info.revision);
235 ret += 1; /* add the size of '\0' */
236 if (fw_size < (size_t)ret)
243 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
245 struct dpaa2_dev_priv *priv = dev->data->dev_private;
247 PMD_INIT_FUNC_TRACE();
249 dev_info->max_mac_addrs = priv->max_mac_filters;
250 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
251 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
252 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
253 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
254 dev_info->rx_offload_capa = dev_rx_offloads_sup |
255 dev_rx_offloads_nodis;
256 dev_info->tx_offload_capa = dev_tx_offloads_sup |
257 dev_tx_offloads_nodis;
258 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
259 RTE_ETH_LINK_SPEED_2_5G |
260 RTE_ETH_LINK_SPEED_10G;
261 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
263 dev_info->max_hash_mac_addrs = 0;
264 dev_info->max_vfs = 0;
265 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
266 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
268 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
269 /* same is rx size for best perf */
270 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
272 dev_info->default_rxportconf.nb_queues = 1;
273 dev_info->default_txportconf.nb_queues = 1;
274 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
275 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
277 if (dpaa2_svr_family == SVR_LX2160A) {
278 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G |
279 RTE_ETH_LINK_SPEED_40G |
280 RTE_ETH_LINK_SPEED_50G |
281 RTE_ETH_LINK_SPEED_100G;
288 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
289 __rte_unused uint16_t queue_id,
290 struct rte_eth_burst_mode *mode)
292 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
295 const struct burst_info {
298 } rx_offload_map[] = {
299 {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"},
300 {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
301 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
302 {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
303 {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
304 {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
305 {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
306 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"},
307 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}
310 /* Update Rx offload info */
311 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
312 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
313 snprintf(mode->info, sizeof(mode->info), "%s",
314 rx_offload_map[i].output);
323 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
324 __rte_unused uint16_t queue_id,
325 struct rte_eth_burst_mode *mode)
327 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
330 const struct burst_info {
333 } tx_offload_map[] = {
334 {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
335 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
336 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
337 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
338 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
339 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
340 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
341 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
342 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
345 /* Update Tx offload info */
346 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
347 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
348 snprintf(mode->info, sizeof(mode->info), "%s",
349 tx_offload_map[i].output);
358 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
360 struct dpaa2_dev_priv *priv = dev->data->dev_private;
363 uint8_t num_rxqueue_per_tc;
364 struct dpaa2_queue *mc_q, *mcq;
367 struct dpaa2_queue *dpaa2_q;
369 PMD_INIT_FUNC_TRACE();
371 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
372 if (priv->flags & DPAA2_TX_CONF_ENABLE)
373 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
375 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
376 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
377 RTE_CACHE_LINE_SIZE);
379 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
383 for (i = 0; i < priv->nb_rx_queues; i++) {
384 mc_q->eth_data = dev->data;
385 priv->rx_vq[i] = mc_q++;
386 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
387 dpaa2_q->q_storage = rte_malloc("dq_storage",
388 sizeof(struct queue_storage_info_t),
389 RTE_CACHE_LINE_SIZE);
390 if (!dpaa2_q->q_storage)
393 memset(dpaa2_q->q_storage, 0,
394 sizeof(struct queue_storage_info_t));
395 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
399 if (dpaa2_enable_err_queue) {
400 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
401 sizeof(struct dpaa2_queue), 0);
403 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
404 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
405 sizeof(struct queue_storage_info_t) *
407 RTE_CACHE_LINE_SIZE);
408 if (!dpaa2_q->q_storage)
411 memset(dpaa2_q->q_storage, 0,
412 sizeof(struct queue_storage_info_t));
413 for (i = 0; i < RTE_MAX_LCORE; i++)
414 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
418 for (i = 0; i < priv->nb_tx_queues; i++) {
419 mc_q->eth_data = dev->data;
420 mc_q->flow_id = 0xffff;
421 priv->tx_vq[i] = mc_q++;
422 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
423 dpaa2_q->cscn = rte_malloc(NULL,
424 sizeof(struct qbman_result), 16);
429 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
430 /*Setup tx confirmation queues*/
431 for (i = 0; i < priv->nb_tx_queues; i++) {
432 mc_q->eth_data = dev->data;
435 priv->tx_conf_vq[i] = mc_q++;
436 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
438 rte_malloc("dq_storage",
439 sizeof(struct queue_storage_info_t),
440 RTE_CACHE_LINE_SIZE);
441 if (!dpaa2_q->q_storage)
444 memset(dpaa2_q->q_storage, 0,
445 sizeof(struct queue_storage_info_t));
446 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
452 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
453 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
454 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
455 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
463 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
464 rte_free(dpaa2_q->q_storage);
465 priv->tx_conf_vq[i--] = NULL;
467 i = priv->nb_tx_queues;
471 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
472 rte_free(dpaa2_q->cscn);
473 priv->tx_vq[i--] = NULL;
475 i = priv->nb_rx_queues;
478 mc_q = priv->rx_vq[0];
480 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
481 dpaa2_free_dq_storage(dpaa2_q->q_storage);
482 rte_free(dpaa2_q->q_storage);
483 priv->rx_vq[i--] = NULL;
486 if (dpaa2_enable_err_queue) {
487 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
488 if (dpaa2_q->q_storage)
489 dpaa2_free_dq_storage(dpaa2_q->q_storage);
490 rte_free(dpaa2_q->q_storage);
498 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
500 struct dpaa2_dev_priv *priv = dev->data->dev_private;
501 struct dpaa2_queue *dpaa2_q;
504 PMD_INIT_FUNC_TRACE();
506 /* Queue allocation base */
507 if (priv->rx_vq[0]) {
508 /* cleaning up queue storage */
509 for (i = 0; i < priv->nb_rx_queues; i++) {
510 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
511 if (dpaa2_q->q_storage)
512 rte_free(dpaa2_q->q_storage);
514 /* cleanup tx queue cscn */
515 for (i = 0; i < priv->nb_tx_queues; i++) {
516 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
517 rte_free(dpaa2_q->cscn);
519 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
520 /* cleanup tx conf queue storage */
521 for (i = 0; i < priv->nb_tx_queues; i++) {
522 dpaa2_q = (struct dpaa2_queue *)
524 rte_free(dpaa2_q->q_storage);
527 /*free memory for all queues (RX+TX) */
528 rte_free(priv->rx_vq[0]);
529 priv->rx_vq[0] = NULL;
534 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
536 struct dpaa2_dev_priv *priv = dev->data->dev_private;
537 struct fsl_mc_io *dpni = dev->process_private;
538 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
539 uint64_t rx_offloads = eth_conf->rxmode.offloads;
540 uint64_t tx_offloads = eth_conf->txmode.offloads;
541 int rx_l3_csum_offload = false;
542 int rx_l4_csum_offload = false;
543 int tx_l3_csum_offload = false;
544 int tx_l4_csum_offload = false;
546 uint32_t max_rx_pktlen;
548 PMD_INIT_FUNC_TRACE();
550 /* Rx offloads which are enabled by default */
551 if (dev_rx_offloads_nodis & ~rx_offloads) {
553 "Some of rx offloads enabled by default - requested 0x%" PRIx64
554 " fixed are 0x%" PRIx64,
555 rx_offloads, dev_rx_offloads_nodis);
558 /* Tx offloads which are enabled by default */
559 if (dev_tx_offloads_nodis & ~tx_offloads) {
561 "Some of tx offloads enabled by default - requested 0x%" PRIx64
562 " fixed are 0x%" PRIx64,
563 tx_offloads, dev_tx_offloads_nodis);
566 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
567 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
568 if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) {
569 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
570 priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN);
572 DPAA2_PMD_ERR("Unable to set mtu. check config");
575 DPAA2_PMD_INFO("MTU configured for the device: %d",
581 if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
582 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
583 ret = dpaa2_setup_flow_dist(dev,
584 eth_conf->rx_adv_conf.rss_conf.rss_hf,
588 "Unable to set flow distribution on tc%d."
589 "Check queue config", tc_index);
595 if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM)
596 rx_l3_csum_offload = true;
598 if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) ||
599 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) ||
600 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM))
601 rx_l4_csum_offload = true;
603 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
604 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
606 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
610 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
611 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
613 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
617 #if !defined(RTE_LIBRTE_IEEE1588)
618 if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
621 ret = rte_mbuf_dyn_rx_timestamp_register(
622 &dpaa2_timestamp_dynfield_offset,
623 &dpaa2_timestamp_rx_dynflag);
625 DPAA2_PMD_ERR("Error to register timestamp field/flag");
628 dpaa2_enable_ts[dev->data->port_id] = true;
631 if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
632 tx_l3_csum_offload = true;
634 if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) ||
635 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) ||
636 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM))
637 tx_l4_csum_offload = true;
639 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
640 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
642 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
646 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
647 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
649 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
653 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
654 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
655 * to 0 for LS2 in the hardware thus disabling data/annotation
656 * stashing. For LX2 this is fixed in hardware and thus hash result and
657 * parse results can be received in FD using this option.
659 if (dpaa2_svr_family == SVR_LX2160A) {
660 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
661 DPNI_FLCTYPE_HASH, true);
663 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
668 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
669 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK);
676 /* Function to setup RX flow information. It contains traffic class ID,
677 * flow ID, destination configuration etc.
680 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
681 uint16_t rx_queue_id,
683 unsigned int socket_id __rte_unused,
684 const struct rte_eth_rxconf *rx_conf,
685 struct rte_mempool *mb_pool)
687 struct dpaa2_dev_priv *priv = dev->data->dev_private;
688 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
689 struct dpaa2_queue *dpaa2_q;
690 struct dpni_queue cfg;
696 PMD_INIT_FUNC_TRACE();
698 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
699 dev, rx_queue_id, mb_pool, rx_conf);
701 total_nb_rx_desc += nb_rx_desc;
702 if (total_nb_rx_desc > MAX_NB_RX_DESC) {
703 DPAA2_PMD_WARN("\nTotal nb_rx_desc exceeds %d limit. Please use Normal buffers",
705 DPAA2_PMD_WARN("To use Normal buffers, run 'export DPNI_NORMAL_BUF=1' before running dynamic_dpl.sh script");
708 /* Rx deferred start is not supported */
709 if (rx_conf->rx_deferred_start) {
710 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
715 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
716 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
717 ret = rte_dpaa2_bpid_info_init(mb_pool);
721 bpid = mempool_to_bpid(mb_pool);
722 ret = dpaa2_attach_bp_list(priv, dpni,
723 rte_dpaa2_bpid_info[bpid].bp_list);
727 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
728 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
729 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
730 dpaa2_q->nb_desc = UINT16_MAX;
731 dpaa2_q->offloads = rx_conf->offloads;
733 /*Get the flow id from given VQ id*/
734 flow_id = dpaa2_q->flow_id;
735 memset(&cfg, 0, sizeof(struct dpni_queue));
737 options = options | DPNI_QUEUE_OPT_USER_CTX;
738 cfg.user_context = (size_t)(dpaa2_q);
740 /* check if a private cgr available. */
741 for (i = 0; i < priv->max_cgs; i++) {
742 if (!priv->cgid_in_use[i]) {
743 priv->cgid_in_use[i] = 1;
748 if (i < priv->max_cgs) {
749 options |= DPNI_QUEUE_OPT_SET_CGID;
751 dpaa2_q->cgid = cfg.cgid;
753 dpaa2_q->cgid = 0xff;
756 /*if ls2088 or rev2 device, enable the stashing */
758 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
759 options |= DPNI_QUEUE_OPT_FLC;
760 cfg.flc.stash_control = true;
761 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
762 /* 00 00 00 - last 6 bit represent annotation, context stashing,
763 * data stashing setting 01 01 00 (0x14)
764 * (in following order ->DS AS CS)
765 * to enable 1 line data, 1 line annotation.
766 * For LX2, this setting should be 01 00 00 (0x10)
768 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
769 cfg.flc.value |= 0x10;
771 cfg.flc.value |= 0x14;
773 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
774 dpaa2_q->tc_index, flow_id, options, &cfg);
776 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
780 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
781 struct dpni_taildrop taildrop;
784 dpaa2_q->nb_desc = nb_rx_desc;
785 /* Private CGR will use tail drop length as nb_rx_desc.
786 * for rest cases we can use standard byte based tail drop.
787 * There is no HW restriction, but number of CGRs are limited,
788 * hence this restriction is placed.
790 if (dpaa2_q->cgid != 0xff) {
791 /*enabling per rx queue congestion control */
792 taildrop.threshold = nb_rx_desc;
793 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
795 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
797 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
798 DPNI_CP_CONGESTION_GROUP,
801 dpaa2_q->cgid, &taildrop);
803 /*enabling per rx queue congestion control */
804 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
805 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
806 taildrop.oal = CONG_RX_OAL;
807 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
809 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
810 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
811 dpaa2_q->tc_index, flow_id,
815 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
819 } else { /* Disable tail Drop */
820 struct dpni_taildrop taildrop = {0};
821 DPAA2_PMD_INFO("Tail drop is disabled on queue");
824 if (dpaa2_q->cgid != 0xff) {
825 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
826 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
828 dpaa2_q->cgid, &taildrop);
830 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
831 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
832 dpaa2_q->tc_index, flow_id, &taildrop);
835 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
841 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
846 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
847 uint16_t tx_queue_id,
849 unsigned int socket_id __rte_unused,
850 const struct rte_eth_txconf *tx_conf)
852 struct dpaa2_dev_priv *priv = dev->data->dev_private;
853 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
854 priv->tx_vq[tx_queue_id];
855 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
856 priv->tx_conf_vq[tx_queue_id];
857 struct fsl_mc_io *dpni = dev->process_private;
858 struct dpni_queue tx_conf_cfg;
859 struct dpni_queue tx_flow_cfg;
860 uint8_t options = 0, flow_id;
862 struct dpni_queue_id qid;
866 PMD_INIT_FUNC_TRACE();
868 /* Tx deferred start is not supported */
869 if (tx_conf->tx_deferred_start) {
870 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
875 dpaa2_q->nb_desc = UINT16_MAX;
876 dpaa2_q->offloads = tx_conf->offloads;
878 /* Return if queue already configured */
879 if (dpaa2_q->flow_id != 0xffff) {
880 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
884 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
885 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
887 if (tx_queue_id == 0) {
888 /*Set tx-conf and error configuration*/
889 if (priv->flags & DPAA2_TX_CONF_ENABLE)
890 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
894 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
898 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
904 tc_id = tx_queue_id % priv->num_tx_tc;
905 channel_id = (uint8_t)(tx_queue_id / priv->num_tx_tc) % priv->num_channels;
908 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
909 ((channel_id << 8) | tc_id), flow_id, options, &tx_flow_cfg);
911 DPAA2_PMD_ERR("Error in setting the tx flow: "
912 "tc_id=%d, flow=%d err=%d",
913 tc_id, flow_id, ret);
917 dpaa2_q->flow_id = flow_id;
919 dpaa2_q->tc_index = tc_id;
921 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
922 DPNI_QUEUE_TX, ((channel_id << 8) | dpaa2_q->tc_index),
923 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
925 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
928 dpaa2_q->fqid = qid.fqid;
930 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
931 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
933 dpaa2_q->nb_desc = nb_tx_desc;
935 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
936 cong_notif_cfg.threshold_entry = nb_tx_desc;
937 /* Notify that the queue is not congested when the data in
938 * the queue is below this threshold.(90% of value)
940 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
941 cong_notif_cfg.message_ctx = 0;
942 cong_notif_cfg.message_iova =
943 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
944 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
945 cong_notif_cfg.notification_mode =
946 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
947 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
948 DPNI_CONG_OPT_COHERENT_WRITE;
949 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
951 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
954 ((channel_id << 8) | tc_id),
958 "Error in setting tx congestion notification: "
963 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
964 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
966 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
967 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
968 options = options | DPNI_QUEUE_OPT_USER_CTX;
969 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
970 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
971 DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index),
972 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
974 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
975 "tc_index=%d, flow=%d err=%d",
976 dpaa2_tx_conf_q->tc_index,
977 dpaa2_tx_conf_q->flow_id, ret);
981 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
982 DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index),
983 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
985 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
988 dpaa2_tx_conf_q->fqid = qid.fqid;
994 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
996 struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id];
997 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
998 struct fsl_mc_io *dpni =
999 (struct fsl_mc_io *)priv->eth_dev->process_private;
1000 uint8_t options = 0;
1002 struct dpni_queue cfg;
1004 memset(&cfg, 0, sizeof(struct dpni_queue));
1005 PMD_INIT_FUNC_TRACE();
1007 total_nb_rx_desc -= dpaa2_q->nb_desc;
1009 if (dpaa2_q->cgid != 0xff) {
1010 options = DPNI_QUEUE_OPT_CLEAR_CGID;
1011 cfg.cgid = dpaa2_q->cgid;
1013 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
1015 dpaa2_q->tc_index, dpaa2_q->flow_id,
1018 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1019 dpaa2_q->fqid, ret);
1020 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1021 dpaa2_q->cgid = 0xff;
1026 dpaa2_dev_rx_queue_count(void *rx_queue)
1029 struct dpaa2_queue *dpaa2_q;
1030 struct qbman_swp *swp;
1031 struct qbman_fq_query_np_rslt state;
1032 uint32_t frame_cnt = 0;
1034 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1035 ret = dpaa2_affine_qbman_swp();
1038 "Failed to allocate IO portal, tid: %d\n",
1043 swp = DPAA2_PER_LCORE_PORTAL;
1047 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1048 frame_cnt = qbman_fq_state_frame_count(&state);
1049 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u",
1050 rx_queue, frame_cnt);
1055 static const uint32_t *
1056 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1058 static const uint32_t ptypes[] = {
1059 /*todo -= add more types */
1062 RTE_PTYPE_L3_IPV4_EXT,
1064 RTE_PTYPE_L3_IPV6_EXT,
1072 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1073 dev->rx_pkt_burst == dpaa2_dev_rx ||
1074 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1080 * Dpaa2 link Interrupt handler
1083 * The address of parameter (struct rte_eth_dev *) registered before.
1089 dpaa2_interrupt_handler(void *param)
1091 struct rte_eth_dev *dev = param;
1092 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1093 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1095 int irq_index = DPNI_IRQ_INDEX;
1096 unsigned int status = 0, clear = 0;
1098 PMD_INIT_FUNC_TRACE();
1101 DPAA2_PMD_ERR("dpni is NULL");
1105 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1106 irq_index, &status);
1107 if (unlikely(ret)) {
1108 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1113 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1114 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1115 dpaa2_dev_link_update(dev, 0);
1116 /* calling all the apps registered for link status event */
1117 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1120 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1123 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1127 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1130 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1131 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1132 int irq_index = DPNI_IRQ_INDEX;
1133 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1135 PMD_INIT_FUNC_TRACE();
1137 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1140 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1145 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1148 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1155 dpaa2_dev_start(struct rte_eth_dev *dev)
1157 struct rte_device *rdev = dev->device;
1158 struct rte_dpaa2_device *dpaa2_dev;
1159 struct rte_eth_dev_data *data = dev->data;
1160 struct dpaa2_dev_priv *priv = data->dev_private;
1161 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1162 struct dpni_queue cfg;
1163 struct dpni_error_cfg err_cfg;
1164 struct dpni_queue_id qid;
1165 struct dpaa2_queue *dpaa2_q;
1167 struct rte_intr_handle *intr_handle;
1169 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1170 intr_handle = dpaa2_dev->intr_handle;
1172 PMD_INIT_FUNC_TRACE();
1173 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1175 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1180 /* Power up the phy. Needed to make the link go UP */
1181 dpaa2_dev_set_link_up(dev);
1183 for (i = 0; i < data->nb_rx_queues; i++) {
1184 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1185 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1186 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1187 dpaa2_q->flow_id, &cfg, &qid);
1189 DPAA2_PMD_ERR("Error in getting flow information: "
1193 dpaa2_q->fqid = qid.fqid;
1196 if (dpaa2_enable_err_queue) {
1197 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1198 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1200 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1204 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1205 dpaa2_q->fqid = qid.fqid;
1206 dpaa2_q->eth_data = dev->data;
1208 err_cfg.errors = DPNI_ERROR_DISC;
1209 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1211 /* checksum errors, send them to normal path
1212 * and set it in annotation
1214 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1216 /* if packet with parse error are not to be dropped */
1217 err_cfg.errors |= DPNI_ERROR_PHE;
1219 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1221 err_cfg.set_frame_annotation = true;
1223 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1224 priv->token, &err_cfg);
1226 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1231 /* if the interrupts were configured on this devices*/
1232 if (intr_handle && rte_intr_fd_get(intr_handle) &&
1233 dev->data->dev_conf.intr_conf.lsc != 0) {
1234 /* Registering LSC interrupt handler */
1235 rte_intr_callback_register(intr_handle,
1236 dpaa2_interrupt_handler,
1239 /* enable vfio intr/eventfd mapping
1240 * Interrupt index 0 is required, so we can not use
1243 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1245 /* enable dpni_irqs */
1246 dpaa2_eth_setup_irqs(dev, 1);
1249 /* Change the tx burst function if ordered queues are used */
1250 if (priv->en_ordered)
1251 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1257 * This routine disables all traffic on the adapter by issuing a
1258 * global reset on the MAC.
1261 dpaa2_dev_stop(struct rte_eth_dev *dev)
1263 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1264 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1266 struct rte_eth_link link;
1267 struct rte_device *rdev = dev->device;
1268 struct rte_intr_handle *intr_handle;
1269 struct rte_dpaa2_device *dpaa2_dev;
1271 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1272 intr_handle = dpaa2_dev->intr_handle;
1274 PMD_INIT_FUNC_TRACE();
1276 /* reset interrupt callback */
1277 if (intr_handle && rte_intr_fd_get(intr_handle) &&
1278 dev->data->dev_conf.intr_conf.lsc != 0) {
1279 /*disable dpni irqs */
1280 dpaa2_eth_setup_irqs(dev, 0);
1282 /* disable vfio intr before callback unregister */
1283 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1285 /* Unregistering LSC interrupt handler */
1286 rte_intr_callback_unregister(intr_handle,
1287 dpaa2_interrupt_handler,
1291 dpaa2_dev_set_link_down(dev);
1293 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1295 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1300 /* clear the recorded link status */
1301 memset(&link, 0, sizeof(link));
1302 rte_eth_linkstatus_set(dev, &link);
1308 dpaa2_dev_close(struct rte_eth_dev *dev)
1310 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1311 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1313 struct rte_eth_link link;
1315 PMD_INIT_FUNC_TRACE();
1317 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1321 DPAA2_PMD_WARN("Already closed or not started");
1325 dpaa2_tm_deinit(dev);
1326 dpaa2_flow_clean(dev);
1327 /* Clean the device first */
1328 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1330 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1334 memset(&link, 0, sizeof(link));
1335 rte_eth_linkstatus_set(dev, &link);
1337 /* Free private queues memory */
1338 dpaa2_free_rx_tx_queues(dev);
1339 /* Close the device at underlying layer*/
1340 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1342 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1346 /* Free the allocated memory for ethernet private data and dpni*/
1348 dev->process_private = NULL;
1351 for (i = 0; i < MAX_TCS; i++)
1352 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1354 if (priv->extract.qos_extract_param)
1355 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1357 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1362 dpaa2_dev_promiscuous_enable(
1363 struct rte_eth_dev *dev)
1366 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1367 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1369 PMD_INIT_FUNC_TRACE();
1372 DPAA2_PMD_ERR("dpni is NULL");
1376 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1378 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1380 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1382 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1388 dpaa2_dev_promiscuous_disable(
1389 struct rte_eth_dev *dev)
1392 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1393 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1395 PMD_INIT_FUNC_TRACE();
1398 DPAA2_PMD_ERR("dpni is NULL");
1402 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1404 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1406 if (dev->data->all_multicast == 0) {
1407 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1408 priv->token, false);
1410 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1418 dpaa2_dev_allmulticast_enable(
1419 struct rte_eth_dev *dev)
1422 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1423 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1425 PMD_INIT_FUNC_TRACE();
1428 DPAA2_PMD_ERR("dpni is NULL");
1432 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1434 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1440 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1443 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1444 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1446 PMD_INIT_FUNC_TRACE();
1449 DPAA2_PMD_ERR("dpni is NULL");
1453 /* must remain on for all promiscuous */
1454 if (dev->data->promiscuous == 1)
1457 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1459 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1465 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1468 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1469 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1470 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1473 PMD_INIT_FUNC_TRACE();
1476 DPAA2_PMD_ERR("dpni is NULL");
1480 /* Set the Max Rx frame length as 'mtu' +
1481 * Maximum Ethernet header length
1483 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1484 frame_size - RTE_ETHER_CRC_LEN);
1486 DPAA2_PMD_ERR("Setting the max frame length failed");
1489 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1494 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1495 struct rte_ether_addr *addr,
1496 __rte_unused uint32_t index,
1497 __rte_unused uint32_t pool)
1500 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1501 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1503 PMD_INIT_FUNC_TRACE();
1506 DPAA2_PMD_ERR("dpni is NULL");
1510 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1511 addr->addr_bytes, 0, 0, 0);
1514 "error: Adding the MAC ADDR failed: err = %d", ret);
1519 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1523 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1524 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1525 struct rte_eth_dev_data *data = dev->data;
1526 struct rte_ether_addr *macaddr;
1528 PMD_INIT_FUNC_TRACE();
1530 macaddr = &data->mac_addrs[index];
1533 DPAA2_PMD_ERR("dpni is NULL");
1537 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1538 priv->token, macaddr->addr_bytes);
1541 "error: Removing the MAC ADDR failed: err = %d", ret);
1545 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1546 struct rte_ether_addr *addr)
1549 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1550 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1552 PMD_INIT_FUNC_TRACE();
1555 DPAA2_PMD_ERR("dpni is NULL");
1559 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1560 priv->token, addr->addr_bytes);
1564 "error: Setting the MAC ADDR failed %d", ret);
1570 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1571 struct rte_eth_stats *stats)
1573 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1574 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1576 uint8_t page0 = 0, page1 = 1, page2 = 2;
1577 union dpni_statistics value;
1579 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1581 memset(&value, 0, sizeof(union dpni_statistics));
1583 PMD_INIT_FUNC_TRACE();
1586 DPAA2_PMD_ERR("dpni is NULL");
1591 DPAA2_PMD_ERR("stats is NULL");
1595 /*Get Counters from page_0*/
1596 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1601 stats->ipackets = value.page_0.ingress_all_frames;
1602 stats->ibytes = value.page_0.ingress_all_bytes;
1604 /*Get Counters from page_1*/
1605 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1610 stats->opackets = value.page_1.egress_all_frames;
1611 stats->obytes = value.page_1.egress_all_bytes;
1613 /*Get Counters from page_2*/
1614 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1619 /* Ingress drop frame count due to configured rules */
1620 stats->ierrors = value.page_2.ingress_filtered_frames;
1621 /* Ingress drop frame count due to error */
1622 stats->ierrors += value.page_2.ingress_discarded_frames;
1624 stats->oerrors = value.page_2.egress_discarded_frames;
1625 stats->imissed = value.page_2.ingress_nobuffer_discards;
1627 /* Fill in per queue stats */
1628 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1629 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1630 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1631 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1633 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1635 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1637 /* Byte counting is not implemented */
1638 stats->q_ibytes[i] = 0;
1639 stats->q_obytes[i] = 0;
1645 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1650 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1653 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1654 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1656 union dpni_statistics value[5] = {};
1657 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1665 /* Get Counters from page_0*/
1666 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1671 /* Get Counters from page_1*/
1672 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1677 /* Get Counters from page_2*/
1678 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1683 for (i = 0; i < priv->max_cgs; i++) {
1684 if (!priv->cgid_in_use[i]) {
1685 /* Get Counters from page_4*/
1686 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1695 for (i = 0; i < num; i++) {
1697 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1698 raw.counter[dpaa2_xstats_strings[i].stats_id];
1702 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1707 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1708 struct rte_eth_xstat_name *xstats_names,
1711 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1713 if (limit < stat_cnt)
1716 if (xstats_names != NULL)
1717 for (i = 0; i < stat_cnt; i++)
1718 strlcpy(xstats_names[i].name,
1719 dpaa2_xstats_strings[i].name,
1720 sizeof(xstats_names[i].name));
1726 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1727 uint64_t *values, unsigned int n)
1729 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1730 uint64_t values_copy[stat_cnt];
1733 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1734 struct fsl_mc_io *dpni =
1735 (struct fsl_mc_io *)dev->process_private;
1737 union dpni_statistics value[5] = {};
1745 /* Get Counters from page_0*/
1746 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1751 /* Get Counters from page_1*/
1752 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1757 /* Get Counters from page_2*/
1758 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1763 /* Get Counters from page_4*/
1764 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1769 for (i = 0; i < stat_cnt; i++) {
1770 values[i] = value[dpaa2_xstats_strings[i].page_id].
1771 raw.counter[dpaa2_xstats_strings[i].stats_id];
1776 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1778 for (i = 0; i < n; i++) {
1779 if (ids[i] >= stat_cnt) {
1780 DPAA2_PMD_ERR("xstats id value isn't valid");
1783 values[i] = values_copy[ids[i]];
1789 dpaa2_xstats_get_names_by_id(
1790 struct rte_eth_dev *dev,
1791 const uint64_t *ids,
1792 struct rte_eth_xstat_name *xstats_names,
1795 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1796 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1799 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1801 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1803 for (i = 0; i < limit; i++) {
1804 if (ids[i] >= stat_cnt) {
1805 DPAA2_PMD_ERR("xstats id value isn't valid");
1808 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1814 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1816 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1817 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1820 struct dpaa2_queue *dpaa2_q;
1822 PMD_INIT_FUNC_TRACE();
1825 DPAA2_PMD_ERR("dpni is NULL");
1829 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1833 /* Reset the per queue stats in dpaa2_queue structure */
1834 for (i = 0; i < priv->nb_rx_queues; i++) {
1835 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1837 dpaa2_q->rx_pkts = 0;
1840 for (i = 0; i < priv->nb_tx_queues; i++) {
1841 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1843 dpaa2_q->tx_pkts = 0;
1849 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1853 /* return 0 means link status changed, -1 means not changed */
1855 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1856 int wait_to_complete)
1859 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1860 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1861 struct rte_eth_link link;
1862 struct dpni_link_state state = {0};
1866 DPAA2_PMD_ERR("dpni is NULL");
1870 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1871 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1874 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1877 if (state.up == RTE_ETH_LINK_DOWN &&
1879 rte_delay_ms(CHECK_INTERVAL);
1884 memset(&link, 0, sizeof(struct rte_eth_link));
1885 link.link_status = state.up;
1886 link.link_speed = state.rate;
1888 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1889 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
1891 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1893 ret = rte_eth_linkstatus_set(dev, &link);
1895 DPAA2_PMD_DEBUG("No change in status");
1897 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1898 link.link_status ? "Up" : "Down");
1904 * Toggle the DPNI to enable, if not already enabled.
1905 * This is not strictly PHY up/down - it is more of logical toggling.
1908 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1911 struct dpaa2_dev_priv *priv;
1912 struct fsl_mc_io *dpni;
1914 struct dpni_link_state state = {0};
1916 priv = dev->data->dev_private;
1917 dpni = (struct fsl_mc_io *)dev->process_private;
1920 DPAA2_PMD_ERR("dpni is NULL");
1924 /* Check if DPNI is currently enabled */
1925 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1927 /* Unable to obtain dpni status; Not continuing */
1928 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1932 /* Enable link if not already enabled */
1934 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1936 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1940 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1942 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1946 /* changing tx burst function to start enqueues */
1947 dev->tx_pkt_burst = dpaa2_dev_tx;
1948 dev->data->dev_link.link_status = state.up;
1949 dev->data->dev_link.link_speed = state.rate;
1952 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1954 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1959 * Toggle the DPNI to disable, if not already disabled.
1960 * This is not strictly PHY up/down - it is more of logical toggling.
1963 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1966 struct dpaa2_dev_priv *priv;
1967 struct fsl_mc_io *dpni;
1968 int dpni_enabled = 0;
1971 PMD_INIT_FUNC_TRACE();
1973 priv = dev->data->dev_private;
1974 dpni = (struct fsl_mc_io *)dev->process_private;
1977 DPAA2_PMD_ERR("Device has not yet been configured");
1981 /*changing tx burst function to avoid any more enqueues */
1982 dev->tx_pkt_burst = dummy_dev_tx;
1984 /* Loop while dpni_disable() attempts to drain the egress FQs
1985 * and confirm them back to us.
1988 ret = dpni_disable(dpni, 0, priv->token);
1990 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1993 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1995 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1999 /* Allow the MC some slack */
2000 rte_delay_us(100 * 1000);
2001 } while (dpni_enabled && --retries);
2004 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2005 /* todo- we may have to manually cleanup queues.
2008 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2009 dev->data->port_id);
2012 dev->data->dev_link.link_status = 0;
2018 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2021 struct dpaa2_dev_priv *priv;
2022 struct fsl_mc_io *dpni;
2023 struct dpni_link_state state = {0};
2025 PMD_INIT_FUNC_TRACE();
2027 priv = dev->data->dev_private;
2028 dpni = (struct fsl_mc_io *)dev->process_private;
2030 if (dpni == NULL || fc_conf == NULL) {
2031 DPAA2_PMD_ERR("device not configured");
2035 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2037 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2041 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2042 if (state.options & DPNI_LINK_OPT_PAUSE) {
2043 /* DPNI_LINK_OPT_PAUSE set
2044 * if ASYM_PAUSE not set,
2045 * RX Side flow control (handle received Pause frame)
2046 * TX side flow control (send Pause frame)
2047 * if ASYM_PAUSE set,
2048 * RX Side flow control (handle received Pause frame)
2049 * No TX side flow control (send Pause frame disabled)
2051 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2052 fc_conf->mode = RTE_ETH_FC_FULL;
2054 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2056 /* DPNI_LINK_OPT_PAUSE not set
2057 * if ASYM_PAUSE set,
2058 * TX side flow control (send Pause frame)
2059 * No RX side flow control (No action on pause frame rx)
2060 * if ASYM_PAUSE not set,
2061 * Flow control disabled
2063 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2064 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2066 fc_conf->mode = RTE_ETH_FC_NONE;
2073 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2076 struct dpaa2_dev_priv *priv;
2077 struct fsl_mc_io *dpni;
2078 struct dpni_link_state state = {0};
2079 struct dpni_link_cfg cfg = {0};
2081 PMD_INIT_FUNC_TRACE();
2083 priv = dev->data->dev_private;
2084 dpni = (struct fsl_mc_io *)dev->process_private;
2087 DPAA2_PMD_ERR("dpni is NULL");
2091 /* It is necessary to obtain the current state before setting fc_conf
2092 * as MC would return error in case rate, autoneg or duplex values are
2095 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2097 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2101 /* Disable link before setting configuration */
2102 dpaa2_dev_set_link_down(dev);
2104 /* Based on fc_conf, update cfg */
2105 cfg.rate = state.rate;
2106 cfg.options = state.options;
2108 /* update cfg with fc_conf */
2109 switch (fc_conf->mode) {
2110 case RTE_ETH_FC_FULL:
2111 /* Full flow control;
2112 * OPT_PAUSE set, ASYM_PAUSE not set
2114 cfg.options |= DPNI_LINK_OPT_PAUSE;
2115 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2117 case RTE_ETH_FC_TX_PAUSE:
2118 /* Enable RX flow control
2119 * OPT_PAUSE not set;
2122 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2123 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2125 case RTE_ETH_FC_RX_PAUSE:
2126 /* Enable TX Flow control
2130 cfg.options |= DPNI_LINK_OPT_PAUSE;
2131 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2133 case RTE_ETH_FC_NONE:
2134 /* Disable Flow control
2136 * ASYM_PAUSE not set
2138 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2139 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2142 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2147 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2149 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2153 dpaa2_dev_set_link_up(dev);
2159 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2160 struct rte_eth_rss_conf *rss_conf)
2162 struct rte_eth_dev_data *data = dev->data;
2163 struct dpaa2_dev_priv *priv = data->dev_private;
2164 struct rte_eth_conf *eth_conf = &data->dev_conf;
2167 PMD_INIT_FUNC_TRACE();
2169 if (rss_conf->rss_hf) {
2170 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2171 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2174 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2180 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2181 ret = dpaa2_remove_flow_dist(dev, tc_index);
2184 "Unable to remove flow dist on tc%d",
2190 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2195 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2196 struct rte_eth_rss_conf *rss_conf)
2198 struct rte_eth_dev_data *data = dev->data;
2199 struct rte_eth_conf *eth_conf = &data->dev_conf;
2201 /* dpaa2 does not support rss_key, so length should be 0*/
2202 rss_conf->rss_key_len = 0;
2203 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2207 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2208 int eth_rx_queue_id,
2209 struct dpaa2_dpcon_dev *dpcon,
2210 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2212 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2213 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2214 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2215 uint8_t flow_id = dpaa2_ethq->flow_id;
2216 struct dpni_queue cfg;
2217 uint8_t options, priority;
2220 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2221 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2222 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2223 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2224 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2225 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2229 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2230 (dpcon->num_priorities - 1);
2232 memset(&cfg, 0, sizeof(struct dpni_queue));
2233 options = DPNI_QUEUE_OPT_DEST;
2234 cfg.destination.type = DPNI_DEST_DPCON;
2235 cfg.destination.id = dpcon->dpcon_id;
2236 cfg.destination.priority = priority;
2238 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2239 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2240 cfg.destination.hold_active = 1;
2243 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2244 !eth_priv->en_ordered) {
2245 struct opr_cfg ocfg;
2247 /* Restoration window size = 256 frames */
2249 /* Restoration window size = 512 frames for LX2 */
2250 if (dpaa2_svr_family == SVR_LX2160A)
2252 /* Auto advance NESN window enabled */
2254 /* Late arrival window size disabled */
2256 /* ORL resource exhaustion advance NESN disabled */
2258 /* Loose ordering enabled */
2260 eth_priv->en_loose_ordered = 1;
2261 /* Strict ordering enabled if explicitly set */
2262 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2264 eth_priv->en_loose_ordered = 0;
2267 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2268 dpaa2_ethq->tc_index, flow_id,
2269 OPR_OPT_CREATE, &ocfg, 0);
2271 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2275 eth_priv->en_ordered = 1;
2278 options |= DPNI_QUEUE_OPT_USER_CTX;
2279 cfg.user_context = (size_t)(dpaa2_ethq);
2281 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2282 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2284 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2288 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2293 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2294 int eth_rx_queue_id)
2296 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2297 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2298 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2299 uint8_t flow_id = dpaa2_ethq->flow_id;
2300 struct dpni_queue cfg;
2304 memset(&cfg, 0, sizeof(struct dpni_queue));
2305 options = DPNI_QUEUE_OPT_DEST;
2306 cfg.destination.type = DPNI_DEST_NONE;
2308 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2309 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2311 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2317 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2318 const struct rte_flow_ops **ops)
2323 *ops = &dpaa2_flow_ops;
2328 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2329 struct rte_eth_rxq_info *qinfo)
2331 struct dpaa2_queue *rxq;
2332 struct dpaa2_dev_priv *priv = dev->data->dev_private;
2333 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2334 uint16_t max_frame_length;
2336 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2338 qinfo->mp = rxq->mb_pool;
2339 qinfo->scattered_rx = dev->data->scattered_rx;
2340 qinfo->nb_desc = rxq->nb_desc;
2341 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2342 &max_frame_length) == 0)
2343 qinfo->rx_buf_size = max_frame_length;
2345 qinfo->conf.rx_free_thresh = 1;
2346 qinfo->conf.rx_drop_en = 1;
2347 qinfo->conf.rx_deferred_start = 0;
2348 qinfo->conf.offloads = rxq->offloads;
2352 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2353 struct rte_eth_txq_info *qinfo)
2355 struct dpaa2_queue *txq;
2357 txq = dev->data->tx_queues[queue_id];
2359 qinfo->nb_desc = txq->nb_desc;
2360 qinfo->conf.tx_thresh.pthresh = 0;
2361 qinfo->conf.tx_thresh.hthresh = 0;
2362 qinfo->conf.tx_thresh.wthresh = 0;
2364 qinfo->conf.tx_free_thresh = 0;
2365 qinfo->conf.tx_rs_thresh = 0;
2366 qinfo->conf.offloads = txq->offloads;
2367 qinfo->conf.tx_deferred_start = 0;
2371 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2373 *(const void **)ops = &dpaa2_tm_ops;
2379 rte_pmd_dpaa2_thread_init(void)
2383 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2384 ret = dpaa2_affine_qbman_swp();
2387 "Failed to allocate IO portal, tid: %d\n",
2394 static struct eth_dev_ops dpaa2_ethdev_ops = {
2395 .dev_configure = dpaa2_eth_dev_configure,
2396 .dev_start = dpaa2_dev_start,
2397 .dev_stop = dpaa2_dev_stop,
2398 .dev_close = dpaa2_dev_close,
2399 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2400 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2401 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2402 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2403 .dev_set_link_up = dpaa2_dev_set_link_up,
2404 .dev_set_link_down = dpaa2_dev_set_link_down,
2405 .link_update = dpaa2_dev_link_update,
2406 .stats_get = dpaa2_dev_stats_get,
2407 .xstats_get = dpaa2_dev_xstats_get,
2408 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2409 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2410 .xstats_get_names = dpaa2_xstats_get_names,
2411 .stats_reset = dpaa2_dev_stats_reset,
2412 .xstats_reset = dpaa2_dev_stats_reset,
2413 .fw_version_get = dpaa2_fw_version_get,
2414 .dev_infos_get = dpaa2_dev_info_get,
2415 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2416 .mtu_set = dpaa2_dev_mtu_set,
2417 .vlan_filter_set = dpaa2_vlan_filter_set,
2418 .vlan_offload_set = dpaa2_vlan_offload_set,
2419 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2420 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2421 .rx_queue_release = dpaa2_dev_rx_queue_release,
2422 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2423 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2424 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2425 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2426 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2427 .mac_addr_add = dpaa2_dev_add_mac_addr,
2428 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2429 .mac_addr_set = dpaa2_dev_set_mac_addr,
2430 .rss_hash_update = dpaa2_dev_rss_hash_update,
2431 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2432 .flow_ops_get = dpaa2_dev_flow_ops_get,
2433 .rxq_info_get = dpaa2_rxq_info_get,
2434 .txq_info_get = dpaa2_txq_info_get,
2435 .tm_ops_get = dpaa2_tm_ops_get,
2436 #if defined(RTE_LIBRTE_IEEE1588)
2437 .timesync_enable = dpaa2_timesync_enable,
2438 .timesync_disable = dpaa2_timesync_disable,
2439 .timesync_read_time = dpaa2_timesync_read_time,
2440 .timesync_write_time = dpaa2_timesync_write_time,
2441 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2442 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2443 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2447 /* Populate the mac address from physically available (u-boot/firmware) and/or
2448 * one set by higher layers like MC (restool) etc.
2449 * Returns the table of MAC entries (multiple entries)
2452 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2453 struct rte_ether_addr *mac_entry)
2456 struct rte_ether_addr phy_mac, prime_mac;
2458 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2459 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2461 /* Get the physical device MAC address */
2462 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2463 phy_mac.addr_bytes);
2465 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2469 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2470 prime_mac.addr_bytes);
2472 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2476 /* Now that both MAC have been obtained, do:
2477 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2479 * If empty_mac(phy), return prime.
2480 * if both are empty, create random MAC, set as prime and return
2482 if (!rte_is_zero_ether_addr(&phy_mac)) {
2483 /* If the addresses are not same, overwrite prime */
2484 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2485 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2487 phy_mac.addr_bytes);
2489 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2493 memcpy(&prime_mac, &phy_mac,
2494 sizeof(struct rte_ether_addr));
2496 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2497 /* In case phys and prime, both are zero, create random MAC */
2498 rte_eth_random_addr(prime_mac.addr_bytes);
2499 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2501 prime_mac.addr_bytes);
2503 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2508 /* prime_mac the final MAC address */
2509 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2517 check_devargs_handler(__rte_unused const char *key, const char *value,
2518 __rte_unused void *opaque)
2520 if (strcmp(value, "1"))
2527 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2529 struct rte_kvargs *kvlist;
2534 kvlist = rte_kvargs_parse(devargs->args, NULL);
2538 if (!rte_kvargs_count(kvlist, key)) {
2539 rte_kvargs_free(kvlist);
2543 if (rte_kvargs_process(kvlist, key,
2544 check_devargs_handler, NULL) < 0) {
2545 rte_kvargs_free(kvlist);
2548 rte_kvargs_free(kvlist);
2554 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2556 struct rte_device *dev = eth_dev->device;
2557 struct rte_dpaa2_device *dpaa2_dev;
2558 struct fsl_mc_io *dpni_dev;
2559 struct dpni_attr attr;
2560 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2561 struct dpni_buffer_layout layout;
2564 PMD_INIT_FUNC_TRACE();
2566 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2568 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2571 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2572 eth_dev->process_private = (void *)dpni_dev;
2574 /* For secondary processes, the primary has done all the work */
2575 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2576 /* In case of secondary, only burst and ops API need to be
2579 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2580 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2581 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2582 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2583 else if (dpaa2_get_devargs(dev->devargs,
2584 DRIVER_NO_PREFETCH_MODE))
2585 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2587 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2588 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2592 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2594 hw_id = dpaa2_dev->object_id;
2595 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2598 "Failure in opening dpni@%d with err code %d",
2604 /* Clean the device first */
2605 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2607 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2612 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2615 "Failure in get dpni@%d attribute, err code %d",
2620 priv->num_rx_tc = attr.num_rx_tcs;
2621 priv->num_tx_tc = attr.num_tx_tcs;
2622 priv->qos_entries = attr.qos_entries;
2623 priv->fs_entries = attr.fs_entries;
2624 priv->dist_queues = attr.num_queues;
2625 priv->num_channels = attr.num_channels;
2626 priv->channel_inuse = 0;
2628 /* only if the custom CG is enabled */
2629 if (attr.options & DPNI_OPT_CUSTOM_CG)
2630 priv->max_cgs = attr.num_cgs;
2634 for (i = 0; i < priv->max_cgs; i++)
2635 priv->cgid_in_use[i] = 0;
2637 for (i = 0; i < attr.num_rx_tcs; i++)
2638 priv->nb_rx_queues += attr.num_queues;
2640 priv->nb_tx_queues = attr.num_tx_tcs * attr.num_channels;
2642 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2643 priv->num_rx_tc, priv->nb_rx_queues,
2644 priv->nb_tx_queues, priv->max_cgs);
2646 priv->hw = dpni_dev;
2647 priv->hw_id = hw_id;
2648 priv->options = attr.options;
2649 priv->max_mac_filters = attr.mac_filter_entries;
2650 priv->max_vlan_filters = attr.vlan_filter_entries;
2652 #if defined(RTE_LIBRTE_IEEE1588)
2653 printf("DPDK IEEE1588 is enabled\n");
2654 priv->flags |= DPAA2_TX_CONF_ENABLE;
2656 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2657 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2658 priv->flags |= DPAA2_TX_CONF_ENABLE;
2659 DPAA2_PMD_INFO("TX_CONF Enabled");
2662 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2663 dpaa2_enable_err_queue = 1;
2664 DPAA2_PMD_INFO("Enable error queue");
2667 /* Allocate memory for hardware structure for queues */
2668 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2670 DPAA2_PMD_ERR("Queue allocation Failed");
2674 /* Allocate memory for storing MAC addresses.
2675 * Table of mac_filter_entries size is allocated so that RTE ether lib
2676 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2678 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2679 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2680 if (eth_dev->data->mac_addrs == NULL) {
2682 "Failed to allocate %d bytes needed to store MAC addresses",
2683 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2688 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2690 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2691 rte_free(eth_dev->data->mac_addrs);
2692 eth_dev->data->mac_addrs = NULL;
2696 /* ... tx buffer layout ... */
2697 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2698 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2699 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2700 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2701 layout.pass_timestamp = true;
2703 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2705 layout.pass_frame_status = 1;
2706 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2707 DPNI_QUEUE_TX, &layout);
2709 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2713 /* ... tx-conf and error buffer layout ... */
2714 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2715 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2716 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2717 layout.pass_timestamp = true;
2719 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2720 layout.pass_frame_status = 1;
2721 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2722 DPNI_QUEUE_TX_CONFIRM, &layout);
2724 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2729 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2731 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2732 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2733 DPAA2_PMD_INFO("Loopback mode");
2734 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2735 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2736 DPAA2_PMD_INFO("No Prefetch mode");
2738 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2740 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2742 /* Init fields w.r.t. classification */
2743 memset(&priv->extract.qos_key_extract, 0,
2744 sizeof(struct dpaa2_key_extract));
2745 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2746 if (!priv->extract.qos_extract_param) {
2747 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2748 " classification ", ret);
2751 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2752 IP_ADDRESS_OFFSET_INVALID;
2753 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2754 IP_ADDRESS_OFFSET_INVALID;
2755 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2756 IP_ADDRESS_OFFSET_INVALID;
2757 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2758 IP_ADDRESS_OFFSET_INVALID;
2760 for (i = 0; i < MAX_TCS; i++) {
2761 memset(&priv->extract.tc_key_extract[i], 0,
2762 sizeof(struct dpaa2_key_extract));
2763 priv->extract.tc_extract_param[i] =
2764 (size_t)rte_malloc(NULL, 256, 64);
2765 if (!priv->extract.tc_extract_param[i]) {
2766 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classification",
2770 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2771 IP_ADDRESS_OFFSET_INVALID;
2772 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2773 IP_ADDRESS_OFFSET_INVALID;
2774 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2775 IP_ADDRESS_OFFSET_INVALID;
2776 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2777 IP_ADDRESS_OFFSET_INVALID;
2780 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2781 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2784 DPAA2_PMD_ERR("Unable to set mtu. check config");
2788 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2789 * with external entity to receive byte code for software sequence
2790 * and same will be offload to the H/W using MC interface.
2791 * Currently it is assumed that DPAA2 driver has byte code by some
2792 * mean and same if offloaded to H/W.
2794 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2795 WRIOP_SS_INITIALIZER(priv);
2796 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2798 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2803 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2806 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2811 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2814 dpaa2_dev_close(eth_dev);
2819 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2821 return dev->device->driver == &rte_dpaa2_pmd.driver;
2825 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2826 struct rte_dpaa2_device *dpaa2_dev)
2828 struct rte_eth_dev *eth_dev;
2829 struct dpaa2_dev_priv *dev_priv;
2832 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2833 RTE_PKTMBUF_HEADROOM) {
2835 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2836 RTE_PKTMBUF_HEADROOM,
2837 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2842 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2843 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2846 dev_priv = rte_zmalloc("ethdev private structure",
2847 sizeof(struct dpaa2_dev_priv),
2848 RTE_CACHE_LINE_SIZE);
2849 if (dev_priv == NULL) {
2851 "Unable to allocate memory for private data");
2852 rte_eth_dev_release_port(eth_dev);
2855 eth_dev->data->dev_private = (void *)dev_priv;
2856 /* Store a pointer to eth_dev in dev_private */
2857 dev_priv->eth_dev = eth_dev;
2859 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2861 DPAA2_PMD_DEBUG("returning enodev");
2866 eth_dev->device = &dpaa2_dev->device;
2868 dpaa2_dev->eth_dev = eth_dev;
2869 eth_dev->data->rx_mbuf_alloc_failed = 0;
2871 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2872 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2874 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2876 /* Invoke PMD device initialization function */
2877 diag = dpaa2_dev_init(eth_dev);
2879 rte_eth_dev_probing_finish(eth_dev);
2883 rte_eth_dev_release_port(eth_dev);
2888 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2890 struct rte_eth_dev *eth_dev;
2893 eth_dev = dpaa2_dev->eth_dev;
2894 dpaa2_dev_close(eth_dev);
2895 ret = rte_eth_dev_release_port(eth_dev);
2900 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2901 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2902 .drv_type = DPAA2_ETH,
2903 .probe = rte_dpaa2_probe,
2904 .remove = rte_dpaa2_remove,
2907 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2908 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2909 DRIVER_LOOPBACK_MODE "=<int> "
2910 DRIVER_NO_PREFETCH_MODE "=<int>"
2911 DRIVER_TX_CONF "=<int>"
2912 DRIVER_ERROR_QUEUE "=<int>");
2913 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);