drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "dpaa2_pmd_logs.h"
  23 #include <fslmc_vfio.h>
  24 #include <dpaa2_hw_pvt.h>
  25 #include <dpaa2_hw_mempool.h>
  26 #include <dpaa2_hw_dpio.h>
  27 #include <mc/fsl_dpmng.h>
  28 #include "dpaa2_ethdev.h"
  29 #include "dpaa2_sparser.h"
  30 #include <fsl_qbman_debug.h>
  31
  32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  34 #define DRIVER_TX_CONF "drv_tx_conf"
  35 #define DRIVER_ERROR_QUEUE  "drv_err_queue"
  36 #define CHECK_INTERVAL         100  /* 100ms */
  37 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  38
  39 /* Supported Rx offloads */
  40 static uint64_t dev_rx_offloads_sup =
  41                 RTE_ETH_RX_OFFLOAD_CHECKSUM |
  42                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
  43                 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  44                 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
  45                 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
  46                 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
  47                 RTE_ETH_RX_OFFLOAD_TIMESTAMP;
  48
  49 /* Rx offloads which cannot be disabled */
  50 static uint64_t dev_rx_offloads_nodis =
  51                 RTE_ETH_RX_OFFLOAD_RSS_HASH |
  52                 RTE_ETH_RX_OFFLOAD_SCATTER;
  53
  54 /* Supported Tx offloads */
  55 static uint64_t dev_tx_offloads_sup =
  56                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
  57                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
  58                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
  59                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
  60                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
  61                 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  62                 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
  63                 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
  64
  65 /* Tx offloads which cannot be disabled */
  66 static uint64_t dev_tx_offloads_nodis =
  67                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
  68
  69 /* enable timestamp in mbuf */
  70 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  71 uint64_t dpaa2_timestamp_rx_dynflag;
  72 int dpaa2_timestamp_dynfield_offset = -1;
  73
  74 /* Enable error queue */
  75 bool dpaa2_enable_err_queue;
  76
  77 #define MAX_NB_RX_DESC          11264
  78 int total_nb_rx_desc;
  79
  80 struct rte_dpaa2_xstats_name_off {
  81         char name[RTE_ETH_XSTATS_NAME_SIZE];
  82         uint8_t page_id; /* dpni statistics page id */
  83         uint8_t stats_id; /* stats id in the given page */
  84 };
  85
  86 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  87         {"ingress_multicast_frames", 0, 2},
  88         {"ingress_multicast_bytes", 0, 3},
  89         {"ingress_broadcast_frames", 0, 4},
  90         {"ingress_broadcast_bytes", 0, 5},
  91         {"egress_multicast_frames", 1, 2},
  92         {"egress_multicast_bytes", 1, 3},
  93         {"egress_broadcast_frames", 1, 4},
  94         {"egress_broadcast_bytes", 1, 5},
  95         {"ingress_filtered_frames", 2, 0},
  96         {"ingress_discarded_frames", 2, 1},
  97         {"ingress_nobuffer_discards", 2, 2},
  98         {"egress_discarded_frames", 2, 3},
  99         {"egress_confirmed_frames", 2, 4},
 100         {"cgr_reject_frames", 4, 0},
 101         {"cgr_reject_bytes", 4, 1},
 102 };
 103
 104 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 105 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 106                                  int wait_to_complete);
 107 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 108 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 109 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 110
 111 static int
 112 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 113 {
 114         int ret;
 115         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 116         struct fsl_mc_io *dpni = dev->process_private;
 117
 118         PMD_INIT_FUNC_TRACE();
 119
 120         if (dpni == NULL) {
 121                 DPAA2_PMD_ERR("dpni is NULL");
 122                 return -1;
 123         }
 124
 125         if (on)
 126                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 127                                        vlan_id, 0, 0, 0);
 128         else
 129                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 130                                           priv->token, vlan_id);
 131
 132         if (ret < 0)
 133                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 134                               ret, vlan_id, priv->hw_id);
 135
 136         return ret;
 137 }
 138
 139 static int
 140 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 141 {
 142         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 143         struct fsl_mc_io *dpni = dev->process_private;
 144         int ret = 0;
 145
 146         PMD_INIT_FUNC_TRACE();
 147
 148         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
 149                 /* VLAN Filter not available */
 150                 if (!priv->max_vlan_filters) {
 151                         DPAA2_PMD_INFO("VLAN filter not available");
 152                         return -ENOTSUP;
 153                 }
 154
 155                 if (dev->data->dev_conf.rxmode.offloads &
 156                         RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 157                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 158                                                       priv->token, true);
 159                 else
 160                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 161                                                       priv->token, false);
 162                 if (ret < 0)
 163                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 164         }
 165
 166         return ret;
 167 }
 168
 169 static int
 170 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 171                       enum rte_vlan_type vlan_type __rte_unused,
 172                       uint16_t tpid)
 173 {
 174         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 175         struct fsl_mc_io *dpni = dev->process_private;
 176         int ret = -ENOTSUP;
 177
 178         PMD_INIT_FUNC_TRACE();
 179
 180         /* nothing to be done for standard vlan tpids */
 181         if (tpid == 0x8100 || tpid == 0x88A8)
 182                 return 0;
 183
 184         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 185                                    priv->token, tpid);
 186         if (ret < 0)
 187                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 188         /* if already configured tpids, remove them first */
 189         if (ret == -EBUSY) {
 190                 struct dpni_custom_tpid_cfg tpid_list = {0};
 191
 192                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 193                                    priv->token, &tpid_list);
 194                 if (ret < 0)
 195                         goto fail;
 196                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 197                                    priv->token, tpid_list.tpid1);
 198                 if (ret < 0)
 199                         goto fail;
 200                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 201                                            priv->token, tpid);
 202         }
 203 fail:
 204         return ret;
 205 }
 206
 207 static int
 208 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 209                      char *fw_version,
 210                      size_t fw_size)
 211 {
 212         int ret;
 213         struct fsl_mc_io *dpni = dev->process_private;
 214         struct mc_soc_version mc_plat_info = {0};
 215         struct mc_version mc_ver_info = {0};
 216
 217         PMD_INIT_FUNC_TRACE();
 218
 219         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 220                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 221
 222         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 223                 DPAA2_PMD_WARN("\tmc_get_version failed");
 224
 225         ret = snprintf(fw_version, fw_size,
 226                        "%x-%d.%d.%d",
 227                        mc_plat_info.svr,
 228                        mc_ver_info.major,
 229                        mc_ver_info.minor,
 230                        mc_ver_info.revision);
 231         if (ret < 0)
 232                 return -EINVAL;
 233
 234         ret += 1; /* add the size of '\0' */
 235         if (fw_size < (size_t)ret)
 236                 return ret;
 237         else
 238                 return 0;
 239 }
 240
 241 static int
 242 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 243 {
 244         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 245
 246         PMD_INIT_FUNC_TRACE();
 247
 248         dev_info->max_mac_addrs = priv->max_mac_filters;
 249         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 250         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 251         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 252         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 253         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 254                                         dev_rx_offloads_nodis;
 255         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 256                                         dev_tx_offloads_nodis;
 257         dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
 258                         RTE_ETH_LINK_SPEED_2_5G |
 259                         RTE_ETH_LINK_SPEED_10G;
 260         dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 261
 262         dev_info->max_hash_mac_addrs = 0;
 263         dev_info->max_vfs = 0;
 264         dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
 265         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 266
 267         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 268         /* same is rx size for best perf */
 269         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 270
 271         dev_info->default_rxportconf.nb_queues = 1;
 272         dev_info->default_txportconf.nb_queues = 1;
 273         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 274         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 275
 276         if (dpaa2_svr_family == SVR_LX2160A) {
 277                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G |
 278                                 RTE_ETH_LINK_SPEED_40G |
 279                                 RTE_ETH_LINK_SPEED_50G |
 280                                 RTE_ETH_LINK_SPEED_100G;
 281         }
 282
 283         return 0;
 284 }
 285
 286 static int
 287 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 288                         __rte_unused uint16_t queue_id,
 289                         struct rte_eth_burst_mode *mode)
 290 {
 291         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 292         int ret = -EINVAL;
 293         unsigned int i;
 294         const struct burst_info {
 295                 uint64_t flags;
 296                 const char *output;
 297         } rx_offload_map[] = {
 298                         {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 299                         {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 300                         {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 301                         {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 302                         {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 303                         {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 304                         {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 305                         {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"},
 306                         {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}
 307         };
 308
 309         /* Update Rx offload info */
 310         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 311                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 312                         snprintf(mode->info, sizeof(mode->info), "%s",
 313                                 rx_offload_map[i].output);
 314                         ret = 0;
 315                         break;
 316                 }
 317         }
 318         return ret;
 319 }
 320
 321 static int
 322 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 323                         __rte_unused uint16_t queue_id,
 324                         struct rte_eth_burst_mode *mode)
 325 {
 326         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 327         int ret = -EINVAL;
 328         unsigned int i;
 329         const struct burst_info {
 330                 uint64_t flags;
 331                 const char *output;
 332         } tx_offload_map[] = {
 333                         {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 334                         {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 335                         {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 336                         {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 337                         {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 338                         {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 339                         {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 340                         {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 341                         {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 342         };
 343
 344         /* Update Tx offload info */
 345         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 346                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 347                         snprintf(mode->info, sizeof(mode->info), "%s",
 348                                 tx_offload_map[i].output);
 349                         ret = 0;
 350                         break;
 351                 }
 352         }
 353         return ret;
 354 }
 355
 356 static int
 357 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 358 {
 359         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 360         uint16_t dist_idx;
 361         uint32_t vq_id;
 362         uint8_t num_rxqueue_per_tc;
 363         struct dpaa2_queue *mc_q, *mcq;
 364         uint32_t tot_queues;
 365         int i;
 366         struct dpaa2_queue *dpaa2_q;
 367
 368         PMD_INIT_FUNC_TRACE();
 369
 370         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 371         if (priv->flags & DPAA2_TX_CONF_ENABLE)
 372                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 373         else
 374                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 375         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 376                           RTE_CACHE_LINE_SIZE);
 377         if (!mc_q) {
 378                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 379                 return -1;
 380         }
 381
 382         for (i = 0; i < priv->nb_rx_queues; i++) {
 383                 mc_q->eth_data = dev->data;
 384                 priv->rx_vq[i] = mc_q++;
 385                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 386                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 387                                         sizeof(struct queue_storage_info_t),
 388                                         RTE_CACHE_LINE_SIZE);
 389                 if (!dpaa2_q->q_storage)
 390                         goto fail;
 391
 392                 memset(dpaa2_q->q_storage, 0,
 393                        sizeof(struct queue_storage_info_t));
 394                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 395                         goto fail;
 396         }
 397
 398         if (dpaa2_enable_err_queue) {
 399                 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
 400                         sizeof(struct dpaa2_queue), 0);
 401
 402                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 403                 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
 404                                         sizeof(struct queue_storage_info_t) *
 405                                         RTE_MAX_LCORE,
 406                                         RTE_CACHE_LINE_SIZE);
 407                 if (!dpaa2_q->q_storage)
 408                         goto fail;
 409
 410                 memset(dpaa2_q->q_storage, 0,
 411                        sizeof(struct queue_storage_info_t));
 412                 for (i = 0; i < RTE_MAX_LCORE; i++)
 413                         if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
 414                                 goto fail;
 415         }
 416
 417         for (i = 0; i < priv->nb_tx_queues; i++) {
 418                 mc_q->eth_data = dev->data;
 419                 mc_q->flow_id = 0xffff;
 420                 priv->tx_vq[i] = mc_q++;
 421                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 422                 dpaa2_q->cscn = rte_malloc(NULL,
 423                                            sizeof(struct qbman_result), 16);
 424                 if (!dpaa2_q->cscn)
 425                         goto fail_tx;
 426         }
 427
 428         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 429                 /*Setup tx confirmation queues*/
 430                 for (i = 0; i < priv->nb_tx_queues; i++) {
 431                         mc_q->eth_data = dev->data;
 432                         mc_q->tc_index = i;
 433                         mc_q->flow_id = 0;
 434                         priv->tx_conf_vq[i] = mc_q++;
 435                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 436                         dpaa2_q->q_storage =
 437                                 rte_malloc("dq_storage",
 438                                         sizeof(struct queue_storage_info_t),
 439                                         RTE_CACHE_LINE_SIZE);
 440                         if (!dpaa2_q->q_storage)
 441                                 goto fail_tx_conf;
 442
 443                         memset(dpaa2_q->q_storage, 0,
 444                                sizeof(struct queue_storage_info_t));
 445                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 446                                 goto fail_tx_conf;
 447                 }
 448         }
 449
 450         vq_id = 0;
 451         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 452                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 453                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 454                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 455                 vq_id++;
 456         }
 457
 458         return 0;
 459 fail_tx_conf:
 460         i -= 1;
 461         while (i >= 0) {
 462                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 463                 rte_free(dpaa2_q->q_storage);
 464                 priv->tx_conf_vq[i--] = NULL;
 465         }
 466         i = priv->nb_tx_queues;
 467 fail_tx:
 468         i -= 1;
 469         while (i >= 0) {
 470                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 471                 rte_free(dpaa2_q->cscn);
 472                 priv->tx_vq[i--] = NULL;
 473         }
 474         i = priv->nb_rx_queues;
 475 fail:
 476         i -= 1;
 477         mc_q = priv->rx_vq[0];
 478         while (i >= 0) {
 479                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 480                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 481                 rte_free(dpaa2_q->q_storage);
 482                 priv->rx_vq[i--] = NULL;
 483         }
 484
 485         if (dpaa2_enable_err_queue) {
 486                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 487                 if (dpaa2_q->q_storage)
 488                         dpaa2_free_dq_storage(dpaa2_q->q_storage);
 489                 rte_free(dpaa2_q->q_storage);
 490         }
 491
 492         rte_free(mc_q);
 493         return -1;
 494 }
 495
 496 static void
 497 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 498 {
 499         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 500         struct dpaa2_queue *dpaa2_q;
 501         int i;
 502
 503         PMD_INIT_FUNC_TRACE();
 504
 505         /* Queue allocation base */
 506         if (priv->rx_vq[0]) {
 507                 /* cleaning up queue storage */
 508                 for (i = 0; i < priv->nb_rx_queues; i++) {
 509                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 510                         if (dpaa2_q->q_storage)
 511                                 rte_free(dpaa2_q->q_storage);
 512                 }
 513                 /* cleanup tx queue cscn */
 514                 for (i = 0; i < priv->nb_tx_queues; i++) {
 515                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 516                         rte_free(dpaa2_q->cscn);
 517                 }
 518                 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 519                         /* cleanup tx conf queue storage */
 520                         for (i = 0; i < priv->nb_tx_queues; i++) {
 521                                 dpaa2_q = (struct dpaa2_queue *)
 522                                                 priv->tx_conf_vq[i];
 523                                 rte_free(dpaa2_q->q_storage);
 524                         }
 525                 }
 526                 /*free memory for all queues (RX+TX) */
 527                 rte_free(priv->rx_vq[0]);
 528                 priv->rx_vq[0] = NULL;
 529         }
 530 }
 531
 532 static int
 533 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 534 {
 535         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 536         struct fsl_mc_io *dpni = dev->process_private;
 537         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 538         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 539         uint64_t tx_offloads = eth_conf->txmode.offloads;
 540         int rx_l3_csum_offload = false;
 541         int rx_l4_csum_offload = false;
 542         int tx_l3_csum_offload = false;
 543         int tx_l4_csum_offload = false;
 544         int ret, tc_index;
 545         uint32_t max_rx_pktlen;
 546
 547         PMD_INIT_FUNC_TRACE();
 548
 549         /* Rx offloads which are enabled by default */
 550         if (dev_rx_offloads_nodis & ~rx_offloads) {
 551                 DPAA2_PMD_INFO(
 552                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 553                 " fixed are 0x%" PRIx64,
 554                 rx_offloads, dev_rx_offloads_nodis);
 555         }
 556
 557         /* Tx offloads which are enabled by default */
 558         if (dev_tx_offloads_nodis & ~tx_offloads) {
 559                 DPAA2_PMD_INFO(
 560                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 561                 " fixed are 0x%" PRIx64,
 562                 tx_offloads, dev_tx_offloads_nodis);
 563         }
 564
 565         max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
 566                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
 567         if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) {
 568                 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 569                         priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN);
 570                 if (ret != 0) {
 571                         DPAA2_PMD_ERR("Unable to set mtu. check config");
 572                         return ret;
 573                 }
 574                 DPAA2_PMD_INFO("MTU configured for the device: %d",
 575                                 dev->data->mtu);
 576         } else {
 577                 return -1;
 578         }
 579
 580         if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
 581                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 582                         ret = dpaa2_setup_flow_dist(dev,
 583                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 584                                         tc_index);
 585                         if (ret) {
 586                                 DPAA2_PMD_ERR(
 587                                         "Unable to set flow distribution on tc%d."
 588                                         "Check queue config", tc_index);
 589                                 return ret;
 590                         }
 591                 }
 592         }
 593
 594         if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM)
 595                 rx_l3_csum_offload = true;
 596
 597         if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) ||
 598                 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) ||
 599                 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM))
 600                 rx_l4_csum_offload = true;
 601
 602         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 603                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 604         if (ret) {
 605                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 606                 return ret;
 607         }
 608
 609         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 610                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 611         if (ret) {
 612                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 613                 return ret;
 614         }
 615
 616 #if !defined(RTE_LIBRTE_IEEE1588)
 617         if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 618 #endif
 619         {
 620                 ret = rte_mbuf_dyn_rx_timestamp_register(
 621                                 &dpaa2_timestamp_dynfield_offset,
 622                                 &dpaa2_timestamp_rx_dynflag);
 623                 if (ret != 0) {
 624                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 625                         return -rte_errno;
 626                 }
 627                 dpaa2_enable_ts[dev->data->port_id] = true;
 628         }
 629
 630         if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
 631                 tx_l3_csum_offload = true;
 632
 633         if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) ||
 634                 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) ||
 635                 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM))
 636                 tx_l4_csum_offload = true;
 637
 638         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 639                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 640         if (ret) {
 641                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 642                 return ret;
 643         }
 644
 645         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 646                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 647         if (ret) {
 648                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 649                 return ret;
 650         }
 651
 652         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 653          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 654          * to 0 for LS2 in the hardware thus disabling data/annotation
 655          * stashing. For LX2 this is fixed in hardware and thus hash result and
 656          * parse results can be received in FD using this option.
 657          */
 658         if (dpaa2_svr_family == SVR_LX2160A) {
 659                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 660                                        DPNI_FLCTYPE_HASH, true);
 661                 if (ret) {
 662                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 663                         return ret;
 664                 }
 665         }
 666
 667         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 668                 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK);
 669
 670         dpaa2_tm_init(dev);
 671
 672         return 0;
 673 }
 674
 675 /* Function to setup RX flow information. It contains traffic class ID,
 676  * flow ID, destination configuration etc.
 677  */
 678 static int
 679 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 680                          uint16_t rx_queue_id,
 681                          uint16_t nb_rx_desc,
 682                          unsigned int socket_id __rte_unused,
 683                          const struct rte_eth_rxconf *rx_conf,
 684                          struct rte_mempool *mb_pool)
 685 {
 686         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 687         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 688         struct dpaa2_queue *dpaa2_q;
 689         struct dpni_queue cfg;
 690         uint8_t options = 0;
 691         uint8_t flow_id;
 692         uint32_t bpid;
 693         int i, ret;
 694
 695         PMD_INIT_FUNC_TRACE();
 696
 697         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 698                         dev, rx_queue_id, mb_pool, rx_conf);
 699
 700         total_nb_rx_desc += nb_rx_desc;
 701         if (total_nb_rx_desc > MAX_NB_RX_DESC) {
 702                 DPAA2_PMD_WARN("\nTotal nb_rx_desc exceeds %d limit. Please use Normal buffers",
 703                                MAX_NB_RX_DESC);
 704                 DPAA2_PMD_WARN("To use Normal buffers, run 'export DPNI_NORMAL_BUF=1' before running dynamic_dpl.sh script");
 705         }
 706
 707         /* Rx deferred start is not supported */
 708         if (rx_conf->rx_deferred_start) {
 709                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 710                                 (void *)dev);
 711                 return -EINVAL;
 712         }
 713
 714         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 715                 bpid = mempool_to_bpid(mb_pool);
 716                 ret = dpaa2_attach_bp_list(priv,
 717                                            rte_dpaa2_bpid_info[bpid].bp_list);
 718                 if (ret)
 719                         return ret;
 720         }
 721         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 722         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 723         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 724         dpaa2_q->nb_desc = UINT16_MAX;
 725         dpaa2_q->offloads = rx_conf->offloads;
 726
 727         /*Get the flow id from given VQ id*/
 728         flow_id = dpaa2_q->flow_id;
 729         memset(&cfg, 0, sizeof(struct dpni_queue));
 730
 731         options = options | DPNI_QUEUE_OPT_USER_CTX;
 732         cfg.user_context = (size_t)(dpaa2_q);
 733
 734         /* check if a private cgr available. */
 735         for (i = 0; i < priv->max_cgs; i++) {
 736                 if (!priv->cgid_in_use[i]) {
 737                         priv->cgid_in_use[i] = 1;
 738                         break;
 739                 }
 740         }
 741
 742         if (i < priv->max_cgs) {
 743                 options |= DPNI_QUEUE_OPT_SET_CGID;
 744                 cfg.cgid = i;
 745                 dpaa2_q->cgid = cfg.cgid;
 746         } else {
 747                 dpaa2_q->cgid = 0xff;
 748         }
 749
 750         /*if ls2088 or rev2 device, enable the stashing */
 751
 752         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 753                 options |= DPNI_QUEUE_OPT_FLC;
 754                 cfg.flc.stash_control = true;
 755                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 756                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 757                  * data stashing setting 01 01 00 (0x14)
 758                  * (in following order ->DS AS CS)
 759                  * to enable 1 line data, 1 line annotation.
 760                  * For LX2, this setting should be 01 00 00 (0x10)
 761                  */
 762                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 763                         cfg.flc.value |= 0x10;
 764                 else
 765                         cfg.flc.value |= 0x14;
 766         }
 767         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 768                              dpaa2_q->tc_index, flow_id, options, &cfg);
 769         if (ret) {
 770                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 771                 return -1;
 772         }
 773
 774         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 775                 struct dpni_taildrop taildrop;
 776
 777                 taildrop.enable = 1;
 778                 dpaa2_q->nb_desc = nb_rx_desc;
 779                 /* Private CGR will use tail drop length as nb_rx_desc.
 780                  * for rest cases we can use standard byte based tail drop.
 781                  * There is no HW restriction, but number of CGRs are limited,
 782                  * hence this restriction is placed.
 783                  */
 784                 if (dpaa2_q->cgid != 0xff) {
 785                         /*enabling per rx queue congestion control */
 786                         taildrop.threshold = nb_rx_desc;
 787                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 788                         taildrop.oal = 0;
 789                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 790                                         rx_queue_id);
 791                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 792                                                 DPNI_CP_CONGESTION_GROUP,
 793                                                 DPNI_QUEUE_RX,
 794                                                 dpaa2_q->tc_index,
 795                                                 dpaa2_q->cgid, &taildrop);
 796                 } else {
 797                         /*enabling per rx queue congestion control */
 798                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 799                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 800                         taildrop.oal = CONG_RX_OAL;
 801                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 802                                         rx_queue_id);
 803                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 804                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 805                                                 dpaa2_q->tc_index, flow_id,
 806                                                 &taildrop);
 807                 }
 808                 if (ret) {
 809                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 810                                       ret);
 811                         return -1;
 812                 }
 813         } else { /* Disable tail Drop */
 814                 struct dpni_taildrop taildrop = {0};
 815                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 816
 817                 taildrop.enable = 0;
 818                 if (dpaa2_q->cgid != 0xff) {
 819                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 820                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 821                                         dpaa2_q->tc_index,
 822                                         dpaa2_q->cgid, &taildrop);
 823                 } else {
 824                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 825                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 826                                         dpaa2_q->tc_index, flow_id, &taildrop);
 827                 }
 828                 if (ret) {
 829                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 830                                       ret);
 831                         return -1;
 832                 }
 833         }
 834
 835         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 836         return 0;
 837 }
 838
 839 static int
 840 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 841                          uint16_t tx_queue_id,
 842                          uint16_t nb_tx_desc,
 843                          unsigned int socket_id __rte_unused,
 844                          const struct rte_eth_txconf *tx_conf)
 845 {
 846         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 847         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 848                 priv->tx_vq[tx_queue_id];
 849         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 850                 priv->tx_conf_vq[tx_queue_id];
 851         struct fsl_mc_io *dpni = dev->process_private;
 852         struct dpni_queue tx_conf_cfg;
 853         struct dpni_queue tx_flow_cfg;
 854         uint8_t options = 0, flow_id;
 855         struct dpni_queue_id qid;
 856         uint32_t tc_id;
 857         int ret;
 858
 859         PMD_INIT_FUNC_TRACE();
 860
 861         /* Tx deferred start is not supported */
 862         if (tx_conf->tx_deferred_start) {
 863                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 864                                 (void *)dev);
 865                 return -EINVAL;
 866         }
 867
 868         dpaa2_q->nb_desc = UINT16_MAX;
 869         dpaa2_q->offloads = tx_conf->offloads;
 870
 871         /* Return if queue already configured */
 872         if (dpaa2_q->flow_id != 0xffff) {
 873                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 874                 return 0;
 875         }
 876
 877         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 878         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 879
 880         tc_id = tx_queue_id;
 881         flow_id = 0;
 882
 883         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 884                         tc_id, flow_id, options, &tx_flow_cfg);
 885         if (ret) {
 886                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 887                         "tc_id=%d, flow=%d err=%d",
 888                         tc_id, flow_id, ret);
 889                         return -1;
 890         }
 891
 892         dpaa2_q->flow_id = flow_id;
 893
 894         if (tx_queue_id == 0) {
 895                 /*Set tx-conf and error configuration*/
 896                 if (priv->flags & DPAA2_TX_CONF_ENABLE)
 897                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 898                                                             priv->token,
 899                                                             DPNI_CONF_AFFINE);
 900                 else
 901                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 902                                                             priv->token,
 903                                                             DPNI_CONF_DISABLE);
 904                 if (ret) {
 905                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 906                                       "err=%d", ret);
 907                         return -1;
 908                 }
 909         }
 910         dpaa2_q->tc_index = tc_id;
 911
 912         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 913                              DPNI_QUEUE_TX, dpaa2_q->tc_index,
 914                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 915         if (ret) {
 916                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 917                 return -1;
 918         }
 919         dpaa2_q->fqid = qid.fqid;
 920
 921         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 922                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 923
 924                 dpaa2_q->nb_desc = nb_tx_desc;
 925
 926                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 927                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 928                 /* Notify that the queue is not congested when the data in
 929                  * the queue is below this threshold.(90% of value)
 930                  */
 931                 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
 932                 cong_notif_cfg.message_ctx = 0;
 933                 cong_notif_cfg.message_iova =
 934                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 935                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 936                 cong_notif_cfg.notification_mode =
 937                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 938                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 939                                          DPNI_CONG_OPT_COHERENT_WRITE;
 940                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 941
 942                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 943                                                        priv->token,
 944                                                        DPNI_QUEUE_TX,
 945                                                        tc_id,
 946                                                        &cong_notif_cfg);
 947                 if (ret) {
 948                         DPAA2_PMD_ERR(
 949                            "Error in setting tx congestion notification: "
 950                            "err=%d", ret);
 951                         return -ret;
 952                 }
 953         }
 954         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 955         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 956
 957         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 958                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 959                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 960                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 961                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 962                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 963                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 964                 if (ret) {
 965                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 966                               "tc_index=%d, flow=%d err=%d",
 967                               dpaa2_tx_conf_q->tc_index,
 968                               dpaa2_tx_conf_q->flow_id, ret);
 969                         return -1;
 970                 }
 971
 972                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 973                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 974                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 975                 if (ret) {
 976                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 977                         return -1;
 978                 }
 979                 dpaa2_tx_conf_q->fqid = qid.fqid;
 980         }
 981         return 0;
 982 }
 983
 984 static void
 985 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 986 {
 987         struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id];
 988         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 989         struct fsl_mc_io *dpni =
 990                 (struct fsl_mc_io *)priv->eth_dev->process_private;
 991         uint8_t options = 0;
 992         int ret;
 993         struct dpni_queue cfg;
 994
 995         memset(&cfg, 0, sizeof(struct dpni_queue));
 996         PMD_INIT_FUNC_TRACE();
 997
 998         total_nb_rx_desc -= dpaa2_q->nb_desc;
 999
1000         if (dpaa2_q->cgid != 0xff) {
1001                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
1002                 cfg.cgid = dpaa2_q->cgid;
1003
1004                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
1005                                      DPNI_QUEUE_RX,
1006                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
1007                                      options, &cfg);
1008                 if (ret)
1009                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1010                                         dpaa2_q->fqid, ret);
1011                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1012                 dpaa2_q->cgid = 0xff;
1013         }
1014 }
1015
1016 static uint32_t
1017 dpaa2_dev_rx_queue_count(void *rx_queue)
1018 {
1019         int32_t ret;
1020         struct dpaa2_queue *dpaa2_q;
1021         struct qbman_swp *swp;
1022         struct qbman_fq_query_np_rslt state;
1023         uint32_t frame_cnt = 0;
1024
1025         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1026                 ret = dpaa2_affine_qbman_swp();
1027                 if (ret) {
1028                         DPAA2_PMD_ERR(
1029                                 "Failed to allocate IO portal, tid: %d\n",
1030                                 rte_gettid());
1031                         return -EINVAL;
1032                 }
1033         }
1034         swp = DPAA2_PER_LCORE_PORTAL;
1035
1036         dpaa2_q = rx_queue;
1037
1038         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1039                 frame_cnt = qbman_fq_state_frame_count(&state);
1040                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u",
1041                                 rx_queue, frame_cnt);
1042         }
1043         return frame_cnt;
1044 }
1045
1046 static const uint32_t *
1047 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1048 {
1049         static const uint32_t ptypes[] = {
1050                 /*todo -= add more types */
1051                 RTE_PTYPE_L2_ETHER,
1052                 RTE_PTYPE_L3_IPV4,
1053                 RTE_PTYPE_L3_IPV4_EXT,
1054                 RTE_PTYPE_L3_IPV6,
1055                 RTE_PTYPE_L3_IPV6_EXT,
1056                 RTE_PTYPE_L4_TCP,
1057                 RTE_PTYPE_L4_UDP,
1058                 RTE_PTYPE_L4_SCTP,
1059                 RTE_PTYPE_L4_ICMP,
1060                 RTE_PTYPE_UNKNOWN
1061         };
1062
1063         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1064                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1065                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1066                 return ptypes;
1067         return NULL;
1068 }
1069
1070 /**
1071  * Dpaa2 link Interrupt handler
1072  *
1073  * @param param
1074  *  The address of parameter (struct rte_eth_dev *) registered before.
1075  *
1076  * @return
1077  *  void
1078  */
1079 static void
1080 dpaa2_interrupt_handler(void *param)
1081 {
1082         struct rte_eth_dev *dev = param;
1083         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1084         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1085         int ret;
1086         int irq_index = DPNI_IRQ_INDEX;
1087         unsigned int status = 0, clear = 0;
1088
1089         PMD_INIT_FUNC_TRACE();
1090
1091         if (dpni == NULL) {
1092                 DPAA2_PMD_ERR("dpni is NULL");
1093                 return;
1094         }
1095
1096         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1097                                   irq_index, &status);
1098         if (unlikely(ret)) {
1099                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1100                 clear = 0xffffffff;
1101                 goto out;
1102         }
1103
1104         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1105                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1106                 dpaa2_dev_link_update(dev, 0);
1107                 /* calling all the apps registered for link status event */
1108                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1109         }
1110 out:
1111         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1112                                     irq_index, clear);
1113         if (unlikely(ret))
1114                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1115 }
1116
1117 static int
1118 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1119 {
1120         int err = 0;
1121         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1122         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1123         int irq_index = DPNI_IRQ_INDEX;
1124         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1125
1126         PMD_INIT_FUNC_TRACE();
1127
1128         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1129                                 irq_index, mask);
1130         if (err < 0) {
1131                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1132                               strerror(-err));
1133                 return err;
1134         }
1135
1136         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1137                                   irq_index, enable);
1138         if (err < 0)
1139                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1140                               strerror(-err));
1141
1142         return err;
1143 }
1144
1145 static int
1146 dpaa2_dev_start(struct rte_eth_dev *dev)
1147 {
1148         struct rte_device *rdev = dev->device;
1149         struct rte_dpaa2_device *dpaa2_dev;
1150         struct rte_eth_dev_data *data = dev->data;
1151         struct dpaa2_dev_priv *priv = data->dev_private;
1152         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1153         struct dpni_queue cfg;
1154         struct dpni_error_cfg   err_cfg;
1155         uint16_t qdid;
1156         struct dpni_queue_id qid;
1157         struct dpaa2_queue *dpaa2_q;
1158         int ret, i;
1159         struct rte_intr_handle *intr_handle;
1160
1161         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1162         intr_handle = dpaa2_dev->intr_handle;
1163
1164         PMD_INIT_FUNC_TRACE();
1165
1166         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1167         if (ret) {
1168                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1169                               priv->hw_id, ret);
1170                 return ret;
1171         }
1172
1173         /* Power up the phy. Needed to make the link go UP */
1174         dpaa2_dev_set_link_up(dev);
1175
1176         ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1177                             DPNI_QUEUE_TX, &qdid);
1178         if (ret) {
1179                 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1180                 return ret;
1181         }
1182         priv->qdid = qdid;
1183
1184         for (i = 0; i < data->nb_rx_queues; i++) {
1185                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1186                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1187                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1188                                        dpaa2_q->flow_id, &cfg, &qid);
1189                 if (ret) {
1190                         DPAA2_PMD_ERR("Error in getting flow information: "
1191                                       "err=%d", ret);
1192                         return ret;
1193                 }
1194                 dpaa2_q->fqid = qid.fqid;
1195         }
1196
1197         if (dpaa2_enable_err_queue) {
1198                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1199                                      DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1200                 if (ret) {
1201                         DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1202                                                 ret);
1203                         return ret;
1204                 }
1205                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1206                 dpaa2_q->fqid = qid.fqid;
1207                 dpaa2_q->eth_data = dev->data;
1208
1209                 err_cfg.errors =  DPNI_ERROR_DISC;
1210                 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1211         } else {
1212                 /* checksum errors, send them to normal path
1213                  * and set it in annotation
1214                  */
1215                 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1216
1217                 /* if packet with parse error are not to be dropped */
1218                 err_cfg.errors |= DPNI_ERROR_PHE;
1219
1220                 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1221         }
1222         err_cfg.set_frame_annotation = true;
1223
1224         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1225                                        priv->token, &err_cfg);
1226         if (ret) {
1227                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1228                               ret);
1229                 return ret;
1230         }
1231
1232         /* if the interrupts were configured on this devices*/
1233         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1234             dev->data->dev_conf.intr_conf.lsc != 0) {
1235                 /* Registering LSC interrupt handler */
1236                 rte_intr_callback_register(intr_handle,
1237                                            dpaa2_interrupt_handler,
1238                                            (void *)dev);
1239
1240                 /* enable vfio intr/eventfd mapping
1241                  * Interrupt index 0 is required, so we can not use
1242                  * rte_intr_enable.
1243                  */
1244                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1245
1246                 /* enable dpni_irqs */
1247                 dpaa2_eth_setup_irqs(dev, 1);
1248         }
1249
1250         /* Change the tx burst function if ordered queues are used */
1251         if (priv->en_ordered)
1252                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1253
1254         return 0;
1255 }
1256
1257 /**
1258  *  This routine disables all traffic on the adapter by issuing a
1259  *  global reset on the MAC.
1260  */
1261 static int
1262 dpaa2_dev_stop(struct rte_eth_dev *dev)
1263 {
1264         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1265         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1266         int ret;
1267         struct rte_eth_link link;
1268         struct rte_device *rdev = dev->device;
1269         struct rte_intr_handle *intr_handle;
1270         struct rte_dpaa2_device *dpaa2_dev;
1271
1272         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1273         intr_handle = dpaa2_dev->intr_handle;
1274
1275         PMD_INIT_FUNC_TRACE();
1276
1277         /* reset interrupt callback  */
1278         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1279             dev->data->dev_conf.intr_conf.lsc != 0) {
1280                 /*disable dpni irqs */
1281                 dpaa2_eth_setup_irqs(dev, 0);
1282
1283                 /* disable vfio intr before callback unregister */
1284                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1285
1286                 /* Unregistering LSC interrupt handler */
1287                 rte_intr_callback_unregister(intr_handle,
1288                                              dpaa2_interrupt_handler,
1289                                              (void *)dev);
1290         }
1291
1292         dpaa2_dev_set_link_down(dev);
1293
1294         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1295         if (ret) {
1296                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1297                               ret, priv->hw_id);
1298                 return ret;
1299         }
1300
1301         /* clear the recorded link status */
1302         memset(&link, 0, sizeof(link));
1303         rte_eth_linkstatus_set(dev, &link);
1304
1305         return 0;
1306 }
1307
1308 static int
1309 dpaa2_dev_close(struct rte_eth_dev *dev)
1310 {
1311         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1312         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1313         int i, ret;
1314         struct rte_eth_link link;
1315
1316         PMD_INIT_FUNC_TRACE();
1317
1318         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1319                 return 0;
1320
1321         if (!dpni) {
1322                 DPAA2_PMD_WARN("Already closed or not started");
1323                 return -1;
1324         }
1325
1326         dpaa2_tm_deinit(dev);
1327         dpaa2_flow_clean(dev);
1328         /* Clean the device first */
1329         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1330         if (ret) {
1331                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1332                 return -1;
1333         }
1334
1335         memset(&link, 0, sizeof(link));
1336         rte_eth_linkstatus_set(dev, &link);
1337
1338         /* Free private queues memory */
1339         dpaa2_free_rx_tx_queues(dev);
1340         /* Close the device at underlying layer*/
1341         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1342         if (ret) {
1343                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1344                               ret);
1345         }
1346
1347         /* Free the allocated memory for ethernet private data and dpni*/
1348         priv->hw = NULL;
1349         dev->process_private = NULL;
1350         rte_free(dpni);
1351
1352         for (i = 0; i < MAX_TCS; i++)
1353                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1354
1355         if (priv->extract.qos_extract_param)
1356                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1357
1358         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1359         return 0;
1360 }
1361
1362 static int
1363 dpaa2_dev_promiscuous_enable(
1364                 struct rte_eth_dev *dev)
1365 {
1366         int ret;
1367         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1368         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1369
1370         PMD_INIT_FUNC_TRACE();
1371
1372         if (dpni == NULL) {
1373                 DPAA2_PMD_ERR("dpni is NULL");
1374                 return -ENODEV;
1375         }
1376
1377         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1378         if (ret < 0)
1379                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1380
1381         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1382         if (ret < 0)
1383                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1384
1385         return ret;
1386 }
1387
1388 static int
1389 dpaa2_dev_promiscuous_disable(
1390                 struct rte_eth_dev *dev)
1391 {
1392         int ret;
1393         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1394         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1395
1396         PMD_INIT_FUNC_TRACE();
1397
1398         if (dpni == NULL) {
1399                 DPAA2_PMD_ERR("dpni is NULL");
1400                 return -ENODEV;
1401         }
1402
1403         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1404         if (ret < 0)
1405                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1406
1407         if (dev->data->all_multicast == 0) {
1408                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1409                                                  priv->token, false);
1410                 if (ret < 0)
1411                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1412                                       ret);
1413         }
1414
1415         return ret;
1416 }
1417
1418 static int
1419 dpaa2_dev_allmulticast_enable(
1420                 struct rte_eth_dev *dev)
1421 {
1422         int ret;
1423         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1424         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1425
1426         PMD_INIT_FUNC_TRACE();
1427
1428         if (dpni == NULL) {
1429                 DPAA2_PMD_ERR("dpni is NULL");
1430                 return -ENODEV;
1431         }
1432
1433         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1434         if (ret < 0)
1435                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1436
1437         return ret;
1438 }
1439
1440 static int
1441 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1442 {
1443         int ret;
1444         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1445         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1446
1447         PMD_INIT_FUNC_TRACE();
1448
1449         if (dpni == NULL) {
1450                 DPAA2_PMD_ERR("dpni is NULL");
1451                 return -ENODEV;
1452         }
1453
1454         /* must remain on for all promiscuous */
1455         if (dev->data->promiscuous == 1)
1456                 return 0;
1457
1458         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1459         if (ret < 0)
1460                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1461
1462         return ret;
1463 }
1464
1465 static int
1466 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1467 {
1468         int ret;
1469         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1470         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1471         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1472                                 + VLAN_TAG_SIZE;
1473
1474         PMD_INIT_FUNC_TRACE();
1475
1476         if (dpni == NULL) {
1477                 DPAA2_PMD_ERR("dpni is NULL");
1478                 return -EINVAL;
1479         }
1480
1481         /* Set the Max Rx frame length as 'mtu' +
1482          * Maximum Ethernet header length
1483          */
1484         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1485                                         frame_size - RTE_ETHER_CRC_LEN);
1486         if (ret) {
1487                 DPAA2_PMD_ERR("Setting the max frame length failed");
1488                 return -1;
1489         }
1490         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1491         return 0;
1492 }
1493
1494 static int
1495 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1496                        struct rte_ether_addr *addr,
1497                        __rte_unused uint32_t index,
1498                        __rte_unused uint32_t pool)
1499 {
1500         int ret;
1501         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1502         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1503
1504         PMD_INIT_FUNC_TRACE();
1505
1506         if (dpni == NULL) {
1507                 DPAA2_PMD_ERR("dpni is NULL");
1508                 return -1;
1509         }
1510
1511         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1512                                 addr->addr_bytes, 0, 0, 0);
1513         if (ret)
1514                 DPAA2_PMD_ERR(
1515                         "error: Adding the MAC ADDR failed: err = %d", ret);
1516         return 0;
1517 }
1518
1519 static void
1520 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1521                           uint32_t index)
1522 {
1523         int ret;
1524         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1525         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1526         struct rte_eth_dev_data *data = dev->data;
1527         struct rte_ether_addr *macaddr;
1528
1529         PMD_INIT_FUNC_TRACE();
1530
1531         macaddr = &data->mac_addrs[index];
1532
1533         if (dpni == NULL) {
1534                 DPAA2_PMD_ERR("dpni is NULL");
1535                 return;
1536         }
1537
1538         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1539                                    priv->token, macaddr->addr_bytes);
1540         if (ret)
1541                 DPAA2_PMD_ERR(
1542                         "error: Removing the MAC ADDR failed: err = %d", ret);
1543 }
1544
1545 static int
1546 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1547                        struct rte_ether_addr *addr)
1548 {
1549         int ret;
1550         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1551         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1552
1553         PMD_INIT_FUNC_TRACE();
1554
1555         if (dpni == NULL) {
1556                 DPAA2_PMD_ERR("dpni is NULL");
1557                 return -EINVAL;
1558         }
1559
1560         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1561                                         priv->token, addr->addr_bytes);
1562
1563         if (ret)
1564                 DPAA2_PMD_ERR(
1565                         "error: Setting the MAC ADDR failed %d", ret);
1566
1567         return ret;
1568 }
1569
1570 static
1571 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1572                          struct rte_eth_stats *stats)
1573 {
1574         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1575         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1576         int32_t  retcode;
1577         uint8_t page0 = 0, page1 = 1, page2 = 2;
1578         union dpni_statistics value;
1579         int i;
1580         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1581
1582         memset(&value, 0, sizeof(union dpni_statistics));
1583
1584         PMD_INIT_FUNC_TRACE();
1585
1586         if (!dpni) {
1587                 DPAA2_PMD_ERR("dpni is NULL");
1588                 return -EINVAL;
1589         }
1590
1591         if (!stats) {
1592                 DPAA2_PMD_ERR("stats is NULL");
1593                 return -EINVAL;
1594         }
1595
1596         /*Get Counters from page_0*/
1597         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1598                                       page0, 0, &value);
1599         if (retcode)
1600                 goto err;
1601
1602         stats->ipackets = value.page_0.ingress_all_frames;
1603         stats->ibytes = value.page_0.ingress_all_bytes;
1604
1605         /*Get Counters from page_1*/
1606         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1607                                       page1, 0, &value);
1608         if (retcode)
1609                 goto err;
1610
1611         stats->opackets = value.page_1.egress_all_frames;
1612         stats->obytes = value.page_1.egress_all_bytes;
1613
1614         /*Get Counters from page_2*/
1615         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1616                                       page2, 0, &value);
1617         if (retcode)
1618                 goto err;
1619
1620         /* Ingress drop frame count due to configured rules */
1621         stats->ierrors = value.page_2.ingress_filtered_frames;
1622         /* Ingress drop frame count due to error */
1623         stats->ierrors += value.page_2.ingress_discarded_frames;
1624
1625         stats->oerrors = value.page_2.egress_discarded_frames;
1626         stats->imissed = value.page_2.ingress_nobuffer_discards;
1627
1628         /* Fill in per queue stats */
1629         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1630                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1631                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1632                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1633                 if (dpaa2_rxq)
1634                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1635                 if (dpaa2_txq)
1636                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1637
1638                 /* Byte counting is not implemented */
1639                 stats->q_ibytes[i]   = 0;
1640                 stats->q_obytes[i]   = 0;
1641         }
1642
1643         return 0;
1644
1645 err:
1646         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1647         return retcode;
1648 };
1649
1650 static int
1651 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1652                      unsigned int n)
1653 {
1654         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1655         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1656         int32_t  retcode;
1657         union dpni_statistics value[5] = {};
1658         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1659
1660         if (n < num)
1661                 return num;
1662
1663         if (xstats == NULL)
1664                 return 0;
1665
1666         /* Get Counters from page_0*/
1667         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1668                                       0, 0, &value[0]);
1669         if (retcode)
1670                 goto err;
1671
1672         /* Get Counters from page_1*/
1673         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1674                                       1, 0, &value[1]);
1675         if (retcode)
1676                 goto err;
1677
1678         /* Get Counters from page_2*/
1679         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1680                                       2, 0, &value[2]);
1681         if (retcode)
1682                 goto err;
1683
1684         for (i = 0; i < priv->max_cgs; i++) {
1685                 if (!priv->cgid_in_use[i]) {
1686                         /* Get Counters from page_4*/
1687                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1688                                                       priv->token,
1689                                                       4, 0, &value[4]);
1690                         if (retcode)
1691                                 goto err;
1692                         break;
1693                 }
1694         }
1695
1696         for (i = 0; i < num; i++) {
1697                 xstats[i].id = i;
1698                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1699                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1700         }
1701         return i;
1702 err:
1703         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1704         return retcode;
1705 }
1706
1707 static int
1708 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1709                        struct rte_eth_xstat_name *xstats_names,
1710                        unsigned int limit)
1711 {
1712         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1713
1714         if (limit < stat_cnt)
1715                 return stat_cnt;
1716
1717         if (xstats_names != NULL)
1718                 for (i = 0; i < stat_cnt; i++)
1719                         strlcpy(xstats_names[i].name,
1720                                 dpaa2_xstats_strings[i].name,
1721                                 sizeof(xstats_names[i].name));
1722
1723         return stat_cnt;
1724 }
1725
1726 static int
1727 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1728                        uint64_t *values, unsigned int n)
1729 {
1730         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1731         uint64_t values_copy[stat_cnt];
1732
1733         if (!ids) {
1734                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1735                 struct fsl_mc_io *dpni =
1736                         (struct fsl_mc_io *)dev->process_private;
1737                 int32_t  retcode;
1738                 union dpni_statistics value[5] = {};
1739
1740                 if (n < stat_cnt)
1741                         return stat_cnt;
1742
1743                 if (!values)
1744                         return 0;
1745
1746                 /* Get Counters from page_0*/
1747                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1748                                               0, 0, &value[0]);
1749                 if (retcode)
1750                         return 0;
1751
1752                 /* Get Counters from page_1*/
1753                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1754                                               1, 0, &value[1]);
1755                 if (retcode)
1756                         return 0;
1757
1758                 /* Get Counters from page_2*/
1759                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1760                                               2, 0, &value[2]);
1761                 if (retcode)
1762                         return 0;
1763
1764                 /* Get Counters from page_4*/
1765                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1766                                               4, 0, &value[4]);
1767                 if (retcode)
1768                         return 0;
1769
1770                 for (i = 0; i < stat_cnt; i++) {
1771                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1772                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1773                 }
1774                 return stat_cnt;
1775         }
1776
1777         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1778
1779         for (i = 0; i < n; i++) {
1780                 if (ids[i] >= stat_cnt) {
1781                         DPAA2_PMD_ERR("xstats id value isn't valid");
1782                         return -1;
1783                 }
1784                 values[i] = values_copy[ids[i]];
1785         }
1786         return n;
1787 }
1788
1789 static int
1790 dpaa2_xstats_get_names_by_id(
1791         struct rte_eth_dev *dev,
1792         const uint64_t *ids,
1793         struct rte_eth_xstat_name *xstats_names,
1794         unsigned int limit)
1795 {
1796         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1797         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1798
1799         if (!ids)
1800                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1801
1802         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1803
1804         for (i = 0; i < limit; i++) {
1805                 if (ids[i] >= stat_cnt) {
1806                         DPAA2_PMD_ERR("xstats id value isn't valid");
1807                         return -1;
1808                 }
1809                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1810         }
1811         return limit;
1812 }
1813
1814 static int
1815 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1816 {
1817         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1818         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1819         int retcode;
1820         int i;
1821         struct dpaa2_queue *dpaa2_q;
1822
1823         PMD_INIT_FUNC_TRACE();
1824
1825         if (dpni == NULL) {
1826                 DPAA2_PMD_ERR("dpni is NULL");
1827                 return -EINVAL;
1828         }
1829
1830         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1831         if (retcode)
1832                 goto error;
1833
1834         /* Reset the per queue stats in dpaa2_queue structure */
1835         for (i = 0; i < priv->nb_rx_queues; i++) {
1836                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1837                 if (dpaa2_q)
1838                         dpaa2_q->rx_pkts = 0;
1839         }
1840
1841         for (i = 0; i < priv->nb_tx_queues; i++) {
1842                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1843                 if (dpaa2_q)
1844                         dpaa2_q->tx_pkts = 0;
1845         }
1846
1847         return 0;
1848
1849 error:
1850         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1851         return retcode;
1852 };
1853
1854 /* return 0 means link status changed, -1 means not changed */
1855 static int
1856 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1857                       int wait_to_complete)
1858 {
1859         int ret;
1860         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1861         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1862         struct rte_eth_link link;
1863         struct dpni_link_state state = {0};
1864         uint8_t count;
1865
1866         if (dpni == NULL) {
1867                 DPAA2_PMD_ERR("dpni is NULL");
1868                 return 0;
1869         }
1870
1871         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1872                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1873                                           &state);
1874                 if (ret < 0) {
1875                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1876                         return -1;
1877                 }
1878                 if (state.up == RTE_ETH_LINK_DOWN &&
1879                     wait_to_complete)
1880                         rte_delay_ms(CHECK_INTERVAL);
1881                 else
1882                         break;
1883         }
1884
1885         memset(&link, 0, sizeof(struct rte_eth_link));
1886         link.link_status = state.up;
1887         link.link_speed = state.rate;
1888
1889         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1890                 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
1891         else
1892                 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1893
1894         ret = rte_eth_linkstatus_set(dev, &link);
1895         if (ret == -1)
1896                 DPAA2_PMD_DEBUG("No change in status");
1897         else
1898                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1899                                link.link_status ? "Up" : "Down");
1900
1901         return ret;
1902 }
1903
1904 /**
1905  * Toggle the DPNI to enable, if not already enabled.
1906  * This is not strictly PHY up/down - it is more of logical toggling.
1907  */
1908 static int
1909 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1910 {
1911         int ret = -EINVAL;
1912         struct dpaa2_dev_priv *priv;
1913         struct fsl_mc_io *dpni;
1914         int en = 0;
1915         struct dpni_link_state state = {0};
1916
1917         priv = dev->data->dev_private;
1918         dpni = (struct fsl_mc_io *)dev->process_private;
1919
1920         if (dpni == NULL) {
1921                 DPAA2_PMD_ERR("dpni is NULL");
1922                 return ret;
1923         }
1924
1925         /* Check if DPNI is currently enabled */
1926         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1927         if (ret) {
1928                 /* Unable to obtain dpni status; Not continuing */
1929                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1930                 return -EINVAL;
1931         }
1932
1933         /* Enable link if not already enabled */
1934         if (!en) {
1935                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1936                 if (ret) {
1937                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1938                         return -EINVAL;
1939                 }
1940         }
1941         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1942         if (ret < 0) {
1943                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1944                 return -1;
1945         }
1946
1947         /* changing tx burst function to start enqueues */
1948         dev->tx_pkt_burst = dpaa2_dev_tx;
1949         dev->data->dev_link.link_status = state.up;
1950         dev->data->dev_link.link_speed = state.rate;
1951
1952         if (state.up)
1953                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1954         else
1955                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1956         return ret;
1957 }
1958
1959 /**
1960  * Toggle the DPNI to disable, if not already disabled.
1961  * This is not strictly PHY up/down - it is more of logical toggling.
1962  */
1963 static int
1964 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1965 {
1966         int ret = -EINVAL;
1967         struct dpaa2_dev_priv *priv;
1968         struct fsl_mc_io *dpni;
1969         int dpni_enabled = 0;
1970         int retries = 10;
1971
1972         PMD_INIT_FUNC_TRACE();
1973
1974         priv = dev->data->dev_private;
1975         dpni = (struct fsl_mc_io *)dev->process_private;
1976
1977         if (dpni == NULL) {
1978                 DPAA2_PMD_ERR("Device has not yet been configured");
1979                 return ret;
1980         }
1981
1982         /*changing  tx burst function to avoid any more enqueues */
1983         dev->tx_pkt_burst = dummy_dev_tx;
1984
1985         /* Loop while dpni_disable() attempts to drain the egress FQs
1986          * and confirm them back to us.
1987          */
1988         do {
1989                 ret = dpni_disable(dpni, 0, priv->token);
1990                 if (ret) {
1991                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1992                         return ret;
1993                 }
1994                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1995                 if (ret) {
1996                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1997                         return ret;
1998                 }
1999                 if (dpni_enabled)
2000                         /* Allow the MC some slack */
2001                         rte_delay_us(100 * 1000);
2002         } while (dpni_enabled && --retries);
2003
2004         if (!retries) {
2005                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2006                 /* todo- we may have to manually cleanup queues.
2007                  */
2008         } else {
2009                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2010                                dev->data->port_id);
2011         }
2012
2013         dev->data->dev_link.link_status = 0;
2014
2015         return ret;
2016 }
2017
2018 static int
2019 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2020 {
2021         int ret = -EINVAL;
2022         struct dpaa2_dev_priv *priv;
2023         struct fsl_mc_io *dpni;
2024         struct dpni_link_state state = {0};
2025
2026         PMD_INIT_FUNC_TRACE();
2027
2028         priv = dev->data->dev_private;
2029         dpni = (struct fsl_mc_io *)dev->process_private;
2030
2031         if (dpni == NULL || fc_conf == NULL) {
2032                 DPAA2_PMD_ERR("device not configured");
2033                 return ret;
2034         }
2035
2036         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2037         if (ret) {
2038                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2039                 return ret;
2040         }
2041
2042         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2043         if (state.options & DPNI_LINK_OPT_PAUSE) {
2044                 /* DPNI_LINK_OPT_PAUSE set
2045                  *  if ASYM_PAUSE not set,
2046                  *      RX Side flow control (handle received Pause frame)
2047                  *      TX side flow control (send Pause frame)
2048                  *  if ASYM_PAUSE set,
2049                  *      RX Side flow control (handle received Pause frame)
2050                  *      No TX side flow control (send Pause frame disabled)
2051                  */
2052                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2053                         fc_conf->mode = RTE_ETH_FC_FULL;
2054                 else
2055                         fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2056         } else {
2057                 /* DPNI_LINK_OPT_PAUSE not set
2058                  *  if ASYM_PAUSE set,
2059                  *      TX side flow control (send Pause frame)
2060                  *      No RX side flow control (No action on pause frame rx)
2061                  *  if ASYM_PAUSE not set,
2062                  *      Flow control disabled
2063                  */
2064                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2065                         fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2066                 else
2067                         fc_conf->mode = RTE_ETH_FC_NONE;
2068         }
2069
2070         return ret;
2071 }
2072
2073 static int
2074 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2075 {
2076         int ret = -EINVAL;
2077         struct dpaa2_dev_priv *priv;
2078         struct fsl_mc_io *dpni;
2079         struct dpni_link_state state = {0};
2080         struct dpni_link_cfg cfg = {0};
2081
2082         PMD_INIT_FUNC_TRACE();
2083
2084         priv = dev->data->dev_private;
2085         dpni = (struct fsl_mc_io *)dev->process_private;
2086
2087         if (dpni == NULL) {
2088                 DPAA2_PMD_ERR("dpni is NULL");
2089                 return ret;
2090         }
2091
2092         /* It is necessary to obtain the current state before setting fc_conf
2093          * as MC would return error in case rate, autoneg or duplex values are
2094          * different.
2095          */
2096         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2097         if (ret) {
2098                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2099                 return -1;
2100         }
2101
2102         /* Disable link before setting configuration */
2103         dpaa2_dev_set_link_down(dev);
2104
2105         /* Based on fc_conf, update cfg */
2106         cfg.rate = state.rate;
2107         cfg.options = state.options;
2108
2109         /* update cfg with fc_conf */
2110         switch (fc_conf->mode) {
2111         case RTE_ETH_FC_FULL:
2112                 /* Full flow control;
2113                  * OPT_PAUSE set, ASYM_PAUSE not set
2114                  */
2115                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2116                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2117                 break;
2118         case RTE_ETH_FC_TX_PAUSE:
2119                 /* Enable RX flow control
2120                  * OPT_PAUSE not set;
2121                  * ASYM_PAUSE set;
2122                  */
2123                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2124                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2125                 break;
2126         case RTE_ETH_FC_RX_PAUSE:
2127                 /* Enable TX Flow control
2128                  * OPT_PAUSE set
2129                  * ASYM_PAUSE set
2130                  */
2131                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2132                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2133                 break;
2134         case RTE_ETH_FC_NONE:
2135                 /* Disable Flow control
2136                  * OPT_PAUSE not set
2137                  * ASYM_PAUSE not set
2138                  */
2139                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2140                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2141                 break;
2142         default:
2143                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2144                               fc_conf->mode);
2145                 return -1;
2146         }
2147
2148         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2149         if (ret)
2150                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2151                               ret);
2152
2153         /* Enable link */
2154         dpaa2_dev_set_link_up(dev);
2155
2156         return ret;
2157 }
2158
2159 static int
2160 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2161                           struct rte_eth_rss_conf *rss_conf)
2162 {
2163         struct rte_eth_dev_data *data = dev->data;
2164         struct dpaa2_dev_priv *priv = data->dev_private;
2165         struct rte_eth_conf *eth_conf = &data->dev_conf;
2166         int ret, tc_index;
2167
2168         PMD_INIT_FUNC_TRACE();
2169
2170         if (rss_conf->rss_hf) {
2171                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2172                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2173                                 tc_index);
2174                         if (ret) {
2175                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2176                                         tc_index);
2177                                 return ret;
2178                         }
2179                 }
2180         } else {
2181                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2182                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2183                         if (ret) {
2184                                 DPAA2_PMD_ERR(
2185                                         "Unable to remove flow dist on tc%d",
2186                                         tc_index);
2187                                 return ret;
2188                         }
2189                 }
2190         }
2191         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2192         return 0;
2193 }
2194
2195 static int
2196 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2197                             struct rte_eth_rss_conf *rss_conf)
2198 {
2199         struct rte_eth_dev_data *data = dev->data;
2200         struct rte_eth_conf *eth_conf = &data->dev_conf;
2201
2202         /* dpaa2 does not support rss_key, so length should be 0*/
2203         rss_conf->rss_key_len = 0;
2204         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2205         return 0;
2206 }
2207
2208 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2209                 int eth_rx_queue_id,
2210                 struct dpaa2_dpcon_dev *dpcon,
2211                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2212 {
2213         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2214         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2215         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2216         uint8_t flow_id = dpaa2_ethq->flow_id;
2217         struct dpni_queue cfg;
2218         uint8_t options, priority;
2219         int ret;
2220
2221         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2222                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2223         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2224                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2225         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2226                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2227         else
2228                 return -EINVAL;
2229
2230         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2231                    (dpcon->num_priorities - 1);
2232
2233         memset(&cfg, 0, sizeof(struct dpni_queue));
2234         options = DPNI_QUEUE_OPT_DEST;
2235         cfg.destination.type = DPNI_DEST_DPCON;
2236         cfg.destination.id = dpcon->dpcon_id;
2237         cfg.destination.priority = priority;
2238
2239         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2240                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2241                 cfg.destination.hold_active = 1;
2242         }
2243
2244         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2245                         !eth_priv->en_ordered) {
2246                 struct opr_cfg ocfg;
2247
2248                 /* Restoration window size = 256 frames */
2249                 ocfg.oprrws = 3;
2250                 /* Restoration window size = 512 frames for LX2 */
2251                 if (dpaa2_svr_family == SVR_LX2160A)
2252                         ocfg.oprrws = 4;
2253                 /* Auto advance NESN window enabled */
2254                 ocfg.oa = 1;
2255                 /* Late arrival window size disabled */
2256                 ocfg.olws = 0;
2257                 /* ORL resource exhaustion advance NESN disabled */
2258                 ocfg.oeane = 0;
2259                 /* Loose ordering enabled */
2260                 ocfg.oloe = 1;
2261                 eth_priv->en_loose_ordered = 1;
2262                 /* Strict ordering enabled if explicitly set */
2263                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2264                         ocfg.oloe = 0;
2265                         eth_priv->en_loose_ordered = 0;
2266                 }
2267
2268                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2269                                    dpaa2_ethq->tc_index, flow_id,
2270                                    OPR_OPT_CREATE, &ocfg, 0);
2271                 if (ret) {
2272                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2273                         return ret;
2274                 }
2275
2276                 eth_priv->en_ordered = 1;
2277         }
2278
2279         options |= DPNI_QUEUE_OPT_USER_CTX;
2280         cfg.user_context = (size_t)(dpaa2_ethq);
2281
2282         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2283                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2284         if (ret) {
2285                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2286                 return ret;
2287         }
2288
2289         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2290
2291         return 0;
2292 }
2293
2294 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2295                 int eth_rx_queue_id)
2296 {
2297         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2298         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2299         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2300         uint8_t flow_id = dpaa2_ethq->flow_id;
2301         struct dpni_queue cfg;
2302         uint8_t options;
2303         int ret;
2304
2305         memset(&cfg, 0, sizeof(struct dpni_queue));
2306         options = DPNI_QUEUE_OPT_DEST;
2307         cfg.destination.type = DPNI_DEST_NONE;
2308
2309         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2310                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2311         if (ret)
2312                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2313
2314         return ret;
2315 }
2316
2317 static int
2318 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2319                        const struct rte_flow_ops **ops)
2320 {
2321         if (!dev)
2322                 return -ENODEV;
2323
2324         *ops = &dpaa2_flow_ops;
2325         return 0;
2326 }
2327
2328 static void
2329 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2330         struct rte_eth_rxq_info *qinfo)
2331 {
2332         struct dpaa2_queue *rxq;
2333         struct dpaa2_dev_priv *priv = dev->data->dev_private;
2334         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2335         uint16_t max_frame_length;
2336
2337         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2338
2339         qinfo->mp = rxq->mb_pool;
2340         qinfo->scattered_rx = dev->data->scattered_rx;
2341         qinfo->nb_desc = rxq->nb_desc;
2342         if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2343                                 &max_frame_length) == 0)
2344                 qinfo->rx_buf_size = max_frame_length;
2345
2346         qinfo->conf.rx_free_thresh = 1;
2347         qinfo->conf.rx_drop_en = 1;
2348         qinfo->conf.rx_deferred_start = 0;
2349         qinfo->conf.offloads = rxq->offloads;
2350 }
2351
2352 static void
2353 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2354         struct rte_eth_txq_info *qinfo)
2355 {
2356         struct dpaa2_queue *txq;
2357
2358         txq = dev->data->tx_queues[queue_id];
2359
2360         qinfo->nb_desc = txq->nb_desc;
2361         qinfo->conf.tx_thresh.pthresh = 0;
2362         qinfo->conf.tx_thresh.hthresh = 0;
2363         qinfo->conf.tx_thresh.wthresh = 0;
2364
2365         qinfo->conf.tx_free_thresh = 0;
2366         qinfo->conf.tx_rs_thresh = 0;
2367         qinfo->conf.offloads = txq->offloads;
2368         qinfo->conf.tx_deferred_start = 0;
2369 }
2370
2371 static int
2372 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2373 {
2374         *(const void **)ops = &dpaa2_tm_ops;
2375
2376         return 0;
2377 }
2378
2379 void
2380 rte_pmd_dpaa2_thread_init(void)
2381 {
2382         int ret;
2383
2384         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2385                 ret = dpaa2_affine_qbman_swp();
2386                 if (ret) {
2387                         DPAA2_PMD_ERR(
2388                                 "Failed to allocate IO portal, tid: %d\n",
2389                                 rte_gettid());
2390                         return;
2391                 }
2392         }
2393 }
2394
2395 static struct eth_dev_ops dpaa2_ethdev_ops = {
2396         .dev_configure    = dpaa2_eth_dev_configure,
2397         .dev_start            = dpaa2_dev_start,
2398         .dev_stop             = dpaa2_dev_stop,
2399         .dev_close            = dpaa2_dev_close,
2400         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2401         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2402         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2403         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2404         .dev_set_link_up      = dpaa2_dev_set_link_up,
2405         .dev_set_link_down    = dpaa2_dev_set_link_down,
2406         .link_update       = dpaa2_dev_link_update,
2407         .stats_get             = dpaa2_dev_stats_get,
2408         .xstats_get            = dpaa2_dev_xstats_get,
2409         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2410         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2411         .xstats_get_names      = dpaa2_xstats_get_names,
2412         .stats_reset       = dpaa2_dev_stats_reset,
2413         .xstats_reset         = dpaa2_dev_stats_reset,
2414         .fw_version_get    = dpaa2_fw_version_get,
2415         .dev_infos_get     = dpaa2_dev_info_get,
2416         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2417         .mtu_set           = dpaa2_dev_mtu_set,
2418         .vlan_filter_set      = dpaa2_vlan_filter_set,
2419         .vlan_offload_set     = dpaa2_vlan_offload_set,
2420         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2421         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2422         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2423         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2424         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2425         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2426         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2427         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2428         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2429         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2430         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2431         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2432         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2433         .flow_ops_get         = dpaa2_dev_flow_ops_get,
2434         .rxq_info_get         = dpaa2_rxq_info_get,
2435         .txq_info_get         = dpaa2_txq_info_get,
2436         .tm_ops_get           = dpaa2_tm_ops_get,
2437 #if defined(RTE_LIBRTE_IEEE1588)
2438         .timesync_enable      = dpaa2_timesync_enable,
2439         .timesync_disable     = dpaa2_timesync_disable,
2440         .timesync_read_time   = dpaa2_timesync_read_time,
2441         .timesync_write_time  = dpaa2_timesync_write_time,
2442         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2443         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2444         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2445 #endif
2446 };
2447
2448 /* Populate the mac address from physically available (u-boot/firmware) and/or
2449  * one set by higher layers like MC (restool) etc.
2450  * Returns the table of MAC entries (multiple entries)
2451  */
2452 static int
2453 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2454                   struct rte_ether_addr *mac_entry)
2455 {
2456         int ret;
2457         struct rte_ether_addr phy_mac, prime_mac;
2458
2459         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2460         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2461
2462         /* Get the physical device MAC address */
2463         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2464                                      phy_mac.addr_bytes);
2465         if (ret) {
2466                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2467                 goto cleanup;
2468         }
2469
2470         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2471                                         prime_mac.addr_bytes);
2472         if (ret) {
2473                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2474                 goto cleanup;
2475         }
2476
2477         /* Now that both MAC have been obtained, do:
2478          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2479          *     and return phy
2480          *  If empty_mac(phy), return prime.
2481          *  if both are empty, create random MAC, set as prime and return
2482          */
2483         if (!rte_is_zero_ether_addr(&phy_mac)) {
2484                 /* If the addresses are not same, overwrite prime */
2485                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2486                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2487                                                         priv->token,
2488                                                         phy_mac.addr_bytes);
2489                         if (ret) {
2490                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2491                                               ret);
2492                                 goto cleanup;
2493                         }
2494                         memcpy(&prime_mac, &phy_mac,
2495                                 sizeof(struct rte_ether_addr));
2496                 }
2497         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2498                 /* In case phys and prime, both are zero, create random MAC */
2499                 rte_eth_random_addr(prime_mac.addr_bytes);
2500                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2501                                                 priv->token,
2502                                                 prime_mac.addr_bytes);
2503                 if (ret) {
2504                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2505                         goto cleanup;
2506                 }
2507         }
2508
2509         /* prime_mac the final MAC address */
2510         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2511         return 0;
2512
2513 cleanup:
2514         return -1;
2515 }
2516
2517 static int
2518 check_devargs_handler(__rte_unused const char *key, const char *value,
2519                       __rte_unused void *opaque)
2520 {
2521         if (strcmp(value, "1"))
2522                 return -1;
2523
2524         return 0;
2525 }
2526
2527 static int
2528 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2529 {
2530         struct rte_kvargs *kvlist;
2531
2532         if (!devargs)
2533                 return 0;
2534
2535         kvlist = rte_kvargs_parse(devargs->args, NULL);
2536         if (!kvlist)
2537                 return 0;
2538
2539         if (!rte_kvargs_count(kvlist, key)) {
2540                 rte_kvargs_free(kvlist);
2541                 return 0;
2542         }
2543
2544         if (rte_kvargs_process(kvlist, key,
2545                                check_devargs_handler, NULL) < 0) {
2546                 rte_kvargs_free(kvlist);
2547                 return 0;
2548         }
2549         rte_kvargs_free(kvlist);
2550
2551         return 1;
2552 }
2553
2554 static int
2555 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2556 {
2557         struct rte_device *dev = eth_dev->device;
2558         struct rte_dpaa2_device *dpaa2_dev;
2559         struct fsl_mc_io *dpni_dev;
2560         struct dpni_attr attr;
2561         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2562         struct dpni_buffer_layout layout;
2563         int ret, hw_id, i;
2564
2565         PMD_INIT_FUNC_TRACE();
2566
2567         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2568         if (!dpni_dev) {
2569                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2570                 return -1;
2571         }
2572         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2573         eth_dev->process_private = (void *)dpni_dev;
2574
2575         /* For secondary processes, the primary has done all the work */
2576         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2577                 /* In case of secondary, only burst and ops API need to be
2578                  * plugged.
2579                  */
2580                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2581                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2582                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2583                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2584                 else if (dpaa2_get_devargs(dev->devargs,
2585                                         DRIVER_NO_PREFETCH_MODE))
2586                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2587                 else
2588                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2589                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2590                 return 0;
2591         }
2592
2593         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2594
2595         hw_id = dpaa2_dev->object_id;
2596         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2597         if (ret) {
2598                 DPAA2_PMD_ERR(
2599                              "Failure in opening dpni@%d with err code %d",
2600                              hw_id, ret);
2601                 rte_free(dpni_dev);
2602                 return -1;
2603         }
2604
2605         /* Clean the device first */
2606         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2607         if (ret) {
2608                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2609                               hw_id, ret);
2610                 goto init_err;
2611         }
2612
2613         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2614         if (ret) {
2615                 DPAA2_PMD_ERR(
2616                              "Failure in get dpni@%d attribute, err code %d",
2617                              hw_id, ret);
2618                 goto init_err;
2619         }
2620
2621         priv->num_rx_tc = attr.num_rx_tcs;
2622         priv->qos_entries = attr.qos_entries;
2623         priv->fs_entries = attr.fs_entries;
2624         priv->dist_queues = attr.num_queues;
2625
2626         /* only if the custom CG is enabled */
2627         if (attr.options & DPNI_OPT_CUSTOM_CG)
2628                 priv->max_cgs = attr.num_cgs;
2629         else
2630                 priv->max_cgs = 0;
2631
2632         for (i = 0; i < priv->max_cgs; i++)
2633                 priv->cgid_in_use[i] = 0;
2634
2635         for (i = 0; i < attr.num_rx_tcs; i++)
2636                 priv->nb_rx_queues += attr.num_queues;
2637
2638         /* Using number of TX queues as number of TX TCs */
2639         priv->nb_tx_queues = attr.num_tx_tcs;
2640
2641         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2642                         priv->num_rx_tc, priv->nb_rx_queues,
2643                         priv->nb_tx_queues, priv->max_cgs);
2644
2645         priv->hw = dpni_dev;
2646         priv->hw_id = hw_id;
2647         priv->options = attr.options;
2648         priv->max_mac_filters = attr.mac_filter_entries;
2649         priv->max_vlan_filters = attr.vlan_filter_entries;
2650         priv->flags = 0;
2651 #if defined(RTE_LIBRTE_IEEE1588)
2652         printf("DPDK IEEE1588 is enabled\n");
2653         priv->flags |= DPAA2_TX_CONF_ENABLE;
2654 #endif
2655         /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2656         if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2657                 priv->flags |= DPAA2_TX_CONF_ENABLE;
2658                 DPAA2_PMD_INFO("TX_CONF Enabled");
2659         }
2660
2661         if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2662                 dpaa2_enable_err_queue = 1;
2663                 DPAA2_PMD_INFO("Enable error queue");
2664         }
2665
2666         /* Allocate memory for hardware structure for queues */
2667         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2668         if (ret) {
2669                 DPAA2_PMD_ERR("Queue allocation Failed");
2670                 goto init_err;
2671         }
2672
2673         /* Allocate memory for storing MAC addresses.
2674          * Table of mac_filter_entries size is allocated so that RTE ether lib
2675          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2676          */
2677         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2678                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2679         if (eth_dev->data->mac_addrs == NULL) {
2680                 DPAA2_PMD_ERR(
2681                    "Failed to allocate %d bytes needed to store MAC addresses",
2682                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2683                 ret = -ENOMEM;
2684                 goto init_err;
2685         }
2686
2687         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2688         if (ret) {
2689                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2690                 rte_free(eth_dev->data->mac_addrs);
2691                 eth_dev->data->mac_addrs = NULL;
2692                 goto init_err;
2693         }
2694
2695         /* ... tx buffer layout ... */
2696         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2697         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2698                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2699                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2700                 layout.pass_timestamp = true;
2701         } else {
2702                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2703         }
2704         layout.pass_frame_status = 1;
2705         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2706                                      DPNI_QUEUE_TX, &layout);
2707         if (ret) {
2708                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2709                 goto init_err;
2710         }
2711
2712         /* ... tx-conf and error buffer layout ... */
2713         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2714         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2715                 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2716                 layout.pass_timestamp = true;
2717         }
2718         layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2719         layout.pass_frame_status = 1;
2720         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2721                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2722         if (ret) {
2723                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2724                              ret);
2725                 goto init_err;
2726         }
2727
2728         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2729
2730         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2731                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2732                 DPAA2_PMD_INFO("Loopback mode");
2733         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2734                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2735                 DPAA2_PMD_INFO("No Prefetch mode");
2736         } else {
2737                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2738         }
2739         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2740
2741         /* Init fields w.r.t. classification */
2742         memset(&priv->extract.qos_key_extract, 0,
2743                 sizeof(struct dpaa2_key_extract));
2744         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2745         if (!priv->extract.qos_extract_param) {
2746                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2747                             " classification ", ret);
2748                 goto init_err;
2749         }
2750         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2751                 IP_ADDRESS_OFFSET_INVALID;
2752         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2753                 IP_ADDRESS_OFFSET_INVALID;
2754         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2755                 IP_ADDRESS_OFFSET_INVALID;
2756         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2757                 IP_ADDRESS_OFFSET_INVALID;
2758
2759         for (i = 0; i < MAX_TCS; i++) {
2760                 memset(&priv->extract.tc_key_extract[i], 0,
2761                         sizeof(struct dpaa2_key_extract));
2762                 priv->extract.tc_extract_param[i] =
2763                         (size_t)rte_malloc(NULL, 256, 64);
2764                 if (!priv->extract.tc_extract_param[i]) {
2765                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classification",
2766                                      ret);
2767                         goto init_err;
2768                 }
2769                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2770                         IP_ADDRESS_OFFSET_INVALID;
2771                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2772                         IP_ADDRESS_OFFSET_INVALID;
2773                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2774                         IP_ADDRESS_OFFSET_INVALID;
2775                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2776                         IP_ADDRESS_OFFSET_INVALID;
2777         }
2778
2779         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2780                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2781                                         + VLAN_TAG_SIZE);
2782         if (ret) {
2783                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2784                 goto init_err;
2785         }
2786
2787         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2788          * with external entity to receive byte code for software sequence
2789          * and same will be offload to the H/W using MC interface.
2790          * Currently it is assumed that DPAA2 driver has byte code by some
2791          * mean and same if offloaded to H/W.
2792          */
2793         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2794                 WRIOP_SS_INITIALIZER(priv);
2795                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2796                 if (ret < 0) {
2797                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2798                                       ret);
2799                         return ret;
2800                 }
2801
2802                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2803                                                          DPNI_SS_INGRESS);
2804                 if (ret < 0) {
2805                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2806                                       ret);
2807                         return ret;
2808                 }
2809         }
2810         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2811         return 0;
2812 init_err:
2813         dpaa2_dev_close(eth_dev);
2814
2815         return ret;
2816 }
2817
2818 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2819 {
2820         return dev->device->driver == &rte_dpaa2_pmd.driver;
2821 }
2822
2823 static int
2824 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2825                 struct rte_dpaa2_device *dpaa2_dev)
2826 {
2827         struct rte_eth_dev *eth_dev;
2828         struct dpaa2_dev_priv *dev_priv;
2829         int diag;
2830
2831         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2832                 RTE_PKTMBUF_HEADROOM) {
2833                 DPAA2_PMD_ERR(
2834                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2835                 RTE_PKTMBUF_HEADROOM,
2836                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2837
2838                 return -1;
2839         }
2840
2841         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2842                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2843                 if (!eth_dev)
2844                         return -ENODEV;
2845                 dev_priv = rte_zmalloc("ethdev private structure",
2846                                        sizeof(struct dpaa2_dev_priv),
2847                                        RTE_CACHE_LINE_SIZE);
2848                 if (dev_priv == NULL) {
2849                         DPAA2_PMD_CRIT(
2850                                 "Unable to allocate memory for private data");
2851                         rte_eth_dev_release_port(eth_dev);
2852                         return -ENOMEM;
2853                 }
2854                 eth_dev->data->dev_private = (void *)dev_priv;
2855                 /* Store a pointer to eth_dev in dev_private */
2856                 dev_priv->eth_dev = eth_dev;
2857         } else {
2858                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2859                 if (!eth_dev) {
2860                         DPAA2_PMD_DEBUG("returning enodev");
2861                         return -ENODEV;
2862                 }
2863         }
2864
2865         eth_dev->device = &dpaa2_dev->device;
2866
2867         dpaa2_dev->eth_dev = eth_dev;
2868         eth_dev->data->rx_mbuf_alloc_failed = 0;
2869
2870         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2871                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2872
2873         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2874
2875         /* Invoke PMD device initialization function */
2876         diag = dpaa2_dev_init(eth_dev);
2877         if (diag == 0) {
2878                 rte_eth_dev_probing_finish(eth_dev);
2879                 return 0;
2880         }
2881
2882         rte_eth_dev_release_port(eth_dev);
2883         return diag;
2884 }
2885
2886 static int
2887 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2888 {
2889         struct rte_eth_dev *eth_dev;
2890         int ret;
2891
2892         eth_dev = dpaa2_dev->eth_dev;
2893         dpaa2_dev_close(eth_dev);
2894         ret = rte_eth_dev_release_port(eth_dev);
2895
2896         return ret;
2897 }
2898
2899 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2900         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2901         .drv_type = DPAA2_ETH,
2902         .probe = rte_dpaa2_probe,
2903         .remove = rte_dpaa2_remove,
2904 };
2905
2906 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2907 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2908                 DRIVER_LOOPBACK_MODE "=<int> "
2909                 DRIVER_NO_PREFETCH_MODE "=<int>"
2910                 DRIVER_TX_CONF "=<int>"
2911                 DRIVER_ERROR_QUEUE "=<int>");
2912 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);