1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2020 NXP
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
35 /* Supported Rx offloads */
36 static uint64_t dev_rx_offloads_sup =
37 DEV_RX_OFFLOAD_CHECKSUM |
38 DEV_RX_OFFLOAD_SCTP_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
41 DEV_RX_OFFLOAD_VLAN_STRIP |
42 DEV_RX_OFFLOAD_VLAN_FILTER |
43 DEV_RX_OFFLOAD_JUMBO_FRAME |
44 DEV_RX_OFFLOAD_TIMESTAMP;
46 /* Rx offloads which cannot be disabled */
47 static uint64_t dev_rx_offloads_nodis =
48 DEV_RX_OFFLOAD_RSS_HASH |
49 DEV_RX_OFFLOAD_SCATTER;
51 /* Supported Tx offloads */
52 static uint64_t dev_tx_offloads_sup =
53 DEV_TX_OFFLOAD_VLAN_INSERT |
54 DEV_TX_OFFLOAD_IPV4_CKSUM |
55 DEV_TX_OFFLOAD_UDP_CKSUM |
56 DEV_TX_OFFLOAD_TCP_CKSUM |
57 DEV_TX_OFFLOAD_SCTP_CKSUM |
58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_MT_LOCKFREE |
60 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
62 /* Tx offloads which cannot be disabled */
63 static uint64_t dev_tx_offloads_nodis =
64 DEV_TX_OFFLOAD_MULTI_SEGS;
66 /* enable timestamp in mbuf */
67 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
68 uint64_t dpaa2_timestamp_rx_dynflag;
69 int dpaa2_timestamp_dynfield_offset = -1;
71 struct rte_dpaa2_xstats_name_off {
72 char name[RTE_ETH_XSTATS_NAME_SIZE];
73 uint8_t page_id; /* dpni statistics page id */
74 uint8_t stats_id; /* stats id in the given page */
77 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
78 {"ingress_multicast_frames", 0, 2},
79 {"ingress_multicast_bytes", 0, 3},
80 {"ingress_broadcast_frames", 0, 4},
81 {"ingress_broadcast_bytes", 0, 5},
82 {"egress_multicast_frames", 1, 2},
83 {"egress_multicast_bytes", 1, 3},
84 {"egress_broadcast_frames", 1, 4},
85 {"egress_broadcast_bytes", 1, 5},
86 {"ingress_filtered_frames", 2, 0},
87 {"ingress_discarded_frames", 2, 1},
88 {"ingress_nobuffer_discards", 2, 2},
89 {"egress_discarded_frames", 2, 3},
90 {"egress_confirmed_frames", 2, 4},
91 {"cgr_reject_frames", 4, 0},
92 {"cgr_reject_bytes", 4, 1},
95 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
97 RTE_ETH_FILTER_DELETE,
98 RTE_ETH_FILTER_UPDATE,
103 static struct rte_dpaa2_driver rte_dpaa2_pmd;
104 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
105 int wait_to_complete);
106 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
107 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
108 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
111 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
114 struct dpaa2_dev_priv *priv = dev->data->dev_private;
115 struct fsl_mc_io *dpni = dev->process_private;
117 PMD_INIT_FUNC_TRACE();
120 DPAA2_PMD_ERR("dpni is NULL");
125 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
128 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
129 priv->token, vlan_id);
132 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
133 ret, vlan_id, priv->hw_id);
139 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
141 struct dpaa2_dev_priv *priv = dev->data->dev_private;
142 struct fsl_mc_io *dpni = dev->process_private;
145 PMD_INIT_FUNC_TRACE();
147 if (mask & ETH_VLAN_FILTER_MASK) {
148 /* VLAN Filter not avaialble */
149 if (!priv->max_vlan_filters) {
150 DPAA2_PMD_INFO("VLAN filter not available");
154 if (dev->data->dev_conf.rxmode.offloads &
155 DEV_RX_OFFLOAD_VLAN_FILTER)
156 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
159 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
162 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
169 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
170 enum rte_vlan_type vlan_type __rte_unused,
173 struct dpaa2_dev_priv *priv = dev->data->dev_private;
174 struct fsl_mc_io *dpni = dev->process_private;
177 PMD_INIT_FUNC_TRACE();
179 /* nothing to be done for standard vlan tpids */
180 if (tpid == 0x8100 || tpid == 0x88A8)
183 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
186 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
187 /* if already configured tpids, remove them first */
189 struct dpni_custom_tpid_cfg tpid_list = {0};
191 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
192 priv->token, &tpid_list);
195 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
196 priv->token, tpid_list.tpid1);
199 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
207 dpaa2_fw_version_get(struct rte_eth_dev *dev,
212 struct fsl_mc_io *dpni = dev->process_private;
213 struct mc_soc_version mc_plat_info = {0};
214 struct mc_version mc_ver_info = {0};
216 PMD_INIT_FUNC_TRACE();
218 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
219 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
221 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
222 DPAA2_PMD_WARN("\tmc_get_version failed");
224 ret = snprintf(fw_version, fw_size,
229 mc_ver_info.revision);
231 ret += 1; /* add the size of '\0' */
232 if (fw_size < (uint32_t)ret)
239 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
241 struct dpaa2_dev_priv *priv = dev->data->dev_private;
243 PMD_INIT_FUNC_TRACE();
245 dev_info->max_mac_addrs = priv->max_mac_filters;
246 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
247 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
248 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
249 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
250 dev_info->rx_offload_capa = dev_rx_offloads_sup |
251 dev_rx_offloads_nodis;
252 dev_info->tx_offload_capa = dev_tx_offloads_sup |
253 dev_tx_offloads_nodis;
254 dev_info->speed_capa = ETH_LINK_SPEED_1G |
255 ETH_LINK_SPEED_2_5G |
258 dev_info->max_hash_mac_addrs = 0;
259 dev_info->max_vfs = 0;
260 dev_info->max_vmdq_pools = ETH_16_POOLS;
261 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
263 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
264 /* same is rx size for best perf */
265 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
267 dev_info->default_rxportconf.nb_queues = 1;
268 dev_info->default_txportconf.nb_queues = 1;
269 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
270 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
272 if (dpaa2_svr_family == SVR_LX2160A) {
273 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
283 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
284 __rte_unused uint16_t queue_id,
285 struct rte_eth_burst_mode *mode)
287 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
290 const struct burst_info {
293 } rx_offload_map[] = {
294 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
295 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
296 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
297 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
298 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
299 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
300 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
301 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
302 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
303 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
306 /* Update Rx offload info */
307 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
308 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
309 snprintf(mode->info, sizeof(mode->info), "%s",
310 rx_offload_map[i].output);
319 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
320 __rte_unused uint16_t queue_id,
321 struct rte_eth_burst_mode *mode)
323 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
326 const struct burst_info {
329 } tx_offload_map[] = {
330 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
331 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
332 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
333 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
334 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
335 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
336 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
337 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
338 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
341 /* Update Tx offload info */
342 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
343 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
344 snprintf(mode->info, sizeof(mode->info), "%s",
345 tx_offload_map[i].output);
354 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
356 struct dpaa2_dev_priv *priv = dev->data->dev_private;
359 uint8_t num_rxqueue_per_tc;
360 struct dpaa2_queue *mc_q, *mcq;
363 struct dpaa2_queue *dpaa2_q;
365 PMD_INIT_FUNC_TRACE();
367 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
368 if (priv->tx_conf_en)
369 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
371 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
372 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
373 RTE_CACHE_LINE_SIZE);
375 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
379 for (i = 0; i < priv->nb_rx_queues; i++) {
380 mc_q->eth_data = dev->data;
381 priv->rx_vq[i] = mc_q++;
382 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
383 dpaa2_q->q_storage = rte_malloc("dq_storage",
384 sizeof(struct queue_storage_info_t),
385 RTE_CACHE_LINE_SIZE);
386 if (!dpaa2_q->q_storage)
389 memset(dpaa2_q->q_storage, 0,
390 sizeof(struct queue_storage_info_t));
391 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
395 for (i = 0; i < priv->nb_tx_queues; i++) {
396 mc_q->eth_data = dev->data;
397 mc_q->flow_id = 0xffff;
398 priv->tx_vq[i] = mc_q++;
399 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
400 dpaa2_q->cscn = rte_malloc(NULL,
401 sizeof(struct qbman_result), 16);
406 if (priv->tx_conf_en) {
407 /*Setup tx confirmation queues*/
408 for (i = 0; i < priv->nb_tx_queues; i++) {
409 mc_q->eth_data = dev->data;
412 priv->tx_conf_vq[i] = mc_q++;
413 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
415 rte_malloc("dq_storage",
416 sizeof(struct queue_storage_info_t),
417 RTE_CACHE_LINE_SIZE);
418 if (!dpaa2_q->q_storage)
421 memset(dpaa2_q->q_storage, 0,
422 sizeof(struct queue_storage_info_t));
423 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
429 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
430 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
431 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
432 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
440 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
441 rte_free(dpaa2_q->q_storage);
442 priv->tx_conf_vq[i--] = NULL;
444 i = priv->nb_tx_queues;
448 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
449 rte_free(dpaa2_q->cscn);
450 priv->tx_vq[i--] = NULL;
452 i = priv->nb_rx_queues;
455 mc_q = priv->rx_vq[0];
457 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
458 dpaa2_free_dq_storage(dpaa2_q->q_storage);
459 rte_free(dpaa2_q->q_storage);
460 priv->rx_vq[i--] = NULL;
467 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
469 struct dpaa2_dev_priv *priv = dev->data->dev_private;
470 struct dpaa2_queue *dpaa2_q;
473 PMD_INIT_FUNC_TRACE();
475 /* Queue allocation base */
476 if (priv->rx_vq[0]) {
477 /* cleaning up queue storage */
478 for (i = 0; i < priv->nb_rx_queues; i++) {
479 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
480 if (dpaa2_q->q_storage)
481 rte_free(dpaa2_q->q_storage);
483 /* cleanup tx queue cscn */
484 for (i = 0; i < priv->nb_tx_queues; i++) {
485 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
486 rte_free(dpaa2_q->cscn);
488 if (priv->tx_conf_en) {
489 /* cleanup tx conf queue storage */
490 for (i = 0; i < priv->nb_tx_queues; i++) {
491 dpaa2_q = (struct dpaa2_queue *)
493 rte_free(dpaa2_q->q_storage);
496 /*free memory for all queues (RX+TX) */
497 rte_free(priv->rx_vq[0]);
498 priv->rx_vq[0] = NULL;
503 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
505 struct dpaa2_dev_priv *priv = dev->data->dev_private;
506 struct fsl_mc_io *dpni = dev->process_private;
507 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
508 uint64_t rx_offloads = eth_conf->rxmode.offloads;
509 uint64_t tx_offloads = eth_conf->txmode.offloads;
510 int rx_l3_csum_offload = false;
511 int rx_l4_csum_offload = false;
512 int tx_l3_csum_offload = false;
513 int tx_l4_csum_offload = false;
516 PMD_INIT_FUNC_TRACE();
518 /* Rx offloads which are enabled by default */
519 if (dev_rx_offloads_nodis & ~rx_offloads) {
521 "Some of rx offloads enabled by default - requested 0x%" PRIx64
522 " fixed are 0x%" PRIx64,
523 rx_offloads, dev_rx_offloads_nodis);
526 /* Tx offloads which are enabled by default */
527 if (dev_tx_offloads_nodis & ~tx_offloads) {
529 "Some of tx offloads enabled by default - requested 0x%" PRIx64
530 " fixed are 0x%" PRIx64,
531 tx_offloads, dev_tx_offloads_nodis);
534 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
535 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
536 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
537 priv->token, eth_conf->rxmode.max_rx_pkt_len
538 - RTE_ETHER_CRC_LEN);
541 "Unable to set mtu. check config");
545 dev->data->dev_conf.rxmode.max_rx_pkt_len -
546 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
553 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
554 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
555 ret = dpaa2_setup_flow_dist(dev,
556 eth_conf->rx_adv_conf.rss_conf.rss_hf,
560 "Unable to set flow distribution on tc%d."
561 "Check queue config", tc_index);
567 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
568 rx_l3_csum_offload = true;
570 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
571 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
572 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
573 rx_l4_csum_offload = true;
575 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
576 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
578 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
582 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
583 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
585 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
589 #if !defined(RTE_LIBRTE_IEEE1588)
590 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
593 ret = rte_mbuf_dyn_rx_timestamp_register(
594 &dpaa2_timestamp_dynfield_offset,
595 &dpaa2_timestamp_rx_dynflag);
597 DPAA2_PMD_ERR("Error to register timestamp field/flag");
600 dpaa2_enable_ts[dev->data->port_id] = true;
603 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
604 tx_l3_csum_offload = true;
606 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
607 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
608 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
609 tx_l4_csum_offload = true;
611 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
612 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
614 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
618 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
619 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
621 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
625 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
626 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
627 * to 0 for LS2 in the hardware thus disabling data/annotation
628 * stashing. For LX2 this is fixed in hardware and thus hash result and
629 * parse results can be received in FD using this option.
631 if (dpaa2_svr_family == SVR_LX2160A) {
632 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
633 DPNI_FLCTYPE_HASH, true);
635 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
640 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
641 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
646 /* Function to setup RX flow information. It contains traffic class ID,
647 * flow ID, destination configuration etc.
650 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
651 uint16_t rx_queue_id,
653 unsigned int socket_id __rte_unused,
654 const struct rte_eth_rxconf *rx_conf,
655 struct rte_mempool *mb_pool)
657 struct dpaa2_dev_priv *priv = dev->data->dev_private;
658 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
659 struct dpaa2_queue *dpaa2_q;
660 struct dpni_queue cfg;
666 PMD_INIT_FUNC_TRACE();
668 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
669 dev, rx_queue_id, mb_pool, rx_conf);
671 /* Rx deferred start is not supported */
672 if (rx_conf->rx_deferred_start) {
673 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
678 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
679 bpid = mempool_to_bpid(mb_pool);
680 ret = dpaa2_attach_bp_list(priv,
681 rte_dpaa2_bpid_info[bpid].bp_list);
685 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
686 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
687 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
688 dpaa2_q->nb_desc = UINT16_MAX;
689 dpaa2_q->offloads = rx_conf->offloads;
691 /*Get the flow id from given VQ id*/
692 flow_id = dpaa2_q->flow_id;
693 memset(&cfg, 0, sizeof(struct dpni_queue));
695 options = options | DPNI_QUEUE_OPT_USER_CTX;
696 cfg.user_context = (size_t)(dpaa2_q);
698 /* check if a private cgr available. */
699 for (i = 0; i < priv->max_cgs; i++) {
700 if (!priv->cgid_in_use[i]) {
701 priv->cgid_in_use[i] = 1;
706 if (i < priv->max_cgs) {
707 options |= DPNI_QUEUE_OPT_SET_CGID;
709 dpaa2_q->cgid = cfg.cgid;
711 dpaa2_q->cgid = 0xff;
714 /*if ls2088 or rev2 device, enable the stashing */
716 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
717 options |= DPNI_QUEUE_OPT_FLC;
718 cfg.flc.stash_control = true;
719 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
720 /* 00 00 00 - last 6 bit represent annotation, context stashing,
721 * data stashing setting 01 01 00 (0x14)
722 * (in following order ->DS AS CS)
723 * to enable 1 line data, 1 line annotation.
724 * For LX2, this setting should be 01 00 00 (0x10)
726 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
727 cfg.flc.value |= 0x10;
729 cfg.flc.value |= 0x14;
731 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
732 dpaa2_q->tc_index, flow_id, options, &cfg);
734 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
738 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
739 struct dpni_taildrop taildrop;
742 dpaa2_q->nb_desc = nb_rx_desc;
743 /* Private CGR will use tail drop length as nb_rx_desc.
744 * for rest cases we can use standard byte based tail drop.
745 * There is no HW restriction, but number of CGRs are limited,
746 * hence this restriction is placed.
748 if (dpaa2_q->cgid != 0xff) {
749 /*enabling per rx queue congestion control */
750 taildrop.threshold = nb_rx_desc;
751 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
753 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
755 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
756 DPNI_CP_CONGESTION_GROUP,
759 dpaa2_q->cgid, &taildrop);
761 /*enabling per rx queue congestion control */
762 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
763 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
764 taildrop.oal = CONG_RX_OAL;
765 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
767 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
768 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
769 dpaa2_q->tc_index, flow_id,
773 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
777 } else { /* Disable tail Drop */
778 struct dpni_taildrop taildrop = {0};
779 DPAA2_PMD_INFO("Tail drop is disabled on queue");
782 if (dpaa2_q->cgid != 0xff) {
783 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
784 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
786 dpaa2_q->cgid, &taildrop);
788 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
789 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
790 dpaa2_q->tc_index, flow_id, &taildrop);
793 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
799 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
804 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
805 uint16_t tx_queue_id,
807 unsigned int socket_id __rte_unused,
808 const struct rte_eth_txconf *tx_conf)
810 struct dpaa2_dev_priv *priv = dev->data->dev_private;
811 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
812 priv->tx_vq[tx_queue_id];
813 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
814 priv->tx_conf_vq[tx_queue_id];
815 struct fsl_mc_io *dpni = dev->process_private;
816 struct dpni_queue tx_conf_cfg;
817 struct dpni_queue tx_flow_cfg;
818 uint8_t options = 0, flow_id;
819 struct dpni_queue_id qid;
823 PMD_INIT_FUNC_TRACE();
825 /* Tx deferred start is not supported */
826 if (tx_conf->tx_deferred_start) {
827 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
832 dpaa2_q->nb_desc = UINT16_MAX;
833 dpaa2_q->offloads = tx_conf->offloads;
835 /* Return if queue already configured */
836 if (dpaa2_q->flow_id != 0xffff) {
837 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
841 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
842 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
847 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
848 tc_id, flow_id, options, &tx_flow_cfg);
850 DPAA2_PMD_ERR("Error in setting the tx flow: "
851 "tc_id=%d, flow=%d err=%d",
852 tc_id, flow_id, ret);
856 dpaa2_q->flow_id = flow_id;
858 if (tx_queue_id == 0) {
859 /*Set tx-conf and error configuration*/
860 if (priv->tx_conf_en)
861 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
865 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
869 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
874 dpaa2_q->tc_index = tc_id;
876 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
877 DPNI_QUEUE_TX, dpaa2_q->tc_index,
878 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
880 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
883 dpaa2_q->fqid = qid.fqid;
885 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
886 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
888 dpaa2_q->nb_desc = nb_tx_desc;
890 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
891 cong_notif_cfg.threshold_entry = nb_tx_desc;
892 /* Notify that the queue is not congested when the data in
893 * the queue is below this thershold.
895 cong_notif_cfg.threshold_exit = nb_tx_desc - 24;
896 cong_notif_cfg.message_ctx = 0;
897 cong_notif_cfg.message_iova =
898 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
899 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
900 cong_notif_cfg.notification_mode =
901 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
902 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
903 DPNI_CONG_OPT_COHERENT_WRITE;
904 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
906 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
913 "Error in setting tx congestion notification: "
918 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
919 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
921 if (priv->tx_conf_en) {
922 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
923 options = options | DPNI_QUEUE_OPT_USER_CTX;
924 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
925 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
926 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
927 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
929 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
930 "tc_index=%d, flow=%d err=%d",
931 dpaa2_tx_conf_q->tc_index,
932 dpaa2_tx_conf_q->flow_id, ret);
936 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
937 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
938 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
940 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
943 dpaa2_tx_conf_q->fqid = qid.fqid;
949 dpaa2_dev_rx_queue_release(void *q __rte_unused)
951 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
952 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
953 struct fsl_mc_io *dpni =
954 (struct fsl_mc_io *)priv->eth_dev->process_private;
957 struct dpni_queue cfg;
959 memset(&cfg, 0, sizeof(struct dpni_queue));
960 PMD_INIT_FUNC_TRACE();
961 if (dpaa2_q->cgid != 0xff) {
962 options = DPNI_QUEUE_OPT_CLEAR_CGID;
963 cfg.cgid = dpaa2_q->cgid;
965 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
967 dpaa2_q->tc_index, dpaa2_q->flow_id,
970 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
972 priv->cgid_in_use[dpaa2_q->cgid] = 0;
973 dpaa2_q->cgid = 0xff;
978 dpaa2_dev_tx_queue_release(void *q __rte_unused)
980 PMD_INIT_FUNC_TRACE();
984 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
987 struct dpaa2_dev_priv *priv = dev->data->dev_private;
988 struct dpaa2_queue *dpaa2_q;
989 struct qbman_swp *swp;
990 struct qbman_fq_query_np_rslt state;
991 uint32_t frame_cnt = 0;
993 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
994 ret = dpaa2_affine_qbman_swp();
997 "Failed to allocate IO portal, tid: %d\n",
1002 swp = DPAA2_PER_LCORE_PORTAL;
1004 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
1006 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1007 frame_cnt = qbman_fq_state_frame_count(&state);
1008 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
1009 rx_queue_id, frame_cnt);
1014 static const uint32_t *
1015 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1017 static const uint32_t ptypes[] = {
1018 /*todo -= add more types */
1021 RTE_PTYPE_L3_IPV4_EXT,
1023 RTE_PTYPE_L3_IPV6_EXT,
1031 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1032 dev->rx_pkt_burst == dpaa2_dev_rx ||
1033 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1039 * Dpaa2 link Interrupt handler
1042 * The address of parameter (struct rte_eth_dev *) regsitered before.
1048 dpaa2_interrupt_handler(void *param)
1050 struct rte_eth_dev *dev = param;
1051 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1052 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1054 int irq_index = DPNI_IRQ_INDEX;
1055 unsigned int status = 0, clear = 0;
1057 PMD_INIT_FUNC_TRACE();
1060 DPAA2_PMD_ERR("dpni is NULL");
1064 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1065 irq_index, &status);
1066 if (unlikely(ret)) {
1067 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1072 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1073 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1074 dpaa2_dev_link_update(dev, 0);
1075 /* calling all the apps registered for link status event */
1076 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1079 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1082 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1086 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1089 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1090 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1091 int irq_index = DPNI_IRQ_INDEX;
1092 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1094 PMD_INIT_FUNC_TRACE();
1096 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1099 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1104 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1107 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1114 dpaa2_dev_start(struct rte_eth_dev *dev)
1116 struct rte_device *rdev = dev->device;
1117 struct rte_dpaa2_device *dpaa2_dev;
1118 struct rte_eth_dev_data *data = dev->data;
1119 struct dpaa2_dev_priv *priv = data->dev_private;
1120 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1121 struct dpni_queue cfg;
1122 struct dpni_error_cfg err_cfg;
1124 struct dpni_queue_id qid;
1125 struct dpaa2_queue *dpaa2_q;
1127 struct rte_intr_handle *intr_handle;
1129 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1130 intr_handle = &dpaa2_dev->intr_handle;
1132 PMD_INIT_FUNC_TRACE();
1134 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1136 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1141 /* Power up the phy. Needed to make the link go UP */
1142 dpaa2_dev_set_link_up(dev);
1144 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1145 DPNI_QUEUE_TX, &qdid);
1147 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1152 for (i = 0; i < data->nb_rx_queues; i++) {
1153 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1154 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1155 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1156 dpaa2_q->flow_id, &cfg, &qid);
1158 DPAA2_PMD_ERR("Error in getting flow information: "
1162 dpaa2_q->fqid = qid.fqid;
1165 /*checksum errors, send them to normal path and set it in annotation */
1166 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1167 err_cfg.errors |= DPNI_ERROR_PHE;
1169 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1170 err_cfg.set_frame_annotation = true;
1172 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1173 priv->token, &err_cfg);
1175 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1180 /* if the interrupts were configured on this devices*/
1181 if (intr_handle && (intr_handle->fd) &&
1182 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1183 /* Registering LSC interrupt handler */
1184 rte_intr_callback_register(intr_handle,
1185 dpaa2_interrupt_handler,
1188 /* enable vfio intr/eventfd mapping
1189 * Interrupt index 0 is required, so we can not use
1192 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1194 /* enable dpni_irqs */
1195 dpaa2_eth_setup_irqs(dev, 1);
1198 /* Change the tx burst function if ordered queues are used */
1199 if (priv->en_ordered)
1200 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1206 * This routine disables all traffic on the adapter by issuing a
1207 * global reset on the MAC.
1210 dpaa2_dev_stop(struct rte_eth_dev *dev)
1212 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1213 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1215 struct rte_eth_link link;
1216 struct rte_intr_handle *intr_handle = dev->intr_handle;
1218 PMD_INIT_FUNC_TRACE();
1220 /* reset interrupt callback */
1221 if (intr_handle && (intr_handle->fd) &&
1222 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1223 /*disable dpni irqs */
1224 dpaa2_eth_setup_irqs(dev, 0);
1226 /* disable vfio intr before callback unregister */
1227 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1229 /* Unregistering LSC interrupt handler */
1230 rte_intr_callback_unregister(intr_handle,
1231 dpaa2_interrupt_handler,
1235 dpaa2_dev_set_link_down(dev);
1237 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1239 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1244 /* clear the recorded link status */
1245 memset(&link, 0, sizeof(link));
1246 rte_eth_linkstatus_set(dev, &link);
1252 dpaa2_dev_close(struct rte_eth_dev *dev)
1254 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1255 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1257 struct rte_eth_link link;
1259 PMD_INIT_FUNC_TRACE();
1261 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1265 DPAA2_PMD_WARN("Already closed or not started");
1269 dpaa2_flow_clean(dev);
1270 /* Clean the device first */
1271 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1273 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1277 memset(&link, 0, sizeof(link));
1278 rte_eth_linkstatus_set(dev, &link);
1280 /* Free private queues memory */
1281 dpaa2_free_rx_tx_queues(dev);
1282 /* Close the device at underlying layer*/
1283 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1285 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1289 /* Free the allocated memory for ethernet private data and dpni*/
1291 dev->process_private = NULL;
1294 for (i = 0; i < MAX_TCS; i++)
1295 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1297 if (priv->extract.qos_extract_param)
1298 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1300 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1305 dpaa2_dev_promiscuous_enable(
1306 struct rte_eth_dev *dev)
1309 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1310 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1312 PMD_INIT_FUNC_TRACE();
1315 DPAA2_PMD_ERR("dpni is NULL");
1319 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1321 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1323 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1325 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1331 dpaa2_dev_promiscuous_disable(
1332 struct rte_eth_dev *dev)
1335 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1336 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1338 PMD_INIT_FUNC_TRACE();
1341 DPAA2_PMD_ERR("dpni is NULL");
1345 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1347 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1349 if (dev->data->all_multicast == 0) {
1350 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1351 priv->token, false);
1353 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1361 dpaa2_dev_allmulticast_enable(
1362 struct rte_eth_dev *dev)
1365 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1366 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1368 PMD_INIT_FUNC_TRACE();
1371 DPAA2_PMD_ERR("dpni is NULL");
1375 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1377 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1383 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1386 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1387 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1389 PMD_INIT_FUNC_TRACE();
1392 DPAA2_PMD_ERR("dpni is NULL");
1396 /* must remain on for all promiscuous */
1397 if (dev->data->promiscuous == 1)
1400 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1402 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1408 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1411 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1412 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1413 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1416 PMD_INIT_FUNC_TRACE();
1419 DPAA2_PMD_ERR("dpni is NULL");
1423 /* check that mtu is within the allowed range */
1424 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1427 if (frame_size > RTE_ETHER_MAX_LEN)
1428 dev->data->dev_conf.rxmode.offloads |=
1429 DEV_RX_OFFLOAD_JUMBO_FRAME;
1431 dev->data->dev_conf.rxmode.offloads &=
1432 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1434 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1436 /* Set the Max Rx frame length as 'mtu' +
1437 * Maximum Ethernet header length
1439 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1440 frame_size - RTE_ETHER_CRC_LEN);
1442 DPAA2_PMD_ERR("Setting the max frame length failed");
1445 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1450 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1451 struct rte_ether_addr *addr,
1452 __rte_unused uint32_t index,
1453 __rte_unused uint32_t pool)
1456 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1457 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1459 PMD_INIT_FUNC_TRACE();
1462 DPAA2_PMD_ERR("dpni is NULL");
1466 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1467 addr->addr_bytes, 0, 0, 0);
1470 "error: Adding the MAC ADDR failed: err = %d", ret);
1475 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1479 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1480 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1481 struct rte_eth_dev_data *data = dev->data;
1482 struct rte_ether_addr *macaddr;
1484 PMD_INIT_FUNC_TRACE();
1486 macaddr = &data->mac_addrs[index];
1489 DPAA2_PMD_ERR("dpni is NULL");
1493 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1494 priv->token, macaddr->addr_bytes);
1497 "error: Removing the MAC ADDR failed: err = %d", ret);
1501 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1502 struct rte_ether_addr *addr)
1505 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1506 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1508 PMD_INIT_FUNC_TRACE();
1511 DPAA2_PMD_ERR("dpni is NULL");
1515 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1516 priv->token, addr->addr_bytes);
1520 "error: Setting the MAC ADDR failed %d", ret);
1526 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1527 struct rte_eth_stats *stats)
1529 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1530 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1532 uint8_t page0 = 0, page1 = 1, page2 = 2;
1533 union dpni_statistics value;
1535 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1537 memset(&value, 0, sizeof(union dpni_statistics));
1539 PMD_INIT_FUNC_TRACE();
1542 DPAA2_PMD_ERR("dpni is NULL");
1547 DPAA2_PMD_ERR("stats is NULL");
1551 /*Get Counters from page_0*/
1552 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1557 stats->ipackets = value.page_0.ingress_all_frames;
1558 stats->ibytes = value.page_0.ingress_all_bytes;
1560 /*Get Counters from page_1*/
1561 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1566 stats->opackets = value.page_1.egress_all_frames;
1567 stats->obytes = value.page_1.egress_all_bytes;
1569 /*Get Counters from page_2*/
1570 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1575 /* Ingress drop frame count due to configured rules */
1576 stats->ierrors = value.page_2.ingress_filtered_frames;
1577 /* Ingress drop frame count due to error */
1578 stats->ierrors += value.page_2.ingress_discarded_frames;
1580 stats->oerrors = value.page_2.egress_discarded_frames;
1581 stats->imissed = value.page_2.ingress_nobuffer_discards;
1583 /* Fill in per queue stats */
1584 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1585 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1586 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1587 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1589 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1591 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1593 /* Byte counting is not implemented */
1594 stats->q_ibytes[i] = 0;
1595 stats->q_obytes[i] = 0;
1601 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1606 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1609 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1610 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1612 union dpni_statistics value[5] = {};
1613 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1621 /* Get Counters from page_0*/
1622 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1627 /* Get Counters from page_1*/
1628 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1633 /* Get Counters from page_2*/
1634 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1639 for (i = 0; i < priv->max_cgs; i++) {
1640 if (!priv->cgid_in_use[i]) {
1641 /* Get Counters from page_4*/
1642 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1651 for (i = 0; i < num; i++) {
1653 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1654 raw.counter[dpaa2_xstats_strings[i].stats_id];
1658 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1663 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1664 struct rte_eth_xstat_name *xstats_names,
1667 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1669 if (limit < stat_cnt)
1672 if (xstats_names != NULL)
1673 for (i = 0; i < stat_cnt; i++)
1674 strlcpy(xstats_names[i].name,
1675 dpaa2_xstats_strings[i].name,
1676 sizeof(xstats_names[i].name));
1682 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1683 uint64_t *values, unsigned int n)
1685 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1686 uint64_t values_copy[stat_cnt];
1689 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1690 struct fsl_mc_io *dpni =
1691 (struct fsl_mc_io *)dev->process_private;
1693 union dpni_statistics value[5] = {};
1701 /* Get Counters from page_0*/
1702 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1707 /* Get Counters from page_1*/
1708 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1713 /* Get Counters from page_2*/
1714 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1719 /* Get Counters from page_4*/
1720 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1725 for (i = 0; i < stat_cnt; i++) {
1726 values[i] = value[dpaa2_xstats_strings[i].page_id].
1727 raw.counter[dpaa2_xstats_strings[i].stats_id];
1732 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1734 for (i = 0; i < n; i++) {
1735 if (ids[i] >= stat_cnt) {
1736 DPAA2_PMD_ERR("xstats id value isn't valid");
1739 values[i] = values_copy[ids[i]];
1745 dpaa2_xstats_get_names_by_id(
1746 struct rte_eth_dev *dev,
1747 struct rte_eth_xstat_name *xstats_names,
1748 const uint64_t *ids,
1751 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1752 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1755 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1757 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1759 for (i = 0; i < limit; i++) {
1760 if (ids[i] >= stat_cnt) {
1761 DPAA2_PMD_ERR("xstats id value isn't valid");
1764 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1770 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1772 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1773 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1776 struct dpaa2_queue *dpaa2_q;
1778 PMD_INIT_FUNC_TRACE();
1781 DPAA2_PMD_ERR("dpni is NULL");
1785 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1789 /* Reset the per queue stats in dpaa2_queue structure */
1790 for (i = 0; i < priv->nb_rx_queues; i++) {
1791 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1793 dpaa2_q->rx_pkts = 0;
1796 for (i = 0; i < priv->nb_tx_queues; i++) {
1797 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1799 dpaa2_q->tx_pkts = 0;
1805 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1809 /* return 0 means link status changed, -1 means not changed */
1811 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1812 int wait_to_complete __rte_unused)
1815 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1816 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1817 struct rte_eth_link link;
1818 struct dpni_link_state state = {0};
1821 DPAA2_PMD_ERR("dpni is NULL");
1825 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1827 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1831 memset(&link, 0, sizeof(struct rte_eth_link));
1832 link.link_status = state.up;
1833 link.link_speed = state.rate;
1835 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1836 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1838 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1840 ret = rte_eth_linkstatus_set(dev, &link);
1842 DPAA2_PMD_DEBUG("No change in status");
1844 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1845 link.link_status ? "Up" : "Down");
1851 * Toggle the DPNI to enable, if not already enabled.
1852 * This is not strictly PHY up/down - it is more of logical toggling.
1855 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1858 struct dpaa2_dev_priv *priv;
1859 struct fsl_mc_io *dpni;
1861 struct dpni_link_state state = {0};
1863 priv = dev->data->dev_private;
1864 dpni = (struct fsl_mc_io *)dev->process_private;
1867 DPAA2_PMD_ERR("dpni is NULL");
1871 /* Check if DPNI is currently enabled */
1872 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1874 /* Unable to obtain dpni status; Not continuing */
1875 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1879 /* Enable link if not already enabled */
1881 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1883 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1887 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1889 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1893 /* changing tx burst function to start enqueues */
1894 dev->tx_pkt_burst = dpaa2_dev_tx;
1895 dev->data->dev_link.link_status = state.up;
1896 dev->data->dev_link.link_speed = state.rate;
1899 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1901 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1906 * Toggle the DPNI to disable, if not already disabled.
1907 * This is not strictly PHY up/down - it is more of logical toggling.
1910 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1913 struct dpaa2_dev_priv *priv;
1914 struct fsl_mc_io *dpni;
1915 int dpni_enabled = 0;
1918 PMD_INIT_FUNC_TRACE();
1920 priv = dev->data->dev_private;
1921 dpni = (struct fsl_mc_io *)dev->process_private;
1924 DPAA2_PMD_ERR("Device has not yet been configured");
1928 /*changing tx burst function to avoid any more enqueues */
1929 dev->tx_pkt_burst = dummy_dev_tx;
1931 /* Loop while dpni_disable() attempts to drain the egress FQs
1932 * and confirm them back to us.
1935 ret = dpni_disable(dpni, 0, priv->token);
1937 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1940 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1942 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1946 /* Allow the MC some slack */
1947 rte_delay_us(100 * 1000);
1948 } while (dpni_enabled && --retries);
1951 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1952 /* todo- we may have to manually cleanup queues.
1955 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1956 dev->data->port_id);
1959 dev->data->dev_link.link_status = 0;
1965 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1968 struct dpaa2_dev_priv *priv;
1969 struct fsl_mc_io *dpni;
1970 struct dpni_link_state state = {0};
1972 PMD_INIT_FUNC_TRACE();
1974 priv = dev->data->dev_private;
1975 dpni = (struct fsl_mc_io *)dev->process_private;
1977 if (dpni == NULL || fc_conf == NULL) {
1978 DPAA2_PMD_ERR("device not configured");
1982 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1984 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1988 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1989 if (state.options & DPNI_LINK_OPT_PAUSE) {
1990 /* DPNI_LINK_OPT_PAUSE set
1991 * if ASYM_PAUSE not set,
1992 * RX Side flow control (handle received Pause frame)
1993 * TX side flow control (send Pause frame)
1994 * if ASYM_PAUSE set,
1995 * RX Side flow control (handle received Pause frame)
1996 * No TX side flow control (send Pause frame disabled)
1998 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1999 fc_conf->mode = RTE_FC_FULL;
2001 fc_conf->mode = RTE_FC_RX_PAUSE;
2003 /* DPNI_LINK_OPT_PAUSE not set
2004 * if ASYM_PAUSE set,
2005 * TX side flow control (send Pause frame)
2006 * No RX side flow control (No action on pause frame rx)
2007 * if ASYM_PAUSE not set,
2008 * Flow control disabled
2010 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2011 fc_conf->mode = RTE_FC_TX_PAUSE;
2013 fc_conf->mode = RTE_FC_NONE;
2020 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2023 struct dpaa2_dev_priv *priv;
2024 struct fsl_mc_io *dpni;
2025 struct dpni_link_state state = {0};
2026 struct dpni_link_cfg cfg = {0};
2028 PMD_INIT_FUNC_TRACE();
2030 priv = dev->data->dev_private;
2031 dpni = (struct fsl_mc_io *)dev->process_private;
2034 DPAA2_PMD_ERR("dpni is NULL");
2038 /* It is necessary to obtain the current state before setting fc_conf
2039 * as MC would return error in case rate, autoneg or duplex values are
2042 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2044 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2048 /* Disable link before setting configuration */
2049 dpaa2_dev_set_link_down(dev);
2051 /* Based on fc_conf, update cfg */
2052 cfg.rate = state.rate;
2053 cfg.options = state.options;
2055 /* update cfg with fc_conf */
2056 switch (fc_conf->mode) {
2058 /* Full flow control;
2059 * OPT_PAUSE set, ASYM_PAUSE not set
2061 cfg.options |= DPNI_LINK_OPT_PAUSE;
2062 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2064 case RTE_FC_TX_PAUSE:
2065 /* Enable RX flow control
2066 * OPT_PAUSE not set;
2069 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2070 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2072 case RTE_FC_RX_PAUSE:
2073 /* Enable TX Flow control
2077 cfg.options |= DPNI_LINK_OPT_PAUSE;
2078 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2081 /* Disable Flow control
2083 * ASYM_PAUSE not set
2085 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2086 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2089 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2094 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2096 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2100 dpaa2_dev_set_link_up(dev);
2106 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2107 struct rte_eth_rss_conf *rss_conf)
2109 struct rte_eth_dev_data *data = dev->data;
2110 struct dpaa2_dev_priv *priv = data->dev_private;
2111 struct rte_eth_conf *eth_conf = &data->dev_conf;
2114 PMD_INIT_FUNC_TRACE();
2116 if (rss_conf->rss_hf) {
2117 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2118 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2121 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2127 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2128 ret = dpaa2_remove_flow_dist(dev, tc_index);
2131 "Unable to remove flow dist on tc%d",
2137 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2142 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2143 struct rte_eth_rss_conf *rss_conf)
2145 struct rte_eth_dev_data *data = dev->data;
2146 struct rte_eth_conf *eth_conf = &data->dev_conf;
2148 /* dpaa2 does not support rss_key, so length should be 0*/
2149 rss_conf->rss_key_len = 0;
2150 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2154 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2155 int eth_rx_queue_id,
2156 struct dpaa2_dpcon_dev *dpcon,
2157 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2159 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2160 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2161 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2162 uint8_t flow_id = dpaa2_ethq->flow_id;
2163 struct dpni_queue cfg;
2164 uint8_t options, priority;
2167 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2168 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2169 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2170 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2171 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2172 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2176 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2177 (dpcon->num_priorities - 1);
2179 memset(&cfg, 0, sizeof(struct dpni_queue));
2180 options = DPNI_QUEUE_OPT_DEST;
2181 cfg.destination.type = DPNI_DEST_DPCON;
2182 cfg.destination.id = dpcon->dpcon_id;
2183 cfg.destination.priority = priority;
2185 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2186 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2187 cfg.destination.hold_active = 1;
2190 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2191 !eth_priv->en_ordered) {
2192 struct opr_cfg ocfg;
2194 /* Restoration window size = 256 frames */
2196 /* Restoration window size = 512 frames for LX2 */
2197 if (dpaa2_svr_family == SVR_LX2160A)
2199 /* Auto advance NESN window enabled */
2201 /* Late arrival window size disabled */
2203 /* ORL resource exhaustaion advance NESN disabled */
2205 /* Loose ordering enabled */
2207 eth_priv->en_loose_ordered = 1;
2208 /* Strict ordering enabled if explicitly set */
2209 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2211 eth_priv->en_loose_ordered = 0;
2214 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2215 dpaa2_ethq->tc_index, flow_id,
2216 OPR_OPT_CREATE, &ocfg);
2218 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2222 eth_priv->en_ordered = 1;
2225 options |= DPNI_QUEUE_OPT_USER_CTX;
2226 cfg.user_context = (size_t)(dpaa2_ethq);
2228 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2229 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2231 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2235 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2240 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2241 int eth_rx_queue_id)
2243 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2244 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2245 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2246 uint8_t flow_id = dpaa2_ethq->flow_id;
2247 struct dpni_queue cfg;
2251 memset(&cfg, 0, sizeof(struct dpni_queue));
2252 options = DPNI_QUEUE_OPT_DEST;
2253 cfg.destination.type = DPNI_DEST_NONE;
2255 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2256 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2258 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2264 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2268 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2269 if (dpaa2_supported_filter_ops[i] == filter_op)
2276 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2277 enum rte_filter_type filter_type,
2278 enum rte_filter_op filter_op,
2286 switch (filter_type) {
2287 case RTE_ETH_FILTER_GENERIC:
2288 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2292 *(const void **)arg = &dpaa2_flow_ops;
2293 dpaa2_filter_type |= filter_type;
2296 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2305 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2306 struct rte_eth_rxq_info *qinfo)
2308 struct dpaa2_queue *rxq;
2310 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2312 qinfo->mp = rxq->mb_pool;
2313 qinfo->scattered_rx = dev->data->scattered_rx;
2314 qinfo->nb_desc = rxq->nb_desc;
2316 qinfo->conf.rx_free_thresh = 1;
2317 qinfo->conf.rx_drop_en = 1;
2318 qinfo->conf.rx_deferred_start = 0;
2319 qinfo->conf.offloads = rxq->offloads;
2323 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2324 struct rte_eth_txq_info *qinfo)
2326 struct dpaa2_queue *txq;
2328 txq = dev->data->tx_queues[queue_id];
2330 qinfo->nb_desc = txq->nb_desc;
2331 qinfo->conf.tx_thresh.pthresh = 0;
2332 qinfo->conf.tx_thresh.hthresh = 0;
2333 qinfo->conf.tx_thresh.wthresh = 0;
2335 qinfo->conf.tx_free_thresh = 0;
2336 qinfo->conf.tx_rs_thresh = 0;
2337 qinfo->conf.offloads = txq->offloads;
2338 qinfo->conf.tx_deferred_start = 0;
2341 static struct eth_dev_ops dpaa2_ethdev_ops = {
2342 .dev_configure = dpaa2_eth_dev_configure,
2343 .dev_start = dpaa2_dev_start,
2344 .dev_stop = dpaa2_dev_stop,
2345 .dev_close = dpaa2_dev_close,
2346 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2347 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2348 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2349 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2350 .dev_set_link_up = dpaa2_dev_set_link_up,
2351 .dev_set_link_down = dpaa2_dev_set_link_down,
2352 .link_update = dpaa2_dev_link_update,
2353 .stats_get = dpaa2_dev_stats_get,
2354 .xstats_get = dpaa2_dev_xstats_get,
2355 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2356 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2357 .xstats_get_names = dpaa2_xstats_get_names,
2358 .stats_reset = dpaa2_dev_stats_reset,
2359 .xstats_reset = dpaa2_dev_stats_reset,
2360 .fw_version_get = dpaa2_fw_version_get,
2361 .dev_infos_get = dpaa2_dev_info_get,
2362 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2363 .mtu_set = dpaa2_dev_mtu_set,
2364 .vlan_filter_set = dpaa2_vlan_filter_set,
2365 .vlan_offload_set = dpaa2_vlan_offload_set,
2366 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2367 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2368 .rx_queue_release = dpaa2_dev_rx_queue_release,
2369 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2370 .tx_queue_release = dpaa2_dev_tx_queue_release,
2371 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2372 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2373 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2374 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2375 .mac_addr_add = dpaa2_dev_add_mac_addr,
2376 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2377 .mac_addr_set = dpaa2_dev_set_mac_addr,
2378 .rss_hash_update = dpaa2_dev_rss_hash_update,
2379 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2380 .filter_ctrl = dpaa2_dev_flow_ctrl,
2381 .rxq_info_get = dpaa2_rxq_info_get,
2382 .txq_info_get = dpaa2_txq_info_get,
2383 #if defined(RTE_LIBRTE_IEEE1588)
2384 .timesync_enable = dpaa2_timesync_enable,
2385 .timesync_disable = dpaa2_timesync_disable,
2386 .timesync_read_time = dpaa2_timesync_read_time,
2387 .timesync_write_time = dpaa2_timesync_write_time,
2388 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2389 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2390 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2394 /* Populate the mac address from physically available (u-boot/firmware) and/or
2395 * one set by higher layers like MC (restool) etc.
2396 * Returns the table of MAC entries (multiple entries)
2399 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2400 struct rte_ether_addr *mac_entry)
2403 struct rte_ether_addr phy_mac, prime_mac;
2405 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2406 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2408 /* Get the physical device MAC address */
2409 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2410 phy_mac.addr_bytes);
2412 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2416 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2417 prime_mac.addr_bytes);
2419 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2423 /* Now that both MAC have been obtained, do:
2424 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2426 * If empty_mac(phy), return prime.
2427 * if both are empty, create random MAC, set as prime and return
2429 if (!rte_is_zero_ether_addr(&phy_mac)) {
2430 /* If the addresses are not same, overwrite prime */
2431 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2432 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2434 phy_mac.addr_bytes);
2436 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2440 memcpy(&prime_mac, &phy_mac,
2441 sizeof(struct rte_ether_addr));
2443 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2444 /* In case phys and prime, both are zero, create random MAC */
2445 rte_eth_random_addr(prime_mac.addr_bytes);
2446 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2448 prime_mac.addr_bytes);
2450 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2455 /* prime_mac the final MAC address */
2456 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2464 check_devargs_handler(__rte_unused const char *key, const char *value,
2465 __rte_unused void *opaque)
2467 if (strcmp(value, "1"))
2474 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2476 struct rte_kvargs *kvlist;
2481 kvlist = rte_kvargs_parse(devargs->args, NULL);
2485 if (!rte_kvargs_count(kvlist, key)) {
2486 rte_kvargs_free(kvlist);
2490 if (rte_kvargs_process(kvlist, key,
2491 check_devargs_handler, NULL) < 0) {
2492 rte_kvargs_free(kvlist);
2495 rte_kvargs_free(kvlist);
2501 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2503 struct rte_device *dev = eth_dev->device;
2504 struct rte_dpaa2_device *dpaa2_dev;
2505 struct fsl_mc_io *dpni_dev;
2506 struct dpni_attr attr;
2507 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2508 struct dpni_buffer_layout layout;
2511 PMD_INIT_FUNC_TRACE();
2513 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2515 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2518 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2519 eth_dev->process_private = (void *)dpni_dev;
2521 /* For secondary processes, the primary has done all the work */
2522 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2523 /* In case of secondary, only burst and ops API need to be
2526 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2527 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2528 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2529 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2530 else if (dpaa2_get_devargs(dev->devargs,
2531 DRIVER_NO_PREFETCH_MODE))
2532 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2534 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2535 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2539 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2541 hw_id = dpaa2_dev->object_id;
2542 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2545 "Failure in opening dpni@%d with err code %d",
2551 /* Clean the device first */
2552 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2554 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2559 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2562 "Failure in get dpni@%d attribute, err code %d",
2567 priv->num_rx_tc = attr.num_rx_tcs;
2568 priv->qos_entries = attr.qos_entries;
2569 priv->fs_entries = attr.fs_entries;
2570 priv->dist_queues = attr.num_queues;
2572 /* only if the custom CG is enabled */
2573 if (attr.options & DPNI_OPT_CUSTOM_CG)
2574 priv->max_cgs = attr.num_cgs;
2578 for (i = 0; i < priv->max_cgs; i++)
2579 priv->cgid_in_use[i] = 0;
2581 for (i = 0; i < attr.num_rx_tcs; i++)
2582 priv->nb_rx_queues += attr.num_queues;
2584 /* Using number of TX queues as number of TX TCs */
2585 priv->nb_tx_queues = attr.num_tx_tcs;
2587 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2588 priv->num_rx_tc, priv->nb_rx_queues,
2589 priv->nb_tx_queues, priv->max_cgs);
2591 priv->hw = dpni_dev;
2592 priv->hw_id = hw_id;
2593 priv->options = attr.options;
2594 priv->max_mac_filters = attr.mac_filter_entries;
2595 priv->max_vlan_filters = attr.vlan_filter_entries;
2597 #if defined(RTE_LIBRTE_IEEE1588)
2598 priv->tx_conf_en = 1;
2600 priv->tx_conf_en = 0;
2603 /* Allocate memory for hardware structure for queues */
2604 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2606 DPAA2_PMD_ERR("Queue allocation Failed");
2610 /* Allocate memory for storing MAC addresses.
2611 * Table of mac_filter_entries size is allocated so that RTE ether lib
2612 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2614 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2615 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2616 if (eth_dev->data->mac_addrs == NULL) {
2618 "Failed to allocate %d bytes needed to store MAC addresses",
2619 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2624 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2626 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2627 rte_free(eth_dev->data->mac_addrs);
2628 eth_dev->data->mac_addrs = NULL;
2632 /* ... tx buffer layout ... */
2633 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2634 if (priv->tx_conf_en) {
2635 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2636 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2637 layout.pass_timestamp = true;
2639 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2641 layout.pass_frame_status = 1;
2642 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2643 DPNI_QUEUE_TX, &layout);
2645 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2649 /* ... tx-conf and error buffer layout ... */
2650 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2651 if (priv->tx_conf_en) {
2652 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2653 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2654 layout.pass_timestamp = true;
2656 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2658 layout.pass_frame_status = 1;
2659 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2660 DPNI_QUEUE_TX_CONFIRM, &layout);
2662 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2667 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2669 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2670 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2671 DPAA2_PMD_INFO("Loopback mode");
2672 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2673 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2674 DPAA2_PMD_INFO("No Prefetch mode");
2676 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2678 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2680 /*Init fields w.r.t. classficaition*/
2681 memset(&priv->extract.qos_key_extract, 0,
2682 sizeof(struct dpaa2_key_extract));
2683 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2684 if (!priv->extract.qos_extract_param) {
2685 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2686 " classificaiton ", ret);
2689 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2690 IP_ADDRESS_OFFSET_INVALID;
2691 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2692 IP_ADDRESS_OFFSET_INVALID;
2693 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2694 IP_ADDRESS_OFFSET_INVALID;
2695 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2696 IP_ADDRESS_OFFSET_INVALID;
2698 for (i = 0; i < MAX_TCS; i++) {
2699 memset(&priv->extract.tc_key_extract[i], 0,
2700 sizeof(struct dpaa2_key_extract));
2701 priv->extract.tc_extract_param[i] =
2702 (size_t)rte_malloc(NULL, 256, 64);
2703 if (!priv->extract.tc_extract_param[i]) {
2704 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2708 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2709 IP_ADDRESS_OFFSET_INVALID;
2710 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2711 IP_ADDRESS_OFFSET_INVALID;
2712 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2713 IP_ADDRESS_OFFSET_INVALID;
2714 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2715 IP_ADDRESS_OFFSET_INVALID;
2718 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2719 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2722 DPAA2_PMD_ERR("Unable to set mtu. check config");
2726 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2727 * with external entity to receive byte code for software sequence
2728 * and same will be offload to the H/W using MC interface.
2729 * Currently it is assumed that DPAA2 driver has byte code by some
2730 * mean and same if offloaded to H/W.
2732 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2733 WRIOP_SS_INITIALIZER(priv);
2734 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2736 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2741 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2744 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2749 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2752 dpaa2_dev_close(eth_dev);
2758 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2759 struct rte_dpaa2_device *dpaa2_dev)
2761 struct rte_eth_dev *eth_dev;
2762 struct dpaa2_dev_priv *dev_priv;
2765 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2766 RTE_PKTMBUF_HEADROOM) {
2768 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2769 RTE_PKTMBUF_HEADROOM,
2770 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2775 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2776 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2779 dev_priv = rte_zmalloc("ethdev private structure",
2780 sizeof(struct dpaa2_dev_priv),
2781 RTE_CACHE_LINE_SIZE);
2782 if (dev_priv == NULL) {
2784 "Unable to allocate memory for private data");
2785 rte_eth_dev_release_port(eth_dev);
2788 eth_dev->data->dev_private = (void *)dev_priv;
2789 /* Store a pointer to eth_dev in dev_private */
2790 dev_priv->eth_dev = eth_dev;
2791 dev_priv->tx_conf_en = 0;
2793 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2795 DPAA2_PMD_DEBUG("returning enodev");
2800 eth_dev->device = &dpaa2_dev->device;
2802 dpaa2_dev->eth_dev = eth_dev;
2803 eth_dev->data->rx_mbuf_alloc_failed = 0;
2805 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2806 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2808 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2810 /* Invoke PMD device initialization function */
2811 diag = dpaa2_dev_init(eth_dev);
2813 rte_eth_dev_probing_finish(eth_dev);
2817 rte_eth_dev_release_port(eth_dev);
2822 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2824 struct rte_eth_dev *eth_dev;
2827 eth_dev = dpaa2_dev->eth_dev;
2828 dpaa2_dev_close(eth_dev);
2829 ret = rte_eth_dev_release_port(eth_dev);
2834 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2835 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2836 .drv_type = DPAA2_ETH,
2837 .probe = rte_dpaa2_probe,
2838 .remove = rte_dpaa2_remove,
2841 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2842 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2843 DRIVER_LOOPBACK_MODE "=<int> "
2844 DRIVER_NO_PREFETCH_MODE "=<int>");
2845 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);