1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include <fsl_qbman_debug.h>
31 #define DRIVER_LOOPBACK_MODE "drv_loopback"
32 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
34 /* Supported Rx offloads */
35 static uint64_t dev_rx_offloads_sup =
36 DEV_RX_OFFLOAD_CHECKSUM |
37 DEV_RX_OFFLOAD_SCTP_CKSUM |
38 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
40 DEV_RX_OFFLOAD_VLAN_STRIP |
41 DEV_RX_OFFLOAD_VLAN_FILTER |
42 DEV_RX_OFFLOAD_JUMBO_FRAME |
43 DEV_RX_OFFLOAD_TIMESTAMP;
45 /* Rx offloads which cannot be disabled */
46 static uint64_t dev_rx_offloads_nodis =
47 DEV_RX_OFFLOAD_SCATTER;
49 /* Supported Tx offloads */
50 static uint64_t dev_tx_offloads_sup =
51 DEV_TX_OFFLOAD_VLAN_INSERT |
52 DEV_TX_OFFLOAD_IPV4_CKSUM |
53 DEV_TX_OFFLOAD_UDP_CKSUM |
54 DEV_TX_OFFLOAD_TCP_CKSUM |
55 DEV_TX_OFFLOAD_SCTP_CKSUM |
56 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
57 DEV_TX_OFFLOAD_MT_LOCKFREE |
58 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
60 /* Tx offloads which cannot be disabled */
61 static uint64_t dev_tx_offloads_nodis =
62 DEV_TX_OFFLOAD_MULTI_SEGS;
64 /* enable timestamp in mbuf */
65 enum pmd_dpaa2_ts dpaa2_enable_ts;
67 struct rte_dpaa2_xstats_name_off {
68 char name[RTE_ETH_XSTATS_NAME_SIZE];
69 uint8_t page_id; /* dpni statistics page id */
70 uint8_t stats_id; /* stats id in the given page */
73 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
74 {"ingress_multicast_frames", 0, 2},
75 {"ingress_multicast_bytes", 0, 3},
76 {"ingress_broadcast_frames", 0, 4},
77 {"ingress_broadcast_bytes", 0, 5},
78 {"egress_multicast_frames", 1, 2},
79 {"egress_multicast_bytes", 1, 3},
80 {"egress_broadcast_frames", 1, 4},
81 {"egress_broadcast_bytes", 1, 5},
82 {"ingress_filtered_frames", 2, 0},
83 {"ingress_discarded_frames", 2, 1},
84 {"ingress_nobuffer_discards", 2, 2},
85 {"egress_discarded_frames", 2, 3},
86 {"egress_confirmed_frames", 2, 4},
87 {"cgr_reject_frames", 4, 0},
88 {"cgr_reject_bytes", 4, 1},
91 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
93 RTE_ETH_FILTER_DELETE,
94 RTE_ETH_FILTER_UPDATE,
99 static struct rte_dpaa2_driver rte_dpaa2_pmd;
100 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
101 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
102 int wait_to_complete);
103 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
104 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
105 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
107 int dpaa2_logtype_pmd;
110 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable)
112 dpaa2_enable_ts = enable;
116 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
119 struct dpaa2_dev_priv *priv = dev->data->dev_private;
120 struct fsl_mc_io *dpni = priv->hw;
122 PMD_INIT_FUNC_TRACE();
125 DPAA2_PMD_ERR("dpni is NULL");
130 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW,
131 priv->token, vlan_id);
133 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
134 priv->token, vlan_id);
137 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
138 ret, vlan_id, priv->hw_id);
144 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
146 struct dpaa2_dev_priv *priv = dev->data->dev_private;
147 struct fsl_mc_io *dpni = priv->hw;
150 PMD_INIT_FUNC_TRACE();
152 if (mask & ETH_VLAN_FILTER_MASK) {
153 /* VLAN Filter not avaialble */
154 if (!priv->max_vlan_filters) {
155 DPAA2_PMD_INFO("VLAN filter not available");
159 if (dev->data->dev_conf.rxmode.offloads &
160 DEV_RX_OFFLOAD_VLAN_FILTER)
161 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
164 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
167 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
170 if (mask & ETH_VLAN_EXTEND_MASK) {
171 if (dev->data->dev_conf.rxmode.offloads &
172 DEV_RX_OFFLOAD_VLAN_EXTEND)
173 DPAA2_PMD_INFO("VLAN extend offload not supported");
180 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
181 enum rte_vlan_type vlan_type __rte_unused,
184 struct dpaa2_dev_priv *priv = dev->data->dev_private;
185 struct fsl_mc_io *dpni = priv->hw;
188 PMD_INIT_FUNC_TRACE();
190 /* nothing to be done for standard vlan tpids */
191 if (tpid == 0x8100 || tpid == 0x88A8)
194 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
197 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
198 /* if already configured tpids, remove them first */
200 struct dpni_custom_tpid_cfg tpid_list = {0};
202 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
203 priv->token, &tpid_list);
206 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
207 priv->token, tpid_list.tpid1);
210 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
218 dpaa2_fw_version_get(struct rte_eth_dev *dev,
223 struct dpaa2_dev_priv *priv = dev->data->dev_private;
224 struct fsl_mc_io *dpni = priv->hw;
225 struct mc_soc_version mc_plat_info = {0};
226 struct mc_version mc_ver_info = {0};
228 PMD_INIT_FUNC_TRACE();
230 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
231 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
233 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
234 DPAA2_PMD_WARN("\tmc_get_version failed");
236 ret = snprintf(fw_version, fw_size,
241 mc_ver_info.revision);
243 ret += 1; /* add the size of '\0' */
244 if (fw_size < (uint32_t)ret)
251 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
253 struct dpaa2_dev_priv *priv = dev->data->dev_private;
255 PMD_INIT_FUNC_TRACE();
257 dev_info->if_index = priv->hw_id;
259 dev_info->max_mac_addrs = priv->max_mac_filters;
260 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
261 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
262 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
263 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
264 dev_info->rx_offload_capa = dev_rx_offloads_sup |
265 dev_rx_offloads_nodis;
266 dev_info->tx_offload_capa = dev_tx_offloads_sup |
267 dev_tx_offloads_nodis;
268 dev_info->speed_capa = ETH_LINK_SPEED_1G |
269 ETH_LINK_SPEED_2_5G |
272 dev_info->max_hash_mac_addrs = 0;
273 dev_info->max_vfs = 0;
274 dev_info->max_vmdq_pools = ETH_16_POOLS;
275 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
281 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
283 struct dpaa2_dev_priv *priv = dev->data->dev_private;
286 uint8_t num_rxqueue_per_tc;
287 struct dpaa2_queue *mc_q, *mcq;
290 struct dpaa2_queue *dpaa2_q;
292 PMD_INIT_FUNC_TRACE();
294 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
295 if (priv->tx_conf_en)
296 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
298 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
299 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
300 RTE_CACHE_LINE_SIZE);
302 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
306 for (i = 0; i < priv->nb_rx_queues; i++) {
307 mc_q->eth_data = dev->data;
308 priv->rx_vq[i] = mc_q++;
309 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
310 dpaa2_q->q_storage = rte_malloc("dq_storage",
311 sizeof(struct queue_storage_info_t),
312 RTE_CACHE_LINE_SIZE);
313 if (!dpaa2_q->q_storage)
316 memset(dpaa2_q->q_storage, 0,
317 sizeof(struct queue_storage_info_t));
318 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
322 for (i = 0; i < priv->nb_tx_queues; i++) {
323 mc_q->eth_data = dev->data;
324 mc_q->flow_id = 0xffff;
325 priv->tx_vq[i] = mc_q++;
326 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
327 dpaa2_q->cscn = rte_malloc(NULL,
328 sizeof(struct qbman_result), 16);
333 if (priv->tx_conf_en) {
334 /*Setup tx confirmation queues*/
335 for (i = 0; i < priv->nb_tx_queues; i++) {
336 mc_q->eth_data = dev->data;
339 priv->tx_conf_vq[i] = mc_q++;
340 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
342 rte_malloc("dq_storage",
343 sizeof(struct queue_storage_info_t),
344 RTE_CACHE_LINE_SIZE);
345 if (!dpaa2_q->q_storage)
348 memset(dpaa2_q->q_storage, 0,
349 sizeof(struct queue_storage_info_t));
350 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
356 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
357 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
358 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
359 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
367 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
368 rte_free(dpaa2_q->q_storage);
369 priv->tx_conf_vq[i--] = NULL;
371 i = priv->nb_tx_queues;
375 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
376 rte_free(dpaa2_q->cscn);
377 priv->tx_vq[i--] = NULL;
379 i = priv->nb_rx_queues;
382 mc_q = priv->rx_vq[0];
384 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
385 dpaa2_free_dq_storage(dpaa2_q->q_storage);
386 rte_free(dpaa2_q->q_storage);
387 priv->rx_vq[i--] = NULL;
394 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
396 struct dpaa2_dev_priv *priv = dev->data->dev_private;
397 struct dpaa2_queue *dpaa2_q;
400 PMD_INIT_FUNC_TRACE();
402 /* Queue allocation base */
403 if (priv->rx_vq[0]) {
404 /* cleaning up queue storage */
405 for (i = 0; i < priv->nb_rx_queues; i++) {
406 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
407 if (dpaa2_q->q_storage)
408 rte_free(dpaa2_q->q_storage);
410 /* cleanup tx queue cscn */
411 for (i = 0; i < priv->nb_tx_queues; i++) {
412 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
413 rte_free(dpaa2_q->cscn);
415 if (priv->tx_conf_en) {
416 /* cleanup tx conf queue storage */
417 for (i = 0; i < priv->nb_tx_queues; i++) {
418 dpaa2_q = (struct dpaa2_queue *)
420 rte_free(dpaa2_q->q_storage);
423 /*free memory for all queues (RX+TX) */
424 rte_free(priv->rx_vq[0]);
425 priv->rx_vq[0] = NULL;
430 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
432 struct dpaa2_dev_priv *priv = dev->data->dev_private;
433 struct fsl_mc_io *dpni = priv->hw;
434 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
435 uint64_t rx_offloads = eth_conf->rxmode.offloads;
436 uint64_t tx_offloads = eth_conf->txmode.offloads;
437 int rx_l3_csum_offload = false;
438 int rx_l4_csum_offload = false;
439 int tx_l3_csum_offload = false;
440 int tx_l4_csum_offload = false;
443 PMD_INIT_FUNC_TRACE();
445 /* Rx offloads which are enabled by default */
446 if (dev_rx_offloads_nodis & ~rx_offloads) {
448 "Some of rx offloads enabled by default - requested 0x%" PRIx64
449 " fixed are 0x%" PRIx64,
450 rx_offloads, dev_rx_offloads_nodis);
453 /* Tx offloads which are enabled by default */
454 if (dev_tx_offloads_nodis & ~tx_offloads) {
456 "Some of tx offloads enabled by default - requested 0x%" PRIx64
457 " fixed are 0x%" PRIx64,
458 tx_offloads, dev_tx_offloads_nodis);
461 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
462 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
463 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
464 priv->token, eth_conf->rxmode.max_rx_pkt_len
465 - RTE_ETHER_CRC_LEN);
468 "Unable to set mtu. check config");
472 dev->data->dev_conf.rxmode.max_rx_pkt_len -
473 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
480 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
481 ret = dpaa2_setup_flow_dist(dev,
482 eth_conf->rx_adv_conf.rss_conf.rss_hf);
484 DPAA2_PMD_ERR("Unable to set flow distribution."
485 "Check queue config");
490 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
491 rx_l3_csum_offload = true;
493 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
494 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
495 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
496 rx_l4_csum_offload = true;
498 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
499 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
501 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
505 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
506 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
508 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
512 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
513 dpaa2_enable_ts = true;
515 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
516 tx_l3_csum_offload = true;
518 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
519 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
520 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
521 tx_l4_csum_offload = true;
523 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
524 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
526 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
530 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
531 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
533 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
537 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
538 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
539 * to 0 for LS2 in the hardware thus disabling data/annotation
540 * stashing. For LX2 this is fixed in hardware and thus hash result and
541 * parse results can be received in FD using this option.
543 if (dpaa2_svr_family == SVR_LX2160A) {
544 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
545 DPNI_FLCTYPE_HASH, true);
547 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
552 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
553 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
555 /* update the current status */
556 dpaa2_dev_link_update(dev, 0);
561 /* Function to setup RX flow information. It contains traffic class ID,
562 * flow ID, destination configuration etc.
565 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
566 uint16_t rx_queue_id,
568 unsigned int socket_id __rte_unused,
569 const struct rte_eth_rxconf *rx_conf __rte_unused,
570 struct rte_mempool *mb_pool)
572 struct dpaa2_dev_priv *priv = dev->data->dev_private;
573 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
574 struct dpaa2_queue *dpaa2_q;
575 struct dpni_queue cfg;
581 PMD_INIT_FUNC_TRACE();
583 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
584 dev, rx_queue_id, mb_pool, rx_conf);
586 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
587 bpid = mempool_to_bpid(mb_pool);
588 ret = dpaa2_attach_bp_list(priv,
589 rte_dpaa2_bpid_info[bpid].bp_list);
593 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
594 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
595 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
597 /*Get the flow id from given VQ id*/
598 flow_id = dpaa2_q->flow_id;
599 memset(&cfg, 0, sizeof(struct dpni_queue));
601 options = options | DPNI_QUEUE_OPT_USER_CTX;
602 cfg.user_context = (size_t)(dpaa2_q);
604 /* check if a private cgr available. */
605 for (i = 0; i < priv->max_cgs; i++) {
606 if (!priv->cgid_in_use[i]) {
607 priv->cgid_in_use[i] = 1;
612 if (i < priv->max_cgs) {
613 options |= DPNI_QUEUE_OPT_SET_CGID;
615 dpaa2_q->cgid = cfg.cgid;
617 dpaa2_q->cgid = 0xff;
620 /*if ls2088 or rev2 device, enable the stashing */
622 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
623 options |= DPNI_QUEUE_OPT_FLC;
624 cfg.flc.stash_control = true;
625 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
626 /* 00 00 00 - last 6 bit represent annotation, context stashing,
627 * data stashing setting 01 01 00 (0x14)
628 * (in following order ->DS AS CS)
629 * to enable 1 line data, 1 line annotation.
630 * For LX2, this setting should be 01 00 00 (0x10)
632 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
633 cfg.flc.value |= 0x10;
635 cfg.flc.value |= 0x14;
637 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
638 dpaa2_q->tc_index, flow_id, options, &cfg);
640 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
644 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
645 struct dpni_taildrop taildrop;
649 /* Private CGR will use tail drop length as nb_rx_desc.
650 * for rest cases we can use standard byte based tail drop.
651 * There is no HW restriction, but number of CGRs are limited,
652 * hence this restriction is placed.
654 if (dpaa2_q->cgid != 0xff) {
655 /*enabling per rx queue congestion control */
656 taildrop.threshold = nb_rx_desc;
657 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
659 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
661 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
662 DPNI_CP_CONGESTION_GROUP,
667 /*enabling per rx queue congestion control */
668 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
669 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
670 taildrop.oal = CONG_RX_OAL;
671 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
673 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
674 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
675 dpaa2_q->tc_index, flow_id,
679 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
683 } else { /* Disable tail Drop */
684 struct dpni_taildrop taildrop = {0};
685 DPAA2_PMD_INFO("Tail drop is disabled on queue");
688 if (dpaa2_q->cgid != 0xff) {
689 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
690 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
694 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
695 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
696 dpaa2_q->tc_index, flow_id, &taildrop);
699 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
705 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
710 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
711 uint16_t tx_queue_id,
712 uint16_t nb_tx_desc __rte_unused,
713 unsigned int socket_id __rte_unused,
714 const struct rte_eth_txconf *tx_conf __rte_unused)
716 struct dpaa2_dev_priv *priv = dev->data->dev_private;
717 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
718 priv->tx_vq[tx_queue_id];
719 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
720 priv->tx_conf_vq[tx_queue_id];
721 struct fsl_mc_io *dpni = priv->hw;
722 struct dpni_queue tx_conf_cfg;
723 struct dpni_queue tx_flow_cfg;
724 uint8_t options = 0, flow_id;
725 struct dpni_queue_id qid;
729 PMD_INIT_FUNC_TRACE();
731 /* Return if queue already configured */
732 if (dpaa2_q->flow_id != 0xffff) {
733 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
737 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
738 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
743 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
744 tc_id, flow_id, options, &tx_flow_cfg);
746 DPAA2_PMD_ERR("Error in setting the tx flow: "
747 "tc_id=%d, flow=%d err=%d",
748 tc_id, flow_id, ret);
752 dpaa2_q->flow_id = flow_id;
754 if (tx_queue_id == 0) {
755 /*Set tx-conf and error configuration*/
756 if (priv->tx_conf_en)
757 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
761 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
765 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
770 dpaa2_q->tc_index = tc_id;
772 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
773 DPNI_QUEUE_TX, dpaa2_q->tc_index,
774 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
776 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
779 dpaa2_q->fqid = qid.fqid;
781 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
782 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
784 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
785 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
786 /* Notify that the queue is not congested when the data in
787 * the queue is below this thershold.
789 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
790 cong_notif_cfg.message_ctx = 0;
791 cong_notif_cfg.message_iova =
792 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
793 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
794 cong_notif_cfg.notification_mode =
795 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
796 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
797 DPNI_CONG_OPT_COHERENT_WRITE;
798 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
800 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
807 "Error in setting tx congestion notification: "
812 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
813 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
815 if (priv->tx_conf_en) {
816 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
817 options = options | DPNI_QUEUE_OPT_USER_CTX;
818 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
819 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
820 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
821 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
823 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
824 "tc_index=%d, flow=%d err=%d",
825 dpaa2_tx_conf_q->tc_index,
826 dpaa2_tx_conf_q->flow_id, ret);
830 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
831 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
832 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
834 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
837 dpaa2_tx_conf_q->fqid = qid.fqid;
843 dpaa2_dev_rx_queue_release(void *q __rte_unused)
845 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
846 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
847 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
850 struct dpni_queue cfg;
852 memset(&cfg, 0, sizeof(struct dpni_queue));
853 PMD_INIT_FUNC_TRACE();
854 if (dpaa2_q->cgid != 0xff) {
855 options = DPNI_QUEUE_OPT_CLEAR_CGID;
856 cfg.cgid = dpaa2_q->cgid;
858 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
860 dpaa2_q->tc_index, dpaa2_q->flow_id,
863 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
865 priv->cgid_in_use[dpaa2_q->cgid] = 0;
866 dpaa2_q->cgid = 0xff;
871 dpaa2_dev_tx_queue_release(void *q __rte_unused)
873 PMD_INIT_FUNC_TRACE();
877 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
880 struct dpaa2_dev_priv *priv = dev->data->dev_private;
881 struct dpaa2_queue *dpaa2_q;
882 struct qbman_swp *swp;
883 struct qbman_fq_query_np_rslt state;
884 uint32_t frame_cnt = 0;
886 PMD_INIT_FUNC_TRACE();
888 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
889 ret = dpaa2_affine_qbman_swp();
891 DPAA2_PMD_ERR("Failure in affining portal");
895 swp = DPAA2_PER_LCORE_PORTAL;
897 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
899 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
900 frame_cnt = qbman_fq_state_frame_count(&state);
901 DPAA2_PMD_DEBUG("RX frame count for q(%d) is %u",
902 rx_queue_id, frame_cnt);
907 static const uint32_t *
908 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
910 static const uint32_t ptypes[] = {
911 /*todo -= add more types */
914 RTE_PTYPE_L3_IPV4_EXT,
916 RTE_PTYPE_L3_IPV6_EXT,
924 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
925 dev->rx_pkt_burst == dpaa2_dev_rx ||
926 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
932 * Dpaa2 link Interrupt handler
935 * The address of parameter (struct rte_eth_dev *) regsitered before.
941 dpaa2_interrupt_handler(void *param)
943 struct rte_eth_dev *dev = param;
944 struct dpaa2_dev_priv *priv = dev->data->dev_private;
945 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
947 int irq_index = DPNI_IRQ_INDEX;
948 unsigned int status = 0, clear = 0;
950 PMD_INIT_FUNC_TRACE();
953 DPAA2_PMD_ERR("dpni is NULL");
957 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
960 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
965 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
966 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
967 dpaa2_dev_link_update(dev, 0);
968 /* calling all the apps registered for link status event */
969 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
973 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
976 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
980 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
983 struct dpaa2_dev_priv *priv = dev->data->dev_private;
984 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
985 int irq_index = DPNI_IRQ_INDEX;
986 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
988 PMD_INIT_FUNC_TRACE();
990 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
993 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
998 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1001 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1008 dpaa2_dev_start(struct rte_eth_dev *dev)
1010 struct rte_device *rdev = dev->device;
1011 struct rte_dpaa2_device *dpaa2_dev;
1012 struct rte_eth_dev_data *data = dev->data;
1013 struct dpaa2_dev_priv *priv = data->dev_private;
1014 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1015 struct dpni_queue cfg;
1016 struct dpni_error_cfg err_cfg;
1018 struct dpni_queue_id qid;
1019 struct dpaa2_queue *dpaa2_q;
1021 struct rte_intr_handle *intr_handle;
1023 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1024 intr_handle = &dpaa2_dev->intr_handle;
1026 PMD_INIT_FUNC_TRACE();
1028 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1030 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1035 /* Power up the phy. Needed to make the link go UP */
1036 dpaa2_dev_set_link_up(dev);
1038 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1039 DPNI_QUEUE_TX, &qdid);
1041 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1046 for (i = 0; i < data->nb_rx_queues; i++) {
1047 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1048 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1049 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1050 dpaa2_q->flow_id, &cfg, &qid);
1052 DPAA2_PMD_ERR("Error in getting flow information: "
1056 dpaa2_q->fqid = qid.fqid;
1059 /*checksum errors, send them to normal path and set it in annotation */
1060 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1061 err_cfg.errors |= DPNI_ERROR_PHE;
1063 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1064 err_cfg.set_frame_annotation = true;
1066 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1067 priv->token, &err_cfg);
1069 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1074 /* if the interrupts were configured on this devices*/
1075 if (intr_handle && (intr_handle->fd) &&
1076 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1077 /* Registering LSC interrupt handler */
1078 rte_intr_callback_register(intr_handle,
1079 dpaa2_interrupt_handler,
1082 /* enable vfio intr/eventfd mapping
1083 * Interrupt index 0 is required, so we can not use
1086 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1088 /* enable dpni_irqs */
1089 dpaa2_eth_setup_irqs(dev, 1);
1092 /* Change the tx burst function if ordered queues are used */
1093 if (priv->en_ordered)
1094 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1100 * This routine disables all traffic on the adapter by issuing a
1101 * global reset on the MAC.
1104 dpaa2_dev_stop(struct rte_eth_dev *dev)
1106 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1107 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1109 struct rte_eth_link link;
1110 struct rte_intr_handle *intr_handle = dev->intr_handle;
1112 PMD_INIT_FUNC_TRACE();
1114 /* reset interrupt callback */
1115 if (intr_handle && (intr_handle->fd) &&
1116 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1117 /*disable dpni irqs */
1118 dpaa2_eth_setup_irqs(dev, 0);
1120 /* disable vfio intr before callback unregister */
1121 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1123 /* Unregistering LSC interrupt handler */
1124 rte_intr_callback_unregister(intr_handle,
1125 dpaa2_interrupt_handler,
1129 dpaa2_dev_set_link_down(dev);
1131 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1133 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1138 /* clear the recorded link status */
1139 memset(&link, 0, sizeof(link));
1140 rte_eth_linkstatus_set(dev, &link);
1144 dpaa2_dev_close(struct rte_eth_dev *dev)
1146 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1147 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1149 struct rte_eth_link link;
1151 PMD_INIT_FUNC_TRACE();
1153 dpaa2_flow_clean(dev);
1155 /* Clean the device first */
1156 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1158 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1162 memset(&link, 0, sizeof(link));
1163 rte_eth_linkstatus_set(dev, &link);
1167 dpaa2_dev_promiscuous_enable(
1168 struct rte_eth_dev *dev)
1171 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1172 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1174 PMD_INIT_FUNC_TRACE();
1177 DPAA2_PMD_ERR("dpni is NULL");
1181 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1183 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1185 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1187 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1193 dpaa2_dev_promiscuous_disable(
1194 struct rte_eth_dev *dev)
1197 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1198 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1200 PMD_INIT_FUNC_TRACE();
1203 DPAA2_PMD_ERR("dpni is NULL");
1207 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1209 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1211 if (dev->data->all_multicast == 0) {
1212 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1213 priv->token, false);
1215 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1223 dpaa2_dev_allmulticast_enable(
1224 struct rte_eth_dev *dev)
1227 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1228 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1230 PMD_INIT_FUNC_TRACE();
1233 DPAA2_PMD_ERR("dpni is NULL");
1237 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1239 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1245 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1248 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1249 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1251 PMD_INIT_FUNC_TRACE();
1254 DPAA2_PMD_ERR("dpni is NULL");
1258 /* must remain on for all promiscuous */
1259 if (dev->data->promiscuous == 1)
1262 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1264 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1270 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1273 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1274 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1275 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1278 PMD_INIT_FUNC_TRACE();
1281 DPAA2_PMD_ERR("dpni is NULL");
1285 /* check that mtu is within the allowed range */
1286 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1289 if (frame_size > RTE_ETHER_MAX_LEN)
1290 dev->data->dev_conf.rxmode.offloads &=
1291 DEV_RX_OFFLOAD_JUMBO_FRAME;
1293 dev->data->dev_conf.rxmode.offloads &=
1294 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1296 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1298 /* Set the Max Rx frame length as 'mtu' +
1299 * Maximum Ethernet header length
1301 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1302 frame_size - RTE_ETHER_CRC_LEN);
1304 DPAA2_PMD_ERR("Setting the max frame length failed");
1307 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1312 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1313 struct rte_ether_addr *addr,
1314 __rte_unused uint32_t index,
1315 __rte_unused uint32_t pool)
1318 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1319 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1321 PMD_INIT_FUNC_TRACE();
1324 DPAA2_PMD_ERR("dpni is NULL");
1328 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW,
1329 priv->token, addr->addr_bytes);
1332 "error: Adding the MAC ADDR failed: err = %d", ret);
1337 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1341 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1342 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1343 struct rte_eth_dev_data *data = dev->data;
1344 struct rte_ether_addr *macaddr;
1346 PMD_INIT_FUNC_TRACE();
1348 macaddr = &data->mac_addrs[index];
1351 DPAA2_PMD_ERR("dpni is NULL");
1355 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1356 priv->token, macaddr->addr_bytes);
1359 "error: Removing the MAC ADDR failed: err = %d", ret);
1363 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1364 struct rte_ether_addr *addr)
1367 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1368 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1370 PMD_INIT_FUNC_TRACE();
1373 DPAA2_PMD_ERR("dpni is NULL");
1377 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1378 priv->token, addr->addr_bytes);
1382 "error: Setting the MAC ADDR failed %d", ret);
1388 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1389 struct rte_eth_stats *stats)
1391 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1392 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1394 uint8_t page0 = 0, page1 = 1, page2 = 2;
1395 union dpni_statistics value;
1397 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1399 memset(&value, 0, sizeof(union dpni_statistics));
1401 PMD_INIT_FUNC_TRACE();
1404 DPAA2_PMD_ERR("dpni is NULL");
1409 DPAA2_PMD_ERR("stats is NULL");
1413 /*Get Counters from page_0*/
1414 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1419 stats->ipackets = value.page_0.ingress_all_frames;
1420 stats->ibytes = value.page_0.ingress_all_bytes;
1422 /*Get Counters from page_1*/
1423 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1428 stats->opackets = value.page_1.egress_all_frames;
1429 stats->obytes = value.page_1.egress_all_bytes;
1431 /*Get Counters from page_2*/
1432 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1437 /* Ingress drop frame count due to configured rules */
1438 stats->ierrors = value.page_2.ingress_filtered_frames;
1439 /* Ingress drop frame count due to error */
1440 stats->ierrors += value.page_2.ingress_discarded_frames;
1442 stats->oerrors = value.page_2.egress_discarded_frames;
1443 stats->imissed = value.page_2.ingress_nobuffer_discards;
1445 /* Fill in per queue stats */
1446 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1447 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1448 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1449 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1451 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1453 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1455 /* Byte counting is not implemented */
1456 stats->q_ibytes[i] = 0;
1457 stats->q_obytes[i] = 0;
1463 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1468 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1471 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1472 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1474 union dpni_statistics value[5] = {};
1475 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1483 /* Get Counters from page_0*/
1484 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1489 /* Get Counters from page_1*/
1490 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1495 /* Get Counters from page_2*/
1496 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1501 for (i = 0; i < priv->max_cgs; i++) {
1502 if (!priv->cgid_in_use[i]) {
1503 /* Get Counters from page_4*/
1504 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1513 for (i = 0; i < num; i++) {
1515 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1516 raw.counter[dpaa2_xstats_strings[i].stats_id];
1520 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1525 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1526 struct rte_eth_xstat_name *xstats_names,
1529 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1531 if (limit < stat_cnt)
1534 if (xstats_names != NULL)
1535 for (i = 0; i < stat_cnt; i++)
1536 strlcpy(xstats_names[i].name,
1537 dpaa2_xstats_strings[i].name,
1538 sizeof(xstats_names[i].name));
1544 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1545 uint64_t *values, unsigned int n)
1547 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1548 uint64_t values_copy[stat_cnt];
1551 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1552 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1554 union dpni_statistics value[5] = {};
1562 /* Get Counters from page_0*/
1563 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1568 /* Get Counters from page_1*/
1569 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1574 /* Get Counters from page_2*/
1575 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1580 /* Get Counters from page_4*/
1581 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1586 for (i = 0; i < stat_cnt; i++) {
1587 values[i] = value[dpaa2_xstats_strings[i].page_id].
1588 raw.counter[dpaa2_xstats_strings[i].stats_id];
1593 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1595 for (i = 0; i < n; i++) {
1596 if (ids[i] >= stat_cnt) {
1597 DPAA2_PMD_ERR("xstats id value isn't valid");
1600 values[i] = values_copy[ids[i]];
1606 dpaa2_xstats_get_names_by_id(
1607 struct rte_eth_dev *dev,
1608 struct rte_eth_xstat_name *xstats_names,
1609 const uint64_t *ids,
1612 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1613 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1616 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1618 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1620 for (i = 0; i < limit; i++) {
1621 if (ids[i] >= stat_cnt) {
1622 DPAA2_PMD_ERR("xstats id value isn't valid");
1625 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1631 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1633 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1634 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1637 struct dpaa2_queue *dpaa2_q;
1639 PMD_INIT_FUNC_TRACE();
1642 DPAA2_PMD_ERR("dpni is NULL");
1646 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1650 /* Reset the per queue stats in dpaa2_queue structure */
1651 for (i = 0; i < priv->nb_rx_queues; i++) {
1652 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1654 dpaa2_q->rx_pkts = 0;
1657 for (i = 0; i < priv->nb_tx_queues; i++) {
1658 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1660 dpaa2_q->tx_pkts = 0;
1666 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1670 /* return 0 means link status changed, -1 means not changed */
1672 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1673 int wait_to_complete __rte_unused)
1676 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1677 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1678 struct rte_eth_link link;
1679 struct dpni_link_state state = {0};
1682 DPAA2_PMD_ERR("dpni is NULL");
1686 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1688 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1692 memset(&link, 0, sizeof(struct rte_eth_link));
1693 link.link_status = state.up;
1694 link.link_speed = state.rate;
1696 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1697 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1699 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1701 ret = rte_eth_linkstatus_set(dev, &link);
1703 DPAA2_PMD_DEBUG("No change in status");
1705 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1706 link.link_status ? "Up" : "Down");
1712 * Toggle the DPNI to enable, if not already enabled.
1713 * This is not strictly PHY up/down - it is more of logical toggling.
1716 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1719 struct dpaa2_dev_priv *priv;
1720 struct fsl_mc_io *dpni;
1722 struct dpni_link_state state = {0};
1724 priv = dev->data->dev_private;
1725 dpni = (struct fsl_mc_io *)priv->hw;
1728 DPAA2_PMD_ERR("dpni is NULL");
1732 /* Check if DPNI is currently enabled */
1733 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1735 /* Unable to obtain dpni status; Not continuing */
1736 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1740 /* Enable link if not already enabled */
1742 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1744 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1748 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1750 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1754 /* changing tx burst function to start enqueues */
1755 dev->tx_pkt_burst = dpaa2_dev_tx;
1756 dev->data->dev_link.link_status = state.up;
1759 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1761 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1766 * Toggle the DPNI to disable, if not already disabled.
1767 * This is not strictly PHY up/down - it is more of logical toggling.
1770 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1773 struct dpaa2_dev_priv *priv;
1774 struct fsl_mc_io *dpni;
1775 int dpni_enabled = 0;
1778 PMD_INIT_FUNC_TRACE();
1780 priv = dev->data->dev_private;
1781 dpni = (struct fsl_mc_io *)priv->hw;
1784 DPAA2_PMD_ERR("Device has not yet been configured");
1788 /*changing tx burst function to avoid any more enqueues */
1789 dev->tx_pkt_burst = dummy_dev_tx;
1791 /* Loop while dpni_disable() attempts to drain the egress FQs
1792 * and confirm them back to us.
1795 ret = dpni_disable(dpni, 0, priv->token);
1797 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1800 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1802 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1806 /* Allow the MC some slack */
1807 rte_delay_us(100 * 1000);
1808 } while (dpni_enabled && --retries);
1811 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1812 /* todo- we may have to manually cleanup queues.
1815 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1816 dev->data->port_id);
1819 dev->data->dev_link.link_status = 0;
1825 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1828 struct dpaa2_dev_priv *priv;
1829 struct fsl_mc_io *dpni;
1830 struct dpni_link_state state = {0};
1832 PMD_INIT_FUNC_TRACE();
1834 priv = dev->data->dev_private;
1835 dpni = (struct fsl_mc_io *)priv->hw;
1837 if (dpni == NULL || fc_conf == NULL) {
1838 DPAA2_PMD_ERR("device not configured");
1842 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1844 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1848 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1849 if (state.options & DPNI_LINK_OPT_PAUSE) {
1850 /* DPNI_LINK_OPT_PAUSE set
1851 * if ASYM_PAUSE not set,
1852 * RX Side flow control (handle received Pause frame)
1853 * TX side flow control (send Pause frame)
1854 * if ASYM_PAUSE set,
1855 * RX Side flow control (handle received Pause frame)
1856 * No TX side flow control (send Pause frame disabled)
1858 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1859 fc_conf->mode = RTE_FC_FULL;
1861 fc_conf->mode = RTE_FC_RX_PAUSE;
1863 /* DPNI_LINK_OPT_PAUSE not set
1864 * if ASYM_PAUSE set,
1865 * TX side flow control (send Pause frame)
1866 * No RX side flow control (No action on pause frame rx)
1867 * if ASYM_PAUSE not set,
1868 * Flow control disabled
1870 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1871 fc_conf->mode = RTE_FC_TX_PAUSE;
1873 fc_conf->mode = RTE_FC_NONE;
1880 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1883 struct dpaa2_dev_priv *priv;
1884 struct fsl_mc_io *dpni;
1885 struct dpni_link_state state = {0};
1886 struct dpni_link_cfg cfg = {0};
1888 PMD_INIT_FUNC_TRACE();
1890 priv = dev->data->dev_private;
1891 dpni = (struct fsl_mc_io *)priv->hw;
1894 DPAA2_PMD_ERR("dpni is NULL");
1898 /* It is necessary to obtain the current state before setting fc_conf
1899 * as MC would return error in case rate, autoneg or duplex values are
1902 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1904 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
1908 /* Disable link before setting configuration */
1909 dpaa2_dev_set_link_down(dev);
1911 /* Based on fc_conf, update cfg */
1912 cfg.rate = state.rate;
1913 cfg.options = state.options;
1915 /* update cfg with fc_conf */
1916 switch (fc_conf->mode) {
1918 /* Full flow control;
1919 * OPT_PAUSE set, ASYM_PAUSE not set
1921 cfg.options |= DPNI_LINK_OPT_PAUSE;
1922 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1924 case RTE_FC_TX_PAUSE:
1925 /* Enable RX flow control
1926 * OPT_PAUSE not set;
1929 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1930 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1932 case RTE_FC_RX_PAUSE:
1933 /* Enable TX Flow control
1937 cfg.options |= DPNI_LINK_OPT_PAUSE;
1938 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1941 /* Disable Flow control
1943 * ASYM_PAUSE not set
1945 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1946 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1949 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
1954 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
1956 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
1960 dpaa2_dev_set_link_up(dev);
1966 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
1967 struct rte_eth_rss_conf *rss_conf)
1969 struct rte_eth_dev_data *data = dev->data;
1970 struct rte_eth_conf *eth_conf = &data->dev_conf;
1973 PMD_INIT_FUNC_TRACE();
1975 if (rss_conf->rss_hf) {
1976 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf);
1978 DPAA2_PMD_ERR("Unable to set flow dist");
1982 ret = dpaa2_remove_flow_dist(dev, 0);
1984 DPAA2_PMD_ERR("Unable to remove flow dist");
1988 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1993 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1994 struct rte_eth_rss_conf *rss_conf)
1996 struct rte_eth_dev_data *data = dev->data;
1997 struct rte_eth_conf *eth_conf = &data->dev_conf;
1999 /* dpaa2 does not support rss_key, so length should be 0*/
2000 rss_conf->rss_key_len = 0;
2001 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2005 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2006 int eth_rx_queue_id,
2008 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2010 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2011 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw;
2012 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2013 uint8_t flow_id = dpaa2_ethq->flow_id;
2014 struct dpni_queue cfg;
2018 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2019 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2020 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2021 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2022 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2023 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2027 memset(&cfg, 0, sizeof(struct dpni_queue));
2028 options = DPNI_QUEUE_OPT_DEST;
2029 cfg.destination.type = DPNI_DEST_DPCON;
2030 cfg.destination.id = dpcon_id;
2031 cfg.destination.priority = queue_conf->ev.priority;
2033 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2034 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2035 cfg.destination.hold_active = 1;
2038 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2039 !eth_priv->en_ordered) {
2040 struct opr_cfg ocfg;
2042 /* Restoration window size = 256 frames */
2044 /* Restoration window size = 512 frames for LX2 */
2045 if (dpaa2_svr_family == SVR_LX2160A)
2047 /* Auto advance NESN window enabled */
2049 /* Late arrival window size disabled */
2051 /* ORL resource exhaustaion advance NESN disabled */
2053 /* Loose ordering enabled */
2055 eth_priv->en_loose_ordered = 1;
2056 /* Strict ordering enabled if explicitly set */
2057 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2059 eth_priv->en_loose_ordered = 0;
2062 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2063 dpaa2_ethq->tc_index, flow_id,
2064 OPR_OPT_CREATE, &ocfg);
2066 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2070 eth_priv->en_ordered = 1;
2073 options |= DPNI_QUEUE_OPT_USER_CTX;
2074 cfg.user_context = (size_t)(dpaa2_ethq);
2076 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2077 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2079 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2083 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2088 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2089 int eth_rx_queue_id)
2091 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2092 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw;
2093 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2094 uint8_t flow_id = dpaa2_ethq->flow_id;
2095 struct dpni_queue cfg;
2099 memset(&cfg, 0, sizeof(struct dpni_queue));
2100 options = DPNI_QUEUE_OPT_DEST;
2101 cfg.destination.type = DPNI_DEST_NONE;
2103 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2104 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2106 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2112 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2116 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2117 if (dpaa2_supported_filter_ops[i] == filter_op)
2124 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2125 enum rte_filter_type filter_type,
2126 enum rte_filter_op filter_op,
2134 switch (filter_type) {
2135 case RTE_ETH_FILTER_GENERIC:
2136 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2140 *(const void **)arg = &dpaa2_flow_ops;
2141 dpaa2_filter_type |= filter_type;
2144 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2152 static struct eth_dev_ops dpaa2_ethdev_ops = {
2153 .dev_configure = dpaa2_eth_dev_configure,
2154 .dev_start = dpaa2_dev_start,
2155 .dev_stop = dpaa2_dev_stop,
2156 .dev_close = dpaa2_dev_close,
2157 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2158 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2159 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2160 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2161 .dev_set_link_up = dpaa2_dev_set_link_up,
2162 .dev_set_link_down = dpaa2_dev_set_link_down,
2163 .link_update = dpaa2_dev_link_update,
2164 .stats_get = dpaa2_dev_stats_get,
2165 .xstats_get = dpaa2_dev_xstats_get,
2166 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2167 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2168 .xstats_get_names = dpaa2_xstats_get_names,
2169 .stats_reset = dpaa2_dev_stats_reset,
2170 .xstats_reset = dpaa2_dev_stats_reset,
2171 .fw_version_get = dpaa2_fw_version_get,
2172 .dev_infos_get = dpaa2_dev_info_get,
2173 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2174 .mtu_set = dpaa2_dev_mtu_set,
2175 .vlan_filter_set = dpaa2_vlan_filter_set,
2176 .vlan_offload_set = dpaa2_vlan_offload_set,
2177 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2178 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2179 .rx_queue_release = dpaa2_dev_rx_queue_release,
2180 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2181 .tx_queue_release = dpaa2_dev_tx_queue_release,
2182 .rx_queue_count = dpaa2_dev_rx_queue_count,
2183 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2184 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2185 .mac_addr_add = dpaa2_dev_add_mac_addr,
2186 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2187 .mac_addr_set = dpaa2_dev_set_mac_addr,
2188 .rss_hash_update = dpaa2_dev_rss_hash_update,
2189 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2190 .filter_ctrl = dpaa2_dev_flow_ctrl,
2193 /* Populate the mac address from physically available (u-boot/firmware) and/or
2194 * one set by higher layers like MC (restool) etc.
2195 * Returns the table of MAC entries (multiple entries)
2198 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2199 struct rte_ether_addr *mac_entry)
2202 struct rte_ether_addr phy_mac, prime_mac;
2204 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2205 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2207 /* Get the physical device MAC address */
2208 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2209 phy_mac.addr_bytes);
2211 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2215 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2216 prime_mac.addr_bytes);
2218 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2222 /* Now that both MAC have been obtained, do:
2223 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2225 * If empty_mac(phy), return prime.
2226 * if both are empty, create random MAC, set as prime and return
2228 if (!rte_is_zero_ether_addr(&phy_mac)) {
2229 /* If the addresses are not same, overwrite prime */
2230 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2231 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2233 phy_mac.addr_bytes);
2235 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2239 memcpy(&prime_mac, &phy_mac,
2240 sizeof(struct rte_ether_addr));
2242 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2243 /* In case phys and prime, both are zero, create random MAC */
2244 rte_eth_random_addr(prime_mac.addr_bytes);
2245 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2247 prime_mac.addr_bytes);
2249 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2254 /* prime_mac the final MAC address */
2255 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2263 check_devargs_handler(__rte_unused const char *key, const char *value,
2264 __rte_unused void *opaque)
2266 if (strcmp(value, "1"))
2273 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2275 struct rte_kvargs *kvlist;
2280 kvlist = rte_kvargs_parse(devargs->args, NULL);
2284 if (!rte_kvargs_count(kvlist, key)) {
2285 rte_kvargs_free(kvlist);
2289 if (rte_kvargs_process(kvlist, key,
2290 check_devargs_handler, NULL) < 0) {
2291 rte_kvargs_free(kvlist);
2294 rte_kvargs_free(kvlist);
2300 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2302 struct rte_device *dev = eth_dev->device;
2303 struct rte_dpaa2_device *dpaa2_dev;
2304 struct fsl_mc_io *dpni_dev;
2305 struct dpni_attr attr;
2306 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2307 struct dpni_buffer_layout layout;
2310 PMD_INIT_FUNC_TRACE();
2312 /* For secondary processes, the primary has done all the work */
2313 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2314 /* In case of secondary, only burst and ops API need to be
2317 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2318 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2319 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2320 else if (dpaa2_get_devargs(dev->devargs,
2321 DRIVER_NO_PREFETCH_MODE))
2322 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2324 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2325 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2329 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2331 hw_id = dpaa2_dev->object_id;
2333 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2335 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2339 dpni_dev->regs = rte_mcp_ptr_list[0];
2340 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2343 "Failure in opening dpni@%d with err code %d",
2349 /* Clean the device first */
2350 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2352 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2357 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2360 "Failure in get dpni@%d attribute, err code %d",
2365 priv->num_rx_tc = attr.num_rx_tcs;
2366 /* only if the custom CG is enabled */
2367 if (attr.options & DPNI_OPT_CUSTOM_CG)
2368 priv->max_cgs = attr.num_cgs;
2372 for (i = 0; i < priv->max_cgs; i++)
2373 priv->cgid_in_use[i] = 0;
2375 for (i = 0; i < attr.num_rx_tcs; i++)
2376 priv->nb_rx_queues += attr.num_queues;
2378 /* Using number of TX queues as number of TX TCs */
2379 priv->nb_tx_queues = attr.num_tx_tcs;
2381 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2382 priv->num_rx_tc, priv->nb_rx_queues,
2383 priv->nb_tx_queues, priv->max_cgs);
2385 priv->hw = dpni_dev;
2386 priv->hw_id = hw_id;
2387 priv->options = attr.options;
2388 priv->max_mac_filters = attr.mac_filter_entries;
2389 priv->max_vlan_filters = attr.vlan_filter_entries;
2391 #if defined(RTE_LIBRTE_IEEE1588)
2392 priv->tx_conf_en = 1;
2394 priv->tx_conf_en = 0;
2397 /* Allocate memory for hardware structure for queues */
2398 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2400 DPAA2_PMD_ERR("Queue allocation Failed");
2404 /* Allocate memory for storing MAC addresses.
2405 * Table of mac_filter_entries size is allocated so that RTE ether lib
2406 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2408 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2409 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2410 if (eth_dev->data->mac_addrs == NULL) {
2412 "Failed to allocate %d bytes needed to store MAC addresses",
2413 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2418 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2420 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2421 rte_free(eth_dev->data->mac_addrs);
2422 eth_dev->data->mac_addrs = NULL;
2426 /* ... tx buffer layout ... */
2427 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2428 if (priv->tx_conf_en) {
2429 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2430 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2431 layout.pass_timestamp = true;
2433 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2435 layout.pass_frame_status = 1;
2436 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2437 DPNI_QUEUE_TX, &layout);
2439 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2443 /* ... tx-conf and error buffer layout ... */
2444 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2445 if (priv->tx_conf_en) {
2446 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2447 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2448 layout.pass_timestamp = true;
2450 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2452 layout.pass_frame_status = 1;
2453 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2454 DPNI_QUEUE_TX_CONFIRM, &layout);
2456 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2461 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2463 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2464 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2465 DPAA2_PMD_INFO("Loopback mode");
2466 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2467 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2468 DPAA2_PMD_INFO("No Prefetch mode");
2470 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2472 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2474 /*Init fields w.r.t. classficaition*/
2475 memset(&priv->extract.qos_key_cfg, 0, sizeof(struct dpkg_profile_cfg));
2476 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2477 if (!priv->extract.qos_extract_param) {
2478 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2479 " classificaiton ", ret);
2482 for (i = 0; i < MAX_TCS; i++) {
2483 memset(&priv->extract.fs_key_cfg[i], 0,
2484 sizeof(struct dpkg_profile_cfg));
2485 priv->extract.fs_extract_param[i] =
2486 (size_t)rte_malloc(NULL, 256, 64);
2487 if (!priv->extract.fs_extract_param[i]) {
2488 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2494 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2495 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2498 DPAA2_PMD_ERR("Unable to set mtu. check config");
2502 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2505 dpaa2_dev_uninit(eth_dev);
2510 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2512 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2513 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
2516 PMD_INIT_FUNC_TRACE();
2518 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2522 DPAA2_PMD_WARN("Already closed or not started");
2526 dpaa2_dev_close(eth_dev);
2528 dpaa2_free_rx_tx_queues(eth_dev);
2530 /* Close the device at underlying layer*/
2531 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2534 "Failure closing dpni device with err code %d",
2538 /* Free the allocated memory for ethernet private data and dpni*/
2542 for (i = 0; i < MAX_TCS; i++) {
2543 if (priv->extract.fs_extract_param[i])
2544 rte_free((void *)(size_t)priv->extract.fs_extract_param[i]);
2547 if (priv->extract.qos_extract_param)
2548 rte_free((void *)(size_t)priv->extract.qos_extract_param);
2550 eth_dev->dev_ops = NULL;
2551 eth_dev->rx_pkt_burst = NULL;
2552 eth_dev->tx_pkt_burst = NULL;
2554 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2559 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2560 struct rte_dpaa2_device *dpaa2_dev)
2562 struct rte_eth_dev *eth_dev;
2563 struct dpaa2_dev_priv *priv;
2566 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2567 RTE_PKTMBUF_HEADROOM) {
2569 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2570 RTE_PKTMBUF_HEADROOM,
2571 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2576 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2577 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2580 eth_dev->data->dev_private = rte_zmalloc(
2581 "ethdev private structure",
2582 sizeof(struct dpaa2_dev_priv),
2583 RTE_CACHE_LINE_SIZE);
2584 if (eth_dev->data->dev_private == NULL) {
2586 "Unable to allocate memory for private data");
2587 rte_eth_dev_release_port(eth_dev);
2591 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2596 eth_dev->device = &dpaa2_dev->device;
2598 dpaa2_dev->eth_dev = eth_dev;
2599 eth_dev->data->rx_mbuf_alloc_failed = 0;
2601 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2602 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2604 /* Invoke PMD device initialization function */
2605 diag = dpaa2_dev_init(eth_dev);
2607 rte_eth_dev_probing_finish(eth_dev);
2611 priv = eth_dev->data->dev_private;
2612 priv->tx_conf_en = 0;
2614 rte_eth_dev_release_port(eth_dev);
2619 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2621 struct rte_eth_dev *eth_dev;
2623 eth_dev = dpaa2_dev->eth_dev;
2624 dpaa2_dev_uninit(eth_dev);
2626 rte_eth_dev_release_port(eth_dev);
2631 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2632 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2633 .drv_type = DPAA2_ETH,
2634 .probe = rte_dpaa2_probe,
2635 .remove = rte_dpaa2_remove,
2638 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2639 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2640 DRIVER_LOOPBACK_MODE "=<int> "
2641 DRIVER_NO_PREFETCH_MODE "=<int>");
2642 RTE_INIT(dpaa2_pmd_init_log)
2644 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2");
2645 if (dpaa2_logtype_pmd >= 0)
2646 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE);