1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2021 NXP
12 #include <ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
34 #define DRIVER_TX_CONF "drv_tx_conf"
35 #define CHECK_INTERVAL 100 /* 100ms */
36 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
38 /* Supported Rx offloads */
39 static uint64_t dev_rx_offloads_sup =
40 DEV_RX_OFFLOAD_CHECKSUM |
41 DEV_RX_OFFLOAD_SCTP_CKSUM |
42 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
43 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
44 DEV_RX_OFFLOAD_VLAN_STRIP |
45 DEV_RX_OFFLOAD_VLAN_FILTER |
46 DEV_RX_OFFLOAD_JUMBO_FRAME |
47 DEV_RX_OFFLOAD_TIMESTAMP;
49 /* Rx offloads which cannot be disabled */
50 static uint64_t dev_rx_offloads_nodis =
51 DEV_RX_OFFLOAD_RSS_HASH |
52 DEV_RX_OFFLOAD_SCATTER;
54 /* Supported Tx offloads */
55 static uint64_t dev_tx_offloads_sup =
56 DEV_TX_OFFLOAD_VLAN_INSERT |
57 DEV_TX_OFFLOAD_IPV4_CKSUM |
58 DEV_TX_OFFLOAD_UDP_CKSUM |
59 DEV_TX_OFFLOAD_TCP_CKSUM |
60 DEV_TX_OFFLOAD_SCTP_CKSUM |
61 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
62 DEV_TX_OFFLOAD_MT_LOCKFREE |
63 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
65 /* Tx offloads which cannot be disabled */
66 static uint64_t dev_tx_offloads_nodis =
67 DEV_TX_OFFLOAD_MULTI_SEGS;
69 /* enable timestamp in mbuf */
70 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
71 uint64_t dpaa2_timestamp_rx_dynflag;
72 int dpaa2_timestamp_dynfield_offset = -1;
74 struct rte_dpaa2_xstats_name_off {
75 char name[RTE_ETH_XSTATS_NAME_SIZE];
76 uint8_t page_id; /* dpni statistics page id */
77 uint8_t stats_id; /* stats id in the given page */
80 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
81 {"ingress_multicast_frames", 0, 2},
82 {"ingress_multicast_bytes", 0, 3},
83 {"ingress_broadcast_frames", 0, 4},
84 {"ingress_broadcast_bytes", 0, 5},
85 {"egress_multicast_frames", 1, 2},
86 {"egress_multicast_bytes", 1, 3},
87 {"egress_broadcast_frames", 1, 4},
88 {"egress_broadcast_bytes", 1, 5},
89 {"ingress_filtered_frames", 2, 0},
90 {"ingress_discarded_frames", 2, 1},
91 {"ingress_nobuffer_discards", 2, 2},
92 {"egress_discarded_frames", 2, 3},
93 {"egress_confirmed_frames", 2, 4},
94 {"cgr_reject_frames", 4, 0},
95 {"cgr_reject_bytes", 4, 1},
98 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
102 static struct rte_dpaa2_driver rte_dpaa2_pmd;
103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
104 int wait_to_complete);
105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
113 struct dpaa2_dev_priv *priv = dev->data->dev_private;
114 struct fsl_mc_io *dpni = dev->process_private;
116 PMD_INIT_FUNC_TRACE();
119 DPAA2_PMD_ERR("dpni is NULL");
124 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
127 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
128 priv->token, vlan_id);
131 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
132 ret, vlan_id, priv->hw_id);
138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
140 struct dpaa2_dev_priv *priv = dev->data->dev_private;
141 struct fsl_mc_io *dpni = dev->process_private;
144 PMD_INIT_FUNC_TRACE();
146 if (mask & ETH_VLAN_FILTER_MASK) {
147 /* VLAN Filter not avaialble */
148 if (!priv->max_vlan_filters) {
149 DPAA2_PMD_INFO("VLAN filter not available");
153 if (dev->data->dev_conf.rxmode.offloads &
154 DEV_RX_OFFLOAD_VLAN_FILTER)
155 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
158 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
161 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
169 enum rte_vlan_type vlan_type __rte_unused,
172 struct dpaa2_dev_priv *priv = dev->data->dev_private;
173 struct fsl_mc_io *dpni = dev->process_private;
176 PMD_INIT_FUNC_TRACE();
178 /* nothing to be done for standard vlan tpids */
179 if (tpid == 0x8100 || tpid == 0x88A8)
182 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
185 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
186 /* if already configured tpids, remove them first */
188 struct dpni_custom_tpid_cfg tpid_list = {0};
190 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
191 priv->token, &tpid_list);
194 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
195 priv->token, tpid_list.tpid1);
198 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
206 dpaa2_fw_version_get(struct rte_eth_dev *dev,
211 struct fsl_mc_io *dpni = dev->process_private;
212 struct mc_soc_version mc_plat_info = {0};
213 struct mc_version mc_ver_info = {0};
215 PMD_INIT_FUNC_TRACE();
217 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
218 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
220 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
221 DPAA2_PMD_WARN("\tmc_get_version failed");
223 ret = snprintf(fw_version, fw_size,
228 mc_ver_info.revision);
230 ret += 1; /* add the size of '\0' */
231 if (fw_size < (uint32_t)ret)
238 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
240 struct dpaa2_dev_priv *priv = dev->data->dev_private;
242 PMD_INIT_FUNC_TRACE();
244 dev_info->max_mac_addrs = priv->max_mac_filters;
245 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
246 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
247 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
248 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
249 dev_info->rx_offload_capa = dev_rx_offloads_sup |
250 dev_rx_offloads_nodis;
251 dev_info->tx_offload_capa = dev_tx_offloads_sup |
252 dev_tx_offloads_nodis;
253 dev_info->speed_capa = ETH_LINK_SPEED_1G |
254 ETH_LINK_SPEED_2_5G |
257 dev_info->max_hash_mac_addrs = 0;
258 dev_info->max_vfs = 0;
259 dev_info->max_vmdq_pools = ETH_16_POOLS;
260 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
262 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
263 /* same is rx size for best perf */
264 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
266 dev_info->default_rxportconf.nb_queues = 1;
267 dev_info->default_txportconf.nb_queues = 1;
268 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
269 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
271 if (dpaa2_svr_family == SVR_LX2160A) {
272 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
282 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
283 __rte_unused uint16_t queue_id,
284 struct rte_eth_burst_mode *mode)
286 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
289 const struct burst_info {
292 } rx_offload_map[] = {
293 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
294 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
295 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
296 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
297 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
298 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
299 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
300 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
301 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
302 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
305 /* Update Rx offload info */
306 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
307 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
308 snprintf(mode->info, sizeof(mode->info), "%s",
309 rx_offload_map[i].output);
318 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
319 __rte_unused uint16_t queue_id,
320 struct rte_eth_burst_mode *mode)
322 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
325 const struct burst_info {
328 } tx_offload_map[] = {
329 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
330 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
331 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
332 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
333 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
334 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
335 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
336 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
337 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
340 /* Update Tx offload info */
341 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
342 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
343 snprintf(mode->info, sizeof(mode->info), "%s",
344 tx_offload_map[i].output);
353 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
355 struct dpaa2_dev_priv *priv = dev->data->dev_private;
358 uint8_t num_rxqueue_per_tc;
359 struct dpaa2_queue *mc_q, *mcq;
362 struct dpaa2_queue *dpaa2_q;
364 PMD_INIT_FUNC_TRACE();
366 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
367 if (priv->flags & DPAA2_TX_CONF_ENABLE)
368 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
370 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
371 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
372 RTE_CACHE_LINE_SIZE);
374 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
378 for (i = 0; i < priv->nb_rx_queues; i++) {
379 mc_q->eth_data = dev->data;
380 priv->rx_vq[i] = mc_q++;
381 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
382 dpaa2_q->q_storage = rte_malloc("dq_storage",
383 sizeof(struct queue_storage_info_t),
384 RTE_CACHE_LINE_SIZE);
385 if (!dpaa2_q->q_storage)
388 memset(dpaa2_q->q_storage, 0,
389 sizeof(struct queue_storage_info_t));
390 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
394 for (i = 0; i < priv->nb_tx_queues; i++) {
395 mc_q->eth_data = dev->data;
396 mc_q->flow_id = 0xffff;
397 priv->tx_vq[i] = mc_q++;
398 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
399 dpaa2_q->cscn = rte_malloc(NULL,
400 sizeof(struct qbman_result), 16);
405 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
406 /*Setup tx confirmation queues*/
407 for (i = 0; i < priv->nb_tx_queues; i++) {
408 mc_q->eth_data = dev->data;
411 priv->tx_conf_vq[i] = mc_q++;
412 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
414 rte_malloc("dq_storage",
415 sizeof(struct queue_storage_info_t),
416 RTE_CACHE_LINE_SIZE);
417 if (!dpaa2_q->q_storage)
420 memset(dpaa2_q->q_storage, 0,
421 sizeof(struct queue_storage_info_t));
422 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
428 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
429 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
430 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
431 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
439 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
440 rte_free(dpaa2_q->q_storage);
441 priv->tx_conf_vq[i--] = NULL;
443 i = priv->nb_tx_queues;
447 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
448 rte_free(dpaa2_q->cscn);
449 priv->tx_vq[i--] = NULL;
451 i = priv->nb_rx_queues;
454 mc_q = priv->rx_vq[0];
456 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
457 dpaa2_free_dq_storage(dpaa2_q->q_storage);
458 rte_free(dpaa2_q->q_storage);
459 priv->rx_vq[i--] = NULL;
466 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
468 struct dpaa2_dev_priv *priv = dev->data->dev_private;
469 struct dpaa2_queue *dpaa2_q;
472 PMD_INIT_FUNC_TRACE();
474 /* Queue allocation base */
475 if (priv->rx_vq[0]) {
476 /* cleaning up queue storage */
477 for (i = 0; i < priv->nb_rx_queues; i++) {
478 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
479 if (dpaa2_q->q_storage)
480 rte_free(dpaa2_q->q_storage);
482 /* cleanup tx queue cscn */
483 for (i = 0; i < priv->nb_tx_queues; i++) {
484 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
485 rte_free(dpaa2_q->cscn);
487 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
488 /* cleanup tx conf queue storage */
489 for (i = 0; i < priv->nb_tx_queues; i++) {
490 dpaa2_q = (struct dpaa2_queue *)
492 rte_free(dpaa2_q->q_storage);
495 /*free memory for all queues (RX+TX) */
496 rte_free(priv->rx_vq[0]);
497 priv->rx_vq[0] = NULL;
502 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
504 struct dpaa2_dev_priv *priv = dev->data->dev_private;
505 struct fsl_mc_io *dpni = dev->process_private;
506 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
507 uint64_t rx_offloads = eth_conf->rxmode.offloads;
508 uint64_t tx_offloads = eth_conf->txmode.offloads;
509 int rx_l3_csum_offload = false;
510 int rx_l4_csum_offload = false;
511 int tx_l3_csum_offload = false;
512 int tx_l4_csum_offload = false;
515 PMD_INIT_FUNC_TRACE();
517 /* Rx offloads which are enabled by default */
518 if (dev_rx_offloads_nodis & ~rx_offloads) {
520 "Some of rx offloads enabled by default - requested 0x%" PRIx64
521 " fixed are 0x%" PRIx64,
522 rx_offloads, dev_rx_offloads_nodis);
525 /* Tx offloads which are enabled by default */
526 if (dev_tx_offloads_nodis & ~tx_offloads) {
528 "Some of tx offloads enabled by default - requested 0x%" PRIx64
529 " fixed are 0x%" PRIx64,
530 tx_offloads, dev_tx_offloads_nodis);
533 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
534 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
535 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
536 priv->token, eth_conf->rxmode.max_rx_pkt_len
537 - RTE_ETHER_CRC_LEN);
540 "Unable to set mtu. check config");
544 dev->data->dev_conf.rxmode.max_rx_pkt_len -
545 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
552 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
553 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
554 ret = dpaa2_setup_flow_dist(dev,
555 eth_conf->rx_adv_conf.rss_conf.rss_hf,
559 "Unable to set flow distribution on tc%d."
560 "Check queue config", tc_index);
566 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
567 rx_l3_csum_offload = true;
569 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
570 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
571 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
572 rx_l4_csum_offload = true;
574 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
575 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
577 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
581 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
582 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
584 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
588 #if !defined(RTE_LIBRTE_IEEE1588)
589 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
592 ret = rte_mbuf_dyn_rx_timestamp_register(
593 &dpaa2_timestamp_dynfield_offset,
594 &dpaa2_timestamp_rx_dynflag);
596 DPAA2_PMD_ERR("Error to register timestamp field/flag");
599 dpaa2_enable_ts[dev->data->port_id] = true;
602 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
603 tx_l3_csum_offload = true;
605 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
606 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
607 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
608 tx_l4_csum_offload = true;
610 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
611 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
613 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
617 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
618 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
620 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
624 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
625 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
626 * to 0 for LS2 in the hardware thus disabling data/annotation
627 * stashing. For LX2 this is fixed in hardware and thus hash result and
628 * parse results can be received in FD using this option.
630 if (dpaa2_svr_family == SVR_LX2160A) {
631 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
632 DPNI_FLCTYPE_HASH, true);
634 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
639 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
640 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
647 /* Function to setup RX flow information. It contains traffic class ID,
648 * flow ID, destination configuration etc.
651 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
652 uint16_t rx_queue_id,
654 unsigned int socket_id __rte_unused,
655 const struct rte_eth_rxconf *rx_conf,
656 struct rte_mempool *mb_pool)
658 struct dpaa2_dev_priv *priv = dev->data->dev_private;
659 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
660 struct dpaa2_queue *dpaa2_q;
661 struct dpni_queue cfg;
667 PMD_INIT_FUNC_TRACE();
669 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
670 dev, rx_queue_id, mb_pool, rx_conf);
672 /* Rx deferred start is not supported */
673 if (rx_conf->rx_deferred_start) {
674 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
679 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
680 bpid = mempool_to_bpid(mb_pool);
681 ret = dpaa2_attach_bp_list(priv,
682 rte_dpaa2_bpid_info[bpid].bp_list);
686 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
687 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
688 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
689 dpaa2_q->nb_desc = UINT16_MAX;
690 dpaa2_q->offloads = rx_conf->offloads;
692 /*Get the flow id from given VQ id*/
693 flow_id = dpaa2_q->flow_id;
694 memset(&cfg, 0, sizeof(struct dpni_queue));
696 options = options | DPNI_QUEUE_OPT_USER_CTX;
697 cfg.user_context = (size_t)(dpaa2_q);
699 /* check if a private cgr available. */
700 for (i = 0; i < priv->max_cgs; i++) {
701 if (!priv->cgid_in_use[i]) {
702 priv->cgid_in_use[i] = 1;
707 if (i < priv->max_cgs) {
708 options |= DPNI_QUEUE_OPT_SET_CGID;
710 dpaa2_q->cgid = cfg.cgid;
712 dpaa2_q->cgid = 0xff;
715 /*if ls2088 or rev2 device, enable the stashing */
717 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
718 options |= DPNI_QUEUE_OPT_FLC;
719 cfg.flc.stash_control = true;
720 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
721 /* 00 00 00 - last 6 bit represent annotation, context stashing,
722 * data stashing setting 01 01 00 (0x14)
723 * (in following order ->DS AS CS)
724 * to enable 1 line data, 1 line annotation.
725 * For LX2, this setting should be 01 00 00 (0x10)
727 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
728 cfg.flc.value |= 0x10;
730 cfg.flc.value |= 0x14;
732 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
733 dpaa2_q->tc_index, flow_id, options, &cfg);
735 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
739 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
740 struct dpni_taildrop taildrop;
743 dpaa2_q->nb_desc = nb_rx_desc;
744 /* Private CGR will use tail drop length as nb_rx_desc.
745 * for rest cases we can use standard byte based tail drop.
746 * There is no HW restriction, but number of CGRs are limited,
747 * hence this restriction is placed.
749 if (dpaa2_q->cgid != 0xff) {
750 /*enabling per rx queue congestion control */
751 taildrop.threshold = nb_rx_desc;
752 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
754 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
756 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
757 DPNI_CP_CONGESTION_GROUP,
760 dpaa2_q->cgid, &taildrop);
762 /*enabling per rx queue congestion control */
763 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
764 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
765 taildrop.oal = CONG_RX_OAL;
766 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
768 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
769 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
770 dpaa2_q->tc_index, flow_id,
774 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
778 } else { /* Disable tail Drop */
779 struct dpni_taildrop taildrop = {0};
780 DPAA2_PMD_INFO("Tail drop is disabled on queue");
783 if (dpaa2_q->cgid != 0xff) {
784 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
785 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
787 dpaa2_q->cgid, &taildrop);
789 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
790 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
791 dpaa2_q->tc_index, flow_id, &taildrop);
794 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
800 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
805 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
806 uint16_t tx_queue_id,
808 unsigned int socket_id __rte_unused,
809 const struct rte_eth_txconf *tx_conf)
811 struct dpaa2_dev_priv *priv = dev->data->dev_private;
812 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
813 priv->tx_vq[tx_queue_id];
814 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
815 priv->tx_conf_vq[tx_queue_id];
816 struct fsl_mc_io *dpni = dev->process_private;
817 struct dpni_queue tx_conf_cfg;
818 struct dpni_queue tx_flow_cfg;
819 uint8_t options = 0, flow_id;
820 struct dpni_queue_id qid;
824 PMD_INIT_FUNC_TRACE();
826 /* Tx deferred start is not supported */
827 if (tx_conf->tx_deferred_start) {
828 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
833 dpaa2_q->nb_desc = UINT16_MAX;
834 dpaa2_q->offloads = tx_conf->offloads;
836 /* Return if queue already configured */
837 if (dpaa2_q->flow_id != 0xffff) {
838 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
842 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
843 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
848 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
849 tc_id, flow_id, options, &tx_flow_cfg);
851 DPAA2_PMD_ERR("Error in setting the tx flow: "
852 "tc_id=%d, flow=%d err=%d",
853 tc_id, flow_id, ret);
857 dpaa2_q->flow_id = flow_id;
859 if (tx_queue_id == 0) {
860 /*Set tx-conf and error configuration*/
861 if (priv->flags & DPAA2_TX_CONF_ENABLE)
862 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
866 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
870 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
875 dpaa2_q->tc_index = tc_id;
877 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
878 DPNI_QUEUE_TX, dpaa2_q->tc_index,
879 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
881 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
884 dpaa2_q->fqid = qid.fqid;
886 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
887 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
889 dpaa2_q->nb_desc = nb_tx_desc;
891 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
892 cong_notif_cfg.threshold_entry = nb_tx_desc;
893 /* Notify that the queue is not congested when the data in
894 * the queue is below this thershold.
896 cong_notif_cfg.threshold_exit = nb_tx_desc - 24;
897 cong_notif_cfg.message_ctx = 0;
898 cong_notif_cfg.message_iova =
899 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
900 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
901 cong_notif_cfg.notification_mode =
902 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
903 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
904 DPNI_CONG_OPT_COHERENT_WRITE;
905 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
907 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
914 "Error in setting tx congestion notification: "
919 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
920 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
922 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
923 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
924 options = options | DPNI_QUEUE_OPT_USER_CTX;
925 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
926 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
927 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
928 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
930 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
931 "tc_index=%d, flow=%d err=%d",
932 dpaa2_tx_conf_q->tc_index,
933 dpaa2_tx_conf_q->flow_id, ret);
937 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
938 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
939 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
941 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
944 dpaa2_tx_conf_q->fqid = qid.fqid;
950 dpaa2_dev_rx_queue_release(void *q __rte_unused)
952 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
953 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
954 struct fsl_mc_io *dpni =
955 (struct fsl_mc_io *)priv->eth_dev->process_private;
958 struct dpni_queue cfg;
960 memset(&cfg, 0, sizeof(struct dpni_queue));
961 PMD_INIT_FUNC_TRACE();
962 if (dpaa2_q->cgid != 0xff) {
963 options = DPNI_QUEUE_OPT_CLEAR_CGID;
964 cfg.cgid = dpaa2_q->cgid;
966 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
968 dpaa2_q->tc_index, dpaa2_q->flow_id,
971 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
973 priv->cgid_in_use[dpaa2_q->cgid] = 0;
974 dpaa2_q->cgid = 0xff;
979 dpaa2_dev_tx_queue_release(void *q __rte_unused)
981 PMD_INIT_FUNC_TRACE();
985 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
988 struct dpaa2_dev_priv *priv = dev->data->dev_private;
989 struct dpaa2_queue *dpaa2_q;
990 struct qbman_swp *swp;
991 struct qbman_fq_query_np_rslt state;
992 uint32_t frame_cnt = 0;
994 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
995 ret = dpaa2_affine_qbman_swp();
998 "Failed to allocate IO portal, tid: %d\n",
1003 swp = DPAA2_PER_LCORE_PORTAL;
1005 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
1007 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1008 frame_cnt = qbman_fq_state_frame_count(&state);
1009 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
1010 rx_queue_id, frame_cnt);
1015 static const uint32_t *
1016 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1018 static const uint32_t ptypes[] = {
1019 /*todo -= add more types */
1022 RTE_PTYPE_L3_IPV4_EXT,
1024 RTE_PTYPE_L3_IPV6_EXT,
1032 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1033 dev->rx_pkt_burst == dpaa2_dev_rx ||
1034 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1040 * Dpaa2 link Interrupt handler
1043 * The address of parameter (struct rte_eth_dev *) regsitered before.
1049 dpaa2_interrupt_handler(void *param)
1051 struct rte_eth_dev *dev = param;
1052 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1053 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1055 int irq_index = DPNI_IRQ_INDEX;
1056 unsigned int status = 0, clear = 0;
1058 PMD_INIT_FUNC_TRACE();
1061 DPAA2_PMD_ERR("dpni is NULL");
1065 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1066 irq_index, &status);
1067 if (unlikely(ret)) {
1068 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1073 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1074 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1075 dpaa2_dev_link_update(dev, 0);
1076 /* calling all the apps registered for link status event */
1077 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1080 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1083 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1087 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1090 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1091 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1092 int irq_index = DPNI_IRQ_INDEX;
1093 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1095 PMD_INIT_FUNC_TRACE();
1097 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1100 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1105 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1108 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1115 dpaa2_dev_start(struct rte_eth_dev *dev)
1117 struct rte_device *rdev = dev->device;
1118 struct rte_dpaa2_device *dpaa2_dev;
1119 struct rte_eth_dev_data *data = dev->data;
1120 struct dpaa2_dev_priv *priv = data->dev_private;
1121 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1122 struct dpni_queue cfg;
1123 struct dpni_error_cfg err_cfg;
1125 struct dpni_queue_id qid;
1126 struct dpaa2_queue *dpaa2_q;
1128 struct rte_intr_handle *intr_handle;
1130 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1131 intr_handle = &dpaa2_dev->intr_handle;
1133 PMD_INIT_FUNC_TRACE();
1135 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1137 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1142 /* Power up the phy. Needed to make the link go UP */
1143 dpaa2_dev_set_link_up(dev);
1145 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1146 DPNI_QUEUE_TX, &qdid);
1148 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1153 for (i = 0; i < data->nb_rx_queues; i++) {
1154 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1155 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1156 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1157 dpaa2_q->flow_id, &cfg, &qid);
1159 DPAA2_PMD_ERR("Error in getting flow information: "
1163 dpaa2_q->fqid = qid.fqid;
1166 /*checksum errors, send them to normal path and set it in annotation */
1167 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1168 err_cfg.errors |= DPNI_ERROR_PHE;
1170 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1171 err_cfg.set_frame_annotation = true;
1173 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1174 priv->token, &err_cfg);
1176 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1181 /* if the interrupts were configured on this devices*/
1182 if (intr_handle && (intr_handle->fd) &&
1183 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1184 /* Registering LSC interrupt handler */
1185 rte_intr_callback_register(intr_handle,
1186 dpaa2_interrupt_handler,
1189 /* enable vfio intr/eventfd mapping
1190 * Interrupt index 0 is required, so we can not use
1193 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1195 /* enable dpni_irqs */
1196 dpaa2_eth_setup_irqs(dev, 1);
1199 /* Change the tx burst function if ordered queues are used */
1200 if (priv->en_ordered)
1201 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1207 * This routine disables all traffic on the adapter by issuing a
1208 * global reset on the MAC.
1211 dpaa2_dev_stop(struct rte_eth_dev *dev)
1213 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1214 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1216 struct rte_eth_link link;
1217 struct rte_intr_handle *intr_handle = dev->intr_handle;
1219 PMD_INIT_FUNC_TRACE();
1221 /* reset interrupt callback */
1222 if (intr_handle && (intr_handle->fd) &&
1223 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1224 /*disable dpni irqs */
1225 dpaa2_eth_setup_irqs(dev, 0);
1227 /* disable vfio intr before callback unregister */
1228 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1230 /* Unregistering LSC interrupt handler */
1231 rte_intr_callback_unregister(intr_handle,
1232 dpaa2_interrupt_handler,
1236 dpaa2_dev_set_link_down(dev);
1238 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1240 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1245 /* clear the recorded link status */
1246 memset(&link, 0, sizeof(link));
1247 rte_eth_linkstatus_set(dev, &link);
1253 dpaa2_dev_close(struct rte_eth_dev *dev)
1255 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1256 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1258 struct rte_eth_link link;
1260 PMD_INIT_FUNC_TRACE();
1262 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1266 DPAA2_PMD_WARN("Already closed or not started");
1270 dpaa2_tm_deinit(dev);
1271 dpaa2_flow_clean(dev);
1272 /* Clean the device first */
1273 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1275 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1279 memset(&link, 0, sizeof(link));
1280 rte_eth_linkstatus_set(dev, &link);
1282 /* Free private queues memory */
1283 dpaa2_free_rx_tx_queues(dev);
1284 /* Close the device at underlying layer*/
1285 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1287 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1291 /* Free the allocated memory for ethernet private data and dpni*/
1293 dev->process_private = NULL;
1296 for (i = 0; i < MAX_TCS; i++)
1297 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1299 if (priv->extract.qos_extract_param)
1300 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1302 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1307 dpaa2_dev_promiscuous_enable(
1308 struct rte_eth_dev *dev)
1311 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1312 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1314 PMD_INIT_FUNC_TRACE();
1317 DPAA2_PMD_ERR("dpni is NULL");
1321 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1323 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1325 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1327 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1333 dpaa2_dev_promiscuous_disable(
1334 struct rte_eth_dev *dev)
1337 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1338 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1340 PMD_INIT_FUNC_TRACE();
1343 DPAA2_PMD_ERR("dpni is NULL");
1347 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1349 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1351 if (dev->data->all_multicast == 0) {
1352 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1353 priv->token, false);
1355 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1363 dpaa2_dev_allmulticast_enable(
1364 struct rte_eth_dev *dev)
1367 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1368 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1370 PMD_INIT_FUNC_TRACE();
1373 DPAA2_PMD_ERR("dpni is NULL");
1377 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1379 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1385 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1388 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1389 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1391 PMD_INIT_FUNC_TRACE();
1394 DPAA2_PMD_ERR("dpni is NULL");
1398 /* must remain on for all promiscuous */
1399 if (dev->data->promiscuous == 1)
1402 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1404 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1410 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1413 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1414 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1415 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1418 PMD_INIT_FUNC_TRACE();
1421 DPAA2_PMD_ERR("dpni is NULL");
1425 /* check that mtu is within the allowed range */
1426 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1429 if (frame_size > DPAA2_ETH_MAX_LEN)
1430 dev->data->dev_conf.rxmode.offloads |=
1431 DEV_RX_OFFLOAD_JUMBO_FRAME;
1433 dev->data->dev_conf.rxmode.offloads &=
1434 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1436 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1438 /* Set the Max Rx frame length as 'mtu' +
1439 * Maximum Ethernet header length
1441 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1442 frame_size - RTE_ETHER_CRC_LEN);
1444 DPAA2_PMD_ERR("Setting the max frame length failed");
1447 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1452 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1453 struct rte_ether_addr *addr,
1454 __rte_unused uint32_t index,
1455 __rte_unused uint32_t pool)
1458 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1459 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1461 PMD_INIT_FUNC_TRACE();
1464 DPAA2_PMD_ERR("dpni is NULL");
1468 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1469 addr->addr_bytes, 0, 0, 0);
1472 "error: Adding the MAC ADDR failed: err = %d", ret);
1477 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1481 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1482 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1483 struct rte_eth_dev_data *data = dev->data;
1484 struct rte_ether_addr *macaddr;
1486 PMD_INIT_FUNC_TRACE();
1488 macaddr = &data->mac_addrs[index];
1491 DPAA2_PMD_ERR("dpni is NULL");
1495 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1496 priv->token, macaddr->addr_bytes);
1499 "error: Removing the MAC ADDR failed: err = %d", ret);
1503 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1504 struct rte_ether_addr *addr)
1507 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1508 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1510 PMD_INIT_FUNC_TRACE();
1513 DPAA2_PMD_ERR("dpni is NULL");
1517 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1518 priv->token, addr->addr_bytes);
1522 "error: Setting the MAC ADDR failed %d", ret);
1528 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1529 struct rte_eth_stats *stats)
1531 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1532 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1534 uint8_t page0 = 0, page1 = 1, page2 = 2;
1535 union dpni_statistics value;
1537 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1539 memset(&value, 0, sizeof(union dpni_statistics));
1541 PMD_INIT_FUNC_TRACE();
1544 DPAA2_PMD_ERR("dpni is NULL");
1549 DPAA2_PMD_ERR("stats is NULL");
1553 /*Get Counters from page_0*/
1554 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1559 stats->ipackets = value.page_0.ingress_all_frames;
1560 stats->ibytes = value.page_0.ingress_all_bytes;
1562 /*Get Counters from page_1*/
1563 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1568 stats->opackets = value.page_1.egress_all_frames;
1569 stats->obytes = value.page_1.egress_all_bytes;
1571 /*Get Counters from page_2*/
1572 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1577 /* Ingress drop frame count due to configured rules */
1578 stats->ierrors = value.page_2.ingress_filtered_frames;
1579 /* Ingress drop frame count due to error */
1580 stats->ierrors += value.page_2.ingress_discarded_frames;
1582 stats->oerrors = value.page_2.egress_discarded_frames;
1583 stats->imissed = value.page_2.ingress_nobuffer_discards;
1585 /* Fill in per queue stats */
1586 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1587 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1588 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1589 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1591 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1593 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1595 /* Byte counting is not implemented */
1596 stats->q_ibytes[i] = 0;
1597 stats->q_obytes[i] = 0;
1603 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1608 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1611 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1612 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1614 union dpni_statistics value[5] = {};
1615 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1623 /* Get Counters from page_0*/
1624 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1629 /* Get Counters from page_1*/
1630 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1635 /* Get Counters from page_2*/
1636 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1641 for (i = 0; i < priv->max_cgs; i++) {
1642 if (!priv->cgid_in_use[i]) {
1643 /* Get Counters from page_4*/
1644 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1653 for (i = 0; i < num; i++) {
1655 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1656 raw.counter[dpaa2_xstats_strings[i].stats_id];
1660 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1665 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1666 struct rte_eth_xstat_name *xstats_names,
1669 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1671 if (limit < stat_cnt)
1674 if (xstats_names != NULL)
1675 for (i = 0; i < stat_cnt; i++)
1676 strlcpy(xstats_names[i].name,
1677 dpaa2_xstats_strings[i].name,
1678 sizeof(xstats_names[i].name));
1684 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1685 uint64_t *values, unsigned int n)
1687 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1688 uint64_t values_copy[stat_cnt];
1691 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1692 struct fsl_mc_io *dpni =
1693 (struct fsl_mc_io *)dev->process_private;
1695 union dpni_statistics value[5] = {};
1703 /* Get Counters from page_0*/
1704 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1709 /* Get Counters from page_1*/
1710 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1715 /* Get Counters from page_2*/
1716 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1721 /* Get Counters from page_4*/
1722 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1727 for (i = 0; i < stat_cnt; i++) {
1728 values[i] = value[dpaa2_xstats_strings[i].page_id].
1729 raw.counter[dpaa2_xstats_strings[i].stats_id];
1734 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1736 for (i = 0; i < n; i++) {
1737 if (ids[i] >= stat_cnt) {
1738 DPAA2_PMD_ERR("xstats id value isn't valid");
1741 values[i] = values_copy[ids[i]];
1747 dpaa2_xstats_get_names_by_id(
1748 struct rte_eth_dev *dev,
1749 struct rte_eth_xstat_name *xstats_names,
1750 const uint64_t *ids,
1753 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1754 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1757 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1759 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1761 for (i = 0; i < limit; i++) {
1762 if (ids[i] >= stat_cnt) {
1763 DPAA2_PMD_ERR("xstats id value isn't valid");
1766 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1772 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1774 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1775 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1778 struct dpaa2_queue *dpaa2_q;
1780 PMD_INIT_FUNC_TRACE();
1783 DPAA2_PMD_ERR("dpni is NULL");
1787 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1791 /* Reset the per queue stats in dpaa2_queue structure */
1792 for (i = 0; i < priv->nb_rx_queues; i++) {
1793 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1795 dpaa2_q->rx_pkts = 0;
1798 for (i = 0; i < priv->nb_tx_queues; i++) {
1799 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1801 dpaa2_q->tx_pkts = 0;
1807 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1811 /* return 0 means link status changed, -1 means not changed */
1813 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1814 int wait_to_complete)
1817 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1818 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1819 struct rte_eth_link link;
1820 struct dpni_link_state state = {0};
1824 DPAA2_PMD_ERR("dpni is NULL");
1828 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1829 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1832 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1835 if (state.up == ETH_LINK_DOWN &&
1837 rte_delay_ms(CHECK_INTERVAL);
1842 memset(&link, 0, sizeof(struct rte_eth_link));
1843 link.link_status = state.up;
1844 link.link_speed = state.rate;
1846 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1847 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1849 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1851 ret = rte_eth_linkstatus_set(dev, &link);
1853 DPAA2_PMD_DEBUG("No change in status");
1855 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1856 link.link_status ? "Up" : "Down");
1862 * Toggle the DPNI to enable, if not already enabled.
1863 * This is not strictly PHY up/down - it is more of logical toggling.
1866 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1869 struct dpaa2_dev_priv *priv;
1870 struct fsl_mc_io *dpni;
1872 struct dpni_link_state state = {0};
1874 priv = dev->data->dev_private;
1875 dpni = (struct fsl_mc_io *)dev->process_private;
1878 DPAA2_PMD_ERR("dpni is NULL");
1882 /* Check if DPNI is currently enabled */
1883 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1885 /* Unable to obtain dpni status; Not continuing */
1886 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1890 /* Enable link if not already enabled */
1892 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1894 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1898 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1900 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1904 /* changing tx burst function to start enqueues */
1905 dev->tx_pkt_burst = dpaa2_dev_tx;
1906 dev->data->dev_link.link_status = state.up;
1907 dev->data->dev_link.link_speed = state.rate;
1910 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1912 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1917 * Toggle the DPNI to disable, if not already disabled.
1918 * This is not strictly PHY up/down - it is more of logical toggling.
1921 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1924 struct dpaa2_dev_priv *priv;
1925 struct fsl_mc_io *dpni;
1926 int dpni_enabled = 0;
1929 PMD_INIT_FUNC_TRACE();
1931 priv = dev->data->dev_private;
1932 dpni = (struct fsl_mc_io *)dev->process_private;
1935 DPAA2_PMD_ERR("Device has not yet been configured");
1939 /*changing tx burst function to avoid any more enqueues */
1940 dev->tx_pkt_burst = dummy_dev_tx;
1942 /* Loop while dpni_disable() attempts to drain the egress FQs
1943 * and confirm them back to us.
1946 ret = dpni_disable(dpni, 0, priv->token);
1948 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1951 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1953 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1957 /* Allow the MC some slack */
1958 rte_delay_us(100 * 1000);
1959 } while (dpni_enabled && --retries);
1962 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1963 /* todo- we may have to manually cleanup queues.
1966 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1967 dev->data->port_id);
1970 dev->data->dev_link.link_status = 0;
1976 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1979 struct dpaa2_dev_priv *priv;
1980 struct fsl_mc_io *dpni;
1981 struct dpni_link_state state = {0};
1983 PMD_INIT_FUNC_TRACE();
1985 priv = dev->data->dev_private;
1986 dpni = (struct fsl_mc_io *)dev->process_private;
1988 if (dpni == NULL || fc_conf == NULL) {
1989 DPAA2_PMD_ERR("device not configured");
1993 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1995 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1999 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2000 if (state.options & DPNI_LINK_OPT_PAUSE) {
2001 /* DPNI_LINK_OPT_PAUSE set
2002 * if ASYM_PAUSE not set,
2003 * RX Side flow control (handle received Pause frame)
2004 * TX side flow control (send Pause frame)
2005 * if ASYM_PAUSE set,
2006 * RX Side flow control (handle received Pause frame)
2007 * No TX side flow control (send Pause frame disabled)
2009 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2010 fc_conf->mode = RTE_FC_FULL;
2012 fc_conf->mode = RTE_FC_RX_PAUSE;
2014 /* DPNI_LINK_OPT_PAUSE not set
2015 * if ASYM_PAUSE set,
2016 * TX side flow control (send Pause frame)
2017 * No RX side flow control (No action on pause frame rx)
2018 * if ASYM_PAUSE not set,
2019 * Flow control disabled
2021 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2022 fc_conf->mode = RTE_FC_TX_PAUSE;
2024 fc_conf->mode = RTE_FC_NONE;
2031 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2034 struct dpaa2_dev_priv *priv;
2035 struct fsl_mc_io *dpni;
2036 struct dpni_link_state state = {0};
2037 struct dpni_link_cfg cfg = {0};
2039 PMD_INIT_FUNC_TRACE();
2041 priv = dev->data->dev_private;
2042 dpni = (struct fsl_mc_io *)dev->process_private;
2045 DPAA2_PMD_ERR("dpni is NULL");
2049 /* It is necessary to obtain the current state before setting fc_conf
2050 * as MC would return error in case rate, autoneg or duplex values are
2053 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2055 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2059 /* Disable link before setting configuration */
2060 dpaa2_dev_set_link_down(dev);
2062 /* Based on fc_conf, update cfg */
2063 cfg.rate = state.rate;
2064 cfg.options = state.options;
2066 /* update cfg with fc_conf */
2067 switch (fc_conf->mode) {
2069 /* Full flow control;
2070 * OPT_PAUSE set, ASYM_PAUSE not set
2072 cfg.options |= DPNI_LINK_OPT_PAUSE;
2073 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2075 case RTE_FC_TX_PAUSE:
2076 /* Enable RX flow control
2077 * OPT_PAUSE not set;
2080 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2081 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2083 case RTE_FC_RX_PAUSE:
2084 /* Enable TX Flow control
2088 cfg.options |= DPNI_LINK_OPT_PAUSE;
2089 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2092 /* Disable Flow control
2094 * ASYM_PAUSE not set
2096 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2097 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2100 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2105 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2107 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2111 dpaa2_dev_set_link_up(dev);
2117 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2118 struct rte_eth_rss_conf *rss_conf)
2120 struct rte_eth_dev_data *data = dev->data;
2121 struct dpaa2_dev_priv *priv = data->dev_private;
2122 struct rte_eth_conf *eth_conf = &data->dev_conf;
2125 PMD_INIT_FUNC_TRACE();
2127 if (rss_conf->rss_hf) {
2128 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2129 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2132 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2138 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2139 ret = dpaa2_remove_flow_dist(dev, tc_index);
2142 "Unable to remove flow dist on tc%d",
2148 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2153 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2154 struct rte_eth_rss_conf *rss_conf)
2156 struct rte_eth_dev_data *data = dev->data;
2157 struct rte_eth_conf *eth_conf = &data->dev_conf;
2159 /* dpaa2 does not support rss_key, so length should be 0*/
2160 rss_conf->rss_key_len = 0;
2161 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2165 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2166 int eth_rx_queue_id,
2167 struct dpaa2_dpcon_dev *dpcon,
2168 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2170 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2171 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2172 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2173 uint8_t flow_id = dpaa2_ethq->flow_id;
2174 struct dpni_queue cfg;
2175 uint8_t options, priority;
2178 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2179 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2180 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2181 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2182 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2183 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2187 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2188 (dpcon->num_priorities - 1);
2190 memset(&cfg, 0, sizeof(struct dpni_queue));
2191 options = DPNI_QUEUE_OPT_DEST;
2192 cfg.destination.type = DPNI_DEST_DPCON;
2193 cfg.destination.id = dpcon->dpcon_id;
2194 cfg.destination.priority = priority;
2196 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2197 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2198 cfg.destination.hold_active = 1;
2201 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2202 !eth_priv->en_ordered) {
2203 struct opr_cfg ocfg;
2205 /* Restoration window size = 256 frames */
2207 /* Restoration window size = 512 frames for LX2 */
2208 if (dpaa2_svr_family == SVR_LX2160A)
2210 /* Auto advance NESN window enabled */
2212 /* Late arrival window size disabled */
2214 /* ORL resource exhaustaion advance NESN disabled */
2216 /* Loose ordering enabled */
2218 eth_priv->en_loose_ordered = 1;
2219 /* Strict ordering enabled if explicitly set */
2220 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2222 eth_priv->en_loose_ordered = 0;
2225 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2226 dpaa2_ethq->tc_index, flow_id,
2227 OPR_OPT_CREATE, &ocfg);
2229 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2233 eth_priv->en_ordered = 1;
2236 options |= DPNI_QUEUE_OPT_USER_CTX;
2237 cfg.user_context = (size_t)(dpaa2_ethq);
2239 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2240 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2242 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2246 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2251 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2252 int eth_rx_queue_id)
2254 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2255 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2256 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2257 uint8_t flow_id = dpaa2_ethq->flow_id;
2258 struct dpni_queue cfg;
2262 memset(&cfg, 0, sizeof(struct dpni_queue));
2263 options = DPNI_QUEUE_OPT_DEST;
2264 cfg.destination.type = DPNI_DEST_NONE;
2266 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2267 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2269 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2275 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2279 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2280 if (dpaa2_supported_filter_ops[i] == filter_op)
2287 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2288 enum rte_filter_type filter_type,
2289 enum rte_filter_op filter_op,
2297 switch (filter_type) {
2298 case RTE_ETH_FILTER_GENERIC:
2299 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2303 *(const void **)arg = &dpaa2_flow_ops;
2304 dpaa2_filter_type |= filter_type;
2307 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2316 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2317 struct rte_eth_rxq_info *qinfo)
2319 struct dpaa2_queue *rxq;
2321 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2323 qinfo->mp = rxq->mb_pool;
2324 qinfo->scattered_rx = dev->data->scattered_rx;
2325 qinfo->nb_desc = rxq->nb_desc;
2327 qinfo->conf.rx_free_thresh = 1;
2328 qinfo->conf.rx_drop_en = 1;
2329 qinfo->conf.rx_deferred_start = 0;
2330 qinfo->conf.offloads = rxq->offloads;
2334 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2335 struct rte_eth_txq_info *qinfo)
2337 struct dpaa2_queue *txq;
2339 txq = dev->data->tx_queues[queue_id];
2341 qinfo->nb_desc = txq->nb_desc;
2342 qinfo->conf.tx_thresh.pthresh = 0;
2343 qinfo->conf.tx_thresh.hthresh = 0;
2344 qinfo->conf.tx_thresh.wthresh = 0;
2346 qinfo->conf.tx_free_thresh = 0;
2347 qinfo->conf.tx_rs_thresh = 0;
2348 qinfo->conf.offloads = txq->offloads;
2349 qinfo->conf.tx_deferred_start = 0;
2353 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2355 *(const void **)ops = &dpaa2_tm_ops;
2360 static struct eth_dev_ops dpaa2_ethdev_ops = {
2361 .dev_configure = dpaa2_eth_dev_configure,
2362 .dev_start = dpaa2_dev_start,
2363 .dev_stop = dpaa2_dev_stop,
2364 .dev_close = dpaa2_dev_close,
2365 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2366 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2367 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2368 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2369 .dev_set_link_up = dpaa2_dev_set_link_up,
2370 .dev_set_link_down = dpaa2_dev_set_link_down,
2371 .link_update = dpaa2_dev_link_update,
2372 .stats_get = dpaa2_dev_stats_get,
2373 .xstats_get = dpaa2_dev_xstats_get,
2374 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2375 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2376 .xstats_get_names = dpaa2_xstats_get_names,
2377 .stats_reset = dpaa2_dev_stats_reset,
2378 .xstats_reset = dpaa2_dev_stats_reset,
2379 .fw_version_get = dpaa2_fw_version_get,
2380 .dev_infos_get = dpaa2_dev_info_get,
2381 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2382 .mtu_set = dpaa2_dev_mtu_set,
2383 .vlan_filter_set = dpaa2_vlan_filter_set,
2384 .vlan_offload_set = dpaa2_vlan_offload_set,
2385 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2386 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2387 .rx_queue_release = dpaa2_dev_rx_queue_release,
2388 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2389 .tx_queue_release = dpaa2_dev_tx_queue_release,
2390 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2391 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2392 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2393 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2394 .mac_addr_add = dpaa2_dev_add_mac_addr,
2395 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2396 .mac_addr_set = dpaa2_dev_set_mac_addr,
2397 .rss_hash_update = dpaa2_dev_rss_hash_update,
2398 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2399 .filter_ctrl = dpaa2_dev_flow_ctrl,
2400 .rxq_info_get = dpaa2_rxq_info_get,
2401 .txq_info_get = dpaa2_txq_info_get,
2402 .tm_ops_get = dpaa2_tm_ops_get,
2403 #if defined(RTE_LIBRTE_IEEE1588)
2404 .timesync_enable = dpaa2_timesync_enable,
2405 .timesync_disable = dpaa2_timesync_disable,
2406 .timesync_read_time = dpaa2_timesync_read_time,
2407 .timesync_write_time = dpaa2_timesync_write_time,
2408 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2409 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2410 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2414 /* Populate the mac address from physically available (u-boot/firmware) and/or
2415 * one set by higher layers like MC (restool) etc.
2416 * Returns the table of MAC entries (multiple entries)
2419 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2420 struct rte_ether_addr *mac_entry)
2423 struct rte_ether_addr phy_mac, prime_mac;
2425 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2426 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2428 /* Get the physical device MAC address */
2429 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2430 phy_mac.addr_bytes);
2432 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2436 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2437 prime_mac.addr_bytes);
2439 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2443 /* Now that both MAC have been obtained, do:
2444 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2446 * If empty_mac(phy), return prime.
2447 * if both are empty, create random MAC, set as prime and return
2449 if (!rte_is_zero_ether_addr(&phy_mac)) {
2450 /* If the addresses are not same, overwrite prime */
2451 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2452 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2454 phy_mac.addr_bytes);
2456 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2460 memcpy(&prime_mac, &phy_mac,
2461 sizeof(struct rte_ether_addr));
2463 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2464 /* In case phys and prime, both are zero, create random MAC */
2465 rte_eth_random_addr(prime_mac.addr_bytes);
2466 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2468 prime_mac.addr_bytes);
2470 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2475 /* prime_mac the final MAC address */
2476 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2484 check_devargs_handler(__rte_unused const char *key, const char *value,
2485 __rte_unused void *opaque)
2487 if (strcmp(value, "1"))
2494 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2496 struct rte_kvargs *kvlist;
2501 kvlist = rte_kvargs_parse(devargs->args, NULL);
2505 if (!rte_kvargs_count(kvlist, key)) {
2506 rte_kvargs_free(kvlist);
2510 if (rte_kvargs_process(kvlist, key,
2511 check_devargs_handler, NULL) < 0) {
2512 rte_kvargs_free(kvlist);
2515 rte_kvargs_free(kvlist);
2521 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2523 struct rte_device *dev = eth_dev->device;
2524 struct rte_dpaa2_device *dpaa2_dev;
2525 struct fsl_mc_io *dpni_dev;
2526 struct dpni_attr attr;
2527 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2528 struct dpni_buffer_layout layout;
2531 PMD_INIT_FUNC_TRACE();
2533 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2535 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2538 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2539 eth_dev->process_private = (void *)dpni_dev;
2541 /* For secondary processes, the primary has done all the work */
2542 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2543 /* In case of secondary, only burst and ops API need to be
2546 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2547 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2548 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2549 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2550 else if (dpaa2_get_devargs(dev->devargs,
2551 DRIVER_NO_PREFETCH_MODE))
2552 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2554 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2555 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2559 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2561 hw_id = dpaa2_dev->object_id;
2562 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2565 "Failure in opening dpni@%d with err code %d",
2571 /* Clean the device first */
2572 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2574 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2579 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2582 "Failure in get dpni@%d attribute, err code %d",
2587 priv->num_rx_tc = attr.num_rx_tcs;
2588 priv->qos_entries = attr.qos_entries;
2589 priv->fs_entries = attr.fs_entries;
2590 priv->dist_queues = attr.num_queues;
2592 /* only if the custom CG is enabled */
2593 if (attr.options & DPNI_OPT_CUSTOM_CG)
2594 priv->max_cgs = attr.num_cgs;
2598 for (i = 0; i < priv->max_cgs; i++)
2599 priv->cgid_in_use[i] = 0;
2601 for (i = 0; i < attr.num_rx_tcs; i++)
2602 priv->nb_rx_queues += attr.num_queues;
2604 /* Using number of TX queues as number of TX TCs */
2605 priv->nb_tx_queues = attr.num_tx_tcs;
2607 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2608 priv->num_rx_tc, priv->nb_rx_queues,
2609 priv->nb_tx_queues, priv->max_cgs);
2611 priv->hw = dpni_dev;
2612 priv->hw_id = hw_id;
2613 priv->options = attr.options;
2614 priv->max_mac_filters = attr.mac_filter_entries;
2615 priv->max_vlan_filters = attr.vlan_filter_entries;
2617 #if defined(RTE_LIBRTE_IEEE1588)
2618 printf("DPDK IEEE1588 is enabled\n");
2619 priv->flags |= DPAA2_TX_CONF_ENABLE;
2621 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2622 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2623 priv->flags |= DPAA2_TX_CONF_ENABLE;
2624 DPAA2_PMD_INFO("TX_CONF Enabled");
2627 /* Allocate memory for hardware structure for queues */
2628 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2630 DPAA2_PMD_ERR("Queue allocation Failed");
2634 /* Allocate memory for storing MAC addresses.
2635 * Table of mac_filter_entries size is allocated so that RTE ether lib
2636 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2638 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2639 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2640 if (eth_dev->data->mac_addrs == NULL) {
2642 "Failed to allocate %d bytes needed to store MAC addresses",
2643 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2648 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2650 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2651 rte_free(eth_dev->data->mac_addrs);
2652 eth_dev->data->mac_addrs = NULL;
2656 /* ... tx buffer layout ... */
2657 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2658 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2659 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2660 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2661 layout.pass_timestamp = true;
2663 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2665 layout.pass_frame_status = 1;
2666 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2667 DPNI_QUEUE_TX, &layout);
2669 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2673 /* ... tx-conf and error buffer layout ... */
2674 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2675 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2676 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2677 layout.pass_timestamp = true;
2679 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2680 layout.pass_frame_status = 1;
2681 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2682 DPNI_QUEUE_TX_CONFIRM, &layout);
2684 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2689 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2691 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2692 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2693 DPAA2_PMD_INFO("Loopback mode");
2694 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2695 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2696 DPAA2_PMD_INFO("No Prefetch mode");
2698 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2700 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2702 /*Init fields w.r.t. classficaition*/
2703 memset(&priv->extract.qos_key_extract, 0,
2704 sizeof(struct dpaa2_key_extract));
2705 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2706 if (!priv->extract.qos_extract_param) {
2707 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2708 " classificaiton ", ret);
2711 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2712 IP_ADDRESS_OFFSET_INVALID;
2713 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2714 IP_ADDRESS_OFFSET_INVALID;
2715 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2716 IP_ADDRESS_OFFSET_INVALID;
2717 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2718 IP_ADDRESS_OFFSET_INVALID;
2720 for (i = 0; i < MAX_TCS; i++) {
2721 memset(&priv->extract.tc_key_extract[i], 0,
2722 sizeof(struct dpaa2_key_extract));
2723 priv->extract.tc_extract_param[i] =
2724 (size_t)rte_malloc(NULL, 256, 64);
2725 if (!priv->extract.tc_extract_param[i]) {
2726 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2730 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2731 IP_ADDRESS_OFFSET_INVALID;
2732 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2733 IP_ADDRESS_OFFSET_INVALID;
2734 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2735 IP_ADDRESS_OFFSET_INVALID;
2736 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2737 IP_ADDRESS_OFFSET_INVALID;
2740 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2741 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2744 DPAA2_PMD_ERR("Unable to set mtu. check config");
2748 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2749 * with external entity to receive byte code for software sequence
2750 * and same will be offload to the H/W using MC interface.
2751 * Currently it is assumed that DPAA2 driver has byte code by some
2752 * mean and same if offloaded to H/W.
2754 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2755 WRIOP_SS_INITIALIZER(priv);
2756 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2758 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2763 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2766 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2771 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2774 dpaa2_dev_close(eth_dev);
2780 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2781 struct rte_dpaa2_device *dpaa2_dev)
2783 struct rte_eth_dev *eth_dev;
2784 struct dpaa2_dev_priv *dev_priv;
2787 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2788 RTE_PKTMBUF_HEADROOM) {
2790 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2791 RTE_PKTMBUF_HEADROOM,
2792 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2797 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2798 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2801 dev_priv = rte_zmalloc("ethdev private structure",
2802 sizeof(struct dpaa2_dev_priv),
2803 RTE_CACHE_LINE_SIZE);
2804 if (dev_priv == NULL) {
2806 "Unable to allocate memory for private data");
2807 rte_eth_dev_release_port(eth_dev);
2810 eth_dev->data->dev_private = (void *)dev_priv;
2811 /* Store a pointer to eth_dev in dev_private */
2812 dev_priv->eth_dev = eth_dev;
2814 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2816 DPAA2_PMD_DEBUG("returning enodev");
2821 eth_dev->device = &dpaa2_dev->device;
2823 dpaa2_dev->eth_dev = eth_dev;
2824 eth_dev->data->rx_mbuf_alloc_failed = 0;
2826 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2827 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2829 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2831 /* Invoke PMD device initialization function */
2832 diag = dpaa2_dev_init(eth_dev);
2834 rte_eth_dev_probing_finish(eth_dev);
2838 rte_eth_dev_release_port(eth_dev);
2843 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2845 struct rte_eth_dev *eth_dev;
2848 eth_dev = dpaa2_dev->eth_dev;
2849 dpaa2_dev_close(eth_dev);
2850 ret = rte_eth_dev_release_port(eth_dev);
2855 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2856 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2857 .drv_type = DPAA2_ETH,
2858 .probe = rte_dpaa2_probe,
2859 .remove = rte_dpaa2_remove,
2862 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2863 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2864 DRIVER_LOOPBACK_MODE "=<int> "
2865 DRIVER_NO_PREFETCH_MODE "=<int>"
2866 DRIVER_TX_CONF "=<int>");
2867 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);