drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "dpaa2_pmd_logs.h"
  23 #include <fslmc_vfio.h>
  24 #include <dpaa2_hw_pvt.h>
  25 #include <dpaa2_hw_mempool.h>
  26 #include <dpaa2_hw_dpio.h>
  27 #include <mc/fsl_dpmng.h>
  28 #include "dpaa2_ethdev.h"
  29 #include "dpaa2_sparser.h"
  30 #include <fsl_qbman_debug.h>
  31
  32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  34 #define DRIVER_TX_CONF "drv_tx_conf"
  35 #define CHECK_INTERVAL         100  /* 100ms */
  36 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  37
  38 /* Supported Rx offloads */
  39 static uint64_t dev_rx_offloads_sup =
  40                 DEV_RX_OFFLOAD_CHECKSUM |
  41                 DEV_RX_OFFLOAD_SCTP_CKSUM |
  42                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  43                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
  44                 DEV_RX_OFFLOAD_VLAN_STRIP |
  45                 DEV_RX_OFFLOAD_VLAN_FILTER |
  46                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  47                 DEV_RX_OFFLOAD_TIMESTAMP;
  48
  49 /* Rx offloads which cannot be disabled */
  50 static uint64_t dev_rx_offloads_nodis =
  51                 DEV_RX_OFFLOAD_RSS_HASH |
  52                 DEV_RX_OFFLOAD_SCATTER;
  53
  54 /* Supported Tx offloads */
  55 static uint64_t dev_tx_offloads_sup =
  56                 DEV_TX_OFFLOAD_VLAN_INSERT |
  57                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  58                 DEV_TX_OFFLOAD_UDP_CKSUM |
  59                 DEV_TX_OFFLOAD_TCP_CKSUM |
  60                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  61                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  62                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  63                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  64
  65 /* Tx offloads which cannot be disabled */
  66 static uint64_t dev_tx_offloads_nodis =
  67                 DEV_TX_OFFLOAD_MULTI_SEGS;
  68
  69 /* enable timestamp in mbuf */
  70 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  71 uint64_t dpaa2_timestamp_rx_dynflag;
  72 int dpaa2_timestamp_dynfield_offset = -1;
  73
  74 struct rte_dpaa2_xstats_name_off {
  75         char name[RTE_ETH_XSTATS_NAME_SIZE];
  76         uint8_t page_id; /* dpni statistics page id */
  77         uint8_t stats_id; /* stats id in the given page */
  78 };
  79
  80 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  81         {"ingress_multicast_frames", 0, 2},
  82         {"ingress_multicast_bytes", 0, 3},
  83         {"ingress_broadcast_frames", 0, 4},
  84         {"ingress_broadcast_bytes", 0, 5},
  85         {"egress_multicast_frames", 1, 2},
  86         {"egress_multicast_bytes", 1, 3},
  87         {"egress_broadcast_frames", 1, 4},
  88         {"egress_broadcast_bytes", 1, 5},
  89         {"ingress_filtered_frames", 2, 0},
  90         {"ingress_discarded_frames", 2, 1},
  91         {"ingress_nobuffer_discards", 2, 2},
  92         {"egress_discarded_frames", 2, 3},
  93         {"egress_confirmed_frames", 2, 4},
  94         {"cgr_reject_frames", 4, 0},
  95         {"cgr_reject_bytes", 4, 1},
  96 };
  97
  98 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
  99         RTE_ETH_FILTER_GET
 100 };
 101
 102 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 104                                  int wait_to_complete);
 105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 108
 109 static int
 110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 111 {
 112         int ret;
 113         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 114         struct fsl_mc_io *dpni = dev->process_private;
 115
 116         PMD_INIT_FUNC_TRACE();
 117
 118         if (dpni == NULL) {
 119                 DPAA2_PMD_ERR("dpni is NULL");
 120                 return -1;
 121         }
 122
 123         if (on)
 124                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 125                                        vlan_id, 0, 0, 0);
 126         else
 127                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 128                                           priv->token, vlan_id);
 129
 130         if (ret < 0)
 131                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 132                               ret, vlan_id, priv->hw_id);
 133
 134         return ret;
 135 }
 136
 137 static int
 138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 139 {
 140         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 141         struct fsl_mc_io *dpni = dev->process_private;
 142         int ret = 0;
 143
 144         PMD_INIT_FUNC_TRACE();
 145
 146         if (mask & ETH_VLAN_FILTER_MASK) {
 147                 /* VLAN Filter not avaialble */
 148                 if (!priv->max_vlan_filters) {
 149                         DPAA2_PMD_INFO("VLAN filter not available");
 150                         return -ENOTSUP;
 151                 }
 152
 153                 if (dev->data->dev_conf.rxmode.offloads &
 154                         DEV_RX_OFFLOAD_VLAN_FILTER)
 155                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 156                                                       priv->token, true);
 157                 else
 158                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 159                                                       priv->token, false);
 160                 if (ret < 0)
 161                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 162         }
 163
 164         return ret;
 165 }
 166
 167 static int
 168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 169                       enum rte_vlan_type vlan_type __rte_unused,
 170                       uint16_t tpid)
 171 {
 172         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 173         struct fsl_mc_io *dpni = dev->process_private;
 174         int ret = -ENOTSUP;
 175
 176         PMD_INIT_FUNC_TRACE();
 177
 178         /* nothing to be done for standard vlan tpids */
 179         if (tpid == 0x8100 || tpid == 0x88A8)
 180                 return 0;
 181
 182         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 183                                    priv->token, tpid);
 184         if (ret < 0)
 185                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 186         /* if already configured tpids, remove them first */
 187         if (ret == -EBUSY) {
 188                 struct dpni_custom_tpid_cfg tpid_list = {0};
 189
 190                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 191                                    priv->token, &tpid_list);
 192                 if (ret < 0)
 193                         goto fail;
 194                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 195                                    priv->token, tpid_list.tpid1);
 196                 if (ret < 0)
 197                         goto fail;
 198                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 199                                            priv->token, tpid);
 200         }
 201 fail:
 202         return ret;
 203 }
 204
 205 static int
 206 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 207                      char *fw_version,
 208                      size_t fw_size)
 209 {
 210         int ret;
 211         struct fsl_mc_io *dpni = dev->process_private;
 212         struct mc_soc_version mc_plat_info = {0};
 213         struct mc_version mc_ver_info = {0};
 214
 215         PMD_INIT_FUNC_TRACE();
 216
 217         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 218                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 219
 220         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 221                 DPAA2_PMD_WARN("\tmc_get_version failed");
 222
 223         ret = snprintf(fw_version, fw_size,
 224                        "%x-%d.%d.%d",
 225                        mc_plat_info.svr,
 226                        mc_ver_info.major,
 227                        mc_ver_info.minor,
 228                        mc_ver_info.revision);
 229
 230         ret += 1; /* add the size of '\0' */
 231         if (fw_size < (uint32_t)ret)
 232                 return ret;
 233         else
 234                 return 0;
 235 }
 236
 237 static int
 238 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 239 {
 240         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 241
 242         PMD_INIT_FUNC_TRACE();
 243
 244         dev_info->max_mac_addrs = priv->max_mac_filters;
 245         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 246         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 247         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 248         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 249         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 250                                         dev_rx_offloads_nodis;
 251         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 252                                         dev_tx_offloads_nodis;
 253         dev_info->speed_capa = ETH_LINK_SPEED_1G |
 254                         ETH_LINK_SPEED_2_5G |
 255                         ETH_LINK_SPEED_10G;
 256
 257         dev_info->max_hash_mac_addrs = 0;
 258         dev_info->max_vfs = 0;
 259         dev_info->max_vmdq_pools = ETH_16_POOLS;
 260         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 261
 262         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 263         /* same is rx size for best perf */
 264         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 265
 266         dev_info->default_rxportconf.nb_queues = 1;
 267         dev_info->default_txportconf.nb_queues = 1;
 268         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 269         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 270
 271         if (dpaa2_svr_family == SVR_LX2160A) {
 272                 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
 273                                 ETH_LINK_SPEED_40G |
 274                                 ETH_LINK_SPEED_50G |
 275                                 ETH_LINK_SPEED_100G;
 276         }
 277
 278         return 0;
 279 }
 280
 281 static int
 282 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 283                         __rte_unused uint16_t queue_id,
 284                         struct rte_eth_burst_mode *mode)
 285 {
 286         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 287         int ret = -EINVAL;
 288         unsigned int i;
 289         const struct burst_info {
 290                 uint64_t flags;
 291                 const char *output;
 292         } rx_offload_map[] = {
 293                         {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 294                         {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 295                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 296                         {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 297                         {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 298                         {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 299                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 300                         {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 301                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
 302                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
 303         };
 304
 305         /* Update Rx offload info */
 306         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 307                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 308                         snprintf(mode->info, sizeof(mode->info), "%s",
 309                                 rx_offload_map[i].output);
 310                         ret = 0;
 311                         break;
 312                 }
 313         }
 314         return ret;
 315 }
 316
 317 static int
 318 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 319                         __rte_unused uint16_t queue_id,
 320                         struct rte_eth_burst_mode *mode)
 321 {
 322         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 323         int ret = -EINVAL;
 324         unsigned int i;
 325         const struct burst_info {
 326                 uint64_t flags;
 327                 const char *output;
 328         } tx_offload_map[] = {
 329                         {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 330                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 331                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 332                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 333                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 334                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 335                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 336                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 337                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 338         };
 339
 340         /* Update Tx offload info */
 341         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 342                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 343                         snprintf(mode->info, sizeof(mode->info), "%s",
 344                                 tx_offload_map[i].output);
 345                         ret = 0;
 346                         break;
 347                 }
 348         }
 349         return ret;
 350 }
 351
 352 static int
 353 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 354 {
 355         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 356         uint16_t dist_idx;
 357         uint32_t vq_id;
 358         uint8_t num_rxqueue_per_tc;
 359         struct dpaa2_queue *mc_q, *mcq;
 360         uint32_t tot_queues;
 361         int i;
 362         struct dpaa2_queue *dpaa2_q;
 363
 364         PMD_INIT_FUNC_TRACE();
 365
 366         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 367         if (priv->flags & DPAA2_TX_CONF_ENABLE)
 368                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 369         else
 370                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 371         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 372                           RTE_CACHE_LINE_SIZE);
 373         if (!mc_q) {
 374                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 375                 return -1;
 376         }
 377
 378         for (i = 0; i < priv->nb_rx_queues; i++) {
 379                 mc_q->eth_data = dev->data;
 380                 priv->rx_vq[i] = mc_q++;
 381                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 382                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 383                                         sizeof(struct queue_storage_info_t),
 384                                         RTE_CACHE_LINE_SIZE);
 385                 if (!dpaa2_q->q_storage)
 386                         goto fail;
 387
 388                 memset(dpaa2_q->q_storage, 0,
 389                        sizeof(struct queue_storage_info_t));
 390                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 391                         goto fail;
 392         }
 393
 394         for (i = 0; i < priv->nb_tx_queues; i++) {
 395                 mc_q->eth_data = dev->data;
 396                 mc_q->flow_id = 0xffff;
 397                 priv->tx_vq[i] = mc_q++;
 398                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 399                 dpaa2_q->cscn = rte_malloc(NULL,
 400                                            sizeof(struct qbman_result), 16);
 401                 if (!dpaa2_q->cscn)
 402                         goto fail_tx;
 403         }
 404
 405         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 406                 /*Setup tx confirmation queues*/
 407                 for (i = 0; i < priv->nb_tx_queues; i++) {
 408                         mc_q->eth_data = dev->data;
 409                         mc_q->tc_index = i;
 410                         mc_q->flow_id = 0;
 411                         priv->tx_conf_vq[i] = mc_q++;
 412                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 413                         dpaa2_q->q_storage =
 414                                 rte_malloc("dq_storage",
 415                                         sizeof(struct queue_storage_info_t),
 416                                         RTE_CACHE_LINE_SIZE);
 417                         if (!dpaa2_q->q_storage)
 418                                 goto fail_tx_conf;
 419
 420                         memset(dpaa2_q->q_storage, 0,
 421                                sizeof(struct queue_storage_info_t));
 422                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 423                                 goto fail_tx_conf;
 424                 }
 425         }
 426
 427         vq_id = 0;
 428         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 429                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 430                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 431                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 432                 vq_id++;
 433         }
 434
 435         return 0;
 436 fail_tx_conf:
 437         i -= 1;
 438         while (i >= 0) {
 439                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 440                 rte_free(dpaa2_q->q_storage);
 441                 priv->tx_conf_vq[i--] = NULL;
 442         }
 443         i = priv->nb_tx_queues;
 444 fail_tx:
 445         i -= 1;
 446         while (i >= 0) {
 447                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 448                 rte_free(dpaa2_q->cscn);
 449                 priv->tx_vq[i--] = NULL;
 450         }
 451         i = priv->nb_rx_queues;
 452 fail:
 453         i -= 1;
 454         mc_q = priv->rx_vq[0];
 455         while (i >= 0) {
 456                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 457                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 458                 rte_free(dpaa2_q->q_storage);
 459                 priv->rx_vq[i--] = NULL;
 460         }
 461         rte_free(mc_q);
 462         return -1;
 463 }
 464
 465 static void
 466 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 467 {
 468         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 469         struct dpaa2_queue *dpaa2_q;
 470         int i;
 471
 472         PMD_INIT_FUNC_TRACE();
 473
 474         /* Queue allocation base */
 475         if (priv->rx_vq[0]) {
 476                 /* cleaning up queue storage */
 477                 for (i = 0; i < priv->nb_rx_queues; i++) {
 478                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 479                         if (dpaa2_q->q_storage)
 480                                 rte_free(dpaa2_q->q_storage);
 481                 }
 482                 /* cleanup tx queue cscn */
 483                 for (i = 0; i < priv->nb_tx_queues; i++) {
 484                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 485                         rte_free(dpaa2_q->cscn);
 486                 }
 487                 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 488                         /* cleanup tx conf queue storage */
 489                         for (i = 0; i < priv->nb_tx_queues; i++) {
 490                                 dpaa2_q = (struct dpaa2_queue *)
 491                                                 priv->tx_conf_vq[i];
 492                                 rte_free(dpaa2_q->q_storage);
 493                         }
 494                 }
 495                 /*free memory for all queues (RX+TX) */
 496                 rte_free(priv->rx_vq[0]);
 497                 priv->rx_vq[0] = NULL;
 498         }
 499 }
 500
 501 static int
 502 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 503 {
 504         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 505         struct fsl_mc_io *dpni = dev->process_private;
 506         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 507         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 508         uint64_t tx_offloads = eth_conf->txmode.offloads;
 509         int rx_l3_csum_offload = false;
 510         int rx_l4_csum_offload = false;
 511         int tx_l3_csum_offload = false;
 512         int tx_l4_csum_offload = false;
 513         int ret, tc_index;
 514
 515         PMD_INIT_FUNC_TRACE();
 516
 517         /* Rx offloads which are enabled by default */
 518         if (dev_rx_offloads_nodis & ~rx_offloads) {
 519                 DPAA2_PMD_INFO(
 520                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 521                 " fixed are 0x%" PRIx64,
 522                 rx_offloads, dev_rx_offloads_nodis);
 523         }
 524
 525         /* Tx offloads which are enabled by default */
 526         if (dev_tx_offloads_nodis & ~tx_offloads) {
 527                 DPAA2_PMD_INFO(
 528                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 529                 " fixed are 0x%" PRIx64,
 530                 tx_offloads, dev_tx_offloads_nodis);
 531         }
 532
 533         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 534                 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
 535                         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 536                                 priv->token, eth_conf->rxmode.max_rx_pkt_len
 537                                 - RTE_ETHER_CRC_LEN);
 538                         if (ret) {
 539                                 DPAA2_PMD_ERR(
 540                                         "Unable to set mtu. check config");
 541                                 return ret;
 542                         }
 543                         dev->data->mtu =
 544                                 dev->data->dev_conf.rxmode.max_rx_pkt_len -
 545                                 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
 546                                 VLAN_TAG_SIZE;
 547                 } else {
 548                         return -1;
 549                 }
 550         }
 551
 552         if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
 553                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 554                         ret = dpaa2_setup_flow_dist(dev,
 555                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 556                                         tc_index);
 557                         if (ret) {
 558                                 DPAA2_PMD_ERR(
 559                                         "Unable to set flow distribution on tc%d."
 560                                         "Check queue config", tc_index);
 561                                 return ret;
 562                         }
 563                 }
 564         }
 565
 566         if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
 567                 rx_l3_csum_offload = true;
 568
 569         if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
 570                 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
 571                 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
 572                 rx_l4_csum_offload = true;
 573
 574         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 575                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 576         if (ret) {
 577                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 578                 return ret;
 579         }
 580
 581         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 582                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 583         if (ret) {
 584                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 585                 return ret;
 586         }
 587
 588 #if !defined(RTE_LIBRTE_IEEE1588)
 589         if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
 590 #endif
 591         {
 592                 ret = rte_mbuf_dyn_rx_timestamp_register(
 593                                 &dpaa2_timestamp_dynfield_offset,
 594                                 &dpaa2_timestamp_rx_dynflag);
 595                 if (ret != 0) {
 596                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 597                         return -rte_errno;
 598                 }
 599                 dpaa2_enable_ts[dev->data->port_id] = true;
 600         }
 601
 602         if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
 603                 tx_l3_csum_offload = true;
 604
 605         if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
 606                 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
 607                 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
 608                 tx_l4_csum_offload = true;
 609
 610         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 611                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 612         if (ret) {
 613                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 614                 return ret;
 615         }
 616
 617         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 618                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 619         if (ret) {
 620                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 621                 return ret;
 622         }
 623
 624         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 625          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 626          * to 0 for LS2 in the hardware thus disabling data/annotation
 627          * stashing. For LX2 this is fixed in hardware and thus hash result and
 628          * parse results can be received in FD using this option.
 629          */
 630         if (dpaa2_svr_family == SVR_LX2160A) {
 631                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 632                                        DPNI_FLCTYPE_HASH, true);
 633                 if (ret) {
 634                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 635                         return ret;
 636                 }
 637         }
 638
 639         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 640                 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
 641
 642         dpaa2_tm_init(dev);
 643
 644         return 0;
 645 }
 646
 647 /* Function to setup RX flow information. It contains traffic class ID,
 648  * flow ID, destination configuration etc.
 649  */
 650 static int
 651 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 652                          uint16_t rx_queue_id,
 653                          uint16_t nb_rx_desc,
 654                          unsigned int socket_id __rte_unused,
 655                          const struct rte_eth_rxconf *rx_conf,
 656                          struct rte_mempool *mb_pool)
 657 {
 658         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 659         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 660         struct dpaa2_queue *dpaa2_q;
 661         struct dpni_queue cfg;
 662         uint8_t options = 0;
 663         uint8_t flow_id;
 664         uint32_t bpid;
 665         int i, ret;
 666
 667         PMD_INIT_FUNC_TRACE();
 668
 669         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 670                         dev, rx_queue_id, mb_pool, rx_conf);
 671
 672         /* Rx deferred start is not supported */
 673         if (rx_conf->rx_deferred_start) {
 674                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 675                                 (void *)dev);
 676                 return -EINVAL;
 677         }
 678
 679         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 680                 bpid = mempool_to_bpid(mb_pool);
 681                 ret = dpaa2_attach_bp_list(priv,
 682                                            rte_dpaa2_bpid_info[bpid].bp_list);
 683                 if (ret)
 684                         return ret;
 685         }
 686         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 687         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 688         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 689         dpaa2_q->nb_desc = UINT16_MAX;
 690         dpaa2_q->offloads = rx_conf->offloads;
 691
 692         /*Get the flow id from given VQ id*/
 693         flow_id = dpaa2_q->flow_id;
 694         memset(&cfg, 0, sizeof(struct dpni_queue));
 695
 696         options = options | DPNI_QUEUE_OPT_USER_CTX;
 697         cfg.user_context = (size_t)(dpaa2_q);
 698
 699         /* check if a private cgr available. */
 700         for (i = 0; i < priv->max_cgs; i++) {
 701                 if (!priv->cgid_in_use[i]) {
 702                         priv->cgid_in_use[i] = 1;
 703                         break;
 704                 }
 705         }
 706
 707         if (i < priv->max_cgs) {
 708                 options |= DPNI_QUEUE_OPT_SET_CGID;
 709                 cfg.cgid = i;
 710                 dpaa2_q->cgid = cfg.cgid;
 711         } else {
 712                 dpaa2_q->cgid = 0xff;
 713         }
 714
 715         /*if ls2088 or rev2 device, enable the stashing */
 716
 717         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 718                 options |= DPNI_QUEUE_OPT_FLC;
 719                 cfg.flc.stash_control = true;
 720                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 721                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 722                  * data stashing setting 01 01 00 (0x14)
 723                  * (in following order ->DS AS CS)
 724                  * to enable 1 line data, 1 line annotation.
 725                  * For LX2, this setting should be 01 00 00 (0x10)
 726                  */
 727                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 728                         cfg.flc.value |= 0x10;
 729                 else
 730                         cfg.flc.value |= 0x14;
 731         }
 732         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 733                              dpaa2_q->tc_index, flow_id, options, &cfg);
 734         if (ret) {
 735                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 736                 return -1;
 737         }
 738
 739         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 740                 struct dpni_taildrop taildrop;
 741
 742                 taildrop.enable = 1;
 743                 dpaa2_q->nb_desc = nb_rx_desc;
 744                 /* Private CGR will use tail drop length as nb_rx_desc.
 745                  * for rest cases we can use standard byte based tail drop.
 746                  * There is no HW restriction, but number of CGRs are limited,
 747                  * hence this restriction is placed.
 748                  */
 749                 if (dpaa2_q->cgid != 0xff) {
 750                         /*enabling per rx queue congestion control */
 751                         taildrop.threshold = nb_rx_desc;
 752                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 753                         taildrop.oal = 0;
 754                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 755                                         rx_queue_id);
 756                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 757                                                 DPNI_CP_CONGESTION_GROUP,
 758                                                 DPNI_QUEUE_RX,
 759                                                 dpaa2_q->tc_index,
 760                                                 dpaa2_q->cgid, &taildrop);
 761                 } else {
 762                         /*enabling per rx queue congestion control */
 763                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 764                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 765                         taildrop.oal = CONG_RX_OAL;
 766                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 767                                         rx_queue_id);
 768                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 769                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 770                                                 dpaa2_q->tc_index, flow_id,
 771                                                 &taildrop);
 772                 }
 773                 if (ret) {
 774                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 775                                       ret);
 776                         return -1;
 777                 }
 778         } else { /* Disable tail Drop */
 779                 struct dpni_taildrop taildrop = {0};
 780                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 781
 782                 taildrop.enable = 0;
 783                 if (dpaa2_q->cgid != 0xff) {
 784                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 785                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 786                                         dpaa2_q->tc_index,
 787                                         dpaa2_q->cgid, &taildrop);
 788                 } else {
 789                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 790                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 791                                         dpaa2_q->tc_index, flow_id, &taildrop);
 792                 }
 793                 if (ret) {
 794                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 795                                       ret);
 796                         return -1;
 797                 }
 798         }
 799
 800         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 801         return 0;
 802 }
 803
 804 static int
 805 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 806                          uint16_t tx_queue_id,
 807                          uint16_t nb_tx_desc,
 808                          unsigned int socket_id __rte_unused,
 809                          const struct rte_eth_txconf *tx_conf)
 810 {
 811         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 812         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 813                 priv->tx_vq[tx_queue_id];
 814         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 815                 priv->tx_conf_vq[tx_queue_id];
 816         struct fsl_mc_io *dpni = dev->process_private;
 817         struct dpni_queue tx_conf_cfg;
 818         struct dpni_queue tx_flow_cfg;
 819         uint8_t options = 0, flow_id;
 820         struct dpni_queue_id qid;
 821         uint32_t tc_id;
 822         int ret;
 823
 824         PMD_INIT_FUNC_TRACE();
 825
 826         /* Tx deferred start is not supported */
 827         if (tx_conf->tx_deferred_start) {
 828                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 829                                 (void *)dev);
 830                 return -EINVAL;
 831         }
 832
 833         dpaa2_q->nb_desc = UINT16_MAX;
 834         dpaa2_q->offloads = tx_conf->offloads;
 835
 836         /* Return if queue already configured */
 837         if (dpaa2_q->flow_id != 0xffff) {
 838                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 839                 return 0;
 840         }
 841
 842         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 843         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 844
 845         tc_id = tx_queue_id;
 846         flow_id = 0;
 847
 848         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 849                         tc_id, flow_id, options, &tx_flow_cfg);
 850         if (ret) {
 851                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 852                         "tc_id=%d, flow=%d err=%d",
 853                         tc_id, flow_id, ret);
 854                         return -1;
 855         }
 856
 857         dpaa2_q->flow_id = flow_id;
 858
 859         if (tx_queue_id == 0) {
 860                 /*Set tx-conf and error configuration*/
 861                 if (priv->flags & DPAA2_TX_CONF_ENABLE)
 862                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 863                                                             priv->token,
 864                                                             DPNI_CONF_AFFINE);
 865                 else
 866                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 867                                                             priv->token,
 868                                                             DPNI_CONF_DISABLE);
 869                 if (ret) {
 870                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 871                                       "err=%d", ret);
 872                         return -1;
 873                 }
 874         }
 875         dpaa2_q->tc_index = tc_id;
 876
 877         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 878                              DPNI_QUEUE_TX, dpaa2_q->tc_index,
 879                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 880         if (ret) {
 881                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 882                 return -1;
 883         }
 884         dpaa2_q->fqid = qid.fqid;
 885
 886         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 887                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 888
 889                 dpaa2_q->nb_desc = nb_tx_desc;
 890
 891                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 892                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 893                 /* Notify that the queue is not congested when the data in
 894                  * the queue is below this thershold.
 895                  */
 896                 cong_notif_cfg.threshold_exit = nb_tx_desc - 24;
 897                 cong_notif_cfg.message_ctx = 0;
 898                 cong_notif_cfg.message_iova =
 899                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 900                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 901                 cong_notif_cfg.notification_mode =
 902                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 903                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 904                                          DPNI_CONG_OPT_COHERENT_WRITE;
 905                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 906
 907                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 908                                                        priv->token,
 909                                                        DPNI_QUEUE_TX,
 910                                                        tc_id,
 911                                                        &cong_notif_cfg);
 912                 if (ret) {
 913                         DPAA2_PMD_ERR(
 914                            "Error in setting tx congestion notification: "
 915                            "err=%d", ret);
 916                         return -ret;
 917                 }
 918         }
 919         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 920         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 921
 922         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 923                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 924                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 925                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 926                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 927                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 928                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 929                 if (ret) {
 930                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 931                               "tc_index=%d, flow=%d err=%d",
 932                               dpaa2_tx_conf_q->tc_index,
 933                               dpaa2_tx_conf_q->flow_id, ret);
 934                         return -1;
 935                 }
 936
 937                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 938                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 939                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 940                 if (ret) {
 941                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 942                         return -1;
 943                 }
 944                 dpaa2_tx_conf_q->fqid = qid.fqid;
 945         }
 946         return 0;
 947 }
 948
 949 static void
 950 dpaa2_dev_rx_queue_release(void *q __rte_unused)
 951 {
 952         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
 953         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 954         struct fsl_mc_io *dpni =
 955                 (struct fsl_mc_io *)priv->eth_dev->process_private;
 956         uint8_t options = 0;
 957         int ret;
 958         struct dpni_queue cfg;
 959
 960         memset(&cfg, 0, sizeof(struct dpni_queue));
 961         PMD_INIT_FUNC_TRACE();
 962         if (dpaa2_q->cgid != 0xff) {
 963                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
 964                 cfg.cgid = dpaa2_q->cgid;
 965
 966                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 967                                      DPNI_QUEUE_RX,
 968                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
 969                                      options, &cfg);
 970                 if (ret)
 971                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
 972                                         dpaa2_q->fqid, ret);
 973                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
 974                 dpaa2_q->cgid = 0xff;
 975         }
 976 }
 977
 978 static void
 979 dpaa2_dev_tx_queue_release(void *q __rte_unused)
 980 {
 981         PMD_INIT_FUNC_TRACE();
 982 }
 983
 984 static uint32_t
 985 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 986 {
 987         int32_t ret;
 988         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 989         struct dpaa2_queue *dpaa2_q;
 990         struct qbman_swp *swp;
 991         struct qbman_fq_query_np_rslt state;
 992         uint32_t frame_cnt = 0;
 993
 994         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 995                 ret = dpaa2_affine_qbman_swp();
 996                 if (ret) {
 997                         DPAA2_PMD_ERR(
 998                                 "Failed to allocate IO portal, tid: %d\n",
 999                                 rte_gettid());
1000                         return -EINVAL;
1001                 }
1002         }
1003         swp = DPAA2_PER_LCORE_PORTAL;
1004
1005         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
1006
1007         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1008                 frame_cnt = qbman_fq_state_frame_count(&state);
1009                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
1010                                 rx_queue_id, frame_cnt);
1011         }
1012         return frame_cnt;
1013 }
1014
1015 static const uint32_t *
1016 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1017 {
1018         static const uint32_t ptypes[] = {
1019                 /*todo -= add more types */
1020                 RTE_PTYPE_L2_ETHER,
1021                 RTE_PTYPE_L3_IPV4,
1022                 RTE_PTYPE_L3_IPV4_EXT,
1023                 RTE_PTYPE_L3_IPV6,
1024                 RTE_PTYPE_L3_IPV6_EXT,
1025                 RTE_PTYPE_L4_TCP,
1026                 RTE_PTYPE_L4_UDP,
1027                 RTE_PTYPE_L4_SCTP,
1028                 RTE_PTYPE_L4_ICMP,
1029                 RTE_PTYPE_UNKNOWN
1030         };
1031
1032         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1033                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1034                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1035                 return ptypes;
1036         return NULL;
1037 }
1038
1039 /**
1040  * Dpaa2 link Interrupt handler
1041  *
1042  * @param param
1043  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1044  *
1045  * @return
1046  *  void
1047  */
1048 static void
1049 dpaa2_interrupt_handler(void *param)
1050 {
1051         struct rte_eth_dev *dev = param;
1052         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1053         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1054         int ret;
1055         int irq_index = DPNI_IRQ_INDEX;
1056         unsigned int status = 0, clear = 0;
1057
1058         PMD_INIT_FUNC_TRACE();
1059
1060         if (dpni == NULL) {
1061                 DPAA2_PMD_ERR("dpni is NULL");
1062                 return;
1063         }
1064
1065         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1066                                   irq_index, &status);
1067         if (unlikely(ret)) {
1068                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1069                 clear = 0xffffffff;
1070                 goto out;
1071         }
1072
1073         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1074                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1075                 dpaa2_dev_link_update(dev, 0);
1076                 /* calling all the apps registered for link status event */
1077                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1078         }
1079 out:
1080         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1081                                     irq_index, clear);
1082         if (unlikely(ret))
1083                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1084 }
1085
1086 static int
1087 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1088 {
1089         int err = 0;
1090         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1091         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1092         int irq_index = DPNI_IRQ_INDEX;
1093         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1094
1095         PMD_INIT_FUNC_TRACE();
1096
1097         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1098                                 irq_index, mask);
1099         if (err < 0) {
1100                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1101                               strerror(-err));
1102                 return err;
1103         }
1104
1105         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1106                                   irq_index, enable);
1107         if (err < 0)
1108                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1109                               strerror(-err));
1110
1111         return err;
1112 }
1113
1114 static int
1115 dpaa2_dev_start(struct rte_eth_dev *dev)
1116 {
1117         struct rte_device *rdev = dev->device;
1118         struct rte_dpaa2_device *dpaa2_dev;
1119         struct rte_eth_dev_data *data = dev->data;
1120         struct dpaa2_dev_priv *priv = data->dev_private;
1121         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1122         struct dpni_queue cfg;
1123         struct dpni_error_cfg   err_cfg;
1124         uint16_t qdid;
1125         struct dpni_queue_id qid;
1126         struct dpaa2_queue *dpaa2_q;
1127         int ret, i;
1128         struct rte_intr_handle *intr_handle;
1129
1130         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1131         intr_handle = &dpaa2_dev->intr_handle;
1132
1133         PMD_INIT_FUNC_TRACE();
1134
1135         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1136         if (ret) {
1137                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1138                               priv->hw_id, ret);
1139                 return ret;
1140         }
1141
1142         /* Power up the phy. Needed to make the link go UP */
1143         dpaa2_dev_set_link_up(dev);
1144
1145         ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1146                             DPNI_QUEUE_TX, &qdid);
1147         if (ret) {
1148                 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1149                 return ret;
1150         }
1151         priv->qdid = qdid;
1152
1153         for (i = 0; i < data->nb_rx_queues; i++) {
1154                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1155                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1156                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1157                                        dpaa2_q->flow_id, &cfg, &qid);
1158                 if (ret) {
1159                         DPAA2_PMD_ERR("Error in getting flow information: "
1160                                       "err=%d", ret);
1161                         return ret;
1162                 }
1163                 dpaa2_q->fqid = qid.fqid;
1164         }
1165
1166         /*checksum errors, send them to normal path and set it in annotation */
1167         err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1168         err_cfg.errors |= DPNI_ERROR_PHE;
1169
1170         err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1171         err_cfg.set_frame_annotation = true;
1172
1173         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1174                                        priv->token, &err_cfg);
1175         if (ret) {
1176                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1177                               ret);
1178                 return ret;
1179         }
1180
1181         /* if the interrupts were configured on this devices*/
1182         if (intr_handle && (intr_handle->fd) &&
1183             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1184                 /* Registering LSC interrupt handler */
1185                 rte_intr_callback_register(intr_handle,
1186                                            dpaa2_interrupt_handler,
1187                                            (void *)dev);
1188
1189                 /* enable vfio intr/eventfd mapping
1190                  * Interrupt index 0 is required, so we can not use
1191                  * rte_intr_enable.
1192                  */
1193                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1194
1195                 /* enable dpni_irqs */
1196                 dpaa2_eth_setup_irqs(dev, 1);
1197         }
1198
1199         /* Change the tx burst function if ordered queues are used */
1200         if (priv->en_ordered)
1201                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1202
1203         return 0;
1204 }
1205
1206 /**
1207  *  This routine disables all traffic on the adapter by issuing a
1208  *  global reset on the MAC.
1209  */
1210 static int
1211 dpaa2_dev_stop(struct rte_eth_dev *dev)
1212 {
1213         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1214         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1215         int ret;
1216         struct rte_eth_link link;
1217         struct rte_intr_handle *intr_handle = dev->intr_handle;
1218
1219         PMD_INIT_FUNC_TRACE();
1220
1221         /* reset interrupt callback  */
1222         if (intr_handle && (intr_handle->fd) &&
1223             (dev->data->dev_conf.intr_conf.lsc != 0)) {
1224                 /*disable dpni irqs */
1225                 dpaa2_eth_setup_irqs(dev, 0);
1226
1227                 /* disable vfio intr before callback unregister */
1228                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1229
1230                 /* Unregistering LSC interrupt handler */
1231                 rte_intr_callback_unregister(intr_handle,
1232                                              dpaa2_interrupt_handler,
1233                                              (void *)dev);
1234         }
1235
1236         dpaa2_dev_set_link_down(dev);
1237
1238         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1239         if (ret) {
1240                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1241                               ret, priv->hw_id);
1242                 return ret;
1243         }
1244
1245         /* clear the recorded link status */
1246         memset(&link, 0, sizeof(link));
1247         rte_eth_linkstatus_set(dev, &link);
1248
1249         return 0;
1250 }
1251
1252 static int
1253 dpaa2_dev_close(struct rte_eth_dev *dev)
1254 {
1255         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1256         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1257         int i, ret;
1258         struct rte_eth_link link;
1259
1260         PMD_INIT_FUNC_TRACE();
1261
1262         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1263                 return 0;
1264
1265         if (!dpni) {
1266                 DPAA2_PMD_WARN("Already closed or not started");
1267                 return -1;
1268         }
1269
1270         dpaa2_tm_deinit(dev);
1271         dpaa2_flow_clean(dev);
1272         /* Clean the device first */
1273         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1274         if (ret) {
1275                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1276                 return -1;
1277         }
1278
1279         memset(&link, 0, sizeof(link));
1280         rte_eth_linkstatus_set(dev, &link);
1281
1282         /* Free private queues memory */
1283         dpaa2_free_rx_tx_queues(dev);
1284         /* Close the device at underlying layer*/
1285         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1286         if (ret) {
1287                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1288                               ret);
1289         }
1290
1291         /* Free the allocated memory for ethernet private data and dpni*/
1292         priv->hw = NULL;
1293         dev->process_private = NULL;
1294         rte_free(dpni);
1295
1296         for (i = 0; i < MAX_TCS; i++)
1297                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1298
1299         if (priv->extract.qos_extract_param)
1300                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1301
1302         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1303         return 0;
1304 }
1305
1306 static int
1307 dpaa2_dev_promiscuous_enable(
1308                 struct rte_eth_dev *dev)
1309 {
1310         int ret;
1311         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1312         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1313
1314         PMD_INIT_FUNC_TRACE();
1315
1316         if (dpni == NULL) {
1317                 DPAA2_PMD_ERR("dpni is NULL");
1318                 return -ENODEV;
1319         }
1320
1321         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1322         if (ret < 0)
1323                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1324
1325         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1326         if (ret < 0)
1327                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1328
1329         return ret;
1330 }
1331
1332 static int
1333 dpaa2_dev_promiscuous_disable(
1334                 struct rte_eth_dev *dev)
1335 {
1336         int ret;
1337         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1338         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1339
1340         PMD_INIT_FUNC_TRACE();
1341
1342         if (dpni == NULL) {
1343                 DPAA2_PMD_ERR("dpni is NULL");
1344                 return -ENODEV;
1345         }
1346
1347         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1348         if (ret < 0)
1349                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1350
1351         if (dev->data->all_multicast == 0) {
1352                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1353                                                  priv->token, false);
1354                 if (ret < 0)
1355                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1356                                       ret);
1357         }
1358
1359         return ret;
1360 }
1361
1362 static int
1363 dpaa2_dev_allmulticast_enable(
1364                 struct rte_eth_dev *dev)
1365 {
1366         int ret;
1367         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1368         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1369
1370         PMD_INIT_FUNC_TRACE();
1371
1372         if (dpni == NULL) {
1373                 DPAA2_PMD_ERR("dpni is NULL");
1374                 return -ENODEV;
1375         }
1376
1377         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1378         if (ret < 0)
1379                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1380
1381         return ret;
1382 }
1383
1384 static int
1385 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1386 {
1387         int ret;
1388         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1389         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1390
1391         PMD_INIT_FUNC_TRACE();
1392
1393         if (dpni == NULL) {
1394                 DPAA2_PMD_ERR("dpni is NULL");
1395                 return -ENODEV;
1396         }
1397
1398         /* must remain on for all promiscuous */
1399         if (dev->data->promiscuous == 1)
1400                 return 0;
1401
1402         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1403         if (ret < 0)
1404                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1405
1406         return ret;
1407 }
1408
1409 static int
1410 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1411 {
1412         int ret;
1413         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1414         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1415         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1416                                 + VLAN_TAG_SIZE;
1417
1418         PMD_INIT_FUNC_TRACE();
1419
1420         if (dpni == NULL) {
1421                 DPAA2_PMD_ERR("dpni is NULL");
1422                 return -EINVAL;
1423         }
1424
1425         /* check that mtu is within the allowed range */
1426         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1427                 return -EINVAL;
1428
1429         if (frame_size > DPAA2_ETH_MAX_LEN)
1430                 dev->data->dev_conf.rxmode.offloads |=
1431                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
1432         else
1433                 dev->data->dev_conf.rxmode.offloads &=
1434                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1435
1436         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1437
1438         /* Set the Max Rx frame length as 'mtu' +
1439          * Maximum Ethernet header length
1440          */
1441         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1442                                         frame_size - RTE_ETHER_CRC_LEN);
1443         if (ret) {
1444                 DPAA2_PMD_ERR("Setting the max frame length failed");
1445                 return -1;
1446         }
1447         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1448         return 0;
1449 }
1450
1451 static int
1452 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1453                        struct rte_ether_addr *addr,
1454                        __rte_unused uint32_t index,
1455                        __rte_unused uint32_t pool)
1456 {
1457         int ret;
1458         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1459         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1460
1461         PMD_INIT_FUNC_TRACE();
1462
1463         if (dpni == NULL) {
1464                 DPAA2_PMD_ERR("dpni is NULL");
1465                 return -1;
1466         }
1467
1468         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1469                                 addr->addr_bytes, 0, 0, 0);
1470         if (ret)
1471                 DPAA2_PMD_ERR(
1472                         "error: Adding the MAC ADDR failed: err = %d", ret);
1473         return 0;
1474 }
1475
1476 static void
1477 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1478                           uint32_t index)
1479 {
1480         int ret;
1481         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1482         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1483         struct rte_eth_dev_data *data = dev->data;
1484         struct rte_ether_addr *macaddr;
1485
1486         PMD_INIT_FUNC_TRACE();
1487
1488         macaddr = &data->mac_addrs[index];
1489
1490         if (dpni == NULL) {
1491                 DPAA2_PMD_ERR("dpni is NULL");
1492                 return;
1493         }
1494
1495         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1496                                    priv->token, macaddr->addr_bytes);
1497         if (ret)
1498                 DPAA2_PMD_ERR(
1499                         "error: Removing the MAC ADDR failed: err = %d", ret);
1500 }
1501
1502 static int
1503 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1504                        struct rte_ether_addr *addr)
1505 {
1506         int ret;
1507         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1508         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1509
1510         PMD_INIT_FUNC_TRACE();
1511
1512         if (dpni == NULL) {
1513                 DPAA2_PMD_ERR("dpni is NULL");
1514                 return -EINVAL;
1515         }
1516
1517         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1518                                         priv->token, addr->addr_bytes);
1519
1520         if (ret)
1521                 DPAA2_PMD_ERR(
1522                         "error: Setting the MAC ADDR failed %d", ret);
1523
1524         return ret;
1525 }
1526
1527 static
1528 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1529                          struct rte_eth_stats *stats)
1530 {
1531         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1532         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1533         int32_t  retcode;
1534         uint8_t page0 = 0, page1 = 1, page2 = 2;
1535         union dpni_statistics value;
1536         int i;
1537         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1538
1539         memset(&value, 0, sizeof(union dpni_statistics));
1540
1541         PMD_INIT_FUNC_TRACE();
1542
1543         if (!dpni) {
1544                 DPAA2_PMD_ERR("dpni is NULL");
1545                 return -EINVAL;
1546         }
1547
1548         if (!stats) {
1549                 DPAA2_PMD_ERR("stats is NULL");
1550                 return -EINVAL;
1551         }
1552
1553         /*Get Counters from page_0*/
1554         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1555                                       page0, 0, &value);
1556         if (retcode)
1557                 goto err;
1558
1559         stats->ipackets = value.page_0.ingress_all_frames;
1560         stats->ibytes = value.page_0.ingress_all_bytes;
1561
1562         /*Get Counters from page_1*/
1563         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1564                                       page1, 0, &value);
1565         if (retcode)
1566                 goto err;
1567
1568         stats->opackets = value.page_1.egress_all_frames;
1569         stats->obytes = value.page_1.egress_all_bytes;
1570
1571         /*Get Counters from page_2*/
1572         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1573                                       page2, 0, &value);
1574         if (retcode)
1575                 goto err;
1576
1577         /* Ingress drop frame count due to configured rules */
1578         stats->ierrors = value.page_2.ingress_filtered_frames;
1579         /* Ingress drop frame count due to error */
1580         stats->ierrors += value.page_2.ingress_discarded_frames;
1581
1582         stats->oerrors = value.page_2.egress_discarded_frames;
1583         stats->imissed = value.page_2.ingress_nobuffer_discards;
1584
1585         /* Fill in per queue stats */
1586         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1587                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1588                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1589                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1590                 if (dpaa2_rxq)
1591                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1592                 if (dpaa2_txq)
1593                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1594
1595                 /* Byte counting is not implemented */
1596                 stats->q_ibytes[i]   = 0;
1597                 stats->q_obytes[i]   = 0;
1598         }
1599
1600         return 0;
1601
1602 err:
1603         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1604         return retcode;
1605 };
1606
1607 static int
1608 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1609                      unsigned int n)
1610 {
1611         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1612         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1613         int32_t  retcode;
1614         union dpni_statistics value[5] = {};
1615         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1616
1617         if (n < num)
1618                 return num;
1619
1620         if (xstats == NULL)
1621                 return 0;
1622
1623         /* Get Counters from page_0*/
1624         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1625                                       0, 0, &value[0]);
1626         if (retcode)
1627                 goto err;
1628
1629         /* Get Counters from page_1*/
1630         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1631                                       1, 0, &value[1]);
1632         if (retcode)
1633                 goto err;
1634
1635         /* Get Counters from page_2*/
1636         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1637                                       2, 0, &value[2]);
1638         if (retcode)
1639                 goto err;
1640
1641         for (i = 0; i < priv->max_cgs; i++) {
1642                 if (!priv->cgid_in_use[i]) {
1643                         /* Get Counters from page_4*/
1644                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1645                                                       priv->token,
1646                                                       4, 0, &value[4]);
1647                         if (retcode)
1648                                 goto err;
1649                         break;
1650                 }
1651         }
1652
1653         for (i = 0; i < num; i++) {
1654                 xstats[i].id = i;
1655                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1656                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1657         }
1658         return i;
1659 err:
1660         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1661         return retcode;
1662 }
1663
1664 static int
1665 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1666                        struct rte_eth_xstat_name *xstats_names,
1667                        unsigned int limit)
1668 {
1669         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1670
1671         if (limit < stat_cnt)
1672                 return stat_cnt;
1673
1674         if (xstats_names != NULL)
1675                 for (i = 0; i < stat_cnt; i++)
1676                         strlcpy(xstats_names[i].name,
1677                                 dpaa2_xstats_strings[i].name,
1678                                 sizeof(xstats_names[i].name));
1679
1680         return stat_cnt;
1681 }
1682
1683 static int
1684 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1685                        uint64_t *values, unsigned int n)
1686 {
1687         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1688         uint64_t values_copy[stat_cnt];
1689
1690         if (!ids) {
1691                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1692                 struct fsl_mc_io *dpni =
1693                         (struct fsl_mc_io *)dev->process_private;
1694                 int32_t  retcode;
1695                 union dpni_statistics value[5] = {};
1696
1697                 if (n < stat_cnt)
1698                         return stat_cnt;
1699
1700                 if (!values)
1701                         return 0;
1702
1703                 /* Get Counters from page_0*/
1704                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1705                                               0, 0, &value[0]);
1706                 if (retcode)
1707                         return 0;
1708
1709                 /* Get Counters from page_1*/
1710                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1711                                               1, 0, &value[1]);
1712                 if (retcode)
1713                         return 0;
1714
1715                 /* Get Counters from page_2*/
1716                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1717                                               2, 0, &value[2]);
1718                 if (retcode)
1719                         return 0;
1720
1721                 /* Get Counters from page_4*/
1722                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1723                                               4, 0, &value[4]);
1724                 if (retcode)
1725                         return 0;
1726
1727                 for (i = 0; i < stat_cnt; i++) {
1728                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1729                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1730                 }
1731                 return stat_cnt;
1732         }
1733
1734         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1735
1736         for (i = 0; i < n; i++) {
1737                 if (ids[i] >= stat_cnt) {
1738                         DPAA2_PMD_ERR("xstats id value isn't valid");
1739                         return -1;
1740                 }
1741                 values[i] = values_copy[ids[i]];
1742         }
1743         return n;
1744 }
1745
1746 static int
1747 dpaa2_xstats_get_names_by_id(
1748         struct rte_eth_dev *dev,
1749         struct rte_eth_xstat_name *xstats_names,
1750         const uint64_t *ids,
1751         unsigned int limit)
1752 {
1753         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1754         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1755
1756         if (!ids)
1757                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1758
1759         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1760
1761         for (i = 0; i < limit; i++) {
1762                 if (ids[i] >= stat_cnt) {
1763                         DPAA2_PMD_ERR("xstats id value isn't valid");
1764                         return -1;
1765                 }
1766                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1767         }
1768         return limit;
1769 }
1770
1771 static int
1772 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1773 {
1774         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1775         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1776         int retcode;
1777         int i;
1778         struct dpaa2_queue *dpaa2_q;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         if (dpni == NULL) {
1783                 DPAA2_PMD_ERR("dpni is NULL");
1784                 return -EINVAL;
1785         }
1786
1787         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1788         if (retcode)
1789                 goto error;
1790
1791         /* Reset the per queue stats in dpaa2_queue structure */
1792         for (i = 0; i < priv->nb_rx_queues; i++) {
1793                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1794                 if (dpaa2_q)
1795                         dpaa2_q->rx_pkts = 0;
1796         }
1797
1798         for (i = 0; i < priv->nb_tx_queues; i++) {
1799                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1800                 if (dpaa2_q)
1801                         dpaa2_q->tx_pkts = 0;
1802         }
1803
1804         return 0;
1805
1806 error:
1807         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1808         return retcode;
1809 };
1810
1811 /* return 0 means link status changed, -1 means not changed */
1812 static int
1813 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1814                       int wait_to_complete)
1815 {
1816         int ret;
1817         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1818         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1819         struct rte_eth_link link;
1820         struct dpni_link_state state = {0};
1821         uint8_t count;
1822
1823         if (dpni == NULL) {
1824                 DPAA2_PMD_ERR("dpni is NULL");
1825                 return 0;
1826         }
1827
1828         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1829                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1830                                           &state);
1831                 if (ret < 0) {
1832                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1833                         return -1;
1834                 }
1835                 if (state.up == ETH_LINK_DOWN &&
1836                     wait_to_complete)
1837                         rte_delay_ms(CHECK_INTERVAL);
1838                 else
1839                         break;
1840         }
1841
1842         memset(&link, 0, sizeof(struct rte_eth_link));
1843         link.link_status = state.up;
1844         link.link_speed = state.rate;
1845
1846         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1847                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1848         else
1849                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1850
1851         ret = rte_eth_linkstatus_set(dev, &link);
1852         if (ret == -1)
1853                 DPAA2_PMD_DEBUG("No change in status");
1854         else
1855                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1856                                link.link_status ? "Up" : "Down");
1857
1858         return ret;
1859 }
1860
1861 /**
1862  * Toggle the DPNI to enable, if not already enabled.
1863  * This is not strictly PHY up/down - it is more of logical toggling.
1864  */
1865 static int
1866 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1867 {
1868         int ret = -EINVAL;
1869         struct dpaa2_dev_priv *priv;
1870         struct fsl_mc_io *dpni;
1871         int en = 0;
1872         struct dpni_link_state state = {0};
1873
1874         priv = dev->data->dev_private;
1875         dpni = (struct fsl_mc_io *)dev->process_private;
1876
1877         if (dpni == NULL) {
1878                 DPAA2_PMD_ERR("dpni is NULL");
1879                 return ret;
1880         }
1881
1882         /* Check if DPNI is currently enabled */
1883         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1884         if (ret) {
1885                 /* Unable to obtain dpni status; Not continuing */
1886                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1887                 return -EINVAL;
1888         }
1889
1890         /* Enable link if not already enabled */
1891         if (!en) {
1892                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1893                 if (ret) {
1894                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1895                         return -EINVAL;
1896                 }
1897         }
1898         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1899         if (ret < 0) {
1900                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1901                 return -1;
1902         }
1903
1904         /* changing tx burst function to start enqueues */
1905         dev->tx_pkt_burst = dpaa2_dev_tx;
1906         dev->data->dev_link.link_status = state.up;
1907         dev->data->dev_link.link_speed = state.rate;
1908
1909         if (state.up)
1910                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1911         else
1912                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1913         return ret;
1914 }
1915
1916 /**
1917  * Toggle the DPNI to disable, if not already disabled.
1918  * This is not strictly PHY up/down - it is more of logical toggling.
1919  */
1920 static int
1921 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1922 {
1923         int ret = -EINVAL;
1924         struct dpaa2_dev_priv *priv;
1925         struct fsl_mc_io *dpni;
1926         int dpni_enabled = 0;
1927         int retries = 10;
1928
1929         PMD_INIT_FUNC_TRACE();
1930
1931         priv = dev->data->dev_private;
1932         dpni = (struct fsl_mc_io *)dev->process_private;
1933
1934         if (dpni == NULL) {
1935                 DPAA2_PMD_ERR("Device has not yet been configured");
1936                 return ret;
1937         }
1938
1939         /*changing  tx burst function to avoid any more enqueues */
1940         dev->tx_pkt_burst = dummy_dev_tx;
1941
1942         /* Loop while dpni_disable() attempts to drain the egress FQs
1943          * and confirm them back to us.
1944          */
1945         do {
1946                 ret = dpni_disable(dpni, 0, priv->token);
1947                 if (ret) {
1948                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1949                         return ret;
1950                 }
1951                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1952                 if (ret) {
1953                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1954                         return ret;
1955                 }
1956                 if (dpni_enabled)
1957                         /* Allow the MC some slack */
1958                         rte_delay_us(100 * 1000);
1959         } while (dpni_enabled && --retries);
1960
1961         if (!retries) {
1962                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1963                 /* todo- we may have to manually cleanup queues.
1964                  */
1965         } else {
1966                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1967                                dev->data->port_id);
1968         }
1969
1970         dev->data->dev_link.link_status = 0;
1971
1972         return ret;
1973 }
1974
1975 static int
1976 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1977 {
1978         int ret = -EINVAL;
1979         struct dpaa2_dev_priv *priv;
1980         struct fsl_mc_io *dpni;
1981         struct dpni_link_state state = {0};
1982
1983         PMD_INIT_FUNC_TRACE();
1984
1985         priv = dev->data->dev_private;
1986         dpni = (struct fsl_mc_io *)dev->process_private;
1987
1988         if (dpni == NULL || fc_conf == NULL) {
1989                 DPAA2_PMD_ERR("device not configured");
1990                 return ret;
1991         }
1992
1993         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1994         if (ret) {
1995                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1996                 return ret;
1997         }
1998
1999         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2000         if (state.options & DPNI_LINK_OPT_PAUSE) {
2001                 /* DPNI_LINK_OPT_PAUSE set
2002                  *  if ASYM_PAUSE not set,
2003                  *      RX Side flow control (handle received Pause frame)
2004                  *      TX side flow control (send Pause frame)
2005                  *  if ASYM_PAUSE set,
2006                  *      RX Side flow control (handle received Pause frame)
2007                  *      No TX side flow control (send Pause frame disabled)
2008                  */
2009                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2010                         fc_conf->mode = RTE_FC_FULL;
2011                 else
2012                         fc_conf->mode = RTE_FC_RX_PAUSE;
2013         } else {
2014                 /* DPNI_LINK_OPT_PAUSE not set
2015                  *  if ASYM_PAUSE set,
2016                  *      TX side flow control (send Pause frame)
2017                  *      No RX side flow control (No action on pause frame rx)
2018                  *  if ASYM_PAUSE not set,
2019                  *      Flow control disabled
2020                  */
2021                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2022                         fc_conf->mode = RTE_FC_TX_PAUSE;
2023                 else
2024                         fc_conf->mode = RTE_FC_NONE;
2025         }
2026
2027         return ret;
2028 }
2029
2030 static int
2031 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2032 {
2033         int ret = -EINVAL;
2034         struct dpaa2_dev_priv *priv;
2035         struct fsl_mc_io *dpni;
2036         struct dpni_link_state state = {0};
2037         struct dpni_link_cfg cfg = {0};
2038
2039         PMD_INIT_FUNC_TRACE();
2040
2041         priv = dev->data->dev_private;
2042         dpni = (struct fsl_mc_io *)dev->process_private;
2043
2044         if (dpni == NULL) {
2045                 DPAA2_PMD_ERR("dpni is NULL");
2046                 return ret;
2047         }
2048
2049         /* It is necessary to obtain the current state before setting fc_conf
2050          * as MC would return error in case rate, autoneg or duplex values are
2051          * different.
2052          */
2053         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2054         if (ret) {
2055                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2056                 return -1;
2057         }
2058
2059         /* Disable link before setting configuration */
2060         dpaa2_dev_set_link_down(dev);
2061
2062         /* Based on fc_conf, update cfg */
2063         cfg.rate = state.rate;
2064         cfg.options = state.options;
2065
2066         /* update cfg with fc_conf */
2067         switch (fc_conf->mode) {
2068         case RTE_FC_FULL:
2069                 /* Full flow control;
2070                  * OPT_PAUSE set, ASYM_PAUSE not set
2071                  */
2072                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2073                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2074                 break;
2075         case RTE_FC_TX_PAUSE:
2076                 /* Enable RX flow control
2077                  * OPT_PAUSE not set;
2078                  * ASYM_PAUSE set;
2079                  */
2080                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2081                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2082                 break;
2083         case RTE_FC_RX_PAUSE:
2084                 /* Enable TX Flow control
2085                  * OPT_PAUSE set
2086                  * ASYM_PAUSE set
2087                  */
2088                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2089                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2090                 break;
2091         case RTE_FC_NONE:
2092                 /* Disable Flow control
2093                  * OPT_PAUSE not set
2094                  * ASYM_PAUSE not set
2095                  */
2096                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2097                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2098                 break;
2099         default:
2100                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2101                               fc_conf->mode);
2102                 return -1;
2103         }
2104
2105         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2106         if (ret)
2107                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2108                               ret);
2109
2110         /* Enable link */
2111         dpaa2_dev_set_link_up(dev);
2112
2113         return ret;
2114 }
2115
2116 static int
2117 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2118                           struct rte_eth_rss_conf *rss_conf)
2119 {
2120         struct rte_eth_dev_data *data = dev->data;
2121         struct dpaa2_dev_priv *priv = data->dev_private;
2122         struct rte_eth_conf *eth_conf = &data->dev_conf;
2123         int ret, tc_index;
2124
2125         PMD_INIT_FUNC_TRACE();
2126
2127         if (rss_conf->rss_hf) {
2128                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2129                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2130                                 tc_index);
2131                         if (ret) {
2132                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2133                                         tc_index);
2134                                 return ret;
2135                         }
2136                 }
2137         } else {
2138                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2139                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2140                         if (ret) {
2141                                 DPAA2_PMD_ERR(
2142                                         "Unable to remove flow dist on tc%d",
2143                                         tc_index);
2144                                 return ret;
2145                         }
2146                 }
2147         }
2148         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2149         return 0;
2150 }
2151
2152 static int
2153 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2154                             struct rte_eth_rss_conf *rss_conf)
2155 {
2156         struct rte_eth_dev_data *data = dev->data;
2157         struct rte_eth_conf *eth_conf = &data->dev_conf;
2158
2159         /* dpaa2 does not support rss_key, so length should be 0*/
2160         rss_conf->rss_key_len = 0;
2161         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2162         return 0;
2163 }
2164
2165 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2166                 int eth_rx_queue_id,
2167                 struct dpaa2_dpcon_dev *dpcon,
2168                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2169 {
2170         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2171         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2172         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2173         uint8_t flow_id = dpaa2_ethq->flow_id;
2174         struct dpni_queue cfg;
2175         uint8_t options, priority;
2176         int ret;
2177
2178         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2179                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2180         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2181                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2182         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2183                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2184         else
2185                 return -EINVAL;
2186
2187         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2188                    (dpcon->num_priorities - 1);
2189
2190         memset(&cfg, 0, sizeof(struct dpni_queue));
2191         options = DPNI_QUEUE_OPT_DEST;
2192         cfg.destination.type = DPNI_DEST_DPCON;
2193         cfg.destination.id = dpcon->dpcon_id;
2194         cfg.destination.priority = priority;
2195
2196         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2197                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2198                 cfg.destination.hold_active = 1;
2199         }
2200
2201         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2202                         !eth_priv->en_ordered) {
2203                 struct opr_cfg ocfg;
2204
2205                 /* Restoration window size = 256 frames */
2206                 ocfg.oprrws = 3;
2207                 /* Restoration window size = 512 frames for LX2 */
2208                 if (dpaa2_svr_family == SVR_LX2160A)
2209                         ocfg.oprrws = 4;
2210                 /* Auto advance NESN window enabled */
2211                 ocfg.oa = 1;
2212                 /* Late arrival window size disabled */
2213                 ocfg.olws = 0;
2214                 /* ORL resource exhaustaion advance NESN disabled */
2215                 ocfg.oeane = 0;
2216                 /* Loose ordering enabled */
2217                 ocfg.oloe = 1;
2218                 eth_priv->en_loose_ordered = 1;
2219                 /* Strict ordering enabled if explicitly set */
2220                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2221                         ocfg.oloe = 0;
2222                         eth_priv->en_loose_ordered = 0;
2223                 }
2224
2225                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2226                                    dpaa2_ethq->tc_index, flow_id,
2227                                    OPR_OPT_CREATE, &ocfg);
2228                 if (ret) {
2229                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2230                         return ret;
2231                 }
2232
2233                 eth_priv->en_ordered = 1;
2234         }
2235
2236         options |= DPNI_QUEUE_OPT_USER_CTX;
2237         cfg.user_context = (size_t)(dpaa2_ethq);
2238
2239         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2240                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2241         if (ret) {
2242                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2243                 return ret;
2244         }
2245
2246         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2247
2248         return 0;
2249 }
2250
2251 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2252                 int eth_rx_queue_id)
2253 {
2254         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2255         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2256         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2257         uint8_t flow_id = dpaa2_ethq->flow_id;
2258         struct dpni_queue cfg;
2259         uint8_t options;
2260         int ret;
2261
2262         memset(&cfg, 0, sizeof(struct dpni_queue));
2263         options = DPNI_QUEUE_OPT_DEST;
2264         cfg.destination.type = DPNI_DEST_NONE;
2265
2266         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2267                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2268         if (ret)
2269                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2270
2271         return ret;
2272 }
2273
2274 static inline int
2275 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2276 {
2277         unsigned int i;
2278
2279         for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2280                 if (dpaa2_supported_filter_ops[i] == filter_op)
2281                         return 0;
2282         }
2283         return -ENOTSUP;
2284 }
2285
2286 static int
2287 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2288                     enum rte_filter_type filter_type,
2289                                  enum rte_filter_op filter_op,
2290                                  void *arg)
2291 {
2292         int ret = 0;
2293
2294         if (!dev)
2295                 return -ENODEV;
2296
2297         switch (filter_type) {
2298         case RTE_ETH_FILTER_GENERIC:
2299                 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2300                         ret = -ENOTSUP;
2301                         break;
2302                 }
2303                 *(const void **)arg = &dpaa2_flow_ops;
2304                 dpaa2_filter_type |= filter_type;
2305                 break;
2306         default:
2307                 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2308                         filter_type);
2309                 ret = -ENOTSUP;
2310                 break;
2311         }
2312         return ret;
2313 }
2314
2315 static void
2316 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2317         struct rte_eth_rxq_info *qinfo)
2318 {
2319         struct dpaa2_queue *rxq;
2320
2321         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2322
2323         qinfo->mp = rxq->mb_pool;
2324         qinfo->scattered_rx = dev->data->scattered_rx;
2325         qinfo->nb_desc = rxq->nb_desc;
2326
2327         qinfo->conf.rx_free_thresh = 1;
2328         qinfo->conf.rx_drop_en = 1;
2329         qinfo->conf.rx_deferred_start = 0;
2330         qinfo->conf.offloads = rxq->offloads;
2331 }
2332
2333 static void
2334 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2335         struct rte_eth_txq_info *qinfo)
2336 {
2337         struct dpaa2_queue *txq;
2338
2339         txq = dev->data->tx_queues[queue_id];
2340
2341         qinfo->nb_desc = txq->nb_desc;
2342         qinfo->conf.tx_thresh.pthresh = 0;
2343         qinfo->conf.tx_thresh.hthresh = 0;
2344         qinfo->conf.tx_thresh.wthresh = 0;
2345
2346         qinfo->conf.tx_free_thresh = 0;
2347         qinfo->conf.tx_rs_thresh = 0;
2348         qinfo->conf.offloads = txq->offloads;
2349         qinfo->conf.tx_deferred_start = 0;
2350 }
2351
2352 static int
2353 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2354 {
2355         *(const void **)ops = &dpaa2_tm_ops;
2356
2357         return 0;
2358 }
2359
2360 static struct eth_dev_ops dpaa2_ethdev_ops = {
2361         .dev_configure    = dpaa2_eth_dev_configure,
2362         .dev_start            = dpaa2_dev_start,
2363         .dev_stop             = dpaa2_dev_stop,
2364         .dev_close            = dpaa2_dev_close,
2365         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2366         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2367         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2368         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2369         .dev_set_link_up      = dpaa2_dev_set_link_up,
2370         .dev_set_link_down    = dpaa2_dev_set_link_down,
2371         .link_update       = dpaa2_dev_link_update,
2372         .stats_get             = dpaa2_dev_stats_get,
2373         .xstats_get            = dpaa2_dev_xstats_get,
2374         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2375         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2376         .xstats_get_names      = dpaa2_xstats_get_names,
2377         .stats_reset       = dpaa2_dev_stats_reset,
2378         .xstats_reset         = dpaa2_dev_stats_reset,
2379         .fw_version_get    = dpaa2_fw_version_get,
2380         .dev_infos_get     = dpaa2_dev_info_get,
2381         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2382         .mtu_set           = dpaa2_dev_mtu_set,
2383         .vlan_filter_set      = dpaa2_vlan_filter_set,
2384         .vlan_offload_set     = dpaa2_vlan_offload_set,
2385         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2386         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2387         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2388         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2389         .tx_queue_release  = dpaa2_dev_tx_queue_release,
2390         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2391         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2392         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2393         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2394         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2395         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2396         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2397         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2398         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2399         .filter_ctrl          = dpaa2_dev_flow_ctrl,
2400         .rxq_info_get         = dpaa2_rxq_info_get,
2401         .txq_info_get         = dpaa2_txq_info_get,
2402         .tm_ops_get           = dpaa2_tm_ops_get,
2403 #if defined(RTE_LIBRTE_IEEE1588)
2404         .timesync_enable      = dpaa2_timesync_enable,
2405         .timesync_disable     = dpaa2_timesync_disable,
2406         .timesync_read_time   = dpaa2_timesync_read_time,
2407         .timesync_write_time  = dpaa2_timesync_write_time,
2408         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2409         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2410         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2411 #endif
2412 };
2413
2414 /* Populate the mac address from physically available (u-boot/firmware) and/or
2415  * one set by higher layers like MC (restool) etc.
2416  * Returns the table of MAC entries (multiple entries)
2417  */
2418 static int
2419 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2420                   struct rte_ether_addr *mac_entry)
2421 {
2422         int ret;
2423         struct rte_ether_addr phy_mac, prime_mac;
2424
2425         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2426         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2427
2428         /* Get the physical device MAC address */
2429         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2430                                      phy_mac.addr_bytes);
2431         if (ret) {
2432                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2433                 goto cleanup;
2434         }
2435
2436         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2437                                         prime_mac.addr_bytes);
2438         if (ret) {
2439                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2440                 goto cleanup;
2441         }
2442
2443         /* Now that both MAC have been obtained, do:
2444          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2445          *     and return phy
2446          *  If empty_mac(phy), return prime.
2447          *  if both are empty, create random MAC, set as prime and return
2448          */
2449         if (!rte_is_zero_ether_addr(&phy_mac)) {
2450                 /* If the addresses are not same, overwrite prime */
2451                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2452                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2453                                                         priv->token,
2454                                                         phy_mac.addr_bytes);
2455                         if (ret) {
2456                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2457                                               ret);
2458                                 goto cleanup;
2459                         }
2460                         memcpy(&prime_mac, &phy_mac,
2461                                 sizeof(struct rte_ether_addr));
2462                 }
2463         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2464                 /* In case phys and prime, both are zero, create random MAC */
2465                 rte_eth_random_addr(prime_mac.addr_bytes);
2466                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2467                                                 priv->token,
2468                                                 prime_mac.addr_bytes);
2469                 if (ret) {
2470                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2471                         goto cleanup;
2472                 }
2473         }
2474
2475         /* prime_mac the final MAC address */
2476         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2477         return 0;
2478
2479 cleanup:
2480         return -1;
2481 }
2482
2483 static int
2484 check_devargs_handler(__rte_unused const char *key, const char *value,
2485                       __rte_unused void *opaque)
2486 {
2487         if (strcmp(value, "1"))
2488                 return -1;
2489
2490         return 0;
2491 }
2492
2493 static int
2494 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2495 {
2496         struct rte_kvargs *kvlist;
2497
2498         if (!devargs)
2499                 return 0;
2500
2501         kvlist = rte_kvargs_parse(devargs->args, NULL);
2502         if (!kvlist)
2503                 return 0;
2504
2505         if (!rte_kvargs_count(kvlist, key)) {
2506                 rte_kvargs_free(kvlist);
2507                 return 0;
2508         }
2509
2510         if (rte_kvargs_process(kvlist, key,
2511                                check_devargs_handler, NULL) < 0) {
2512                 rte_kvargs_free(kvlist);
2513                 return 0;
2514         }
2515         rte_kvargs_free(kvlist);
2516
2517         return 1;
2518 }
2519
2520 static int
2521 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2522 {
2523         struct rte_device *dev = eth_dev->device;
2524         struct rte_dpaa2_device *dpaa2_dev;
2525         struct fsl_mc_io *dpni_dev;
2526         struct dpni_attr attr;
2527         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2528         struct dpni_buffer_layout layout;
2529         int ret, hw_id, i;
2530
2531         PMD_INIT_FUNC_TRACE();
2532
2533         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2534         if (!dpni_dev) {
2535                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2536                 return -1;
2537         }
2538         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2539         eth_dev->process_private = (void *)dpni_dev;
2540
2541         /* For secondary processes, the primary has done all the work */
2542         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2543                 /* In case of secondary, only burst and ops API need to be
2544                  * plugged.
2545                  */
2546                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2547                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2548                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2549                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2550                 else if (dpaa2_get_devargs(dev->devargs,
2551                                         DRIVER_NO_PREFETCH_MODE))
2552                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2553                 else
2554                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2555                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2556                 return 0;
2557         }
2558
2559         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2560
2561         hw_id = dpaa2_dev->object_id;
2562         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2563         if (ret) {
2564                 DPAA2_PMD_ERR(
2565                              "Failure in opening dpni@%d with err code %d",
2566                              hw_id, ret);
2567                 rte_free(dpni_dev);
2568                 return -1;
2569         }
2570
2571         /* Clean the device first */
2572         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2573         if (ret) {
2574                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2575                               hw_id, ret);
2576                 goto init_err;
2577         }
2578
2579         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2580         if (ret) {
2581                 DPAA2_PMD_ERR(
2582                              "Failure in get dpni@%d attribute, err code %d",
2583                              hw_id, ret);
2584                 goto init_err;
2585         }
2586
2587         priv->num_rx_tc = attr.num_rx_tcs;
2588         priv->qos_entries = attr.qos_entries;
2589         priv->fs_entries = attr.fs_entries;
2590         priv->dist_queues = attr.num_queues;
2591
2592         /* only if the custom CG is enabled */
2593         if (attr.options & DPNI_OPT_CUSTOM_CG)
2594                 priv->max_cgs = attr.num_cgs;
2595         else
2596                 priv->max_cgs = 0;
2597
2598         for (i = 0; i < priv->max_cgs; i++)
2599                 priv->cgid_in_use[i] = 0;
2600
2601         for (i = 0; i < attr.num_rx_tcs; i++)
2602                 priv->nb_rx_queues += attr.num_queues;
2603
2604         /* Using number of TX queues as number of TX TCs */
2605         priv->nb_tx_queues = attr.num_tx_tcs;
2606
2607         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2608                         priv->num_rx_tc, priv->nb_rx_queues,
2609                         priv->nb_tx_queues, priv->max_cgs);
2610
2611         priv->hw = dpni_dev;
2612         priv->hw_id = hw_id;
2613         priv->options = attr.options;
2614         priv->max_mac_filters = attr.mac_filter_entries;
2615         priv->max_vlan_filters = attr.vlan_filter_entries;
2616         priv->flags = 0;
2617 #if defined(RTE_LIBRTE_IEEE1588)
2618         printf("DPDK IEEE1588 is enabled\n");
2619         priv->flags |= DPAA2_TX_CONF_ENABLE;
2620 #endif
2621         /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2622         if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2623                 priv->flags |= DPAA2_TX_CONF_ENABLE;
2624                 DPAA2_PMD_INFO("TX_CONF Enabled");
2625         }
2626
2627         /* Allocate memory for hardware structure for queues */
2628         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2629         if (ret) {
2630                 DPAA2_PMD_ERR("Queue allocation Failed");
2631                 goto init_err;
2632         }
2633
2634         /* Allocate memory for storing MAC addresses.
2635          * Table of mac_filter_entries size is allocated so that RTE ether lib
2636          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2637          */
2638         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2639                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2640         if (eth_dev->data->mac_addrs == NULL) {
2641                 DPAA2_PMD_ERR(
2642                    "Failed to allocate %d bytes needed to store MAC addresses",
2643                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2644                 ret = -ENOMEM;
2645                 goto init_err;
2646         }
2647
2648         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2649         if (ret) {
2650                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2651                 rte_free(eth_dev->data->mac_addrs);
2652                 eth_dev->data->mac_addrs = NULL;
2653                 goto init_err;
2654         }
2655
2656         /* ... tx buffer layout ... */
2657         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2658         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2659                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2660                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2661                 layout.pass_timestamp = true;
2662         } else {
2663                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2664         }
2665         layout.pass_frame_status = 1;
2666         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2667                                      DPNI_QUEUE_TX, &layout);
2668         if (ret) {
2669                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2670                 goto init_err;
2671         }
2672
2673         /* ... tx-conf and error buffer layout ... */
2674         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2675         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2676                 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2677                 layout.pass_timestamp = true;
2678         }
2679         layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2680         layout.pass_frame_status = 1;
2681         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2682                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2683         if (ret) {
2684                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2685                              ret);
2686                 goto init_err;
2687         }
2688
2689         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2690
2691         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2692                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2693                 DPAA2_PMD_INFO("Loopback mode");
2694         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2695                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2696                 DPAA2_PMD_INFO("No Prefetch mode");
2697         } else {
2698                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2699         }
2700         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2701
2702         /*Init fields w.r.t. classficaition*/
2703         memset(&priv->extract.qos_key_extract, 0,
2704                 sizeof(struct dpaa2_key_extract));
2705         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2706         if (!priv->extract.qos_extract_param) {
2707                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2708                             " classificaiton ", ret);
2709                 goto init_err;
2710         }
2711         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2712                 IP_ADDRESS_OFFSET_INVALID;
2713         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2714                 IP_ADDRESS_OFFSET_INVALID;
2715         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2716                 IP_ADDRESS_OFFSET_INVALID;
2717         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2718                 IP_ADDRESS_OFFSET_INVALID;
2719
2720         for (i = 0; i < MAX_TCS; i++) {
2721                 memset(&priv->extract.tc_key_extract[i], 0,
2722                         sizeof(struct dpaa2_key_extract));
2723                 priv->extract.tc_extract_param[i] =
2724                         (size_t)rte_malloc(NULL, 256, 64);
2725                 if (!priv->extract.tc_extract_param[i]) {
2726                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2727                                      ret);
2728                         goto init_err;
2729                 }
2730                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2731                         IP_ADDRESS_OFFSET_INVALID;
2732                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2733                         IP_ADDRESS_OFFSET_INVALID;
2734                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2735                         IP_ADDRESS_OFFSET_INVALID;
2736                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2737                         IP_ADDRESS_OFFSET_INVALID;
2738         }
2739
2740         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2741                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2742                                         + VLAN_TAG_SIZE);
2743         if (ret) {
2744                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2745                 goto init_err;
2746         }
2747
2748         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2749          * with external entity to receive byte code for software sequence
2750          * and same will be offload to the H/W using MC interface.
2751          * Currently it is assumed that DPAA2 driver has byte code by some
2752          * mean and same if offloaded to H/W.
2753          */
2754         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2755                 WRIOP_SS_INITIALIZER(priv);
2756                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2757                 if (ret < 0) {
2758                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2759                                       ret);
2760                         return ret;
2761                 }
2762
2763                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2764                                                          DPNI_SS_INGRESS);
2765                 if (ret < 0) {
2766                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2767                                       ret);
2768                         return ret;
2769                 }
2770         }
2771         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2772         return 0;
2773 init_err:
2774         dpaa2_dev_close(eth_dev);
2775
2776         return ret;
2777 }
2778
2779 static int
2780 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2781                 struct rte_dpaa2_device *dpaa2_dev)
2782 {
2783         struct rte_eth_dev *eth_dev;
2784         struct dpaa2_dev_priv *dev_priv;
2785         int diag;
2786
2787         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2788                 RTE_PKTMBUF_HEADROOM) {
2789                 DPAA2_PMD_ERR(
2790                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2791                 RTE_PKTMBUF_HEADROOM,
2792                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2793
2794                 return -1;
2795         }
2796
2797         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2798                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2799                 if (!eth_dev)
2800                         return -ENODEV;
2801                 dev_priv = rte_zmalloc("ethdev private structure",
2802                                        sizeof(struct dpaa2_dev_priv),
2803                                        RTE_CACHE_LINE_SIZE);
2804                 if (dev_priv == NULL) {
2805                         DPAA2_PMD_CRIT(
2806                                 "Unable to allocate memory for private data");
2807                         rte_eth_dev_release_port(eth_dev);
2808                         return -ENOMEM;
2809                 }
2810                 eth_dev->data->dev_private = (void *)dev_priv;
2811                 /* Store a pointer to eth_dev in dev_private */
2812                 dev_priv->eth_dev = eth_dev;
2813         } else {
2814                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2815                 if (!eth_dev) {
2816                         DPAA2_PMD_DEBUG("returning enodev");
2817                         return -ENODEV;
2818                 }
2819         }
2820
2821         eth_dev->device = &dpaa2_dev->device;
2822
2823         dpaa2_dev->eth_dev = eth_dev;
2824         eth_dev->data->rx_mbuf_alloc_failed = 0;
2825
2826         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2827                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2828
2829         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2830
2831         /* Invoke PMD device initialization function */
2832         diag = dpaa2_dev_init(eth_dev);
2833         if (diag == 0) {
2834                 rte_eth_dev_probing_finish(eth_dev);
2835                 return 0;
2836         }
2837
2838         rte_eth_dev_release_port(eth_dev);
2839         return diag;
2840 }
2841
2842 static int
2843 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2844 {
2845         struct rte_eth_dev *eth_dev;
2846         int ret;
2847
2848         eth_dev = dpaa2_dev->eth_dev;
2849         dpaa2_dev_close(eth_dev);
2850         ret = rte_eth_dev_release_port(eth_dev);
2851
2852         return ret;
2853 }
2854
2855 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2856         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2857         .drv_type = DPAA2_ETH,
2858         .probe = rte_dpaa2_probe,
2859         .remove = rte_dpaa2_remove,
2860 };
2861
2862 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2863 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2864                 DRIVER_LOOPBACK_MODE "=<int> "
2865                 DRIVER_NO_PREFETCH_MODE "=<int>"
2866                 DRIVER_TX_CONF "=<int>");
2867 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);