drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21 #include "rte_dpaa2_mempool.h"
  22
  23 #include "dpaa2_pmd_logs.h"
  24 #include <fslmc_vfio.h>
  25 #include <dpaa2_hw_pvt.h>
  26 #include <dpaa2_hw_mempool.h>
  27 #include <dpaa2_hw_dpio.h>
  28 #include <mc/fsl_dpmng.h>
  29 #include "dpaa2_ethdev.h"
  30 #include "dpaa2_sparser.h"
  31 #include <fsl_qbman_debug.h>
  32
  33 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  34 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  35 #define DRIVER_TX_CONF "drv_tx_conf"
  36 #define DRIVER_ERROR_QUEUE  "drv_err_queue"
  37 #define CHECK_INTERVAL         100  /* 100ms */
  38 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  39
  40 /* Supported Rx offloads */
  41 static uint64_t dev_rx_offloads_sup =
  42                 RTE_ETH_RX_OFFLOAD_CHECKSUM |
  43                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
  44                 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  45                 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
  46                 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
  47                 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
  48                 RTE_ETH_RX_OFFLOAD_TIMESTAMP;
  49
  50 /* Rx offloads which cannot be disabled */
  51 static uint64_t dev_rx_offloads_nodis =
  52                 RTE_ETH_RX_OFFLOAD_RSS_HASH |
  53                 RTE_ETH_RX_OFFLOAD_SCATTER;
  54
  55 /* Supported Tx offloads */
  56 static uint64_t dev_tx_offloads_sup =
  57                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
  58                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
  59                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
  60                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
  61                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
  62                 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  63                 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
  64                 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
  65
  66 /* Tx offloads which cannot be disabled */
  67 static uint64_t dev_tx_offloads_nodis =
  68                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
  69
  70 /* enable timestamp in mbuf */
  71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  72 uint64_t dpaa2_timestamp_rx_dynflag;
  73 int dpaa2_timestamp_dynfield_offset = -1;
  74
  75 /* Enable error queue */
  76 bool dpaa2_enable_err_queue;
  77
  78 #define MAX_NB_RX_DESC          11264
  79 int total_nb_rx_desc;
  80
  81 struct rte_dpaa2_xstats_name_off {
  82         char name[RTE_ETH_XSTATS_NAME_SIZE];
  83         uint8_t page_id; /* dpni statistics page id */
  84         uint8_t stats_id; /* stats id in the given page */
  85 };
  86
  87 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  88         {"ingress_multicast_frames", 0, 2},
  89         {"ingress_multicast_bytes", 0, 3},
  90         {"ingress_broadcast_frames", 0, 4},
  91         {"ingress_broadcast_bytes", 0, 5},
  92         {"egress_multicast_frames", 1, 2},
  93         {"egress_multicast_bytes", 1, 3},
  94         {"egress_broadcast_frames", 1, 4},
  95         {"egress_broadcast_bytes", 1, 5},
  96         {"ingress_filtered_frames", 2, 0},
  97         {"ingress_discarded_frames", 2, 1},
  98         {"ingress_nobuffer_discards", 2, 2},
  99         {"egress_discarded_frames", 2, 3},
 100         {"egress_confirmed_frames", 2, 4},
 101         {"cgr_reject_frames", 4, 0},
 102         {"cgr_reject_bytes", 4, 1},
 103 };
 104
 105 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 106 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 107                                  int wait_to_complete);
 108 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 109 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 110 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 111
 112 static int
 113 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 114 {
 115         int ret;
 116         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 117         struct fsl_mc_io *dpni = dev->process_private;
 118
 119         PMD_INIT_FUNC_TRACE();
 120
 121         if (dpni == NULL) {
 122                 DPAA2_PMD_ERR("dpni is NULL");
 123                 return -1;
 124         }
 125
 126         if (on)
 127                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 128                                        vlan_id, 0, 0, 0);
 129         else
 130                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 131                                           priv->token, vlan_id);
 132
 133         if (ret < 0)
 134                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 135                               ret, vlan_id, priv->hw_id);
 136
 137         return ret;
 138 }
 139
 140 static int
 141 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 142 {
 143         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 144         struct fsl_mc_io *dpni = dev->process_private;
 145         int ret = 0;
 146
 147         PMD_INIT_FUNC_TRACE();
 148
 149         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
 150                 /* VLAN Filter not available */
 151                 if (!priv->max_vlan_filters) {
 152                         DPAA2_PMD_INFO("VLAN filter not available");
 153                         return -ENOTSUP;
 154                 }
 155
 156                 if (dev->data->dev_conf.rxmode.offloads &
 157                         RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 158                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 159                                                       priv->token, true);
 160                 else
 161                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 162                                                       priv->token, false);
 163                 if (ret < 0)
 164                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 165         }
 166
 167         return ret;
 168 }
 169
 170 static int
 171 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 172                       enum rte_vlan_type vlan_type __rte_unused,
 173                       uint16_t tpid)
 174 {
 175         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 176         struct fsl_mc_io *dpni = dev->process_private;
 177         int ret = -ENOTSUP;
 178
 179         PMD_INIT_FUNC_TRACE();
 180
 181         /* nothing to be done for standard vlan tpids */
 182         if (tpid == 0x8100 || tpid == 0x88A8)
 183                 return 0;
 184
 185         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 186                                    priv->token, tpid);
 187         if (ret < 0)
 188                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 189         /* if already configured tpids, remove them first */
 190         if (ret == -EBUSY) {
 191                 struct dpni_custom_tpid_cfg tpid_list = {0};
 192
 193                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 194                                    priv->token, &tpid_list);
 195                 if (ret < 0)
 196                         goto fail;
 197                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 198                                    priv->token, tpid_list.tpid1);
 199                 if (ret < 0)
 200                         goto fail;
 201                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 202                                            priv->token, tpid);
 203         }
 204 fail:
 205         return ret;
 206 }
 207
 208 static int
 209 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 210                      char *fw_version,
 211                      size_t fw_size)
 212 {
 213         int ret;
 214         struct fsl_mc_io *dpni = dev->process_private;
 215         struct mc_soc_version mc_plat_info = {0};
 216         struct mc_version mc_ver_info = {0};
 217
 218         PMD_INIT_FUNC_TRACE();
 219
 220         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 221                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 222
 223         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 224                 DPAA2_PMD_WARN("\tmc_get_version failed");
 225
 226         ret = snprintf(fw_version, fw_size,
 227                        "%x-%d.%d.%d",
 228                        mc_plat_info.svr,
 229                        mc_ver_info.major,
 230                        mc_ver_info.minor,
 231                        mc_ver_info.revision);
 232         if (ret < 0)
 233                 return -EINVAL;
 234
 235         ret += 1; /* add the size of '\0' */
 236         if (fw_size < (size_t)ret)
 237                 return ret;
 238         else
 239                 return 0;
 240 }
 241
 242 static int
 243 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 244 {
 245         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 246
 247         PMD_INIT_FUNC_TRACE();
 248
 249         dev_info->max_mac_addrs = priv->max_mac_filters;
 250         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 251         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 252         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 253         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 254         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 255                                         dev_rx_offloads_nodis;
 256         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 257                                         dev_tx_offloads_nodis;
 258         dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
 259                         RTE_ETH_LINK_SPEED_2_5G |
 260                         RTE_ETH_LINK_SPEED_10G;
 261         dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 262
 263         dev_info->max_hash_mac_addrs = 0;
 264         dev_info->max_vfs = 0;
 265         dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
 266         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 267
 268         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 269         /* same is rx size for best perf */
 270         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 271
 272         dev_info->default_rxportconf.nb_queues = 1;
 273         dev_info->default_txportconf.nb_queues = 1;
 274         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 275         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 276
 277         if (dpaa2_svr_family == SVR_LX2160A) {
 278                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G |
 279                                 RTE_ETH_LINK_SPEED_40G |
 280                                 RTE_ETH_LINK_SPEED_50G |
 281                                 RTE_ETH_LINK_SPEED_100G;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static int
 288 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 289                         __rte_unused uint16_t queue_id,
 290                         struct rte_eth_burst_mode *mode)
 291 {
 292         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 293         int ret = -EINVAL;
 294         unsigned int i;
 295         const struct burst_info {
 296                 uint64_t flags;
 297                 const char *output;
 298         } rx_offload_map[] = {
 299                         {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 300                         {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 301                         {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 302                         {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 303                         {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 304                         {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 305                         {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 306                         {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"},
 307                         {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}
 308         };
 309
 310         /* Update Rx offload info */
 311         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 312                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 313                         snprintf(mode->info, sizeof(mode->info), "%s",
 314                                 rx_offload_map[i].output);
 315                         ret = 0;
 316                         break;
 317                 }
 318         }
 319         return ret;
 320 }
 321
 322 static int
 323 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 324                         __rte_unused uint16_t queue_id,
 325                         struct rte_eth_burst_mode *mode)
 326 {
 327         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 328         int ret = -EINVAL;
 329         unsigned int i;
 330         const struct burst_info {
 331                 uint64_t flags;
 332                 const char *output;
 333         } tx_offload_map[] = {
 334                         {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 335                         {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 336                         {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 337                         {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 338                         {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 339                         {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 340                         {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 341                         {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 342                         {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 343         };
 344
 345         /* Update Tx offload info */
 346         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 347                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 348                         snprintf(mode->info, sizeof(mode->info), "%s",
 349                                 tx_offload_map[i].output);
 350                         ret = 0;
 351                         break;
 352                 }
 353         }
 354         return ret;
 355 }
 356
 357 static int
 358 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 359 {
 360         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 361         uint16_t dist_idx;
 362         uint32_t vq_id;
 363         uint8_t num_rxqueue_per_tc;
 364         struct dpaa2_queue *mc_q, *mcq;
 365         uint32_t tot_queues;
 366         int i;
 367         struct dpaa2_queue *dpaa2_q;
 368
 369         PMD_INIT_FUNC_TRACE();
 370
 371         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 372         if (priv->flags & DPAA2_TX_CONF_ENABLE)
 373                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 374         else
 375                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 376         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 377                           RTE_CACHE_LINE_SIZE);
 378         if (!mc_q) {
 379                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 380                 return -1;
 381         }
 382
 383         for (i = 0; i < priv->nb_rx_queues; i++) {
 384                 mc_q->eth_data = dev->data;
 385                 priv->rx_vq[i] = mc_q++;
 386                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 387                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 388                                         sizeof(struct queue_storage_info_t),
 389                                         RTE_CACHE_LINE_SIZE);
 390                 if (!dpaa2_q->q_storage)
 391                         goto fail;
 392
 393                 memset(dpaa2_q->q_storage, 0,
 394                        sizeof(struct queue_storage_info_t));
 395                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 396                         goto fail;
 397         }
 398
 399         if (dpaa2_enable_err_queue) {
 400                 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
 401                         sizeof(struct dpaa2_queue), 0);
 402                 if (!priv->rx_err_vq)
 403                         goto fail;
 404
 405                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 406                 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
 407                                         sizeof(struct queue_storage_info_t) *
 408                                         RTE_MAX_LCORE,
 409                                         RTE_CACHE_LINE_SIZE);
 410                 if (!dpaa2_q->q_storage)
 411                         goto fail;
 412
 413                 memset(dpaa2_q->q_storage, 0,
 414                        sizeof(struct queue_storage_info_t));
 415                 for (i = 0; i < RTE_MAX_LCORE; i++)
 416                         if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
 417                                 goto fail;
 418         }
 419
 420         for (i = 0; i < priv->nb_tx_queues; i++) {
 421                 mc_q->eth_data = dev->data;
 422                 mc_q->flow_id = 0xffff;
 423                 priv->tx_vq[i] = mc_q++;
 424                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 425                 dpaa2_q->cscn = rte_malloc(NULL,
 426                                            sizeof(struct qbman_result), 16);
 427                 if (!dpaa2_q->cscn)
 428                         goto fail_tx;
 429         }
 430
 431         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 432                 /*Setup tx confirmation queues*/
 433                 for (i = 0; i < priv->nb_tx_queues; i++) {
 434                         mc_q->eth_data = dev->data;
 435                         mc_q->tc_index = i;
 436                         mc_q->flow_id = 0;
 437                         priv->tx_conf_vq[i] = mc_q++;
 438                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 439                         dpaa2_q->q_storage =
 440                                 rte_malloc("dq_storage",
 441                                         sizeof(struct queue_storage_info_t),
 442                                         RTE_CACHE_LINE_SIZE);
 443                         if (!dpaa2_q->q_storage)
 444                                 goto fail_tx_conf;
 445
 446                         memset(dpaa2_q->q_storage, 0,
 447                                sizeof(struct queue_storage_info_t));
 448                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 449                                 goto fail_tx_conf;
 450                 }
 451         }
 452
 453         vq_id = 0;
 454         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 455                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 456                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 457                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 458                 vq_id++;
 459         }
 460
 461         return 0;
 462 fail_tx_conf:
 463         i -= 1;
 464         while (i >= 0) {
 465                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 466                 rte_free(dpaa2_q->q_storage);
 467                 priv->tx_conf_vq[i--] = NULL;
 468         }
 469         i = priv->nb_tx_queues;
 470 fail_tx:
 471         i -= 1;
 472         while (i >= 0) {
 473                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 474                 rte_free(dpaa2_q->cscn);
 475                 priv->tx_vq[i--] = NULL;
 476         }
 477         i = priv->nb_rx_queues;
 478 fail:
 479         i -= 1;
 480         mc_q = priv->rx_vq[0];
 481         while (i >= 0) {
 482                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 483                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 484                 rte_free(dpaa2_q->q_storage);
 485                 priv->rx_vq[i--] = NULL;
 486         }
 487
 488         if (dpaa2_enable_err_queue) {
 489                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 490                 if (dpaa2_q->q_storage)
 491                         dpaa2_free_dq_storage(dpaa2_q->q_storage);
 492                 rte_free(dpaa2_q->q_storage);
 493         }
 494
 495         rte_free(mc_q);
 496         return -1;
 497 }
 498
 499 static void
 500 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 501 {
 502         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 503         struct dpaa2_queue *dpaa2_q;
 504         int i;
 505
 506         PMD_INIT_FUNC_TRACE();
 507
 508         /* Queue allocation base */
 509         if (priv->rx_vq[0]) {
 510                 /* cleaning up queue storage */
 511                 for (i = 0; i < priv->nb_rx_queues; i++) {
 512                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 513                         rte_free(dpaa2_q->q_storage);
 514                 }
 515                 /* cleanup tx queue cscn */
 516                 for (i = 0; i < priv->nb_tx_queues; i++) {
 517                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 518                         rte_free(dpaa2_q->cscn);
 519                 }
 520                 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 521                         /* cleanup tx conf queue storage */
 522                         for (i = 0; i < priv->nb_tx_queues; i++) {
 523                                 dpaa2_q = (struct dpaa2_queue *)
 524                                                 priv->tx_conf_vq[i];
 525                                 rte_free(dpaa2_q->q_storage);
 526                         }
 527                 }
 528                 /*free memory for all queues (RX+TX) */
 529                 rte_free(priv->rx_vq[0]);
 530                 priv->rx_vq[0] = NULL;
 531         }
 532 }
 533
 534 static int
 535 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 536 {
 537         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 538         struct fsl_mc_io *dpni = dev->process_private;
 539         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 540         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 541         uint64_t tx_offloads = eth_conf->txmode.offloads;
 542         int rx_l3_csum_offload = false;
 543         int rx_l4_csum_offload = false;
 544         int tx_l3_csum_offload = false;
 545         int tx_l4_csum_offload = false;
 546         int ret, tc_index;
 547         uint32_t max_rx_pktlen;
 548
 549         PMD_INIT_FUNC_TRACE();
 550
 551         /* Rx offloads which are enabled by default */
 552         if (dev_rx_offloads_nodis & ~rx_offloads) {
 553                 DPAA2_PMD_INFO(
 554                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 555                 " fixed are 0x%" PRIx64,
 556                 rx_offloads, dev_rx_offloads_nodis);
 557         }
 558
 559         /* Tx offloads which are enabled by default */
 560         if (dev_tx_offloads_nodis & ~tx_offloads) {
 561                 DPAA2_PMD_INFO(
 562                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 563                 " fixed are 0x%" PRIx64,
 564                 tx_offloads, dev_tx_offloads_nodis);
 565         }
 566
 567         max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
 568                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
 569         if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) {
 570                 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 571                         priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN);
 572                 if (ret != 0) {
 573                         DPAA2_PMD_ERR("Unable to set mtu. check config");
 574                         return ret;
 575                 }
 576                 DPAA2_PMD_INFO("MTU configured for the device: %d",
 577                                 dev->data->mtu);
 578         } else {
 579                 return -1;
 580         }
 581
 582         if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
 583                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 584                         ret = dpaa2_setup_flow_dist(dev,
 585                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 586                                         tc_index);
 587                         if (ret) {
 588                                 DPAA2_PMD_ERR(
 589                                         "Unable to set flow distribution on tc%d."
 590                                         "Check queue config", tc_index);
 591                                 return ret;
 592                         }
 593                 }
 594         }
 595
 596         if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM)
 597                 rx_l3_csum_offload = true;
 598
 599         if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) ||
 600                 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) ||
 601                 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM))
 602                 rx_l4_csum_offload = true;
 603
 604         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 605                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 606         if (ret) {
 607                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 608                 return ret;
 609         }
 610
 611         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 612                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 613         if (ret) {
 614                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 615                 return ret;
 616         }
 617
 618 #if !defined(RTE_LIBRTE_IEEE1588)
 619         if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 620 #endif
 621         {
 622                 ret = rte_mbuf_dyn_rx_timestamp_register(
 623                                 &dpaa2_timestamp_dynfield_offset,
 624                                 &dpaa2_timestamp_rx_dynflag);
 625                 if (ret != 0) {
 626                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 627                         return -rte_errno;
 628                 }
 629                 dpaa2_enable_ts[dev->data->port_id] = true;
 630         }
 631
 632         if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
 633                 tx_l3_csum_offload = true;
 634
 635         if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) ||
 636                 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) ||
 637                 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM))
 638                 tx_l4_csum_offload = true;
 639
 640         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 641                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 642         if (ret) {
 643                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 644                 return ret;
 645         }
 646
 647         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 648                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 649         if (ret) {
 650                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 651                 return ret;
 652         }
 653
 654         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 655          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 656          * to 0 for LS2 in the hardware thus disabling data/annotation
 657          * stashing. For LX2 this is fixed in hardware and thus hash result and
 658          * parse results can be received in FD using this option.
 659          */
 660         if (dpaa2_svr_family == SVR_LX2160A) {
 661                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 662                                        DPNI_FLCTYPE_HASH, true);
 663                 if (ret) {
 664                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 665                         return ret;
 666                 }
 667         }
 668
 669         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 670                 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK);
 671
 672         if (eth_conf->lpbk_mode) {
 673                 ret = dpaa2_dev_recycle_config(dev);
 674                 if (ret) {
 675                         DPAA2_PMD_ERR("Error to configure %s to recycle port.",
 676                                 dev->data->name);
 677
 678                         return ret;
 679                 }
 680         } else {
 681                 /** User may disable loopback mode by calling
 682                  * "dev_configure" with lpbk_mode cleared.
 683                  * No matter the port was configured recycle or not,
 684                  * recycle de-configure is called here.
 685                  * If port is not recycled, the de-configure will return directly.
 686                  */
 687                 ret = dpaa2_dev_recycle_deconfig(dev);
 688                 if (ret) {
 689                         DPAA2_PMD_ERR("Error to de-configure recycle port %s.",
 690                                 dev->data->name);
 691
 692                         return ret;
 693                 }
 694         }
 695
 696         dpaa2_tm_init(dev);
 697
 698         return 0;
 699 }
 700
 701 /* Function to setup RX flow information. It contains traffic class ID,
 702  * flow ID, destination configuration etc.
 703  */
 704 static int
 705 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 706                          uint16_t rx_queue_id,
 707                          uint16_t nb_rx_desc,
 708                          unsigned int socket_id __rte_unused,
 709                          const struct rte_eth_rxconf *rx_conf,
 710                          struct rte_mempool *mb_pool)
 711 {
 712         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 713         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 714         struct dpaa2_queue *dpaa2_q;
 715         struct dpni_queue cfg;
 716         uint8_t options = 0;
 717         uint8_t flow_id;
 718         uint32_t bpid;
 719         int i, ret;
 720
 721         PMD_INIT_FUNC_TRACE();
 722
 723         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 724                         dev, rx_queue_id, mb_pool, rx_conf);
 725
 726         total_nb_rx_desc += nb_rx_desc;
 727         if (total_nb_rx_desc > MAX_NB_RX_DESC) {
 728                 DPAA2_PMD_WARN("\nTotal nb_rx_desc exceeds %d limit. Please use Normal buffers",
 729                                MAX_NB_RX_DESC);
 730                 DPAA2_PMD_WARN("To use Normal buffers, run 'export DPNI_NORMAL_BUF=1' before running dynamic_dpl.sh script");
 731         }
 732
 733         /* Rx deferred start is not supported */
 734         if (rx_conf->rx_deferred_start) {
 735                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 736                                 (void *)dev);
 737                 return -EINVAL;
 738         }
 739
 740         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 741                 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 742                         ret = rte_dpaa2_bpid_info_init(mb_pool);
 743                         if (ret)
 744                                 return ret;
 745                 }
 746                 bpid = mempool_to_bpid(mb_pool);
 747                 ret = dpaa2_attach_bp_list(priv, dpni,
 748                                 rte_dpaa2_bpid_info[bpid].bp_list);
 749                 if (ret)
 750                         return ret;
 751         }
 752         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 753         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 754         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 755         dpaa2_q->nb_desc = UINT16_MAX;
 756         dpaa2_q->offloads = rx_conf->offloads;
 757
 758         /*Get the flow id from given VQ id*/
 759         flow_id = dpaa2_q->flow_id;
 760         memset(&cfg, 0, sizeof(struct dpni_queue));
 761
 762         options = options | DPNI_QUEUE_OPT_USER_CTX;
 763         cfg.user_context = (size_t)(dpaa2_q);
 764
 765         /* check if a private cgr available. */
 766         for (i = 0; i < priv->max_cgs; i++) {
 767                 if (!priv->cgid_in_use[i]) {
 768                         priv->cgid_in_use[i] = 1;
 769                         break;
 770                 }
 771         }
 772
 773         if (i < priv->max_cgs) {
 774                 options |= DPNI_QUEUE_OPT_SET_CGID;
 775                 cfg.cgid = i;
 776                 dpaa2_q->cgid = cfg.cgid;
 777         } else {
 778                 dpaa2_q->cgid = 0xff;
 779         }
 780
 781         /*if ls2088 or rev2 device, enable the stashing */
 782
 783         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 784                 options |= DPNI_QUEUE_OPT_FLC;
 785                 cfg.flc.stash_control = true;
 786                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 787                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 788                  * data stashing setting 01 01 00 (0x14)
 789                  * (in following order ->DS AS CS)
 790                  * to enable 1 line data, 1 line annotation.
 791                  * For LX2, this setting should be 01 00 00 (0x10)
 792                  */
 793                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 794                         cfg.flc.value |= 0x10;
 795                 else
 796                         cfg.flc.value |= 0x14;
 797         }
 798         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 799                              dpaa2_q->tc_index, flow_id, options, &cfg);
 800         if (ret) {
 801                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 802                 return -1;
 803         }
 804
 805         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 806                 struct dpni_taildrop taildrop;
 807
 808                 taildrop.enable = 1;
 809                 dpaa2_q->nb_desc = nb_rx_desc;
 810                 /* Private CGR will use tail drop length as nb_rx_desc.
 811                  * for rest cases we can use standard byte based tail drop.
 812                  * There is no HW restriction, but number of CGRs are limited,
 813                  * hence this restriction is placed.
 814                  */
 815                 if (dpaa2_q->cgid != 0xff) {
 816                         /*enabling per rx queue congestion control */
 817                         taildrop.threshold = nb_rx_desc;
 818                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 819                         taildrop.oal = 0;
 820                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 821                                         rx_queue_id);
 822                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 823                                                 DPNI_CP_CONGESTION_GROUP,
 824                                                 DPNI_QUEUE_RX,
 825                                                 dpaa2_q->tc_index,
 826                                                 dpaa2_q->cgid, &taildrop);
 827                 } else {
 828                         /*enabling per rx queue congestion control */
 829                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 830                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 831                         taildrop.oal = CONG_RX_OAL;
 832                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 833                                         rx_queue_id);
 834                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 835                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 836                                                 dpaa2_q->tc_index, flow_id,
 837                                                 &taildrop);
 838                 }
 839                 if (ret) {
 840                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 841                                       ret);
 842                         return -1;
 843                 }
 844         } else { /* Disable tail Drop */
 845                 struct dpni_taildrop taildrop = {0};
 846                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 847
 848                 taildrop.enable = 0;
 849                 if (dpaa2_q->cgid != 0xff) {
 850                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 851                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 852                                         dpaa2_q->tc_index,
 853                                         dpaa2_q->cgid, &taildrop);
 854                 } else {
 855                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 856                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 857                                         dpaa2_q->tc_index, flow_id, &taildrop);
 858                 }
 859                 if (ret) {
 860                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 861                                       ret);
 862                         return -1;
 863                 }
 864         }
 865
 866         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 867         return 0;
 868 }
 869
 870 static int
 871 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 872                          uint16_t tx_queue_id,
 873                          uint16_t nb_tx_desc,
 874                          unsigned int socket_id __rte_unused,
 875                          const struct rte_eth_txconf *tx_conf)
 876 {
 877         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 878         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 879                 priv->tx_vq[tx_queue_id];
 880         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 881                 priv->tx_conf_vq[tx_queue_id];
 882         struct fsl_mc_io *dpni = dev->process_private;
 883         struct dpni_queue tx_conf_cfg;
 884         struct dpni_queue tx_flow_cfg;
 885         uint8_t options = 0, flow_id;
 886         uint16_t channel_id;
 887         struct dpni_queue_id qid;
 888         uint32_t tc_id;
 889         int ret;
 890
 891         PMD_INIT_FUNC_TRACE();
 892
 893         /* Tx deferred start is not supported */
 894         if (tx_conf->tx_deferred_start) {
 895                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 896                                 (void *)dev);
 897                 return -EINVAL;
 898         }
 899
 900         dpaa2_q->nb_desc = UINT16_MAX;
 901         dpaa2_q->offloads = tx_conf->offloads;
 902
 903         /* Return if queue already configured */
 904         if (dpaa2_q->flow_id != 0xffff) {
 905                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 906                 return 0;
 907         }
 908
 909         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 910         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 911
 912         if (tx_queue_id == 0) {
 913                 /*Set tx-conf and error configuration*/
 914                 if (priv->flags & DPAA2_TX_CONF_ENABLE)
 915                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 916                                                             priv->token,
 917                                                             DPNI_CONF_AFFINE);
 918                 else
 919                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 920                                                             priv->token,
 921                                                             DPNI_CONF_DISABLE);
 922                 if (ret) {
 923                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 924                                       "err=%d", ret);
 925                         return -1;
 926                 }
 927         }
 928
 929         tc_id = tx_queue_id % priv->num_tx_tc;
 930         channel_id = (uint8_t)(tx_queue_id / priv->num_tx_tc) % priv->num_channels;
 931         flow_id = 0;
 932
 933         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 934                         ((channel_id << 8) | tc_id), flow_id, options, &tx_flow_cfg);
 935         if (ret) {
 936                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 937                         "tc_id=%d, flow=%d err=%d",
 938                         tc_id, flow_id, ret);
 939                         return -1;
 940         }
 941
 942         dpaa2_q->flow_id = flow_id;
 943
 944         dpaa2_q->tc_index = tc_id;
 945
 946         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 947                              DPNI_QUEUE_TX, ((channel_id << 8) | dpaa2_q->tc_index),
 948                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 949         if (ret) {
 950                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 951                 return -1;
 952         }
 953         dpaa2_q->fqid = qid.fqid;
 954
 955         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 956                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 957
 958                 dpaa2_q->nb_desc = nb_tx_desc;
 959
 960                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 961                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 962                 /* Notify that the queue is not congested when the data in
 963                  * the queue is below this threshold.(90% of value)
 964                  */
 965                 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
 966                 cong_notif_cfg.message_ctx = 0;
 967                 cong_notif_cfg.message_iova =
 968                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 969                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 970                 cong_notif_cfg.notification_mode =
 971                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 972                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 973                                          DPNI_CONG_OPT_COHERENT_WRITE;
 974                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 975
 976                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 977                                                        priv->token,
 978                                                        DPNI_QUEUE_TX,
 979                                                        ((channel_id << 8) | tc_id),
 980                                                        &cong_notif_cfg);
 981                 if (ret) {
 982                         DPAA2_PMD_ERR(
 983                            "Error in setting tx congestion notification: "
 984                            "err=%d", ret);
 985                         return -ret;
 986                 }
 987         }
 988         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 989         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 990
 991         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 992                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 993                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 994                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 995                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 996                              DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index),
 997                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 998                 if (ret) {
 999                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
1000                               "tc_index=%d, flow=%d err=%d",
1001                               dpaa2_tx_conf_q->tc_index,
1002                               dpaa2_tx_conf_q->flow_id, ret);
1003                         return -1;
1004                 }
1005
1006                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1007                              DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index),
1008                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
1009                 if (ret) {
1010                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
1011                         return -1;
1012                 }
1013                 dpaa2_tx_conf_q->fqid = qid.fqid;
1014         }
1015         return 0;
1016 }
1017
1018 static void
1019 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1020 {
1021         struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id];
1022         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
1023         struct fsl_mc_io *dpni =
1024                 (struct fsl_mc_io *)priv->eth_dev->process_private;
1025         uint8_t options = 0;
1026         int ret;
1027         struct dpni_queue cfg;
1028
1029         memset(&cfg, 0, sizeof(struct dpni_queue));
1030         PMD_INIT_FUNC_TRACE();
1031
1032         total_nb_rx_desc -= dpaa2_q->nb_desc;
1033
1034         if (dpaa2_q->cgid != 0xff) {
1035                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
1036                 cfg.cgid = dpaa2_q->cgid;
1037
1038                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
1039                                      DPNI_QUEUE_RX,
1040                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
1041                                      options, &cfg);
1042                 if (ret)
1043                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1044                                         dpaa2_q->fqid, ret);
1045                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1046                 dpaa2_q->cgid = 0xff;
1047         }
1048 }
1049
1050 static uint32_t
1051 dpaa2_dev_rx_queue_count(void *rx_queue)
1052 {
1053         int32_t ret;
1054         struct dpaa2_queue *dpaa2_q;
1055         struct qbman_swp *swp;
1056         struct qbman_fq_query_np_rslt state;
1057         uint32_t frame_cnt = 0;
1058
1059         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1060                 ret = dpaa2_affine_qbman_swp();
1061                 if (ret) {
1062                         DPAA2_PMD_ERR(
1063                                 "Failed to allocate IO portal, tid: %d\n",
1064                                 rte_gettid());
1065                         return -EINVAL;
1066                 }
1067         }
1068         swp = DPAA2_PER_LCORE_PORTAL;
1069
1070         dpaa2_q = rx_queue;
1071
1072         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1073                 frame_cnt = qbman_fq_state_frame_count(&state);
1074                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u",
1075                                 rx_queue, frame_cnt);
1076         }
1077         return frame_cnt;
1078 }
1079
1080 static const uint32_t *
1081 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1082 {
1083         static const uint32_t ptypes[] = {
1084                 /*todo -= add more types */
1085                 RTE_PTYPE_L2_ETHER,
1086                 RTE_PTYPE_L3_IPV4,
1087                 RTE_PTYPE_L3_IPV4_EXT,
1088                 RTE_PTYPE_L3_IPV6,
1089                 RTE_PTYPE_L3_IPV6_EXT,
1090                 RTE_PTYPE_L4_TCP,
1091                 RTE_PTYPE_L4_UDP,
1092                 RTE_PTYPE_L4_SCTP,
1093                 RTE_PTYPE_L4_ICMP,
1094                 RTE_PTYPE_UNKNOWN
1095         };
1096
1097         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1098                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1099                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1100                 return ptypes;
1101         return NULL;
1102 }
1103
1104 /**
1105  * Dpaa2 link Interrupt handler
1106  *
1107  * @param param
1108  *  The address of parameter (struct rte_eth_dev *) registered before.
1109  *
1110  * @return
1111  *  void
1112  */
1113 static void
1114 dpaa2_interrupt_handler(void *param)
1115 {
1116         struct rte_eth_dev *dev = param;
1117         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1118         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1119         int ret;
1120         int irq_index = DPNI_IRQ_INDEX;
1121         unsigned int status = 0, clear = 0;
1122
1123         PMD_INIT_FUNC_TRACE();
1124
1125         if (dpni == NULL) {
1126                 DPAA2_PMD_ERR("dpni is NULL");
1127                 return;
1128         }
1129
1130         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1131                                   irq_index, &status);
1132         if (unlikely(ret)) {
1133                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1134                 clear = 0xffffffff;
1135                 goto out;
1136         }
1137
1138         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1139                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1140                 dpaa2_dev_link_update(dev, 0);
1141                 /* calling all the apps registered for link status event */
1142                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1143         }
1144 out:
1145         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1146                                     irq_index, clear);
1147         if (unlikely(ret))
1148                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1149 }
1150
1151 static int
1152 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1153 {
1154         int err = 0;
1155         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1156         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1157         int irq_index = DPNI_IRQ_INDEX;
1158         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1159
1160         PMD_INIT_FUNC_TRACE();
1161
1162         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1163                                 irq_index, mask);
1164         if (err < 0) {
1165                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1166                               strerror(-err));
1167                 return err;
1168         }
1169
1170         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1171                                   irq_index, enable);
1172         if (err < 0)
1173                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1174                               strerror(-err));
1175
1176         return err;
1177 }
1178
1179 static int
1180 dpaa2_dev_start(struct rte_eth_dev *dev)
1181 {
1182         struct rte_device *rdev = dev->device;
1183         struct rte_dpaa2_device *dpaa2_dev;
1184         struct rte_eth_dev_data *data = dev->data;
1185         struct dpaa2_dev_priv *priv = data->dev_private;
1186         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1187         struct dpni_queue cfg;
1188         struct dpni_error_cfg   err_cfg;
1189         struct dpni_queue_id qid;
1190         struct dpaa2_queue *dpaa2_q;
1191         int ret, i;
1192         struct rte_intr_handle *intr_handle;
1193
1194         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1195         intr_handle = dpaa2_dev->intr_handle;
1196
1197         PMD_INIT_FUNC_TRACE();
1198         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1199         if (ret) {
1200                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1201                               priv->hw_id, ret);
1202                 return ret;
1203         }
1204
1205         /* Power up the phy. Needed to make the link go UP */
1206         dpaa2_dev_set_link_up(dev);
1207
1208         for (i = 0; i < data->nb_rx_queues; i++) {
1209                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1210                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1211                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1212                                        dpaa2_q->flow_id, &cfg, &qid);
1213                 if (ret) {
1214                         DPAA2_PMD_ERR("Error in getting flow information: "
1215                                       "err=%d", ret);
1216                         return ret;
1217                 }
1218                 dpaa2_q->fqid = qid.fqid;
1219         }
1220
1221         if (dpaa2_enable_err_queue) {
1222                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1223                                      DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1224                 if (ret) {
1225                         DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1226                                                 ret);
1227                         return ret;
1228                 }
1229                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1230                 dpaa2_q->fqid = qid.fqid;
1231                 dpaa2_q->eth_data = dev->data;
1232
1233                 err_cfg.errors =  DPNI_ERROR_DISC;
1234                 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1235         } else {
1236                 /* checksum errors, send them to normal path
1237                  * and set it in annotation
1238                  */
1239                 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1240
1241                 /* if packet with parse error are not to be dropped */
1242                 err_cfg.errors |= DPNI_ERROR_PHE;
1243
1244                 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1245         }
1246         err_cfg.set_frame_annotation = true;
1247
1248         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1249                                        priv->token, &err_cfg);
1250         if (ret) {
1251                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1252                               ret);
1253                 return ret;
1254         }
1255
1256         /* if the interrupts were configured on this devices*/
1257         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1258             dev->data->dev_conf.intr_conf.lsc != 0) {
1259                 /* Registering LSC interrupt handler */
1260                 rte_intr_callback_register(intr_handle,
1261                                            dpaa2_interrupt_handler,
1262                                            (void *)dev);
1263
1264                 /* enable vfio intr/eventfd mapping
1265                  * Interrupt index 0 is required, so we can not use
1266                  * rte_intr_enable.
1267                  */
1268                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1269
1270                 /* enable dpni_irqs */
1271                 dpaa2_eth_setup_irqs(dev, 1);
1272         }
1273
1274         /* Change the tx burst function if ordered queues are used */
1275         if (priv->en_ordered)
1276                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1277
1278         return 0;
1279 }
1280
1281 /**
1282  *  This routine disables all traffic on the adapter by issuing a
1283  *  global reset on the MAC.
1284  */
1285 static int
1286 dpaa2_dev_stop(struct rte_eth_dev *dev)
1287 {
1288         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1289         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1290         int ret;
1291         struct rte_eth_link link;
1292         struct rte_device *rdev = dev->device;
1293         struct rte_intr_handle *intr_handle;
1294         struct rte_dpaa2_device *dpaa2_dev;
1295
1296         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1297         intr_handle = dpaa2_dev->intr_handle;
1298
1299         PMD_INIT_FUNC_TRACE();
1300
1301         /* reset interrupt callback  */
1302         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1303             dev->data->dev_conf.intr_conf.lsc != 0) {
1304                 /*disable dpni irqs */
1305                 dpaa2_eth_setup_irqs(dev, 0);
1306
1307                 /* disable vfio intr before callback unregister */
1308                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1309
1310                 /* Unregistering LSC interrupt handler */
1311                 rte_intr_callback_unregister(intr_handle,
1312                                              dpaa2_interrupt_handler,
1313                                              (void *)dev);
1314         }
1315
1316         dpaa2_dev_set_link_down(dev);
1317
1318         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1319         if (ret) {
1320                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1321                               ret, priv->hw_id);
1322                 return ret;
1323         }
1324
1325         /* clear the recorded link status */
1326         memset(&link, 0, sizeof(link));
1327         rte_eth_linkstatus_set(dev, &link);
1328
1329         return 0;
1330 }
1331
1332 static int
1333 dpaa2_dev_close(struct rte_eth_dev *dev)
1334 {
1335         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1336         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1337         int i, ret;
1338         struct rte_eth_link link;
1339
1340         PMD_INIT_FUNC_TRACE();
1341
1342         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1343                 return 0;
1344
1345         if (!dpni) {
1346                 DPAA2_PMD_WARN("Already closed or not started");
1347                 return -1;
1348         }
1349
1350         dpaa2_tm_deinit(dev);
1351         dpaa2_flow_clean(dev);
1352         /* Clean the device first */
1353         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1354         if (ret) {
1355                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1356                 return -1;
1357         }
1358
1359         memset(&link, 0, sizeof(link));
1360         rte_eth_linkstatus_set(dev, &link);
1361
1362         /* Free private queues memory */
1363         dpaa2_free_rx_tx_queues(dev);
1364         /* Close the device at underlying layer*/
1365         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1366         if (ret) {
1367                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1368                               ret);
1369         }
1370
1371         /* Free the allocated memory for ethernet private data and dpni*/
1372         priv->hw = NULL;
1373         dev->process_private = NULL;
1374         rte_free(dpni);
1375
1376         for (i = 0; i < MAX_TCS; i++)
1377                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1378
1379         if (priv->extract.qos_extract_param)
1380                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1381
1382         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1383         return 0;
1384 }
1385
1386 static int
1387 dpaa2_dev_promiscuous_enable(
1388                 struct rte_eth_dev *dev)
1389 {
1390         int ret;
1391         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1392         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1393
1394         PMD_INIT_FUNC_TRACE();
1395
1396         if (dpni == NULL) {
1397                 DPAA2_PMD_ERR("dpni is NULL");
1398                 return -ENODEV;
1399         }
1400
1401         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1402         if (ret < 0)
1403                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1404
1405         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1406         if (ret < 0)
1407                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1408
1409         return ret;
1410 }
1411
1412 static int
1413 dpaa2_dev_promiscuous_disable(
1414                 struct rte_eth_dev *dev)
1415 {
1416         int ret;
1417         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1418         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1419
1420         PMD_INIT_FUNC_TRACE();
1421
1422         if (dpni == NULL) {
1423                 DPAA2_PMD_ERR("dpni is NULL");
1424                 return -ENODEV;
1425         }
1426
1427         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1428         if (ret < 0)
1429                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1430
1431         if (dev->data->all_multicast == 0) {
1432                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1433                                                  priv->token, false);
1434                 if (ret < 0)
1435                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1436                                       ret);
1437         }
1438
1439         return ret;
1440 }
1441
1442 static int
1443 dpaa2_dev_allmulticast_enable(
1444                 struct rte_eth_dev *dev)
1445 {
1446         int ret;
1447         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1448         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1449
1450         PMD_INIT_FUNC_TRACE();
1451
1452         if (dpni == NULL) {
1453                 DPAA2_PMD_ERR("dpni is NULL");
1454                 return -ENODEV;
1455         }
1456
1457         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1458         if (ret < 0)
1459                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1460
1461         return ret;
1462 }
1463
1464 static int
1465 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1466 {
1467         int ret;
1468         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1469         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1470
1471         PMD_INIT_FUNC_TRACE();
1472
1473         if (dpni == NULL) {
1474                 DPAA2_PMD_ERR("dpni is NULL");
1475                 return -ENODEV;
1476         }
1477
1478         /* must remain on for all promiscuous */
1479         if (dev->data->promiscuous == 1)
1480                 return 0;
1481
1482         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1483         if (ret < 0)
1484                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1485
1486         return ret;
1487 }
1488
1489 static int
1490 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1491 {
1492         int ret;
1493         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1494         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1495         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1496                                 + VLAN_TAG_SIZE;
1497
1498         PMD_INIT_FUNC_TRACE();
1499
1500         if (dpni == NULL) {
1501                 DPAA2_PMD_ERR("dpni is NULL");
1502                 return -EINVAL;
1503         }
1504
1505         /* Set the Max Rx frame length as 'mtu' +
1506          * Maximum Ethernet header length
1507          */
1508         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1509                                         frame_size - RTE_ETHER_CRC_LEN);
1510         if (ret) {
1511                 DPAA2_PMD_ERR("Setting the max frame length failed");
1512                 return -1;
1513         }
1514         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1515         return 0;
1516 }
1517
1518 static int
1519 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1520                        struct rte_ether_addr *addr,
1521                        __rte_unused uint32_t index,
1522                        __rte_unused uint32_t pool)
1523 {
1524         int ret;
1525         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1526         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1527
1528         PMD_INIT_FUNC_TRACE();
1529
1530         if (dpni == NULL) {
1531                 DPAA2_PMD_ERR("dpni is NULL");
1532                 return -1;
1533         }
1534
1535         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1536                                 addr->addr_bytes, 0, 0, 0);
1537         if (ret)
1538                 DPAA2_PMD_ERR(
1539                         "error: Adding the MAC ADDR failed: err = %d", ret);
1540         return 0;
1541 }
1542
1543 static void
1544 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1545                           uint32_t index)
1546 {
1547         int ret;
1548         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1549         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1550         struct rte_eth_dev_data *data = dev->data;
1551         struct rte_ether_addr *macaddr;
1552
1553         PMD_INIT_FUNC_TRACE();
1554
1555         macaddr = &data->mac_addrs[index];
1556
1557         if (dpni == NULL) {
1558                 DPAA2_PMD_ERR("dpni is NULL");
1559                 return;
1560         }
1561
1562         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1563                                    priv->token, macaddr->addr_bytes);
1564         if (ret)
1565                 DPAA2_PMD_ERR(
1566                         "error: Removing the MAC ADDR failed: err = %d", ret);
1567 }
1568
1569 static int
1570 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1571                        struct rte_ether_addr *addr)
1572 {
1573         int ret;
1574         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1575         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1576
1577         PMD_INIT_FUNC_TRACE();
1578
1579         if (dpni == NULL) {
1580                 DPAA2_PMD_ERR("dpni is NULL");
1581                 return -EINVAL;
1582         }
1583
1584         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1585                                         priv->token, addr->addr_bytes);
1586
1587         if (ret)
1588                 DPAA2_PMD_ERR(
1589                         "error: Setting the MAC ADDR failed %d", ret);
1590
1591         return ret;
1592 }
1593
1594 static
1595 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1596                          struct rte_eth_stats *stats)
1597 {
1598         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1599         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1600         int32_t  retcode;
1601         uint8_t page0 = 0, page1 = 1, page2 = 2;
1602         union dpni_statistics value;
1603         int i;
1604         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1605
1606         memset(&value, 0, sizeof(union dpni_statistics));
1607
1608         PMD_INIT_FUNC_TRACE();
1609
1610         if (!dpni) {
1611                 DPAA2_PMD_ERR("dpni is NULL");
1612                 return -EINVAL;
1613         }
1614
1615         if (!stats) {
1616                 DPAA2_PMD_ERR("stats is NULL");
1617                 return -EINVAL;
1618         }
1619
1620         /*Get Counters from page_0*/
1621         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1622                                       page0, 0, &value);
1623         if (retcode)
1624                 goto err;
1625
1626         stats->ipackets = value.page_0.ingress_all_frames;
1627         stats->ibytes = value.page_0.ingress_all_bytes;
1628
1629         /*Get Counters from page_1*/
1630         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1631                                       page1, 0, &value);
1632         if (retcode)
1633                 goto err;
1634
1635         stats->opackets = value.page_1.egress_all_frames;
1636         stats->obytes = value.page_1.egress_all_bytes;
1637
1638         /*Get Counters from page_2*/
1639         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1640                                       page2, 0, &value);
1641         if (retcode)
1642                 goto err;
1643
1644         /* Ingress drop frame count due to configured rules */
1645         stats->ierrors = value.page_2.ingress_filtered_frames;
1646         /* Ingress drop frame count due to error */
1647         stats->ierrors += value.page_2.ingress_discarded_frames;
1648
1649         stats->oerrors = value.page_2.egress_discarded_frames;
1650         stats->imissed = value.page_2.ingress_nobuffer_discards;
1651
1652         /* Fill in per queue stats */
1653         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1654                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1655                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1656                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1657                 if (dpaa2_rxq)
1658                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1659                 if (dpaa2_txq)
1660                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1661
1662                 /* Byte counting is not implemented */
1663                 stats->q_ibytes[i]   = 0;
1664                 stats->q_obytes[i]   = 0;
1665         }
1666
1667         return 0;
1668
1669 err:
1670         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1671         return retcode;
1672 };
1673
1674 static int
1675 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1676                      unsigned int n)
1677 {
1678         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1679         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1680         int32_t  retcode;
1681         union dpni_statistics value[5] = {};
1682         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1683
1684         if (n < num)
1685                 return num;
1686
1687         if (xstats == NULL)
1688                 return 0;
1689
1690         /* Get Counters from page_0*/
1691         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1692                                       0, 0, &value[0]);
1693         if (retcode)
1694                 goto err;
1695
1696         /* Get Counters from page_1*/
1697         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1698                                       1, 0, &value[1]);
1699         if (retcode)
1700                 goto err;
1701
1702         /* Get Counters from page_2*/
1703         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1704                                       2, 0, &value[2]);
1705         if (retcode)
1706                 goto err;
1707
1708         for (i = 0; i < priv->max_cgs; i++) {
1709                 if (!priv->cgid_in_use[i]) {
1710                         /* Get Counters from page_4*/
1711                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1712                                                       priv->token,
1713                                                       4, 0, &value[4]);
1714                         if (retcode)
1715                                 goto err;
1716                         break;
1717                 }
1718         }
1719
1720         for (i = 0; i < num; i++) {
1721                 xstats[i].id = i;
1722                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1723                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1724         }
1725         return i;
1726 err:
1727         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1728         return retcode;
1729 }
1730
1731 static int
1732 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1733                        struct rte_eth_xstat_name *xstats_names,
1734                        unsigned int limit)
1735 {
1736         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1737
1738         if (limit < stat_cnt)
1739                 return stat_cnt;
1740
1741         if (xstats_names != NULL)
1742                 for (i = 0; i < stat_cnt; i++)
1743                         strlcpy(xstats_names[i].name,
1744                                 dpaa2_xstats_strings[i].name,
1745                                 sizeof(xstats_names[i].name));
1746
1747         return stat_cnt;
1748 }
1749
1750 static int
1751 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1752                        uint64_t *values, unsigned int n)
1753 {
1754         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1755         uint64_t values_copy[stat_cnt];
1756
1757         if (!ids) {
1758                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1759                 struct fsl_mc_io *dpni =
1760                         (struct fsl_mc_io *)dev->process_private;
1761                 int32_t  retcode;
1762                 union dpni_statistics value[5] = {};
1763
1764                 if (n < stat_cnt)
1765                         return stat_cnt;
1766
1767                 if (!values)
1768                         return 0;
1769
1770                 /* Get Counters from page_0*/
1771                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1772                                               0, 0, &value[0]);
1773                 if (retcode)
1774                         return 0;
1775
1776                 /* Get Counters from page_1*/
1777                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1778                                               1, 0, &value[1]);
1779                 if (retcode)
1780                         return 0;
1781
1782                 /* Get Counters from page_2*/
1783                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1784                                               2, 0, &value[2]);
1785                 if (retcode)
1786                         return 0;
1787
1788                 /* Get Counters from page_4*/
1789                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1790                                               4, 0, &value[4]);
1791                 if (retcode)
1792                         return 0;
1793
1794                 for (i = 0; i < stat_cnt; i++) {
1795                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1796                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1797                 }
1798                 return stat_cnt;
1799         }
1800
1801         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1802
1803         for (i = 0; i < n; i++) {
1804                 if (ids[i] >= stat_cnt) {
1805                         DPAA2_PMD_ERR("xstats id value isn't valid");
1806                         return -1;
1807                 }
1808                 values[i] = values_copy[ids[i]];
1809         }
1810         return n;
1811 }
1812
1813 static int
1814 dpaa2_xstats_get_names_by_id(
1815         struct rte_eth_dev *dev,
1816         const uint64_t *ids,
1817         struct rte_eth_xstat_name *xstats_names,
1818         unsigned int limit)
1819 {
1820         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1821         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1822
1823         if (!ids)
1824                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1825
1826         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1827
1828         for (i = 0; i < limit; i++) {
1829                 if (ids[i] >= stat_cnt) {
1830                         DPAA2_PMD_ERR("xstats id value isn't valid");
1831                         return -1;
1832                 }
1833                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1834         }
1835         return limit;
1836 }
1837
1838 static int
1839 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1840 {
1841         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1842         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1843         int retcode;
1844         int i;
1845         struct dpaa2_queue *dpaa2_q;
1846
1847         PMD_INIT_FUNC_TRACE();
1848
1849         if (dpni == NULL) {
1850                 DPAA2_PMD_ERR("dpni is NULL");
1851                 return -EINVAL;
1852         }
1853
1854         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1855         if (retcode)
1856                 goto error;
1857
1858         /* Reset the per queue stats in dpaa2_queue structure */
1859         for (i = 0; i < priv->nb_rx_queues; i++) {
1860                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1861                 if (dpaa2_q)
1862                         dpaa2_q->rx_pkts = 0;
1863         }
1864
1865         for (i = 0; i < priv->nb_tx_queues; i++) {
1866                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1867                 if (dpaa2_q)
1868                         dpaa2_q->tx_pkts = 0;
1869         }
1870
1871         return 0;
1872
1873 error:
1874         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1875         return retcode;
1876 };
1877
1878 /* return 0 means link status changed, -1 means not changed */
1879 static int
1880 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1881                       int wait_to_complete)
1882 {
1883         int ret;
1884         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1885         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1886         struct rte_eth_link link;
1887         struct dpni_link_state state = {0};
1888         uint8_t count;
1889
1890         if (dpni == NULL) {
1891                 DPAA2_PMD_ERR("dpni is NULL");
1892                 return 0;
1893         }
1894
1895         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1896                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1897                                           &state);
1898                 if (ret < 0) {
1899                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1900                         return -1;
1901                 }
1902                 if (state.up == RTE_ETH_LINK_DOWN &&
1903                     wait_to_complete)
1904                         rte_delay_ms(CHECK_INTERVAL);
1905                 else
1906                         break;
1907         }
1908
1909         memset(&link, 0, sizeof(struct rte_eth_link));
1910         link.link_status = state.up;
1911         link.link_speed = state.rate;
1912
1913         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1914                 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
1915         else
1916                 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1917
1918         ret = rte_eth_linkstatus_set(dev, &link);
1919         if (ret == -1)
1920                 DPAA2_PMD_DEBUG("No change in status");
1921         else
1922                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1923                                link.link_status ? "Up" : "Down");
1924
1925         return ret;
1926 }
1927
1928 /**
1929  * Toggle the DPNI to enable, if not already enabled.
1930  * This is not strictly PHY up/down - it is more of logical toggling.
1931  */
1932 static int
1933 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1934 {
1935         int ret = -EINVAL;
1936         struct dpaa2_dev_priv *priv;
1937         struct fsl_mc_io *dpni;
1938         int en = 0;
1939         struct dpni_link_state state = {0};
1940
1941         priv = dev->data->dev_private;
1942         dpni = (struct fsl_mc_io *)dev->process_private;
1943
1944         if (dpni == NULL) {
1945                 DPAA2_PMD_ERR("dpni is NULL");
1946                 return ret;
1947         }
1948
1949         /* Check if DPNI is currently enabled */
1950         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1951         if (ret) {
1952                 /* Unable to obtain dpni status; Not continuing */
1953                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1954                 return -EINVAL;
1955         }
1956
1957         /* Enable link if not already enabled */
1958         if (!en) {
1959                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1960                 if (ret) {
1961                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1962                         return -EINVAL;
1963                 }
1964         }
1965         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1966         if (ret < 0) {
1967                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1968                 return -1;
1969         }
1970
1971         /* changing tx burst function to start enqueues */
1972         dev->tx_pkt_burst = dpaa2_dev_tx;
1973         dev->data->dev_link.link_status = state.up;
1974         dev->data->dev_link.link_speed = state.rate;
1975
1976         if (state.up)
1977                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1978         else
1979                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1980         return ret;
1981 }
1982
1983 /**
1984  * Toggle the DPNI to disable, if not already disabled.
1985  * This is not strictly PHY up/down - it is more of logical toggling.
1986  */
1987 static int
1988 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1989 {
1990         int ret = -EINVAL;
1991         struct dpaa2_dev_priv *priv;
1992         struct fsl_mc_io *dpni;
1993         int dpni_enabled = 0;
1994         int retries = 10;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         priv = dev->data->dev_private;
1999         dpni = (struct fsl_mc_io *)dev->process_private;
2000
2001         if (dpni == NULL) {
2002                 DPAA2_PMD_ERR("Device has not yet been configured");
2003                 return ret;
2004         }
2005
2006         /*changing  tx burst function to avoid any more enqueues */
2007         dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
2008
2009         /* Loop while dpni_disable() attempts to drain the egress FQs
2010          * and confirm them back to us.
2011          */
2012         do {
2013                 ret = dpni_disable(dpni, 0, priv->token);
2014                 if (ret) {
2015                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
2016                         return ret;
2017                 }
2018                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
2019                 if (ret) {
2020                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
2021                         return ret;
2022                 }
2023                 if (dpni_enabled)
2024                         /* Allow the MC some slack */
2025                         rte_delay_us(100 * 1000);
2026         } while (dpni_enabled && --retries);
2027
2028         if (!retries) {
2029                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2030                 /* todo- we may have to manually cleanup queues.
2031                  */
2032         } else {
2033                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2034                                dev->data->port_id);
2035         }
2036
2037         dev->data->dev_link.link_status = 0;
2038
2039         return ret;
2040 }
2041
2042 static int
2043 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2044 {
2045         int ret = -EINVAL;
2046         struct dpaa2_dev_priv *priv;
2047         struct fsl_mc_io *dpni;
2048         struct dpni_link_state state = {0};
2049
2050         PMD_INIT_FUNC_TRACE();
2051
2052         priv = dev->data->dev_private;
2053         dpni = (struct fsl_mc_io *)dev->process_private;
2054
2055         if (dpni == NULL || fc_conf == NULL) {
2056                 DPAA2_PMD_ERR("device not configured");
2057                 return ret;
2058         }
2059
2060         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2061         if (ret) {
2062                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2063                 return ret;
2064         }
2065
2066         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2067         if (state.options & DPNI_LINK_OPT_PAUSE) {
2068                 /* DPNI_LINK_OPT_PAUSE set
2069                  *  if ASYM_PAUSE not set,
2070                  *      RX Side flow control (handle received Pause frame)
2071                  *      TX side flow control (send Pause frame)
2072                  *  if ASYM_PAUSE set,
2073                  *      RX Side flow control (handle received Pause frame)
2074                  *      No TX side flow control (send Pause frame disabled)
2075                  */
2076                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2077                         fc_conf->mode = RTE_ETH_FC_FULL;
2078                 else
2079                         fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2080         } else {
2081                 /* DPNI_LINK_OPT_PAUSE not set
2082                  *  if ASYM_PAUSE set,
2083                  *      TX side flow control (send Pause frame)
2084                  *      No RX side flow control (No action on pause frame rx)
2085                  *  if ASYM_PAUSE not set,
2086                  *      Flow control disabled
2087                  */
2088                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2089                         fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2090                 else
2091                         fc_conf->mode = RTE_ETH_FC_NONE;
2092         }
2093
2094         return ret;
2095 }
2096
2097 static int
2098 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2099 {
2100         int ret = -EINVAL;
2101         struct dpaa2_dev_priv *priv;
2102         struct fsl_mc_io *dpni;
2103         struct dpni_link_state state = {0};
2104         struct dpni_link_cfg cfg = {0};
2105
2106         PMD_INIT_FUNC_TRACE();
2107
2108         priv = dev->data->dev_private;
2109         dpni = (struct fsl_mc_io *)dev->process_private;
2110
2111         if (dpni == NULL) {
2112                 DPAA2_PMD_ERR("dpni is NULL");
2113                 return ret;
2114         }
2115
2116         /* It is necessary to obtain the current state before setting fc_conf
2117          * as MC would return error in case rate, autoneg or duplex values are
2118          * different.
2119          */
2120         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2121         if (ret) {
2122                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2123                 return -1;
2124         }
2125
2126         /* Disable link before setting configuration */
2127         dpaa2_dev_set_link_down(dev);
2128
2129         /* Based on fc_conf, update cfg */
2130         cfg.rate = state.rate;
2131         cfg.options = state.options;
2132
2133         /* update cfg with fc_conf */
2134         switch (fc_conf->mode) {
2135         case RTE_ETH_FC_FULL:
2136                 /* Full flow control;
2137                  * OPT_PAUSE set, ASYM_PAUSE not set
2138                  */
2139                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2140                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2141                 break;
2142         case RTE_ETH_FC_TX_PAUSE:
2143                 /* Enable RX flow control
2144                  * OPT_PAUSE not set;
2145                  * ASYM_PAUSE set;
2146                  */
2147                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2148                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2149                 break;
2150         case RTE_ETH_FC_RX_PAUSE:
2151                 /* Enable TX Flow control
2152                  * OPT_PAUSE set
2153                  * ASYM_PAUSE set
2154                  */
2155                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2156                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2157                 break;
2158         case RTE_ETH_FC_NONE:
2159                 /* Disable Flow control
2160                  * OPT_PAUSE not set
2161                  * ASYM_PAUSE not set
2162                  */
2163                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2164                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2165                 break;
2166         default:
2167                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2168                               fc_conf->mode);
2169                 return -1;
2170         }
2171
2172         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2173         if (ret)
2174                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2175                               ret);
2176
2177         /* Enable link */
2178         dpaa2_dev_set_link_up(dev);
2179
2180         return ret;
2181 }
2182
2183 static int
2184 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2185                           struct rte_eth_rss_conf *rss_conf)
2186 {
2187         struct rte_eth_dev_data *data = dev->data;
2188         struct dpaa2_dev_priv *priv = data->dev_private;
2189         struct rte_eth_conf *eth_conf = &data->dev_conf;
2190         int ret, tc_index;
2191
2192         PMD_INIT_FUNC_TRACE();
2193
2194         if (rss_conf->rss_hf) {
2195                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2196                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2197                                 tc_index);
2198                         if (ret) {
2199                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2200                                         tc_index);
2201                                 return ret;
2202                         }
2203                 }
2204         } else {
2205                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2206                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2207                         if (ret) {
2208                                 DPAA2_PMD_ERR(
2209                                         "Unable to remove flow dist on tc%d",
2210                                         tc_index);
2211                                 return ret;
2212                         }
2213                 }
2214         }
2215         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2216         return 0;
2217 }
2218
2219 static int
2220 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2221                             struct rte_eth_rss_conf *rss_conf)
2222 {
2223         struct rte_eth_dev_data *data = dev->data;
2224         struct rte_eth_conf *eth_conf = &data->dev_conf;
2225
2226         /* dpaa2 does not support rss_key, so length should be 0*/
2227         rss_conf->rss_key_len = 0;
2228         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2229         return 0;
2230 }
2231
2232 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2233                 int eth_rx_queue_id,
2234                 struct dpaa2_dpcon_dev *dpcon,
2235                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2236 {
2237         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2238         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2239         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2240         uint8_t flow_id = dpaa2_ethq->flow_id;
2241         struct dpni_queue cfg;
2242         uint8_t options, priority;
2243         int ret;
2244
2245         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2246                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2247         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2248                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2249         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2250                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2251         else
2252                 return -EINVAL;
2253
2254         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2255                    (dpcon->num_priorities - 1);
2256
2257         memset(&cfg, 0, sizeof(struct dpni_queue));
2258         options = DPNI_QUEUE_OPT_DEST;
2259         cfg.destination.type = DPNI_DEST_DPCON;
2260         cfg.destination.id = dpcon->dpcon_id;
2261         cfg.destination.priority = priority;
2262
2263         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2264                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2265                 cfg.destination.hold_active = 1;
2266         }
2267
2268         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2269                         !eth_priv->en_ordered) {
2270                 struct opr_cfg ocfg;
2271
2272                 /* Restoration window size = 256 frames */
2273                 ocfg.oprrws = 3;
2274                 /* Restoration window size = 512 frames for LX2 */
2275                 if (dpaa2_svr_family == SVR_LX2160A)
2276                         ocfg.oprrws = 4;
2277                 /* Auto advance NESN window enabled */
2278                 ocfg.oa = 1;
2279                 /* Late arrival window size disabled */
2280                 ocfg.olws = 0;
2281                 /* ORL resource exhaustion advance NESN disabled */
2282                 ocfg.oeane = 0;
2283                 /* Loose ordering enabled */
2284                 ocfg.oloe = 1;
2285                 eth_priv->en_loose_ordered = 1;
2286                 /* Strict ordering enabled if explicitly set */
2287                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2288                         ocfg.oloe = 0;
2289                         eth_priv->en_loose_ordered = 0;
2290                 }
2291
2292                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2293                                    dpaa2_ethq->tc_index, flow_id,
2294                                    OPR_OPT_CREATE, &ocfg, 0);
2295                 if (ret) {
2296                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2297                         return ret;
2298                 }
2299
2300                 eth_priv->en_ordered = 1;
2301         }
2302
2303         options |= DPNI_QUEUE_OPT_USER_CTX;
2304         cfg.user_context = (size_t)(dpaa2_ethq);
2305
2306         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2307                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2308         if (ret) {
2309                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2310                 return ret;
2311         }
2312
2313         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2314
2315         return 0;
2316 }
2317
2318 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2319                 int eth_rx_queue_id)
2320 {
2321         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2322         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2323         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2324         uint8_t flow_id = dpaa2_ethq->flow_id;
2325         struct dpni_queue cfg;
2326         uint8_t options;
2327         int ret;
2328
2329         memset(&cfg, 0, sizeof(struct dpni_queue));
2330         options = DPNI_QUEUE_OPT_DEST;
2331         cfg.destination.type = DPNI_DEST_NONE;
2332
2333         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2334                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2335         if (ret)
2336                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2337
2338         return ret;
2339 }
2340
2341 static int
2342 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2343                        const struct rte_flow_ops **ops)
2344 {
2345         if (!dev)
2346                 return -ENODEV;
2347
2348         *ops = &dpaa2_flow_ops;
2349         return 0;
2350 }
2351
2352 static void
2353 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2354         struct rte_eth_rxq_info *qinfo)
2355 {
2356         struct dpaa2_queue *rxq;
2357         struct dpaa2_dev_priv *priv = dev->data->dev_private;
2358         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2359         uint16_t max_frame_length;
2360
2361         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2362
2363         qinfo->mp = rxq->mb_pool;
2364         qinfo->scattered_rx = dev->data->scattered_rx;
2365         qinfo->nb_desc = rxq->nb_desc;
2366         if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2367                                 &max_frame_length) == 0)
2368                 qinfo->rx_buf_size = max_frame_length;
2369
2370         qinfo->conf.rx_free_thresh = 1;
2371         qinfo->conf.rx_drop_en = 1;
2372         qinfo->conf.rx_deferred_start = 0;
2373         qinfo->conf.offloads = rxq->offloads;
2374 }
2375
2376 static void
2377 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2378         struct rte_eth_txq_info *qinfo)
2379 {
2380         struct dpaa2_queue *txq;
2381
2382         txq = dev->data->tx_queues[queue_id];
2383
2384         qinfo->nb_desc = txq->nb_desc;
2385         qinfo->conf.tx_thresh.pthresh = 0;
2386         qinfo->conf.tx_thresh.hthresh = 0;
2387         qinfo->conf.tx_thresh.wthresh = 0;
2388
2389         qinfo->conf.tx_free_thresh = 0;
2390         qinfo->conf.tx_rs_thresh = 0;
2391         qinfo->conf.offloads = txq->offloads;
2392         qinfo->conf.tx_deferred_start = 0;
2393 }
2394
2395 static int
2396 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2397 {
2398         *(const void **)ops = &dpaa2_tm_ops;
2399
2400         return 0;
2401 }
2402
2403 void
2404 rte_pmd_dpaa2_thread_init(void)
2405 {
2406         int ret;
2407
2408         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2409                 ret = dpaa2_affine_qbman_swp();
2410                 if (ret) {
2411                         DPAA2_PMD_ERR(
2412                                 "Failed to allocate IO portal, tid: %d\n",
2413                                 rte_gettid());
2414                         return;
2415                 }
2416         }
2417 }
2418
2419 static struct eth_dev_ops dpaa2_ethdev_ops = {
2420         .dev_configure    = dpaa2_eth_dev_configure,
2421         .dev_start            = dpaa2_dev_start,
2422         .dev_stop             = dpaa2_dev_stop,
2423         .dev_close            = dpaa2_dev_close,
2424         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2425         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2426         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2427         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2428         .dev_set_link_up      = dpaa2_dev_set_link_up,
2429         .dev_set_link_down    = dpaa2_dev_set_link_down,
2430         .link_update       = dpaa2_dev_link_update,
2431         .stats_get             = dpaa2_dev_stats_get,
2432         .xstats_get            = dpaa2_dev_xstats_get,
2433         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2434         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2435         .xstats_get_names      = dpaa2_xstats_get_names,
2436         .stats_reset       = dpaa2_dev_stats_reset,
2437         .xstats_reset         = dpaa2_dev_stats_reset,
2438         .fw_version_get    = dpaa2_fw_version_get,
2439         .dev_infos_get     = dpaa2_dev_info_get,
2440         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2441         .mtu_set           = dpaa2_dev_mtu_set,
2442         .vlan_filter_set      = dpaa2_vlan_filter_set,
2443         .vlan_offload_set     = dpaa2_vlan_offload_set,
2444         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2445         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2446         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2447         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2448         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2449         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2450         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2451         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2452         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2453         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2454         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2455         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2456         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2457         .flow_ops_get         = dpaa2_dev_flow_ops_get,
2458         .rxq_info_get         = dpaa2_rxq_info_get,
2459         .txq_info_get         = dpaa2_txq_info_get,
2460         .tm_ops_get           = dpaa2_tm_ops_get,
2461 #if defined(RTE_LIBRTE_IEEE1588)
2462         .timesync_enable      = dpaa2_timesync_enable,
2463         .timesync_disable     = dpaa2_timesync_disable,
2464         .timesync_read_time   = dpaa2_timesync_read_time,
2465         .timesync_write_time  = dpaa2_timesync_write_time,
2466         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2467         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2468         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2469 #endif
2470 };
2471
2472 /* Populate the mac address from physically available (u-boot/firmware) and/or
2473  * one set by higher layers like MC (restool) etc.
2474  * Returns the table of MAC entries (multiple entries)
2475  */
2476 static int
2477 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2478                   struct rte_ether_addr *mac_entry)
2479 {
2480         int ret;
2481         struct rte_ether_addr phy_mac, prime_mac;
2482
2483         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2484         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2485
2486         /* Get the physical device MAC address */
2487         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2488                                      phy_mac.addr_bytes);
2489         if (ret) {
2490                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2491                 goto cleanup;
2492         }
2493
2494         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2495                                         prime_mac.addr_bytes);
2496         if (ret) {
2497                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2498                 goto cleanup;
2499         }
2500
2501         /* Now that both MAC have been obtained, do:
2502          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2503          *     and return phy
2504          *  If empty_mac(phy), return prime.
2505          *  if both are empty, create random MAC, set as prime and return
2506          */
2507         if (!rte_is_zero_ether_addr(&phy_mac)) {
2508                 /* If the addresses are not same, overwrite prime */
2509                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2510                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2511                                                         priv->token,
2512                                                         phy_mac.addr_bytes);
2513                         if (ret) {
2514                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2515                                               ret);
2516                                 goto cleanup;
2517                         }
2518                         memcpy(&prime_mac, &phy_mac,
2519                                 sizeof(struct rte_ether_addr));
2520                 }
2521         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2522                 /* In case phys and prime, both are zero, create random MAC */
2523                 rte_eth_random_addr(prime_mac.addr_bytes);
2524                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2525                                                 priv->token,
2526                                                 prime_mac.addr_bytes);
2527                 if (ret) {
2528                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2529                         goto cleanup;
2530                 }
2531         }
2532
2533         /* prime_mac the final MAC address */
2534         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2535         return 0;
2536
2537 cleanup:
2538         return -1;
2539 }
2540
2541 static int
2542 check_devargs_handler(__rte_unused const char *key, const char *value,
2543                       __rte_unused void *opaque)
2544 {
2545         if (strcmp(value, "1"))
2546                 return -1;
2547
2548         return 0;
2549 }
2550
2551 static int
2552 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2553 {
2554         struct rte_kvargs *kvlist;
2555
2556         if (!devargs)
2557                 return 0;
2558
2559         kvlist = rte_kvargs_parse(devargs->args, NULL);
2560         if (!kvlist)
2561                 return 0;
2562
2563         if (!rte_kvargs_count(kvlist, key)) {
2564                 rte_kvargs_free(kvlist);
2565                 return 0;
2566         }
2567
2568         if (rte_kvargs_process(kvlist, key,
2569                                check_devargs_handler, NULL) < 0) {
2570                 rte_kvargs_free(kvlist);
2571                 return 0;
2572         }
2573         rte_kvargs_free(kvlist);
2574
2575         return 1;
2576 }
2577
2578 static int
2579 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2580 {
2581         struct rte_device *dev = eth_dev->device;
2582         struct rte_dpaa2_device *dpaa2_dev;
2583         struct fsl_mc_io *dpni_dev;
2584         struct dpni_attr attr;
2585         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2586         struct dpni_buffer_layout layout;
2587         int ret, hw_id, i;
2588
2589         PMD_INIT_FUNC_TRACE();
2590
2591         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2592         if (!dpni_dev) {
2593                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2594                 return -1;
2595         }
2596         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2597         eth_dev->process_private = (void *)dpni_dev;
2598
2599         /* For secondary processes, the primary has done all the work */
2600         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2601                 /* In case of secondary, only burst and ops API need to be
2602                  * plugged.
2603                  */
2604                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2605                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2606                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2607                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2608                 else if (dpaa2_get_devargs(dev->devargs,
2609                                         DRIVER_NO_PREFETCH_MODE))
2610                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2611                 else
2612                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2613                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2614                 return 0;
2615         }
2616
2617         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2618
2619         hw_id = dpaa2_dev->object_id;
2620         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2621         if (ret) {
2622                 DPAA2_PMD_ERR(
2623                              "Failure in opening dpni@%d with err code %d",
2624                              hw_id, ret);
2625                 rte_free(dpni_dev);
2626                 return -1;
2627         }
2628
2629         if (eth_dev->data->dev_conf.lpbk_mode)
2630                 dpaa2_dev_recycle_deconfig(eth_dev);
2631
2632         /* Clean the device first */
2633         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2634         if (ret) {
2635                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2636                               hw_id, ret);
2637                 goto init_err;
2638         }
2639
2640         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2641         if (ret) {
2642                 DPAA2_PMD_ERR(
2643                              "Failure in get dpni@%d attribute, err code %d",
2644                              hw_id, ret);
2645                 goto init_err;
2646         }
2647
2648         priv->num_rx_tc = attr.num_rx_tcs;
2649         priv->num_tx_tc = attr.num_tx_tcs;
2650         priv->qos_entries = attr.qos_entries;
2651         priv->fs_entries = attr.fs_entries;
2652         priv->dist_queues = attr.num_queues;
2653         priv->num_channels = attr.num_channels;
2654         priv->channel_inuse = 0;
2655         rte_spinlock_init(&priv->lpbk_qp_lock);
2656
2657         /* only if the custom CG is enabled */
2658         if (attr.options & DPNI_OPT_CUSTOM_CG)
2659                 priv->max_cgs = attr.num_cgs;
2660         else
2661                 priv->max_cgs = 0;
2662
2663         for (i = 0; i < priv->max_cgs; i++)
2664                 priv->cgid_in_use[i] = 0;
2665
2666         for (i = 0; i < attr.num_rx_tcs; i++)
2667                 priv->nb_rx_queues += attr.num_queues;
2668
2669         priv->nb_tx_queues = attr.num_tx_tcs * attr.num_channels;
2670
2671         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2672                         priv->num_rx_tc, priv->nb_rx_queues,
2673                         priv->nb_tx_queues, priv->max_cgs);
2674
2675         priv->hw = dpni_dev;
2676         priv->hw_id = hw_id;
2677         priv->options = attr.options;
2678         priv->max_mac_filters = attr.mac_filter_entries;
2679         priv->max_vlan_filters = attr.vlan_filter_entries;
2680         priv->flags = 0;
2681 #if defined(RTE_LIBRTE_IEEE1588)
2682         printf("DPDK IEEE1588 is enabled\n");
2683         priv->flags |= DPAA2_TX_CONF_ENABLE;
2684 #endif
2685         /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2686         if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2687                 priv->flags |= DPAA2_TX_CONF_ENABLE;
2688                 DPAA2_PMD_INFO("TX_CONF Enabled");
2689         }
2690
2691         if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2692                 dpaa2_enable_err_queue = 1;
2693                 DPAA2_PMD_INFO("Enable error queue");
2694         }
2695
2696         /* Allocate memory for hardware structure for queues */
2697         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2698         if (ret) {
2699                 DPAA2_PMD_ERR("Queue allocation Failed");
2700                 goto init_err;
2701         }
2702
2703         /* Allocate memory for storing MAC addresses.
2704          * Table of mac_filter_entries size is allocated so that RTE ether lib
2705          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2706          */
2707         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2708                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2709         if (eth_dev->data->mac_addrs == NULL) {
2710                 DPAA2_PMD_ERR(
2711                    "Failed to allocate %d bytes needed to store MAC addresses",
2712                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2713                 ret = -ENOMEM;
2714                 goto init_err;
2715         }
2716
2717         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2718         if (ret) {
2719                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2720                 rte_free(eth_dev->data->mac_addrs);
2721                 eth_dev->data->mac_addrs = NULL;
2722                 goto init_err;
2723         }
2724
2725         /* ... tx buffer layout ... */
2726         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2727         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2728                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2729                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2730                 layout.pass_timestamp = true;
2731         } else {
2732                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2733         }
2734         layout.pass_frame_status = 1;
2735         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2736                                      DPNI_QUEUE_TX, &layout);
2737         if (ret) {
2738                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2739                 goto init_err;
2740         }
2741
2742         /* ... tx-conf and error buffer layout ... */
2743         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2744         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2745                 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2746                 layout.pass_timestamp = true;
2747         }
2748         layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2749         layout.pass_frame_status = 1;
2750         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2751                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2752         if (ret) {
2753                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2754                              ret);
2755                 goto init_err;
2756         }
2757
2758         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2759
2760         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2761                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2762                 DPAA2_PMD_INFO("Loopback mode");
2763         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2764                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2765                 DPAA2_PMD_INFO("No Prefetch mode");
2766         } else {
2767                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2768         }
2769         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2770
2771         /* Init fields w.r.t. classification */
2772         memset(&priv->extract.qos_key_extract, 0,
2773                 sizeof(struct dpaa2_key_extract));
2774         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2775         if (!priv->extract.qos_extract_param) {
2776                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2777                             " classification ", ret);
2778                 goto init_err;
2779         }
2780         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2781                 IP_ADDRESS_OFFSET_INVALID;
2782         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2783                 IP_ADDRESS_OFFSET_INVALID;
2784         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2785                 IP_ADDRESS_OFFSET_INVALID;
2786         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2787                 IP_ADDRESS_OFFSET_INVALID;
2788
2789         for (i = 0; i < MAX_TCS; i++) {
2790                 memset(&priv->extract.tc_key_extract[i], 0,
2791                         sizeof(struct dpaa2_key_extract));
2792                 priv->extract.tc_extract_param[i] =
2793                         (size_t)rte_malloc(NULL, 256, 64);
2794                 if (!priv->extract.tc_extract_param[i]) {
2795                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classification",
2796                                      ret);
2797                         goto init_err;
2798                 }
2799                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2800                         IP_ADDRESS_OFFSET_INVALID;
2801                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2802                         IP_ADDRESS_OFFSET_INVALID;
2803                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2804                         IP_ADDRESS_OFFSET_INVALID;
2805                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2806                         IP_ADDRESS_OFFSET_INVALID;
2807         }
2808
2809         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2810                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2811                                         + VLAN_TAG_SIZE);
2812         if (ret) {
2813                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2814                 goto init_err;
2815         }
2816
2817         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2818          * with external entity to receive byte code for software sequence
2819          * and same will be offload to the H/W using MC interface.
2820          * Currently it is assumed that DPAA2 driver has byte code by some
2821          * mean and same if offloaded to H/W.
2822          */
2823         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2824                 WRIOP_SS_INITIALIZER(priv);
2825                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2826                 if (ret < 0) {
2827                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2828                                       ret);
2829                         return ret;
2830                 }
2831
2832                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2833                                                          DPNI_SS_INGRESS);
2834                 if (ret < 0) {
2835                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2836                                       ret);
2837                         return ret;
2838                 }
2839         }
2840         RTE_LOG(INFO, PMD, "%s: netdev created, connected to %s\n",
2841                 eth_dev->data->name, dpaa2_dev->ep_name);
2842
2843         return 0;
2844 init_err:
2845         dpaa2_dev_close(eth_dev);
2846
2847         return ret;
2848 }
2849
2850 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2851 {
2852         return dev->device->driver == &rte_dpaa2_pmd.driver;
2853 }
2854
2855 static int
2856 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2857                 struct rte_dpaa2_device *dpaa2_dev)
2858 {
2859         struct rte_eth_dev *eth_dev;
2860         struct dpaa2_dev_priv *dev_priv;
2861         int diag;
2862
2863         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2864                 RTE_PKTMBUF_HEADROOM) {
2865                 DPAA2_PMD_ERR(
2866                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2867                 RTE_PKTMBUF_HEADROOM,
2868                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2869
2870                 return -1;
2871         }
2872
2873         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2874                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2875                 if (!eth_dev)
2876                         return -ENODEV;
2877                 dev_priv = rte_zmalloc("ethdev private structure",
2878                                        sizeof(struct dpaa2_dev_priv),
2879                                        RTE_CACHE_LINE_SIZE);
2880                 if (dev_priv == NULL) {
2881                         DPAA2_PMD_CRIT(
2882                                 "Unable to allocate memory for private data");
2883                         rte_eth_dev_release_port(eth_dev);
2884                         return -ENOMEM;
2885                 }
2886                 eth_dev->data->dev_private = (void *)dev_priv;
2887                 /* Store a pointer to eth_dev in dev_private */
2888                 dev_priv->eth_dev = eth_dev;
2889         } else {
2890                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2891                 if (!eth_dev) {
2892                         DPAA2_PMD_DEBUG("returning enodev");
2893                         return -ENODEV;
2894                 }
2895         }
2896
2897         eth_dev->device = &dpaa2_dev->device;
2898
2899         dpaa2_dev->eth_dev = eth_dev;
2900         eth_dev->data->rx_mbuf_alloc_failed = 0;
2901
2902         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2903                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2904
2905         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2906
2907         /* Invoke PMD device initialization function */
2908         diag = dpaa2_dev_init(eth_dev);
2909         if (diag == 0) {
2910                 rte_eth_dev_probing_finish(eth_dev);
2911                 return 0;
2912         }
2913
2914         rte_eth_dev_release_port(eth_dev);
2915         return diag;
2916 }
2917
2918 static int
2919 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2920 {
2921         struct rte_eth_dev *eth_dev;
2922         int ret;
2923
2924         eth_dev = dpaa2_dev->eth_dev;
2925         dpaa2_dev_close(eth_dev);
2926         ret = rte_eth_dev_release_port(eth_dev);
2927
2928         return ret;
2929 }
2930
2931 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2932         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2933         .drv_type = DPAA2_ETH,
2934         .probe = rte_dpaa2_probe,
2935         .remove = rte_dpaa2_remove,
2936 };
2937
2938 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2939 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2940                 DRIVER_LOOPBACK_MODE "=<int> "
2941                 DRIVER_NO_PREFETCH_MODE "=<int>"
2942                 DRIVER_TX_CONF "=<int>"
2943                 DRIVER_ERROR_QUEUE "=<int>");
2944 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);