1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2021 NXP
12 #include <ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
34 #define DRIVER_TX_CONF "drv_tx_conf"
35 #define DRIVER_ERROR_QUEUE "drv_err_queue"
36 #define CHECK_INTERVAL 100 /* 100ms */
37 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
39 /* Supported Rx offloads */
40 static uint64_t dev_rx_offloads_sup =
41 DEV_RX_OFFLOAD_CHECKSUM |
42 DEV_RX_OFFLOAD_SCTP_CKSUM |
43 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
44 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
45 DEV_RX_OFFLOAD_VLAN_STRIP |
46 DEV_RX_OFFLOAD_VLAN_FILTER |
47 DEV_RX_OFFLOAD_JUMBO_FRAME |
48 DEV_RX_OFFLOAD_TIMESTAMP;
50 /* Rx offloads which cannot be disabled */
51 static uint64_t dev_rx_offloads_nodis =
52 DEV_RX_OFFLOAD_RSS_HASH |
53 DEV_RX_OFFLOAD_SCATTER;
55 /* Supported Tx offloads */
56 static uint64_t dev_tx_offloads_sup =
57 DEV_TX_OFFLOAD_VLAN_INSERT |
58 DEV_TX_OFFLOAD_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_UDP_CKSUM |
60 DEV_TX_OFFLOAD_TCP_CKSUM |
61 DEV_TX_OFFLOAD_SCTP_CKSUM |
62 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
63 DEV_TX_OFFLOAD_MT_LOCKFREE |
64 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
66 /* Tx offloads which cannot be disabled */
67 static uint64_t dev_tx_offloads_nodis =
68 DEV_TX_OFFLOAD_MULTI_SEGS;
70 /* enable timestamp in mbuf */
71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
72 uint64_t dpaa2_timestamp_rx_dynflag;
73 int dpaa2_timestamp_dynfield_offset = -1;
75 /* Enable error queue */
76 bool dpaa2_enable_err_queue;
78 struct rte_dpaa2_xstats_name_off {
79 char name[RTE_ETH_XSTATS_NAME_SIZE];
80 uint8_t page_id; /* dpni statistics page id */
81 uint8_t stats_id; /* stats id in the given page */
84 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
85 {"ingress_multicast_frames", 0, 2},
86 {"ingress_multicast_bytes", 0, 3},
87 {"ingress_broadcast_frames", 0, 4},
88 {"ingress_broadcast_bytes", 0, 5},
89 {"egress_multicast_frames", 1, 2},
90 {"egress_multicast_bytes", 1, 3},
91 {"egress_broadcast_frames", 1, 4},
92 {"egress_broadcast_bytes", 1, 5},
93 {"ingress_filtered_frames", 2, 0},
94 {"ingress_discarded_frames", 2, 1},
95 {"ingress_nobuffer_discards", 2, 2},
96 {"egress_discarded_frames", 2, 3},
97 {"egress_confirmed_frames", 2, 4},
98 {"cgr_reject_frames", 4, 0},
99 {"cgr_reject_bytes", 4, 1},
102 static struct rte_dpaa2_driver rte_dpaa2_pmd;
103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
104 int wait_to_complete);
105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
113 struct dpaa2_dev_priv *priv = dev->data->dev_private;
114 struct fsl_mc_io *dpni = dev->process_private;
116 PMD_INIT_FUNC_TRACE();
119 DPAA2_PMD_ERR("dpni is NULL");
124 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
127 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
128 priv->token, vlan_id);
131 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
132 ret, vlan_id, priv->hw_id);
138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
140 struct dpaa2_dev_priv *priv = dev->data->dev_private;
141 struct fsl_mc_io *dpni = dev->process_private;
144 PMD_INIT_FUNC_TRACE();
146 if (mask & ETH_VLAN_FILTER_MASK) {
147 /* VLAN Filter not avaialble */
148 if (!priv->max_vlan_filters) {
149 DPAA2_PMD_INFO("VLAN filter not available");
153 if (dev->data->dev_conf.rxmode.offloads &
154 DEV_RX_OFFLOAD_VLAN_FILTER)
155 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
158 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
161 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
169 enum rte_vlan_type vlan_type __rte_unused,
172 struct dpaa2_dev_priv *priv = dev->data->dev_private;
173 struct fsl_mc_io *dpni = dev->process_private;
176 PMD_INIT_FUNC_TRACE();
178 /* nothing to be done for standard vlan tpids */
179 if (tpid == 0x8100 || tpid == 0x88A8)
182 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
185 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
186 /* if already configured tpids, remove them first */
188 struct dpni_custom_tpid_cfg tpid_list = {0};
190 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
191 priv->token, &tpid_list);
194 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
195 priv->token, tpid_list.tpid1);
198 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
206 dpaa2_fw_version_get(struct rte_eth_dev *dev,
211 struct fsl_mc_io *dpni = dev->process_private;
212 struct mc_soc_version mc_plat_info = {0};
213 struct mc_version mc_ver_info = {0};
215 PMD_INIT_FUNC_TRACE();
217 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
218 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
220 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
221 DPAA2_PMD_WARN("\tmc_get_version failed");
223 ret = snprintf(fw_version, fw_size,
228 mc_ver_info.revision);
230 ret += 1; /* add the size of '\0' */
231 if (fw_size < (uint32_t)ret)
238 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
240 struct dpaa2_dev_priv *priv = dev->data->dev_private;
242 PMD_INIT_FUNC_TRACE();
244 dev_info->max_mac_addrs = priv->max_mac_filters;
245 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
246 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
247 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
248 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
249 dev_info->rx_offload_capa = dev_rx_offloads_sup |
250 dev_rx_offloads_nodis;
251 dev_info->tx_offload_capa = dev_tx_offloads_sup |
252 dev_tx_offloads_nodis;
253 dev_info->speed_capa = ETH_LINK_SPEED_1G |
254 ETH_LINK_SPEED_2_5G |
257 dev_info->max_hash_mac_addrs = 0;
258 dev_info->max_vfs = 0;
259 dev_info->max_vmdq_pools = ETH_16_POOLS;
260 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
262 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
263 /* same is rx size for best perf */
264 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
266 dev_info->default_rxportconf.nb_queues = 1;
267 dev_info->default_txportconf.nb_queues = 1;
268 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
269 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
271 if (dpaa2_svr_family == SVR_LX2160A) {
272 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
282 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
283 __rte_unused uint16_t queue_id,
284 struct rte_eth_burst_mode *mode)
286 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
289 const struct burst_info {
292 } rx_offload_map[] = {
293 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
294 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
295 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
296 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
297 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
298 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
299 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
300 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
301 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
302 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
305 /* Update Rx offload info */
306 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
307 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
308 snprintf(mode->info, sizeof(mode->info), "%s",
309 rx_offload_map[i].output);
318 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
319 __rte_unused uint16_t queue_id,
320 struct rte_eth_burst_mode *mode)
322 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
325 const struct burst_info {
328 } tx_offload_map[] = {
329 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
330 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
331 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
332 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
333 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
334 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
335 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
336 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
337 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
340 /* Update Tx offload info */
341 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
342 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
343 snprintf(mode->info, sizeof(mode->info), "%s",
344 tx_offload_map[i].output);
353 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
355 struct dpaa2_dev_priv *priv = dev->data->dev_private;
358 uint8_t num_rxqueue_per_tc;
359 struct dpaa2_queue *mc_q, *mcq;
362 struct dpaa2_queue *dpaa2_q;
364 PMD_INIT_FUNC_TRACE();
366 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
367 if (priv->flags & DPAA2_TX_CONF_ENABLE)
368 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
370 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
371 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
372 RTE_CACHE_LINE_SIZE);
374 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
378 for (i = 0; i < priv->nb_rx_queues; i++) {
379 mc_q->eth_data = dev->data;
380 priv->rx_vq[i] = mc_q++;
381 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
382 dpaa2_q->q_storage = rte_malloc("dq_storage",
383 sizeof(struct queue_storage_info_t),
384 RTE_CACHE_LINE_SIZE);
385 if (!dpaa2_q->q_storage)
388 memset(dpaa2_q->q_storage, 0,
389 sizeof(struct queue_storage_info_t));
390 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
394 if (dpaa2_enable_err_queue) {
395 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
396 sizeof(struct dpaa2_queue), 0);
398 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
399 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
400 sizeof(struct queue_storage_info_t) *
402 RTE_CACHE_LINE_SIZE);
403 if (!dpaa2_q->q_storage)
406 memset(dpaa2_q->q_storage, 0,
407 sizeof(struct queue_storage_info_t));
408 for (i = 0; i < RTE_MAX_LCORE; i++)
409 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
413 for (i = 0; i < priv->nb_tx_queues; i++) {
414 mc_q->eth_data = dev->data;
415 mc_q->flow_id = 0xffff;
416 priv->tx_vq[i] = mc_q++;
417 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
418 dpaa2_q->cscn = rte_malloc(NULL,
419 sizeof(struct qbman_result), 16);
424 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
425 /*Setup tx confirmation queues*/
426 for (i = 0; i < priv->nb_tx_queues; i++) {
427 mc_q->eth_data = dev->data;
430 priv->tx_conf_vq[i] = mc_q++;
431 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
433 rte_malloc("dq_storage",
434 sizeof(struct queue_storage_info_t),
435 RTE_CACHE_LINE_SIZE);
436 if (!dpaa2_q->q_storage)
439 memset(dpaa2_q->q_storage, 0,
440 sizeof(struct queue_storage_info_t));
441 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
447 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
448 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
449 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
450 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
458 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
459 rte_free(dpaa2_q->q_storage);
460 priv->tx_conf_vq[i--] = NULL;
462 i = priv->nb_tx_queues;
466 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
467 rte_free(dpaa2_q->cscn);
468 priv->tx_vq[i--] = NULL;
470 i = priv->nb_rx_queues;
473 mc_q = priv->rx_vq[0];
475 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
476 dpaa2_free_dq_storage(dpaa2_q->q_storage);
477 rte_free(dpaa2_q->q_storage);
478 priv->rx_vq[i--] = NULL;
481 if (dpaa2_enable_err_queue) {
482 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
483 if (dpaa2_q->q_storage)
484 dpaa2_free_dq_storage(dpaa2_q->q_storage);
485 rte_free(dpaa2_q->q_storage);
493 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
495 struct dpaa2_dev_priv *priv = dev->data->dev_private;
496 struct dpaa2_queue *dpaa2_q;
499 PMD_INIT_FUNC_TRACE();
501 /* Queue allocation base */
502 if (priv->rx_vq[0]) {
503 /* cleaning up queue storage */
504 for (i = 0; i < priv->nb_rx_queues; i++) {
505 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
506 if (dpaa2_q->q_storage)
507 rte_free(dpaa2_q->q_storage);
509 /* cleanup tx queue cscn */
510 for (i = 0; i < priv->nb_tx_queues; i++) {
511 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
512 rte_free(dpaa2_q->cscn);
514 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
515 /* cleanup tx conf queue storage */
516 for (i = 0; i < priv->nb_tx_queues; i++) {
517 dpaa2_q = (struct dpaa2_queue *)
519 rte_free(dpaa2_q->q_storage);
522 /*free memory for all queues (RX+TX) */
523 rte_free(priv->rx_vq[0]);
524 priv->rx_vq[0] = NULL;
529 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
531 struct dpaa2_dev_priv *priv = dev->data->dev_private;
532 struct fsl_mc_io *dpni = dev->process_private;
533 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
534 uint64_t rx_offloads = eth_conf->rxmode.offloads;
535 uint64_t tx_offloads = eth_conf->txmode.offloads;
536 int rx_l3_csum_offload = false;
537 int rx_l4_csum_offload = false;
538 int tx_l3_csum_offload = false;
539 int tx_l4_csum_offload = false;
542 PMD_INIT_FUNC_TRACE();
544 /* Rx offloads which are enabled by default */
545 if (dev_rx_offloads_nodis & ~rx_offloads) {
547 "Some of rx offloads enabled by default - requested 0x%" PRIx64
548 " fixed are 0x%" PRIx64,
549 rx_offloads, dev_rx_offloads_nodis);
552 /* Tx offloads which are enabled by default */
553 if (dev_tx_offloads_nodis & ~tx_offloads) {
555 "Some of tx offloads enabled by default - requested 0x%" PRIx64
556 " fixed are 0x%" PRIx64,
557 tx_offloads, dev_tx_offloads_nodis);
560 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
561 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
562 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
563 priv->token, eth_conf->rxmode.max_rx_pkt_len
564 - RTE_ETHER_CRC_LEN);
567 "Unable to set mtu. check config");
571 dev->data->dev_conf.rxmode.max_rx_pkt_len -
572 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
579 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
580 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
581 ret = dpaa2_setup_flow_dist(dev,
582 eth_conf->rx_adv_conf.rss_conf.rss_hf,
586 "Unable to set flow distribution on tc%d."
587 "Check queue config", tc_index);
593 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
594 rx_l3_csum_offload = true;
596 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
597 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
598 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
599 rx_l4_csum_offload = true;
601 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
602 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
604 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
608 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
609 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
611 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
615 #if !defined(RTE_LIBRTE_IEEE1588)
616 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
619 ret = rte_mbuf_dyn_rx_timestamp_register(
620 &dpaa2_timestamp_dynfield_offset,
621 &dpaa2_timestamp_rx_dynflag);
623 DPAA2_PMD_ERR("Error to register timestamp field/flag");
626 dpaa2_enable_ts[dev->data->port_id] = true;
629 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
630 tx_l3_csum_offload = true;
632 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
633 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
634 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
635 tx_l4_csum_offload = true;
637 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
638 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
640 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
644 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
645 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
647 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
651 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
652 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
653 * to 0 for LS2 in the hardware thus disabling data/annotation
654 * stashing. For LX2 this is fixed in hardware and thus hash result and
655 * parse results can be received in FD using this option.
657 if (dpaa2_svr_family == SVR_LX2160A) {
658 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
659 DPNI_FLCTYPE_HASH, true);
661 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
666 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
667 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
674 /* Function to setup RX flow information. It contains traffic class ID,
675 * flow ID, destination configuration etc.
678 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
679 uint16_t rx_queue_id,
681 unsigned int socket_id __rte_unused,
682 const struct rte_eth_rxconf *rx_conf,
683 struct rte_mempool *mb_pool)
685 struct dpaa2_dev_priv *priv = dev->data->dev_private;
686 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
687 struct dpaa2_queue *dpaa2_q;
688 struct dpni_queue cfg;
694 PMD_INIT_FUNC_TRACE();
696 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
697 dev, rx_queue_id, mb_pool, rx_conf);
699 /* Rx deferred start is not supported */
700 if (rx_conf->rx_deferred_start) {
701 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
706 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
707 bpid = mempool_to_bpid(mb_pool);
708 ret = dpaa2_attach_bp_list(priv,
709 rte_dpaa2_bpid_info[bpid].bp_list);
713 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
714 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
715 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
716 dpaa2_q->nb_desc = UINT16_MAX;
717 dpaa2_q->offloads = rx_conf->offloads;
719 /*Get the flow id from given VQ id*/
720 flow_id = dpaa2_q->flow_id;
721 memset(&cfg, 0, sizeof(struct dpni_queue));
723 options = options | DPNI_QUEUE_OPT_USER_CTX;
724 cfg.user_context = (size_t)(dpaa2_q);
726 /* check if a private cgr available. */
727 for (i = 0; i < priv->max_cgs; i++) {
728 if (!priv->cgid_in_use[i]) {
729 priv->cgid_in_use[i] = 1;
734 if (i < priv->max_cgs) {
735 options |= DPNI_QUEUE_OPT_SET_CGID;
737 dpaa2_q->cgid = cfg.cgid;
739 dpaa2_q->cgid = 0xff;
742 /*if ls2088 or rev2 device, enable the stashing */
744 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
745 options |= DPNI_QUEUE_OPT_FLC;
746 cfg.flc.stash_control = true;
747 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
748 /* 00 00 00 - last 6 bit represent annotation, context stashing,
749 * data stashing setting 01 01 00 (0x14)
750 * (in following order ->DS AS CS)
751 * to enable 1 line data, 1 line annotation.
752 * For LX2, this setting should be 01 00 00 (0x10)
754 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
755 cfg.flc.value |= 0x10;
757 cfg.flc.value |= 0x14;
759 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
760 dpaa2_q->tc_index, flow_id, options, &cfg);
762 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
766 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
767 struct dpni_taildrop taildrop;
770 dpaa2_q->nb_desc = nb_rx_desc;
771 /* Private CGR will use tail drop length as nb_rx_desc.
772 * for rest cases we can use standard byte based tail drop.
773 * There is no HW restriction, but number of CGRs are limited,
774 * hence this restriction is placed.
776 if (dpaa2_q->cgid != 0xff) {
777 /*enabling per rx queue congestion control */
778 taildrop.threshold = nb_rx_desc;
779 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
781 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
783 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
784 DPNI_CP_CONGESTION_GROUP,
787 dpaa2_q->cgid, &taildrop);
789 /*enabling per rx queue congestion control */
790 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
791 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
792 taildrop.oal = CONG_RX_OAL;
793 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
795 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
796 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
797 dpaa2_q->tc_index, flow_id,
801 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
805 } else { /* Disable tail Drop */
806 struct dpni_taildrop taildrop = {0};
807 DPAA2_PMD_INFO("Tail drop is disabled on queue");
810 if (dpaa2_q->cgid != 0xff) {
811 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
812 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
814 dpaa2_q->cgid, &taildrop);
816 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
817 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
818 dpaa2_q->tc_index, flow_id, &taildrop);
821 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
827 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
832 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
833 uint16_t tx_queue_id,
835 unsigned int socket_id __rte_unused,
836 const struct rte_eth_txconf *tx_conf)
838 struct dpaa2_dev_priv *priv = dev->data->dev_private;
839 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
840 priv->tx_vq[tx_queue_id];
841 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
842 priv->tx_conf_vq[tx_queue_id];
843 struct fsl_mc_io *dpni = dev->process_private;
844 struct dpni_queue tx_conf_cfg;
845 struct dpni_queue tx_flow_cfg;
846 uint8_t options = 0, flow_id;
847 struct dpni_queue_id qid;
851 PMD_INIT_FUNC_TRACE();
853 /* Tx deferred start is not supported */
854 if (tx_conf->tx_deferred_start) {
855 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
860 dpaa2_q->nb_desc = UINT16_MAX;
861 dpaa2_q->offloads = tx_conf->offloads;
863 /* Return if queue already configured */
864 if (dpaa2_q->flow_id != 0xffff) {
865 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
869 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
870 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
875 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
876 tc_id, flow_id, options, &tx_flow_cfg);
878 DPAA2_PMD_ERR("Error in setting the tx flow: "
879 "tc_id=%d, flow=%d err=%d",
880 tc_id, flow_id, ret);
884 dpaa2_q->flow_id = flow_id;
886 if (tx_queue_id == 0) {
887 /*Set tx-conf and error configuration*/
888 if (priv->flags & DPAA2_TX_CONF_ENABLE)
889 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
893 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
897 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
902 dpaa2_q->tc_index = tc_id;
904 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
905 DPNI_QUEUE_TX, dpaa2_q->tc_index,
906 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
908 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
911 dpaa2_q->fqid = qid.fqid;
913 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
914 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
916 dpaa2_q->nb_desc = nb_tx_desc;
918 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
919 cong_notif_cfg.threshold_entry = nb_tx_desc;
920 /* Notify that the queue is not congested when the data in
921 * the queue is below this thershold.(90% of value)
923 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
924 cong_notif_cfg.message_ctx = 0;
925 cong_notif_cfg.message_iova =
926 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
927 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
928 cong_notif_cfg.notification_mode =
929 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
930 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
931 DPNI_CONG_OPT_COHERENT_WRITE;
932 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
934 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
941 "Error in setting tx congestion notification: "
946 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
947 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
949 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
950 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
951 options = options | DPNI_QUEUE_OPT_USER_CTX;
952 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
953 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
954 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
955 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
957 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
958 "tc_index=%d, flow=%d err=%d",
959 dpaa2_tx_conf_q->tc_index,
960 dpaa2_tx_conf_q->flow_id, ret);
964 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
965 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
966 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
968 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
971 dpaa2_tx_conf_q->fqid = qid.fqid;
977 dpaa2_dev_rx_queue_release(void *q __rte_unused)
979 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
980 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
981 struct fsl_mc_io *dpni =
982 (struct fsl_mc_io *)priv->eth_dev->process_private;
985 struct dpni_queue cfg;
987 memset(&cfg, 0, sizeof(struct dpni_queue));
988 PMD_INIT_FUNC_TRACE();
989 if (dpaa2_q->cgid != 0xff) {
990 options = DPNI_QUEUE_OPT_CLEAR_CGID;
991 cfg.cgid = dpaa2_q->cgid;
993 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
995 dpaa2_q->tc_index, dpaa2_q->flow_id,
998 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1000 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1001 dpaa2_q->cgid = 0xff;
1006 dpaa2_dev_tx_queue_release(void *q __rte_unused)
1008 PMD_INIT_FUNC_TRACE();
1012 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1015 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1016 struct dpaa2_queue *dpaa2_q;
1017 struct qbman_swp *swp;
1018 struct qbman_fq_query_np_rslt state;
1019 uint32_t frame_cnt = 0;
1021 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1022 ret = dpaa2_affine_qbman_swp();
1025 "Failed to allocate IO portal, tid: %d\n",
1030 swp = DPAA2_PER_LCORE_PORTAL;
1032 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
1034 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1035 frame_cnt = qbman_fq_state_frame_count(&state);
1036 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
1037 rx_queue_id, frame_cnt);
1042 static const uint32_t *
1043 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1045 static const uint32_t ptypes[] = {
1046 /*todo -= add more types */
1049 RTE_PTYPE_L3_IPV4_EXT,
1051 RTE_PTYPE_L3_IPV6_EXT,
1059 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1060 dev->rx_pkt_burst == dpaa2_dev_rx ||
1061 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1067 * Dpaa2 link Interrupt handler
1070 * The address of parameter (struct rte_eth_dev *) regsitered before.
1076 dpaa2_interrupt_handler(void *param)
1078 struct rte_eth_dev *dev = param;
1079 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1080 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1082 int irq_index = DPNI_IRQ_INDEX;
1083 unsigned int status = 0, clear = 0;
1085 PMD_INIT_FUNC_TRACE();
1088 DPAA2_PMD_ERR("dpni is NULL");
1092 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1093 irq_index, &status);
1094 if (unlikely(ret)) {
1095 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1100 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1101 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1102 dpaa2_dev_link_update(dev, 0);
1103 /* calling all the apps registered for link status event */
1104 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1107 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1110 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1114 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1117 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1118 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1119 int irq_index = DPNI_IRQ_INDEX;
1120 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1122 PMD_INIT_FUNC_TRACE();
1124 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1127 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1132 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1135 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1142 dpaa2_dev_start(struct rte_eth_dev *dev)
1144 struct rte_device *rdev = dev->device;
1145 struct rte_dpaa2_device *dpaa2_dev;
1146 struct rte_eth_dev_data *data = dev->data;
1147 struct dpaa2_dev_priv *priv = data->dev_private;
1148 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1149 struct dpni_queue cfg;
1150 struct dpni_error_cfg err_cfg;
1152 struct dpni_queue_id qid;
1153 struct dpaa2_queue *dpaa2_q;
1155 struct rte_intr_handle *intr_handle;
1157 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1158 intr_handle = &dpaa2_dev->intr_handle;
1160 PMD_INIT_FUNC_TRACE();
1162 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1164 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1169 /* Power up the phy. Needed to make the link go UP */
1170 dpaa2_dev_set_link_up(dev);
1172 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1173 DPNI_QUEUE_TX, &qdid);
1175 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1180 for (i = 0; i < data->nb_rx_queues; i++) {
1181 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1182 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1183 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1184 dpaa2_q->flow_id, &cfg, &qid);
1186 DPAA2_PMD_ERR("Error in getting flow information: "
1190 dpaa2_q->fqid = qid.fqid;
1193 if (dpaa2_enable_err_queue) {
1194 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1195 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1197 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1201 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1202 dpaa2_q->fqid = qid.fqid;
1203 dpaa2_q->eth_data = dev->data;
1205 err_cfg.errors = DPNI_ERROR_DISC;
1206 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1208 /* checksum errors, send them to normal path
1209 * and set it in annotation
1211 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1213 /* if packet with parse error are not to be dropped */
1214 err_cfg.errors |= DPNI_ERROR_PHE;
1216 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1218 err_cfg.set_frame_annotation = true;
1220 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1221 priv->token, &err_cfg);
1223 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1228 /* if the interrupts were configured on this devices*/
1229 if (intr_handle && (intr_handle->fd) &&
1230 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1231 /* Registering LSC interrupt handler */
1232 rte_intr_callback_register(intr_handle,
1233 dpaa2_interrupt_handler,
1236 /* enable vfio intr/eventfd mapping
1237 * Interrupt index 0 is required, so we can not use
1240 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1242 /* enable dpni_irqs */
1243 dpaa2_eth_setup_irqs(dev, 1);
1246 /* Change the tx burst function if ordered queues are used */
1247 if (priv->en_ordered)
1248 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1254 * This routine disables all traffic on the adapter by issuing a
1255 * global reset on the MAC.
1258 dpaa2_dev_stop(struct rte_eth_dev *dev)
1260 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1261 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1263 struct rte_eth_link link;
1264 struct rte_intr_handle *intr_handle = dev->intr_handle;
1266 PMD_INIT_FUNC_TRACE();
1268 /* reset interrupt callback */
1269 if (intr_handle && (intr_handle->fd) &&
1270 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1271 /*disable dpni irqs */
1272 dpaa2_eth_setup_irqs(dev, 0);
1274 /* disable vfio intr before callback unregister */
1275 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1277 /* Unregistering LSC interrupt handler */
1278 rte_intr_callback_unregister(intr_handle,
1279 dpaa2_interrupt_handler,
1283 dpaa2_dev_set_link_down(dev);
1285 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1287 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1292 /* clear the recorded link status */
1293 memset(&link, 0, sizeof(link));
1294 rte_eth_linkstatus_set(dev, &link);
1300 dpaa2_dev_close(struct rte_eth_dev *dev)
1302 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1303 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1305 struct rte_eth_link link;
1307 PMD_INIT_FUNC_TRACE();
1309 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1313 DPAA2_PMD_WARN("Already closed or not started");
1317 dpaa2_tm_deinit(dev);
1318 dpaa2_flow_clean(dev);
1319 /* Clean the device first */
1320 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1322 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1326 memset(&link, 0, sizeof(link));
1327 rte_eth_linkstatus_set(dev, &link);
1329 /* Free private queues memory */
1330 dpaa2_free_rx_tx_queues(dev);
1331 /* Close the device at underlying layer*/
1332 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1334 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1338 /* Free the allocated memory for ethernet private data and dpni*/
1340 dev->process_private = NULL;
1343 for (i = 0; i < MAX_TCS; i++)
1344 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1346 if (priv->extract.qos_extract_param)
1347 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1349 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1354 dpaa2_dev_promiscuous_enable(
1355 struct rte_eth_dev *dev)
1358 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1359 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1361 PMD_INIT_FUNC_TRACE();
1364 DPAA2_PMD_ERR("dpni is NULL");
1368 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1370 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1372 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1374 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1380 dpaa2_dev_promiscuous_disable(
1381 struct rte_eth_dev *dev)
1384 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1385 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1387 PMD_INIT_FUNC_TRACE();
1390 DPAA2_PMD_ERR("dpni is NULL");
1394 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1396 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1398 if (dev->data->all_multicast == 0) {
1399 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1400 priv->token, false);
1402 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1410 dpaa2_dev_allmulticast_enable(
1411 struct rte_eth_dev *dev)
1414 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1415 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1417 PMD_INIT_FUNC_TRACE();
1420 DPAA2_PMD_ERR("dpni is NULL");
1424 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1426 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1432 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1435 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1436 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1438 PMD_INIT_FUNC_TRACE();
1441 DPAA2_PMD_ERR("dpni is NULL");
1445 /* must remain on for all promiscuous */
1446 if (dev->data->promiscuous == 1)
1449 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1451 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1457 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1460 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1461 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1462 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1465 PMD_INIT_FUNC_TRACE();
1468 DPAA2_PMD_ERR("dpni is NULL");
1472 /* check that mtu is within the allowed range */
1473 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1476 if (frame_size > DPAA2_ETH_MAX_LEN)
1477 dev->data->dev_conf.rxmode.offloads |=
1478 DEV_RX_OFFLOAD_JUMBO_FRAME;
1480 dev->data->dev_conf.rxmode.offloads &=
1481 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1483 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1485 /* Set the Max Rx frame length as 'mtu' +
1486 * Maximum Ethernet header length
1488 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1489 frame_size - RTE_ETHER_CRC_LEN);
1491 DPAA2_PMD_ERR("Setting the max frame length failed");
1494 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1499 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1500 struct rte_ether_addr *addr,
1501 __rte_unused uint32_t index,
1502 __rte_unused uint32_t pool)
1505 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1506 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1508 PMD_INIT_FUNC_TRACE();
1511 DPAA2_PMD_ERR("dpni is NULL");
1515 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1516 addr->addr_bytes, 0, 0, 0);
1519 "error: Adding the MAC ADDR failed: err = %d", ret);
1524 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1528 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1529 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1530 struct rte_eth_dev_data *data = dev->data;
1531 struct rte_ether_addr *macaddr;
1533 PMD_INIT_FUNC_TRACE();
1535 macaddr = &data->mac_addrs[index];
1538 DPAA2_PMD_ERR("dpni is NULL");
1542 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1543 priv->token, macaddr->addr_bytes);
1546 "error: Removing the MAC ADDR failed: err = %d", ret);
1550 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1551 struct rte_ether_addr *addr)
1554 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1555 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1557 PMD_INIT_FUNC_TRACE();
1560 DPAA2_PMD_ERR("dpni is NULL");
1564 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1565 priv->token, addr->addr_bytes);
1569 "error: Setting the MAC ADDR failed %d", ret);
1575 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1576 struct rte_eth_stats *stats)
1578 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1579 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1581 uint8_t page0 = 0, page1 = 1, page2 = 2;
1582 union dpni_statistics value;
1584 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1586 memset(&value, 0, sizeof(union dpni_statistics));
1588 PMD_INIT_FUNC_TRACE();
1591 DPAA2_PMD_ERR("dpni is NULL");
1596 DPAA2_PMD_ERR("stats is NULL");
1600 /*Get Counters from page_0*/
1601 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1606 stats->ipackets = value.page_0.ingress_all_frames;
1607 stats->ibytes = value.page_0.ingress_all_bytes;
1609 /*Get Counters from page_1*/
1610 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1615 stats->opackets = value.page_1.egress_all_frames;
1616 stats->obytes = value.page_1.egress_all_bytes;
1618 /*Get Counters from page_2*/
1619 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1624 /* Ingress drop frame count due to configured rules */
1625 stats->ierrors = value.page_2.ingress_filtered_frames;
1626 /* Ingress drop frame count due to error */
1627 stats->ierrors += value.page_2.ingress_discarded_frames;
1629 stats->oerrors = value.page_2.egress_discarded_frames;
1630 stats->imissed = value.page_2.ingress_nobuffer_discards;
1632 /* Fill in per queue stats */
1633 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1634 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1635 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1636 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1638 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1640 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1642 /* Byte counting is not implemented */
1643 stats->q_ibytes[i] = 0;
1644 stats->q_obytes[i] = 0;
1650 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1655 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1658 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1659 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1661 union dpni_statistics value[5] = {};
1662 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1670 /* Get Counters from page_0*/
1671 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1676 /* Get Counters from page_1*/
1677 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1682 /* Get Counters from page_2*/
1683 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1688 for (i = 0; i < priv->max_cgs; i++) {
1689 if (!priv->cgid_in_use[i]) {
1690 /* Get Counters from page_4*/
1691 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1700 for (i = 0; i < num; i++) {
1702 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1703 raw.counter[dpaa2_xstats_strings[i].stats_id];
1707 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1712 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1713 struct rte_eth_xstat_name *xstats_names,
1716 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1718 if (limit < stat_cnt)
1721 if (xstats_names != NULL)
1722 for (i = 0; i < stat_cnt; i++)
1723 strlcpy(xstats_names[i].name,
1724 dpaa2_xstats_strings[i].name,
1725 sizeof(xstats_names[i].name));
1731 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1732 uint64_t *values, unsigned int n)
1734 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1735 uint64_t values_copy[stat_cnt];
1738 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1739 struct fsl_mc_io *dpni =
1740 (struct fsl_mc_io *)dev->process_private;
1742 union dpni_statistics value[5] = {};
1750 /* Get Counters from page_0*/
1751 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1756 /* Get Counters from page_1*/
1757 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1762 /* Get Counters from page_2*/
1763 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1768 /* Get Counters from page_4*/
1769 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1774 for (i = 0; i < stat_cnt; i++) {
1775 values[i] = value[dpaa2_xstats_strings[i].page_id].
1776 raw.counter[dpaa2_xstats_strings[i].stats_id];
1781 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1783 for (i = 0; i < n; i++) {
1784 if (ids[i] >= stat_cnt) {
1785 DPAA2_PMD_ERR("xstats id value isn't valid");
1788 values[i] = values_copy[ids[i]];
1794 dpaa2_xstats_get_names_by_id(
1795 struct rte_eth_dev *dev,
1796 struct rte_eth_xstat_name *xstats_names,
1797 const uint64_t *ids,
1800 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1801 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1804 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1806 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1808 for (i = 0; i < limit; i++) {
1809 if (ids[i] >= stat_cnt) {
1810 DPAA2_PMD_ERR("xstats id value isn't valid");
1813 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1819 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1821 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1822 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1825 struct dpaa2_queue *dpaa2_q;
1827 PMD_INIT_FUNC_TRACE();
1830 DPAA2_PMD_ERR("dpni is NULL");
1834 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1838 /* Reset the per queue stats in dpaa2_queue structure */
1839 for (i = 0; i < priv->nb_rx_queues; i++) {
1840 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1842 dpaa2_q->rx_pkts = 0;
1845 for (i = 0; i < priv->nb_tx_queues; i++) {
1846 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1848 dpaa2_q->tx_pkts = 0;
1854 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1858 /* return 0 means link status changed, -1 means not changed */
1860 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1861 int wait_to_complete)
1864 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1865 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1866 struct rte_eth_link link;
1867 struct dpni_link_state state = {0};
1871 DPAA2_PMD_ERR("dpni is NULL");
1875 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1876 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1879 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1882 if (state.up == ETH_LINK_DOWN &&
1884 rte_delay_ms(CHECK_INTERVAL);
1889 memset(&link, 0, sizeof(struct rte_eth_link));
1890 link.link_status = state.up;
1891 link.link_speed = state.rate;
1893 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1894 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1896 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1898 ret = rte_eth_linkstatus_set(dev, &link);
1900 DPAA2_PMD_DEBUG("No change in status");
1902 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1903 link.link_status ? "Up" : "Down");
1909 * Toggle the DPNI to enable, if not already enabled.
1910 * This is not strictly PHY up/down - it is more of logical toggling.
1913 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1916 struct dpaa2_dev_priv *priv;
1917 struct fsl_mc_io *dpni;
1919 struct dpni_link_state state = {0};
1921 priv = dev->data->dev_private;
1922 dpni = (struct fsl_mc_io *)dev->process_private;
1925 DPAA2_PMD_ERR("dpni is NULL");
1929 /* Check if DPNI is currently enabled */
1930 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1932 /* Unable to obtain dpni status; Not continuing */
1933 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1937 /* Enable link if not already enabled */
1939 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1941 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1945 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1947 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1951 /* changing tx burst function to start enqueues */
1952 dev->tx_pkt_burst = dpaa2_dev_tx;
1953 dev->data->dev_link.link_status = state.up;
1954 dev->data->dev_link.link_speed = state.rate;
1957 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1959 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1964 * Toggle the DPNI to disable, if not already disabled.
1965 * This is not strictly PHY up/down - it is more of logical toggling.
1968 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1971 struct dpaa2_dev_priv *priv;
1972 struct fsl_mc_io *dpni;
1973 int dpni_enabled = 0;
1976 PMD_INIT_FUNC_TRACE();
1978 priv = dev->data->dev_private;
1979 dpni = (struct fsl_mc_io *)dev->process_private;
1982 DPAA2_PMD_ERR("Device has not yet been configured");
1986 /*changing tx burst function to avoid any more enqueues */
1987 dev->tx_pkt_burst = dummy_dev_tx;
1989 /* Loop while dpni_disable() attempts to drain the egress FQs
1990 * and confirm them back to us.
1993 ret = dpni_disable(dpni, 0, priv->token);
1995 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1998 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
2000 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
2004 /* Allow the MC some slack */
2005 rte_delay_us(100 * 1000);
2006 } while (dpni_enabled && --retries);
2009 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2010 /* todo- we may have to manually cleanup queues.
2013 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2014 dev->data->port_id);
2017 dev->data->dev_link.link_status = 0;
2023 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2026 struct dpaa2_dev_priv *priv;
2027 struct fsl_mc_io *dpni;
2028 struct dpni_link_state state = {0};
2030 PMD_INIT_FUNC_TRACE();
2032 priv = dev->data->dev_private;
2033 dpni = (struct fsl_mc_io *)dev->process_private;
2035 if (dpni == NULL || fc_conf == NULL) {
2036 DPAA2_PMD_ERR("device not configured");
2040 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2042 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2046 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2047 if (state.options & DPNI_LINK_OPT_PAUSE) {
2048 /* DPNI_LINK_OPT_PAUSE set
2049 * if ASYM_PAUSE not set,
2050 * RX Side flow control (handle received Pause frame)
2051 * TX side flow control (send Pause frame)
2052 * if ASYM_PAUSE set,
2053 * RX Side flow control (handle received Pause frame)
2054 * No TX side flow control (send Pause frame disabled)
2056 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2057 fc_conf->mode = RTE_FC_FULL;
2059 fc_conf->mode = RTE_FC_RX_PAUSE;
2061 /* DPNI_LINK_OPT_PAUSE not set
2062 * if ASYM_PAUSE set,
2063 * TX side flow control (send Pause frame)
2064 * No RX side flow control (No action on pause frame rx)
2065 * if ASYM_PAUSE not set,
2066 * Flow control disabled
2068 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2069 fc_conf->mode = RTE_FC_TX_PAUSE;
2071 fc_conf->mode = RTE_FC_NONE;
2078 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2081 struct dpaa2_dev_priv *priv;
2082 struct fsl_mc_io *dpni;
2083 struct dpni_link_state state = {0};
2084 struct dpni_link_cfg cfg = {0};
2086 PMD_INIT_FUNC_TRACE();
2088 priv = dev->data->dev_private;
2089 dpni = (struct fsl_mc_io *)dev->process_private;
2092 DPAA2_PMD_ERR("dpni is NULL");
2096 /* It is necessary to obtain the current state before setting fc_conf
2097 * as MC would return error in case rate, autoneg or duplex values are
2100 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2102 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2106 /* Disable link before setting configuration */
2107 dpaa2_dev_set_link_down(dev);
2109 /* Based on fc_conf, update cfg */
2110 cfg.rate = state.rate;
2111 cfg.options = state.options;
2113 /* update cfg with fc_conf */
2114 switch (fc_conf->mode) {
2116 /* Full flow control;
2117 * OPT_PAUSE set, ASYM_PAUSE not set
2119 cfg.options |= DPNI_LINK_OPT_PAUSE;
2120 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2122 case RTE_FC_TX_PAUSE:
2123 /* Enable RX flow control
2124 * OPT_PAUSE not set;
2127 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2128 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2130 case RTE_FC_RX_PAUSE:
2131 /* Enable TX Flow control
2135 cfg.options |= DPNI_LINK_OPT_PAUSE;
2136 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2139 /* Disable Flow control
2141 * ASYM_PAUSE not set
2143 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2144 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2147 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2152 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2154 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2158 dpaa2_dev_set_link_up(dev);
2164 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2165 struct rte_eth_rss_conf *rss_conf)
2167 struct rte_eth_dev_data *data = dev->data;
2168 struct dpaa2_dev_priv *priv = data->dev_private;
2169 struct rte_eth_conf *eth_conf = &data->dev_conf;
2172 PMD_INIT_FUNC_TRACE();
2174 if (rss_conf->rss_hf) {
2175 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2176 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2179 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2185 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2186 ret = dpaa2_remove_flow_dist(dev, tc_index);
2189 "Unable to remove flow dist on tc%d",
2195 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2200 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2201 struct rte_eth_rss_conf *rss_conf)
2203 struct rte_eth_dev_data *data = dev->data;
2204 struct rte_eth_conf *eth_conf = &data->dev_conf;
2206 /* dpaa2 does not support rss_key, so length should be 0*/
2207 rss_conf->rss_key_len = 0;
2208 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2212 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2213 int eth_rx_queue_id,
2214 struct dpaa2_dpcon_dev *dpcon,
2215 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2217 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2218 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2219 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2220 uint8_t flow_id = dpaa2_ethq->flow_id;
2221 struct dpni_queue cfg;
2222 uint8_t options, priority;
2225 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2226 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2227 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2228 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2229 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2230 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2234 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2235 (dpcon->num_priorities - 1);
2237 memset(&cfg, 0, sizeof(struct dpni_queue));
2238 options = DPNI_QUEUE_OPT_DEST;
2239 cfg.destination.type = DPNI_DEST_DPCON;
2240 cfg.destination.id = dpcon->dpcon_id;
2241 cfg.destination.priority = priority;
2243 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2244 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2245 cfg.destination.hold_active = 1;
2248 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2249 !eth_priv->en_ordered) {
2250 struct opr_cfg ocfg;
2252 /* Restoration window size = 256 frames */
2254 /* Restoration window size = 512 frames for LX2 */
2255 if (dpaa2_svr_family == SVR_LX2160A)
2257 /* Auto advance NESN window enabled */
2259 /* Late arrival window size disabled */
2261 /* ORL resource exhaustaion advance NESN disabled */
2263 /* Loose ordering enabled */
2265 eth_priv->en_loose_ordered = 1;
2266 /* Strict ordering enabled if explicitly set */
2267 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2269 eth_priv->en_loose_ordered = 0;
2272 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2273 dpaa2_ethq->tc_index, flow_id,
2274 OPR_OPT_CREATE, &ocfg);
2276 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2280 eth_priv->en_ordered = 1;
2283 options |= DPNI_QUEUE_OPT_USER_CTX;
2284 cfg.user_context = (size_t)(dpaa2_ethq);
2286 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2287 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2289 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2293 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2298 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2299 int eth_rx_queue_id)
2301 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2302 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2303 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2304 uint8_t flow_id = dpaa2_ethq->flow_id;
2305 struct dpni_queue cfg;
2309 memset(&cfg, 0, sizeof(struct dpni_queue));
2310 options = DPNI_QUEUE_OPT_DEST;
2311 cfg.destination.type = DPNI_DEST_NONE;
2313 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2314 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2316 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2322 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2323 const struct rte_flow_ops **ops)
2328 *ops = &dpaa2_flow_ops;
2333 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2334 struct rte_eth_rxq_info *qinfo)
2336 struct dpaa2_queue *rxq;
2337 struct dpaa2_dev_priv *priv = dev->data->dev_private;
2338 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2339 uint16_t max_frame_length;
2341 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2343 qinfo->mp = rxq->mb_pool;
2344 qinfo->scattered_rx = dev->data->scattered_rx;
2345 qinfo->nb_desc = rxq->nb_desc;
2346 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2347 &max_frame_length) == 0)
2348 qinfo->rx_buf_size = max_frame_length;
2350 qinfo->conf.rx_free_thresh = 1;
2351 qinfo->conf.rx_drop_en = 1;
2352 qinfo->conf.rx_deferred_start = 0;
2353 qinfo->conf.offloads = rxq->offloads;
2357 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2358 struct rte_eth_txq_info *qinfo)
2360 struct dpaa2_queue *txq;
2362 txq = dev->data->tx_queues[queue_id];
2364 qinfo->nb_desc = txq->nb_desc;
2365 qinfo->conf.tx_thresh.pthresh = 0;
2366 qinfo->conf.tx_thresh.hthresh = 0;
2367 qinfo->conf.tx_thresh.wthresh = 0;
2369 qinfo->conf.tx_free_thresh = 0;
2370 qinfo->conf.tx_rs_thresh = 0;
2371 qinfo->conf.offloads = txq->offloads;
2372 qinfo->conf.tx_deferred_start = 0;
2376 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2378 *(const void **)ops = &dpaa2_tm_ops;
2383 static struct eth_dev_ops dpaa2_ethdev_ops = {
2384 .dev_configure = dpaa2_eth_dev_configure,
2385 .dev_start = dpaa2_dev_start,
2386 .dev_stop = dpaa2_dev_stop,
2387 .dev_close = dpaa2_dev_close,
2388 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2389 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2390 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2391 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2392 .dev_set_link_up = dpaa2_dev_set_link_up,
2393 .dev_set_link_down = dpaa2_dev_set_link_down,
2394 .link_update = dpaa2_dev_link_update,
2395 .stats_get = dpaa2_dev_stats_get,
2396 .xstats_get = dpaa2_dev_xstats_get,
2397 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2398 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2399 .xstats_get_names = dpaa2_xstats_get_names,
2400 .stats_reset = dpaa2_dev_stats_reset,
2401 .xstats_reset = dpaa2_dev_stats_reset,
2402 .fw_version_get = dpaa2_fw_version_get,
2403 .dev_infos_get = dpaa2_dev_info_get,
2404 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2405 .mtu_set = dpaa2_dev_mtu_set,
2406 .vlan_filter_set = dpaa2_vlan_filter_set,
2407 .vlan_offload_set = dpaa2_vlan_offload_set,
2408 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2409 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2410 .rx_queue_release = dpaa2_dev_rx_queue_release,
2411 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2412 .tx_queue_release = dpaa2_dev_tx_queue_release,
2413 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2414 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2415 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2416 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2417 .mac_addr_add = dpaa2_dev_add_mac_addr,
2418 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2419 .mac_addr_set = dpaa2_dev_set_mac_addr,
2420 .rss_hash_update = dpaa2_dev_rss_hash_update,
2421 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2422 .flow_ops_get = dpaa2_dev_flow_ops_get,
2423 .rxq_info_get = dpaa2_rxq_info_get,
2424 .txq_info_get = dpaa2_txq_info_get,
2425 .tm_ops_get = dpaa2_tm_ops_get,
2426 #if defined(RTE_LIBRTE_IEEE1588)
2427 .timesync_enable = dpaa2_timesync_enable,
2428 .timesync_disable = dpaa2_timesync_disable,
2429 .timesync_read_time = dpaa2_timesync_read_time,
2430 .timesync_write_time = dpaa2_timesync_write_time,
2431 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2432 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2433 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2437 /* Populate the mac address from physically available (u-boot/firmware) and/or
2438 * one set by higher layers like MC (restool) etc.
2439 * Returns the table of MAC entries (multiple entries)
2442 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2443 struct rte_ether_addr *mac_entry)
2446 struct rte_ether_addr phy_mac, prime_mac;
2448 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2449 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2451 /* Get the physical device MAC address */
2452 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2453 phy_mac.addr_bytes);
2455 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2459 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2460 prime_mac.addr_bytes);
2462 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2466 /* Now that both MAC have been obtained, do:
2467 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2469 * If empty_mac(phy), return prime.
2470 * if both are empty, create random MAC, set as prime and return
2472 if (!rte_is_zero_ether_addr(&phy_mac)) {
2473 /* If the addresses are not same, overwrite prime */
2474 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2475 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2477 phy_mac.addr_bytes);
2479 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2483 memcpy(&prime_mac, &phy_mac,
2484 sizeof(struct rte_ether_addr));
2486 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2487 /* In case phys and prime, both are zero, create random MAC */
2488 rte_eth_random_addr(prime_mac.addr_bytes);
2489 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2491 prime_mac.addr_bytes);
2493 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2498 /* prime_mac the final MAC address */
2499 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2507 check_devargs_handler(__rte_unused const char *key, const char *value,
2508 __rte_unused void *opaque)
2510 if (strcmp(value, "1"))
2517 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2519 struct rte_kvargs *kvlist;
2524 kvlist = rte_kvargs_parse(devargs->args, NULL);
2528 if (!rte_kvargs_count(kvlist, key)) {
2529 rte_kvargs_free(kvlist);
2533 if (rte_kvargs_process(kvlist, key,
2534 check_devargs_handler, NULL) < 0) {
2535 rte_kvargs_free(kvlist);
2538 rte_kvargs_free(kvlist);
2544 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2546 struct rte_device *dev = eth_dev->device;
2547 struct rte_dpaa2_device *dpaa2_dev;
2548 struct fsl_mc_io *dpni_dev;
2549 struct dpni_attr attr;
2550 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2551 struct dpni_buffer_layout layout;
2554 PMD_INIT_FUNC_TRACE();
2556 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2558 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2561 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2562 eth_dev->process_private = (void *)dpni_dev;
2564 /* For secondary processes, the primary has done all the work */
2565 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2566 /* In case of secondary, only burst and ops API need to be
2569 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2570 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2571 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2572 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2573 else if (dpaa2_get_devargs(dev->devargs,
2574 DRIVER_NO_PREFETCH_MODE))
2575 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2577 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2578 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2582 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2584 hw_id = dpaa2_dev->object_id;
2585 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2588 "Failure in opening dpni@%d with err code %d",
2594 /* Clean the device first */
2595 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2597 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2602 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2605 "Failure in get dpni@%d attribute, err code %d",
2610 priv->num_rx_tc = attr.num_rx_tcs;
2611 priv->qos_entries = attr.qos_entries;
2612 priv->fs_entries = attr.fs_entries;
2613 priv->dist_queues = attr.num_queues;
2615 /* only if the custom CG is enabled */
2616 if (attr.options & DPNI_OPT_CUSTOM_CG)
2617 priv->max_cgs = attr.num_cgs;
2621 for (i = 0; i < priv->max_cgs; i++)
2622 priv->cgid_in_use[i] = 0;
2624 for (i = 0; i < attr.num_rx_tcs; i++)
2625 priv->nb_rx_queues += attr.num_queues;
2627 /* Using number of TX queues as number of TX TCs */
2628 priv->nb_tx_queues = attr.num_tx_tcs;
2630 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2631 priv->num_rx_tc, priv->nb_rx_queues,
2632 priv->nb_tx_queues, priv->max_cgs);
2634 priv->hw = dpni_dev;
2635 priv->hw_id = hw_id;
2636 priv->options = attr.options;
2637 priv->max_mac_filters = attr.mac_filter_entries;
2638 priv->max_vlan_filters = attr.vlan_filter_entries;
2640 #if defined(RTE_LIBRTE_IEEE1588)
2641 printf("DPDK IEEE1588 is enabled\n");
2642 priv->flags |= DPAA2_TX_CONF_ENABLE;
2644 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2645 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2646 priv->flags |= DPAA2_TX_CONF_ENABLE;
2647 DPAA2_PMD_INFO("TX_CONF Enabled");
2650 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2651 dpaa2_enable_err_queue = 1;
2652 DPAA2_PMD_INFO("Enable error queue");
2655 /* Allocate memory for hardware structure for queues */
2656 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2658 DPAA2_PMD_ERR("Queue allocation Failed");
2662 /* Allocate memory for storing MAC addresses.
2663 * Table of mac_filter_entries size is allocated so that RTE ether lib
2664 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2666 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2667 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2668 if (eth_dev->data->mac_addrs == NULL) {
2670 "Failed to allocate %d bytes needed to store MAC addresses",
2671 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2676 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2678 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2679 rte_free(eth_dev->data->mac_addrs);
2680 eth_dev->data->mac_addrs = NULL;
2684 /* ... tx buffer layout ... */
2685 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2686 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2687 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2688 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2689 layout.pass_timestamp = true;
2691 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2693 layout.pass_frame_status = 1;
2694 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2695 DPNI_QUEUE_TX, &layout);
2697 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2701 /* ... tx-conf and error buffer layout ... */
2702 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2703 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2704 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2705 layout.pass_timestamp = true;
2707 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2708 layout.pass_frame_status = 1;
2709 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2710 DPNI_QUEUE_TX_CONFIRM, &layout);
2712 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2717 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2719 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2720 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2721 DPAA2_PMD_INFO("Loopback mode");
2722 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2723 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2724 DPAA2_PMD_INFO("No Prefetch mode");
2726 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2728 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2730 /*Init fields w.r.t. classficaition*/
2731 memset(&priv->extract.qos_key_extract, 0,
2732 sizeof(struct dpaa2_key_extract));
2733 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2734 if (!priv->extract.qos_extract_param) {
2735 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2736 " classificaiton ", ret);
2739 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2740 IP_ADDRESS_OFFSET_INVALID;
2741 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2742 IP_ADDRESS_OFFSET_INVALID;
2743 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2744 IP_ADDRESS_OFFSET_INVALID;
2745 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2746 IP_ADDRESS_OFFSET_INVALID;
2748 for (i = 0; i < MAX_TCS; i++) {
2749 memset(&priv->extract.tc_key_extract[i], 0,
2750 sizeof(struct dpaa2_key_extract));
2751 priv->extract.tc_extract_param[i] =
2752 (size_t)rte_malloc(NULL, 256, 64);
2753 if (!priv->extract.tc_extract_param[i]) {
2754 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2758 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2759 IP_ADDRESS_OFFSET_INVALID;
2760 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2761 IP_ADDRESS_OFFSET_INVALID;
2762 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2763 IP_ADDRESS_OFFSET_INVALID;
2764 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2765 IP_ADDRESS_OFFSET_INVALID;
2768 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2769 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2772 DPAA2_PMD_ERR("Unable to set mtu. check config");
2776 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2777 * with external entity to receive byte code for software sequence
2778 * and same will be offload to the H/W using MC interface.
2779 * Currently it is assumed that DPAA2 driver has byte code by some
2780 * mean and same if offloaded to H/W.
2782 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2783 WRIOP_SS_INITIALIZER(priv);
2784 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2786 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2791 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2794 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2799 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2802 dpaa2_dev_close(eth_dev);
2808 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2809 struct rte_dpaa2_device *dpaa2_dev)
2811 struct rte_eth_dev *eth_dev;
2812 struct dpaa2_dev_priv *dev_priv;
2815 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2816 RTE_PKTMBUF_HEADROOM) {
2818 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2819 RTE_PKTMBUF_HEADROOM,
2820 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2825 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2826 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2829 dev_priv = rte_zmalloc("ethdev private structure",
2830 sizeof(struct dpaa2_dev_priv),
2831 RTE_CACHE_LINE_SIZE);
2832 if (dev_priv == NULL) {
2834 "Unable to allocate memory for private data");
2835 rte_eth_dev_release_port(eth_dev);
2838 eth_dev->data->dev_private = (void *)dev_priv;
2839 /* Store a pointer to eth_dev in dev_private */
2840 dev_priv->eth_dev = eth_dev;
2842 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2844 DPAA2_PMD_DEBUG("returning enodev");
2849 eth_dev->device = &dpaa2_dev->device;
2851 dpaa2_dev->eth_dev = eth_dev;
2852 eth_dev->data->rx_mbuf_alloc_failed = 0;
2854 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2855 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2857 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2859 /* Invoke PMD device initialization function */
2860 diag = dpaa2_dev_init(eth_dev);
2862 rte_eth_dev_probing_finish(eth_dev);
2866 rte_eth_dev_release_port(eth_dev);
2871 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2873 struct rte_eth_dev *eth_dev;
2876 eth_dev = dpaa2_dev->eth_dev;
2877 dpaa2_dev_close(eth_dev);
2878 ret = rte_eth_dev_release_port(eth_dev);
2883 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2884 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2885 .drv_type = DPAA2_ETH,
2886 .probe = rte_dpaa2_probe,
2887 .remove = rte_dpaa2_remove,
2890 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2891 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2892 DRIVER_LOOPBACK_MODE "=<int> "
2893 DRIVER_NO_PREFETCH_MODE "=<int>"
2894 DRIVER_TX_CONF "=<int>"
2895 DRIVER_ERROR_QUEUE "=<int>");
2896 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);