1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2020 NXP
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
35 /* Supported Rx offloads */
36 static uint64_t dev_rx_offloads_sup =
37 DEV_RX_OFFLOAD_CHECKSUM |
38 DEV_RX_OFFLOAD_SCTP_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
41 DEV_RX_OFFLOAD_VLAN_STRIP |
42 DEV_RX_OFFLOAD_VLAN_FILTER |
43 DEV_RX_OFFLOAD_JUMBO_FRAME |
44 DEV_RX_OFFLOAD_TIMESTAMP;
46 /* Rx offloads which cannot be disabled */
47 static uint64_t dev_rx_offloads_nodis =
48 DEV_RX_OFFLOAD_RSS_HASH |
49 DEV_RX_OFFLOAD_SCATTER;
51 /* Supported Tx offloads */
52 static uint64_t dev_tx_offloads_sup =
53 DEV_TX_OFFLOAD_VLAN_INSERT |
54 DEV_TX_OFFLOAD_IPV4_CKSUM |
55 DEV_TX_OFFLOAD_UDP_CKSUM |
56 DEV_TX_OFFLOAD_TCP_CKSUM |
57 DEV_TX_OFFLOAD_SCTP_CKSUM |
58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_MT_LOCKFREE |
60 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
62 /* Tx offloads which cannot be disabled */
63 static uint64_t dev_tx_offloads_nodis =
64 DEV_TX_OFFLOAD_MULTI_SEGS;
66 /* enable timestamp in mbuf */
67 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
68 uint64_t dpaa2_timestamp_rx_dynflag;
69 int dpaa2_timestamp_dynfield_offset = -1;
71 struct rte_dpaa2_xstats_name_off {
72 char name[RTE_ETH_XSTATS_NAME_SIZE];
73 uint8_t page_id; /* dpni statistics page id */
74 uint8_t stats_id; /* stats id in the given page */
77 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
78 {"ingress_multicast_frames", 0, 2},
79 {"ingress_multicast_bytes", 0, 3},
80 {"ingress_broadcast_frames", 0, 4},
81 {"ingress_broadcast_bytes", 0, 5},
82 {"egress_multicast_frames", 1, 2},
83 {"egress_multicast_bytes", 1, 3},
84 {"egress_broadcast_frames", 1, 4},
85 {"egress_broadcast_bytes", 1, 5},
86 {"ingress_filtered_frames", 2, 0},
87 {"ingress_discarded_frames", 2, 1},
88 {"ingress_nobuffer_discards", 2, 2},
89 {"egress_discarded_frames", 2, 3},
90 {"egress_confirmed_frames", 2, 4},
91 {"cgr_reject_frames", 4, 0},
92 {"cgr_reject_bytes", 4, 1},
95 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
99 static struct rte_dpaa2_driver rte_dpaa2_pmd;
100 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
101 int wait_to_complete);
102 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
103 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
104 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
107 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
110 struct dpaa2_dev_priv *priv = dev->data->dev_private;
111 struct fsl_mc_io *dpni = dev->process_private;
113 PMD_INIT_FUNC_TRACE();
116 DPAA2_PMD_ERR("dpni is NULL");
121 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
124 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
125 priv->token, vlan_id);
128 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
129 ret, vlan_id, priv->hw_id);
135 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
137 struct dpaa2_dev_priv *priv = dev->data->dev_private;
138 struct fsl_mc_io *dpni = dev->process_private;
141 PMD_INIT_FUNC_TRACE();
143 if (mask & ETH_VLAN_FILTER_MASK) {
144 /* VLAN Filter not avaialble */
145 if (!priv->max_vlan_filters) {
146 DPAA2_PMD_INFO("VLAN filter not available");
150 if (dev->data->dev_conf.rxmode.offloads &
151 DEV_RX_OFFLOAD_VLAN_FILTER)
152 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
155 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
158 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
165 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
166 enum rte_vlan_type vlan_type __rte_unused,
169 struct dpaa2_dev_priv *priv = dev->data->dev_private;
170 struct fsl_mc_io *dpni = dev->process_private;
173 PMD_INIT_FUNC_TRACE();
175 /* nothing to be done for standard vlan tpids */
176 if (tpid == 0x8100 || tpid == 0x88A8)
179 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
182 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
183 /* if already configured tpids, remove them first */
185 struct dpni_custom_tpid_cfg tpid_list = {0};
187 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
188 priv->token, &tpid_list);
191 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
192 priv->token, tpid_list.tpid1);
195 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
203 dpaa2_fw_version_get(struct rte_eth_dev *dev,
208 struct fsl_mc_io *dpni = dev->process_private;
209 struct mc_soc_version mc_plat_info = {0};
210 struct mc_version mc_ver_info = {0};
212 PMD_INIT_FUNC_TRACE();
214 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
215 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
217 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
218 DPAA2_PMD_WARN("\tmc_get_version failed");
220 ret = snprintf(fw_version, fw_size,
225 mc_ver_info.revision);
227 ret += 1; /* add the size of '\0' */
228 if (fw_size < (uint32_t)ret)
235 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
237 struct dpaa2_dev_priv *priv = dev->data->dev_private;
239 PMD_INIT_FUNC_TRACE();
241 dev_info->max_mac_addrs = priv->max_mac_filters;
242 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
243 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
244 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
245 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
246 dev_info->rx_offload_capa = dev_rx_offloads_sup |
247 dev_rx_offloads_nodis;
248 dev_info->tx_offload_capa = dev_tx_offloads_sup |
249 dev_tx_offloads_nodis;
250 dev_info->speed_capa = ETH_LINK_SPEED_1G |
251 ETH_LINK_SPEED_2_5G |
254 dev_info->max_hash_mac_addrs = 0;
255 dev_info->max_vfs = 0;
256 dev_info->max_vmdq_pools = ETH_16_POOLS;
257 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
259 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
260 /* same is rx size for best perf */
261 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
263 dev_info->default_rxportconf.nb_queues = 1;
264 dev_info->default_txportconf.nb_queues = 1;
265 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
266 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
268 if (dpaa2_svr_family == SVR_LX2160A) {
269 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
279 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
280 __rte_unused uint16_t queue_id,
281 struct rte_eth_burst_mode *mode)
283 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
286 const struct burst_info {
289 } rx_offload_map[] = {
290 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
291 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
292 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
293 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
294 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
295 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
296 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
297 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
298 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
299 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
302 /* Update Rx offload info */
303 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
304 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
305 snprintf(mode->info, sizeof(mode->info), "%s",
306 rx_offload_map[i].output);
315 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
316 __rte_unused uint16_t queue_id,
317 struct rte_eth_burst_mode *mode)
319 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
322 const struct burst_info {
325 } tx_offload_map[] = {
326 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
327 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
328 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
329 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
330 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
331 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
332 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
333 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
334 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
337 /* Update Tx offload info */
338 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
339 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
340 snprintf(mode->info, sizeof(mode->info), "%s",
341 tx_offload_map[i].output);
350 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
352 struct dpaa2_dev_priv *priv = dev->data->dev_private;
355 uint8_t num_rxqueue_per_tc;
356 struct dpaa2_queue *mc_q, *mcq;
359 struct dpaa2_queue *dpaa2_q;
361 PMD_INIT_FUNC_TRACE();
363 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
364 if (priv->tx_conf_en)
365 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
367 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
368 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
369 RTE_CACHE_LINE_SIZE);
371 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
375 for (i = 0; i < priv->nb_rx_queues; i++) {
376 mc_q->eth_data = dev->data;
377 priv->rx_vq[i] = mc_q++;
378 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
379 dpaa2_q->q_storage = rte_malloc("dq_storage",
380 sizeof(struct queue_storage_info_t),
381 RTE_CACHE_LINE_SIZE);
382 if (!dpaa2_q->q_storage)
385 memset(dpaa2_q->q_storage, 0,
386 sizeof(struct queue_storage_info_t));
387 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
391 for (i = 0; i < priv->nb_tx_queues; i++) {
392 mc_q->eth_data = dev->data;
393 mc_q->flow_id = 0xffff;
394 priv->tx_vq[i] = mc_q++;
395 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
396 dpaa2_q->cscn = rte_malloc(NULL,
397 sizeof(struct qbman_result), 16);
402 if (priv->tx_conf_en) {
403 /*Setup tx confirmation queues*/
404 for (i = 0; i < priv->nb_tx_queues; i++) {
405 mc_q->eth_data = dev->data;
408 priv->tx_conf_vq[i] = mc_q++;
409 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
411 rte_malloc("dq_storage",
412 sizeof(struct queue_storage_info_t),
413 RTE_CACHE_LINE_SIZE);
414 if (!dpaa2_q->q_storage)
417 memset(dpaa2_q->q_storage, 0,
418 sizeof(struct queue_storage_info_t));
419 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
425 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
426 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
427 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
428 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
436 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
437 rte_free(dpaa2_q->q_storage);
438 priv->tx_conf_vq[i--] = NULL;
440 i = priv->nb_tx_queues;
444 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
445 rte_free(dpaa2_q->cscn);
446 priv->tx_vq[i--] = NULL;
448 i = priv->nb_rx_queues;
451 mc_q = priv->rx_vq[0];
453 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
454 dpaa2_free_dq_storage(dpaa2_q->q_storage);
455 rte_free(dpaa2_q->q_storage);
456 priv->rx_vq[i--] = NULL;
463 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
465 struct dpaa2_dev_priv *priv = dev->data->dev_private;
466 struct dpaa2_queue *dpaa2_q;
469 PMD_INIT_FUNC_TRACE();
471 /* Queue allocation base */
472 if (priv->rx_vq[0]) {
473 /* cleaning up queue storage */
474 for (i = 0; i < priv->nb_rx_queues; i++) {
475 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
476 if (dpaa2_q->q_storage)
477 rte_free(dpaa2_q->q_storage);
479 /* cleanup tx queue cscn */
480 for (i = 0; i < priv->nb_tx_queues; i++) {
481 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
482 rte_free(dpaa2_q->cscn);
484 if (priv->tx_conf_en) {
485 /* cleanup tx conf queue storage */
486 for (i = 0; i < priv->nb_tx_queues; i++) {
487 dpaa2_q = (struct dpaa2_queue *)
489 rte_free(dpaa2_q->q_storage);
492 /*free memory for all queues (RX+TX) */
493 rte_free(priv->rx_vq[0]);
494 priv->rx_vq[0] = NULL;
499 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
501 struct dpaa2_dev_priv *priv = dev->data->dev_private;
502 struct fsl_mc_io *dpni = dev->process_private;
503 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
504 uint64_t rx_offloads = eth_conf->rxmode.offloads;
505 uint64_t tx_offloads = eth_conf->txmode.offloads;
506 int rx_l3_csum_offload = false;
507 int rx_l4_csum_offload = false;
508 int tx_l3_csum_offload = false;
509 int tx_l4_csum_offload = false;
512 PMD_INIT_FUNC_TRACE();
514 /* Rx offloads which are enabled by default */
515 if (dev_rx_offloads_nodis & ~rx_offloads) {
517 "Some of rx offloads enabled by default - requested 0x%" PRIx64
518 " fixed are 0x%" PRIx64,
519 rx_offloads, dev_rx_offloads_nodis);
522 /* Tx offloads which are enabled by default */
523 if (dev_tx_offloads_nodis & ~tx_offloads) {
525 "Some of tx offloads enabled by default - requested 0x%" PRIx64
526 " fixed are 0x%" PRIx64,
527 tx_offloads, dev_tx_offloads_nodis);
530 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
531 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
532 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
533 priv->token, eth_conf->rxmode.max_rx_pkt_len
534 - RTE_ETHER_CRC_LEN);
537 "Unable to set mtu. check config");
541 dev->data->dev_conf.rxmode.max_rx_pkt_len -
542 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
549 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
550 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
551 ret = dpaa2_setup_flow_dist(dev,
552 eth_conf->rx_adv_conf.rss_conf.rss_hf,
556 "Unable to set flow distribution on tc%d."
557 "Check queue config", tc_index);
563 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
564 rx_l3_csum_offload = true;
566 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
567 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
568 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
569 rx_l4_csum_offload = true;
571 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
572 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
574 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
578 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
579 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
581 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
585 #if !defined(RTE_LIBRTE_IEEE1588)
586 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
589 ret = rte_mbuf_dyn_rx_timestamp_register(
590 &dpaa2_timestamp_dynfield_offset,
591 &dpaa2_timestamp_rx_dynflag);
593 DPAA2_PMD_ERR("Error to register timestamp field/flag");
596 dpaa2_enable_ts[dev->data->port_id] = true;
599 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
600 tx_l3_csum_offload = true;
602 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
603 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
604 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
605 tx_l4_csum_offload = true;
607 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
608 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
610 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
614 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
615 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
617 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
621 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
622 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
623 * to 0 for LS2 in the hardware thus disabling data/annotation
624 * stashing. For LX2 this is fixed in hardware and thus hash result and
625 * parse results can be received in FD using this option.
627 if (dpaa2_svr_family == SVR_LX2160A) {
628 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
629 DPNI_FLCTYPE_HASH, true);
631 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
636 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
637 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
642 /* Function to setup RX flow information. It contains traffic class ID,
643 * flow ID, destination configuration etc.
646 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
647 uint16_t rx_queue_id,
649 unsigned int socket_id __rte_unused,
650 const struct rte_eth_rxconf *rx_conf,
651 struct rte_mempool *mb_pool)
653 struct dpaa2_dev_priv *priv = dev->data->dev_private;
654 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
655 struct dpaa2_queue *dpaa2_q;
656 struct dpni_queue cfg;
662 PMD_INIT_FUNC_TRACE();
664 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
665 dev, rx_queue_id, mb_pool, rx_conf);
667 /* Rx deferred start is not supported */
668 if (rx_conf->rx_deferred_start) {
669 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
674 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
675 bpid = mempool_to_bpid(mb_pool);
676 ret = dpaa2_attach_bp_list(priv,
677 rte_dpaa2_bpid_info[bpid].bp_list);
681 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
682 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
683 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
684 dpaa2_q->nb_desc = UINT16_MAX;
685 dpaa2_q->offloads = rx_conf->offloads;
687 /*Get the flow id from given VQ id*/
688 flow_id = dpaa2_q->flow_id;
689 memset(&cfg, 0, sizeof(struct dpni_queue));
691 options = options | DPNI_QUEUE_OPT_USER_CTX;
692 cfg.user_context = (size_t)(dpaa2_q);
694 /* check if a private cgr available. */
695 for (i = 0; i < priv->max_cgs; i++) {
696 if (!priv->cgid_in_use[i]) {
697 priv->cgid_in_use[i] = 1;
702 if (i < priv->max_cgs) {
703 options |= DPNI_QUEUE_OPT_SET_CGID;
705 dpaa2_q->cgid = cfg.cgid;
707 dpaa2_q->cgid = 0xff;
710 /*if ls2088 or rev2 device, enable the stashing */
712 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
713 options |= DPNI_QUEUE_OPT_FLC;
714 cfg.flc.stash_control = true;
715 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
716 /* 00 00 00 - last 6 bit represent annotation, context stashing,
717 * data stashing setting 01 01 00 (0x14)
718 * (in following order ->DS AS CS)
719 * to enable 1 line data, 1 line annotation.
720 * For LX2, this setting should be 01 00 00 (0x10)
722 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
723 cfg.flc.value |= 0x10;
725 cfg.flc.value |= 0x14;
727 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
728 dpaa2_q->tc_index, flow_id, options, &cfg);
730 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
734 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
735 struct dpni_taildrop taildrop;
738 dpaa2_q->nb_desc = nb_rx_desc;
739 /* Private CGR will use tail drop length as nb_rx_desc.
740 * for rest cases we can use standard byte based tail drop.
741 * There is no HW restriction, but number of CGRs are limited,
742 * hence this restriction is placed.
744 if (dpaa2_q->cgid != 0xff) {
745 /*enabling per rx queue congestion control */
746 taildrop.threshold = nb_rx_desc;
747 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
749 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
751 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
752 DPNI_CP_CONGESTION_GROUP,
755 dpaa2_q->cgid, &taildrop);
757 /*enabling per rx queue congestion control */
758 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
759 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
760 taildrop.oal = CONG_RX_OAL;
761 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
763 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
764 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
765 dpaa2_q->tc_index, flow_id,
769 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
773 } else { /* Disable tail Drop */
774 struct dpni_taildrop taildrop = {0};
775 DPAA2_PMD_INFO("Tail drop is disabled on queue");
778 if (dpaa2_q->cgid != 0xff) {
779 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
780 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
782 dpaa2_q->cgid, &taildrop);
784 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
785 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
786 dpaa2_q->tc_index, flow_id, &taildrop);
789 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
795 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
800 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
801 uint16_t tx_queue_id,
803 unsigned int socket_id __rte_unused,
804 const struct rte_eth_txconf *tx_conf)
806 struct dpaa2_dev_priv *priv = dev->data->dev_private;
807 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
808 priv->tx_vq[tx_queue_id];
809 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
810 priv->tx_conf_vq[tx_queue_id];
811 struct fsl_mc_io *dpni = dev->process_private;
812 struct dpni_queue tx_conf_cfg;
813 struct dpni_queue tx_flow_cfg;
814 uint8_t options = 0, flow_id;
815 struct dpni_queue_id qid;
819 PMD_INIT_FUNC_TRACE();
821 /* Tx deferred start is not supported */
822 if (tx_conf->tx_deferred_start) {
823 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
828 dpaa2_q->nb_desc = UINT16_MAX;
829 dpaa2_q->offloads = tx_conf->offloads;
831 /* Return if queue already configured */
832 if (dpaa2_q->flow_id != 0xffff) {
833 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
837 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
838 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
843 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
844 tc_id, flow_id, options, &tx_flow_cfg);
846 DPAA2_PMD_ERR("Error in setting the tx flow: "
847 "tc_id=%d, flow=%d err=%d",
848 tc_id, flow_id, ret);
852 dpaa2_q->flow_id = flow_id;
854 if (tx_queue_id == 0) {
855 /*Set tx-conf and error configuration*/
856 if (priv->tx_conf_en)
857 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
861 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
865 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
870 dpaa2_q->tc_index = tc_id;
872 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
873 DPNI_QUEUE_TX, dpaa2_q->tc_index,
874 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
876 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
879 dpaa2_q->fqid = qid.fqid;
881 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
882 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
884 dpaa2_q->nb_desc = nb_tx_desc;
886 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
887 cong_notif_cfg.threshold_entry = nb_tx_desc;
888 /* Notify that the queue is not congested when the data in
889 * the queue is below this thershold.
891 cong_notif_cfg.threshold_exit = nb_tx_desc - 24;
892 cong_notif_cfg.message_ctx = 0;
893 cong_notif_cfg.message_iova =
894 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
895 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
896 cong_notif_cfg.notification_mode =
897 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
898 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
899 DPNI_CONG_OPT_COHERENT_WRITE;
900 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
902 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
909 "Error in setting tx congestion notification: "
914 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
915 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
917 if (priv->tx_conf_en) {
918 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
919 options = options | DPNI_QUEUE_OPT_USER_CTX;
920 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
921 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
922 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
923 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
925 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
926 "tc_index=%d, flow=%d err=%d",
927 dpaa2_tx_conf_q->tc_index,
928 dpaa2_tx_conf_q->flow_id, ret);
932 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
933 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
934 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
936 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
939 dpaa2_tx_conf_q->fqid = qid.fqid;
945 dpaa2_dev_rx_queue_release(void *q __rte_unused)
947 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
948 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
949 struct fsl_mc_io *dpni =
950 (struct fsl_mc_io *)priv->eth_dev->process_private;
953 struct dpni_queue cfg;
955 memset(&cfg, 0, sizeof(struct dpni_queue));
956 PMD_INIT_FUNC_TRACE();
957 if (dpaa2_q->cgid != 0xff) {
958 options = DPNI_QUEUE_OPT_CLEAR_CGID;
959 cfg.cgid = dpaa2_q->cgid;
961 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
963 dpaa2_q->tc_index, dpaa2_q->flow_id,
966 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
968 priv->cgid_in_use[dpaa2_q->cgid] = 0;
969 dpaa2_q->cgid = 0xff;
974 dpaa2_dev_tx_queue_release(void *q __rte_unused)
976 PMD_INIT_FUNC_TRACE();
980 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
983 struct dpaa2_dev_priv *priv = dev->data->dev_private;
984 struct dpaa2_queue *dpaa2_q;
985 struct qbman_swp *swp;
986 struct qbman_fq_query_np_rslt state;
987 uint32_t frame_cnt = 0;
989 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
990 ret = dpaa2_affine_qbman_swp();
993 "Failed to allocate IO portal, tid: %d\n",
998 swp = DPAA2_PER_LCORE_PORTAL;
1000 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
1002 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1003 frame_cnt = qbman_fq_state_frame_count(&state);
1004 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
1005 rx_queue_id, frame_cnt);
1010 static const uint32_t *
1011 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1013 static const uint32_t ptypes[] = {
1014 /*todo -= add more types */
1017 RTE_PTYPE_L3_IPV4_EXT,
1019 RTE_PTYPE_L3_IPV6_EXT,
1027 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1028 dev->rx_pkt_burst == dpaa2_dev_rx ||
1029 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1035 * Dpaa2 link Interrupt handler
1038 * The address of parameter (struct rte_eth_dev *) regsitered before.
1044 dpaa2_interrupt_handler(void *param)
1046 struct rte_eth_dev *dev = param;
1047 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1048 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1050 int irq_index = DPNI_IRQ_INDEX;
1051 unsigned int status = 0, clear = 0;
1053 PMD_INIT_FUNC_TRACE();
1056 DPAA2_PMD_ERR("dpni is NULL");
1060 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1061 irq_index, &status);
1062 if (unlikely(ret)) {
1063 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1068 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1069 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1070 dpaa2_dev_link_update(dev, 0);
1071 /* calling all the apps registered for link status event */
1072 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1075 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1078 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1082 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1085 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1086 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1087 int irq_index = DPNI_IRQ_INDEX;
1088 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1090 PMD_INIT_FUNC_TRACE();
1092 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1095 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1100 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1103 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1110 dpaa2_dev_start(struct rte_eth_dev *dev)
1112 struct rte_device *rdev = dev->device;
1113 struct rte_dpaa2_device *dpaa2_dev;
1114 struct rte_eth_dev_data *data = dev->data;
1115 struct dpaa2_dev_priv *priv = data->dev_private;
1116 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1117 struct dpni_queue cfg;
1118 struct dpni_error_cfg err_cfg;
1120 struct dpni_queue_id qid;
1121 struct dpaa2_queue *dpaa2_q;
1123 struct rte_intr_handle *intr_handle;
1125 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1126 intr_handle = &dpaa2_dev->intr_handle;
1128 PMD_INIT_FUNC_TRACE();
1130 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1132 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1137 /* Power up the phy. Needed to make the link go UP */
1138 dpaa2_dev_set_link_up(dev);
1140 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1141 DPNI_QUEUE_TX, &qdid);
1143 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1148 for (i = 0; i < data->nb_rx_queues; i++) {
1149 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1150 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1151 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1152 dpaa2_q->flow_id, &cfg, &qid);
1154 DPAA2_PMD_ERR("Error in getting flow information: "
1158 dpaa2_q->fqid = qid.fqid;
1161 /*checksum errors, send them to normal path and set it in annotation */
1162 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1163 err_cfg.errors |= DPNI_ERROR_PHE;
1165 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1166 err_cfg.set_frame_annotation = true;
1168 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1169 priv->token, &err_cfg);
1171 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1176 /* if the interrupts were configured on this devices*/
1177 if (intr_handle && (intr_handle->fd) &&
1178 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1179 /* Registering LSC interrupt handler */
1180 rte_intr_callback_register(intr_handle,
1181 dpaa2_interrupt_handler,
1184 /* enable vfio intr/eventfd mapping
1185 * Interrupt index 0 is required, so we can not use
1188 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1190 /* enable dpni_irqs */
1191 dpaa2_eth_setup_irqs(dev, 1);
1194 /* Change the tx burst function if ordered queues are used */
1195 if (priv->en_ordered)
1196 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1202 * This routine disables all traffic on the adapter by issuing a
1203 * global reset on the MAC.
1206 dpaa2_dev_stop(struct rte_eth_dev *dev)
1208 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1209 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1211 struct rte_eth_link link;
1212 struct rte_intr_handle *intr_handle = dev->intr_handle;
1214 PMD_INIT_FUNC_TRACE();
1216 /* reset interrupt callback */
1217 if (intr_handle && (intr_handle->fd) &&
1218 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1219 /*disable dpni irqs */
1220 dpaa2_eth_setup_irqs(dev, 0);
1222 /* disable vfio intr before callback unregister */
1223 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1225 /* Unregistering LSC interrupt handler */
1226 rte_intr_callback_unregister(intr_handle,
1227 dpaa2_interrupt_handler,
1231 dpaa2_dev_set_link_down(dev);
1233 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1235 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1240 /* clear the recorded link status */
1241 memset(&link, 0, sizeof(link));
1242 rte_eth_linkstatus_set(dev, &link);
1248 dpaa2_dev_close(struct rte_eth_dev *dev)
1250 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1251 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1253 struct rte_eth_link link;
1255 PMD_INIT_FUNC_TRACE();
1257 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1261 DPAA2_PMD_WARN("Already closed or not started");
1265 dpaa2_flow_clean(dev);
1266 /* Clean the device first */
1267 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1269 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1273 memset(&link, 0, sizeof(link));
1274 rte_eth_linkstatus_set(dev, &link);
1276 /* Free private queues memory */
1277 dpaa2_free_rx_tx_queues(dev);
1278 /* Close the device at underlying layer*/
1279 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1281 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1285 /* Free the allocated memory for ethernet private data and dpni*/
1287 dev->process_private = NULL;
1290 for (i = 0; i < MAX_TCS; i++)
1291 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1293 if (priv->extract.qos_extract_param)
1294 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1296 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1301 dpaa2_dev_promiscuous_enable(
1302 struct rte_eth_dev *dev)
1305 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1306 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1308 PMD_INIT_FUNC_TRACE();
1311 DPAA2_PMD_ERR("dpni is NULL");
1315 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1317 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1319 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1321 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1327 dpaa2_dev_promiscuous_disable(
1328 struct rte_eth_dev *dev)
1331 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1332 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1334 PMD_INIT_FUNC_TRACE();
1337 DPAA2_PMD_ERR("dpni is NULL");
1341 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1343 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1345 if (dev->data->all_multicast == 0) {
1346 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1347 priv->token, false);
1349 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1357 dpaa2_dev_allmulticast_enable(
1358 struct rte_eth_dev *dev)
1361 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1362 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1364 PMD_INIT_FUNC_TRACE();
1367 DPAA2_PMD_ERR("dpni is NULL");
1371 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1373 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1379 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1382 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1383 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1385 PMD_INIT_FUNC_TRACE();
1388 DPAA2_PMD_ERR("dpni is NULL");
1392 /* must remain on for all promiscuous */
1393 if (dev->data->promiscuous == 1)
1396 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1398 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1404 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1407 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1408 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1409 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1412 PMD_INIT_FUNC_TRACE();
1415 DPAA2_PMD_ERR("dpni is NULL");
1419 /* check that mtu is within the allowed range */
1420 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1423 if (frame_size > RTE_ETHER_MAX_LEN)
1424 dev->data->dev_conf.rxmode.offloads |=
1425 DEV_RX_OFFLOAD_JUMBO_FRAME;
1427 dev->data->dev_conf.rxmode.offloads &=
1428 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1430 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1432 /* Set the Max Rx frame length as 'mtu' +
1433 * Maximum Ethernet header length
1435 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1436 frame_size - RTE_ETHER_CRC_LEN);
1438 DPAA2_PMD_ERR("Setting the max frame length failed");
1441 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1446 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1447 struct rte_ether_addr *addr,
1448 __rte_unused uint32_t index,
1449 __rte_unused uint32_t pool)
1452 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1453 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1455 PMD_INIT_FUNC_TRACE();
1458 DPAA2_PMD_ERR("dpni is NULL");
1462 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1463 addr->addr_bytes, 0, 0, 0);
1466 "error: Adding the MAC ADDR failed: err = %d", ret);
1471 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1475 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1476 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1477 struct rte_eth_dev_data *data = dev->data;
1478 struct rte_ether_addr *macaddr;
1480 PMD_INIT_FUNC_TRACE();
1482 macaddr = &data->mac_addrs[index];
1485 DPAA2_PMD_ERR("dpni is NULL");
1489 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1490 priv->token, macaddr->addr_bytes);
1493 "error: Removing the MAC ADDR failed: err = %d", ret);
1497 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1498 struct rte_ether_addr *addr)
1501 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1502 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1504 PMD_INIT_FUNC_TRACE();
1507 DPAA2_PMD_ERR("dpni is NULL");
1511 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1512 priv->token, addr->addr_bytes);
1516 "error: Setting the MAC ADDR failed %d", ret);
1522 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1523 struct rte_eth_stats *stats)
1525 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1526 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1528 uint8_t page0 = 0, page1 = 1, page2 = 2;
1529 union dpni_statistics value;
1531 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1533 memset(&value, 0, sizeof(union dpni_statistics));
1535 PMD_INIT_FUNC_TRACE();
1538 DPAA2_PMD_ERR("dpni is NULL");
1543 DPAA2_PMD_ERR("stats is NULL");
1547 /*Get Counters from page_0*/
1548 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1553 stats->ipackets = value.page_0.ingress_all_frames;
1554 stats->ibytes = value.page_0.ingress_all_bytes;
1556 /*Get Counters from page_1*/
1557 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1562 stats->opackets = value.page_1.egress_all_frames;
1563 stats->obytes = value.page_1.egress_all_bytes;
1565 /*Get Counters from page_2*/
1566 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1571 /* Ingress drop frame count due to configured rules */
1572 stats->ierrors = value.page_2.ingress_filtered_frames;
1573 /* Ingress drop frame count due to error */
1574 stats->ierrors += value.page_2.ingress_discarded_frames;
1576 stats->oerrors = value.page_2.egress_discarded_frames;
1577 stats->imissed = value.page_2.ingress_nobuffer_discards;
1579 /* Fill in per queue stats */
1580 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1581 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1582 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1583 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1585 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1587 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1589 /* Byte counting is not implemented */
1590 stats->q_ibytes[i] = 0;
1591 stats->q_obytes[i] = 0;
1597 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1602 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1605 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1606 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1608 union dpni_statistics value[5] = {};
1609 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1617 /* Get Counters from page_0*/
1618 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1623 /* Get Counters from page_1*/
1624 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1629 /* Get Counters from page_2*/
1630 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1635 for (i = 0; i < priv->max_cgs; i++) {
1636 if (!priv->cgid_in_use[i]) {
1637 /* Get Counters from page_4*/
1638 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1647 for (i = 0; i < num; i++) {
1649 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1650 raw.counter[dpaa2_xstats_strings[i].stats_id];
1654 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1659 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1660 struct rte_eth_xstat_name *xstats_names,
1663 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1665 if (limit < stat_cnt)
1668 if (xstats_names != NULL)
1669 for (i = 0; i < stat_cnt; i++)
1670 strlcpy(xstats_names[i].name,
1671 dpaa2_xstats_strings[i].name,
1672 sizeof(xstats_names[i].name));
1678 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1679 uint64_t *values, unsigned int n)
1681 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1682 uint64_t values_copy[stat_cnt];
1685 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1686 struct fsl_mc_io *dpni =
1687 (struct fsl_mc_io *)dev->process_private;
1689 union dpni_statistics value[5] = {};
1697 /* Get Counters from page_0*/
1698 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1703 /* Get Counters from page_1*/
1704 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1709 /* Get Counters from page_2*/
1710 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1715 /* Get Counters from page_4*/
1716 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1721 for (i = 0; i < stat_cnt; i++) {
1722 values[i] = value[dpaa2_xstats_strings[i].page_id].
1723 raw.counter[dpaa2_xstats_strings[i].stats_id];
1728 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1730 for (i = 0; i < n; i++) {
1731 if (ids[i] >= stat_cnt) {
1732 DPAA2_PMD_ERR("xstats id value isn't valid");
1735 values[i] = values_copy[ids[i]];
1741 dpaa2_xstats_get_names_by_id(
1742 struct rte_eth_dev *dev,
1743 struct rte_eth_xstat_name *xstats_names,
1744 const uint64_t *ids,
1747 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1748 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1751 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1753 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1755 for (i = 0; i < limit; i++) {
1756 if (ids[i] >= stat_cnt) {
1757 DPAA2_PMD_ERR("xstats id value isn't valid");
1760 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1766 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1768 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1769 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1772 struct dpaa2_queue *dpaa2_q;
1774 PMD_INIT_FUNC_TRACE();
1777 DPAA2_PMD_ERR("dpni is NULL");
1781 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1785 /* Reset the per queue stats in dpaa2_queue structure */
1786 for (i = 0; i < priv->nb_rx_queues; i++) {
1787 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1789 dpaa2_q->rx_pkts = 0;
1792 for (i = 0; i < priv->nb_tx_queues; i++) {
1793 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1795 dpaa2_q->tx_pkts = 0;
1801 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1805 /* return 0 means link status changed, -1 means not changed */
1807 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1808 int wait_to_complete __rte_unused)
1811 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1812 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1813 struct rte_eth_link link;
1814 struct dpni_link_state state = {0};
1817 DPAA2_PMD_ERR("dpni is NULL");
1821 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1823 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1827 memset(&link, 0, sizeof(struct rte_eth_link));
1828 link.link_status = state.up;
1829 link.link_speed = state.rate;
1831 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1832 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1834 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1836 ret = rte_eth_linkstatus_set(dev, &link);
1838 DPAA2_PMD_DEBUG("No change in status");
1840 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1841 link.link_status ? "Up" : "Down");
1847 * Toggle the DPNI to enable, if not already enabled.
1848 * This is not strictly PHY up/down - it is more of logical toggling.
1851 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1854 struct dpaa2_dev_priv *priv;
1855 struct fsl_mc_io *dpni;
1857 struct dpni_link_state state = {0};
1859 priv = dev->data->dev_private;
1860 dpni = (struct fsl_mc_io *)dev->process_private;
1863 DPAA2_PMD_ERR("dpni is NULL");
1867 /* Check if DPNI is currently enabled */
1868 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1870 /* Unable to obtain dpni status; Not continuing */
1871 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1875 /* Enable link if not already enabled */
1877 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1879 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1883 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1885 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1889 /* changing tx burst function to start enqueues */
1890 dev->tx_pkt_burst = dpaa2_dev_tx;
1891 dev->data->dev_link.link_status = state.up;
1892 dev->data->dev_link.link_speed = state.rate;
1895 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1897 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1902 * Toggle the DPNI to disable, if not already disabled.
1903 * This is not strictly PHY up/down - it is more of logical toggling.
1906 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1909 struct dpaa2_dev_priv *priv;
1910 struct fsl_mc_io *dpni;
1911 int dpni_enabled = 0;
1914 PMD_INIT_FUNC_TRACE();
1916 priv = dev->data->dev_private;
1917 dpni = (struct fsl_mc_io *)dev->process_private;
1920 DPAA2_PMD_ERR("Device has not yet been configured");
1924 /*changing tx burst function to avoid any more enqueues */
1925 dev->tx_pkt_burst = dummy_dev_tx;
1927 /* Loop while dpni_disable() attempts to drain the egress FQs
1928 * and confirm them back to us.
1931 ret = dpni_disable(dpni, 0, priv->token);
1933 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1936 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1938 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1942 /* Allow the MC some slack */
1943 rte_delay_us(100 * 1000);
1944 } while (dpni_enabled && --retries);
1947 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1948 /* todo- we may have to manually cleanup queues.
1951 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1952 dev->data->port_id);
1955 dev->data->dev_link.link_status = 0;
1961 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1964 struct dpaa2_dev_priv *priv;
1965 struct fsl_mc_io *dpni;
1966 struct dpni_link_state state = {0};
1968 PMD_INIT_FUNC_TRACE();
1970 priv = dev->data->dev_private;
1971 dpni = (struct fsl_mc_io *)dev->process_private;
1973 if (dpni == NULL || fc_conf == NULL) {
1974 DPAA2_PMD_ERR("device not configured");
1978 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1980 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1984 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1985 if (state.options & DPNI_LINK_OPT_PAUSE) {
1986 /* DPNI_LINK_OPT_PAUSE set
1987 * if ASYM_PAUSE not set,
1988 * RX Side flow control (handle received Pause frame)
1989 * TX side flow control (send Pause frame)
1990 * if ASYM_PAUSE set,
1991 * RX Side flow control (handle received Pause frame)
1992 * No TX side flow control (send Pause frame disabled)
1994 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1995 fc_conf->mode = RTE_FC_FULL;
1997 fc_conf->mode = RTE_FC_RX_PAUSE;
1999 /* DPNI_LINK_OPT_PAUSE not set
2000 * if ASYM_PAUSE set,
2001 * TX side flow control (send Pause frame)
2002 * No RX side flow control (No action on pause frame rx)
2003 * if ASYM_PAUSE not set,
2004 * Flow control disabled
2006 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2007 fc_conf->mode = RTE_FC_TX_PAUSE;
2009 fc_conf->mode = RTE_FC_NONE;
2016 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2019 struct dpaa2_dev_priv *priv;
2020 struct fsl_mc_io *dpni;
2021 struct dpni_link_state state = {0};
2022 struct dpni_link_cfg cfg = {0};
2024 PMD_INIT_FUNC_TRACE();
2026 priv = dev->data->dev_private;
2027 dpni = (struct fsl_mc_io *)dev->process_private;
2030 DPAA2_PMD_ERR("dpni is NULL");
2034 /* It is necessary to obtain the current state before setting fc_conf
2035 * as MC would return error in case rate, autoneg or duplex values are
2038 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2040 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2044 /* Disable link before setting configuration */
2045 dpaa2_dev_set_link_down(dev);
2047 /* Based on fc_conf, update cfg */
2048 cfg.rate = state.rate;
2049 cfg.options = state.options;
2051 /* update cfg with fc_conf */
2052 switch (fc_conf->mode) {
2054 /* Full flow control;
2055 * OPT_PAUSE set, ASYM_PAUSE not set
2057 cfg.options |= DPNI_LINK_OPT_PAUSE;
2058 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2060 case RTE_FC_TX_PAUSE:
2061 /* Enable RX flow control
2062 * OPT_PAUSE not set;
2065 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2066 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2068 case RTE_FC_RX_PAUSE:
2069 /* Enable TX Flow control
2073 cfg.options |= DPNI_LINK_OPT_PAUSE;
2074 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2077 /* Disable Flow control
2079 * ASYM_PAUSE not set
2081 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2082 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2085 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2090 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2092 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2096 dpaa2_dev_set_link_up(dev);
2102 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2103 struct rte_eth_rss_conf *rss_conf)
2105 struct rte_eth_dev_data *data = dev->data;
2106 struct dpaa2_dev_priv *priv = data->dev_private;
2107 struct rte_eth_conf *eth_conf = &data->dev_conf;
2110 PMD_INIT_FUNC_TRACE();
2112 if (rss_conf->rss_hf) {
2113 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2114 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2117 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2123 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2124 ret = dpaa2_remove_flow_dist(dev, tc_index);
2127 "Unable to remove flow dist on tc%d",
2133 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2138 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2139 struct rte_eth_rss_conf *rss_conf)
2141 struct rte_eth_dev_data *data = dev->data;
2142 struct rte_eth_conf *eth_conf = &data->dev_conf;
2144 /* dpaa2 does not support rss_key, so length should be 0*/
2145 rss_conf->rss_key_len = 0;
2146 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2150 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2151 int eth_rx_queue_id,
2152 struct dpaa2_dpcon_dev *dpcon,
2153 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2155 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2156 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2157 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2158 uint8_t flow_id = dpaa2_ethq->flow_id;
2159 struct dpni_queue cfg;
2160 uint8_t options, priority;
2163 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2164 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2165 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2166 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2167 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2168 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2172 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2173 (dpcon->num_priorities - 1);
2175 memset(&cfg, 0, sizeof(struct dpni_queue));
2176 options = DPNI_QUEUE_OPT_DEST;
2177 cfg.destination.type = DPNI_DEST_DPCON;
2178 cfg.destination.id = dpcon->dpcon_id;
2179 cfg.destination.priority = priority;
2181 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2182 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2183 cfg.destination.hold_active = 1;
2186 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2187 !eth_priv->en_ordered) {
2188 struct opr_cfg ocfg;
2190 /* Restoration window size = 256 frames */
2192 /* Restoration window size = 512 frames for LX2 */
2193 if (dpaa2_svr_family == SVR_LX2160A)
2195 /* Auto advance NESN window enabled */
2197 /* Late arrival window size disabled */
2199 /* ORL resource exhaustaion advance NESN disabled */
2201 /* Loose ordering enabled */
2203 eth_priv->en_loose_ordered = 1;
2204 /* Strict ordering enabled if explicitly set */
2205 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2207 eth_priv->en_loose_ordered = 0;
2210 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2211 dpaa2_ethq->tc_index, flow_id,
2212 OPR_OPT_CREATE, &ocfg);
2214 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2218 eth_priv->en_ordered = 1;
2221 options |= DPNI_QUEUE_OPT_USER_CTX;
2222 cfg.user_context = (size_t)(dpaa2_ethq);
2224 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2225 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2227 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2231 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2236 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2237 int eth_rx_queue_id)
2239 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2240 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2241 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2242 uint8_t flow_id = dpaa2_ethq->flow_id;
2243 struct dpni_queue cfg;
2247 memset(&cfg, 0, sizeof(struct dpni_queue));
2248 options = DPNI_QUEUE_OPT_DEST;
2249 cfg.destination.type = DPNI_DEST_NONE;
2251 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2252 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2254 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2260 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2264 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2265 if (dpaa2_supported_filter_ops[i] == filter_op)
2272 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2273 enum rte_filter_type filter_type,
2274 enum rte_filter_op filter_op,
2282 switch (filter_type) {
2283 case RTE_ETH_FILTER_GENERIC:
2284 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2288 *(const void **)arg = &dpaa2_flow_ops;
2289 dpaa2_filter_type |= filter_type;
2292 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2301 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2302 struct rte_eth_rxq_info *qinfo)
2304 struct dpaa2_queue *rxq;
2306 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2308 qinfo->mp = rxq->mb_pool;
2309 qinfo->scattered_rx = dev->data->scattered_rx;
2310 qinfo->nb_desc = rxq->nb_desc;
2312 qinfo->conf.rx_free_thresh = 1;
2313 qinfo->conf.rx_drop_en = 1;
2314 qinfo->conf.rx_deferred_start = 0;
2315 qinfo->conf.offloads = rxq->offloads;
2319 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2320 struct rte_eth_txq_info *qinfo)
2322 struct dpaa2_queue *txq;
2324 txq = dev->data->tx_queues[queue_id];
2326 qinfo->nb_desc = txq->nb_desc;
2327 qinfo->conf.tx_thresh.pthresh = 0;
2328 qinfo->conf.tx_thresh.hthresh = 0;
2329 qinfo->conf.tx_thresh.wthresh = 0;
2331 qinfo->conf.tx_free_thresh = 0;
2332 qinfo->conf.tx_rs_thresh = 0;
2333 qinfo->conf.offloads = txq->offloads;
2334 qinfo->conf.tx_deferred_start = 0;
2337 static struct eth_dev_ops dpaa2_ethdev_ops = {
2338 .dev_configure = dpaa2_eth_dev_configure,
2339 .dev_start = dpaa2_dev_start,
2340 .dev_stop = dpaa2_dev_stop,
2341 .dev_close = dpaa2_dev_close,
2342 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2343 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2344 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2345 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2346 .dev_set_link_up = dpaa2_dev_set_link_up,
2347 .dev_set_link_down = dpaa2_dev_set_link_down,
2348 .link_update = dpaa2_dev_link_update,
2349 .stats_get = dpaa2_dev_stats_get,
2350 .xstats_get = dpaa2_dev_xstats_get,
2351 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2352 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2353 .xstats_get_names = dpaa2_xstats_get_names,
2354 .stats_reset = dpaa2_dev_stats_reset,
2355 .xstats_reset = dpaa2_dev_stats_reset,
2356 .fw_version_get = dpaa2_fw_version_get,
2357 .dev_infos_get = dpaa2_dev_info_get,
2358 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2359 .mtu_set = dpaa2_dev_mtu_set,
2360 .vlan_filter_set = dpaa2_vlan_filter_set,
2361 .vlan_offload_set = dpaa2_vlan_offload_set,
2362 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2363 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2364 .rx_queue_release = dpaa2_dev_rx_queue_release,
2365 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2366 .tx_queue_release = dpaa2_dev_tx_queue_release,
2367 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2368 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2369 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2370 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2371 .mac_addr_add = dpaa2_dev_add_mac_addr,
2372 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2373 .mac_addr_set = dpaa2_dev_set_mac_addr,
2374 .rss_hash_update = dpaa2_dev_rss_hash_update,
2375 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2376 .filter_ctrl = dpaa2_dev_flow_ctrl,
2377 .rxq_info_get = dpaa2_rxq_info_get,
2378 .txq_info_get = dpaa2_txq_info_get,
2379 #if defined(RTE_LIBRTE_IEEE1588)
2380 .timesync_enable = dpaa2_timesync_enable,
2381 .timesync_disable = dpaa2_timesync_disable,
2382 .timesync_read_time = dpaa2_timesync_read_time,
2383 .timesync_write_time = dpaa2_timesync_write_time,
2384 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2385 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2386 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2390 /* Populate the mac address from physically available (u-boot/firmware) and/or
2391 * one set by higher layers like MC (restool) etc.
2392 * Returns the table of MAC entries (multiple entries)
2395 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2396 struct rte_ether_addr *mac_entry)
2399 struct rte_ether_addr phy_mac, prime_mac;
2401 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2402 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2404 /* Get the physical device MAC address */
2405 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2406 phy_mac.addr_bytes);
2408 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2412 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2413 prime_mac.addr_bytes);
2415 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2419 /* Now that both MAC have been obtained, do:
2420 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2422 * If empty_mac(phy), return prime.
2423 * if both are empty, create random MAC, set as prime and return
2425 if (!rte_is_zero_ether_addr(&phy_mac)) {
2426 /* If the addresses are not same, overwrite prime */
2427 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2428 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2430 phy_mac.addr_bytes);
2432 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2436 memcpy(&prime_mac, &phy_mac,
2437 sizeof(struct rte_ether_addr));
2439 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2440 /* In case phys and prime, both are zero, create random MAC */
2441 rte_eth_random_addr(prime_mac.addr_bytes);
2442 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2444 prime_mac.addr_bytes);
2446 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2451 /* prime_mac the final MAC address */
2452 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2460 check_devargs_handler(__rte_unused const char *key, const char *value,
2461 __rte_unused void *opaque)
2463 if (strcmp(value, "1"))
2470 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2472 struct rte_kvargs *kvlist;
2477 kvlist = rte_kvargs_parse(devargs->args, NULL);
2481 if (!rte_kvargs_count(kvlist, key)) {
2482 rte_kvargs_free(kvlist);
2486 if (rte_kvargs_process(kvlist, key,
2487 check_devargs_handler, NULL) < 0) {
2488 rte_kvargs_free(kvlist);
2491 rte_kvargs_free(kvlist);
2497 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2499 struct rte_device *dev = eth_dev->device;
2500 struct rte_dpaa2_device *dpaa2_dev;
2501 struct fsl_mc_io *dpni_dev;
2502 struct dpni_attr attr;
2503 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2504 struct dpni_buffer_layout layout;
2507 PMD_INIT_FUNC_TRACE();
2509 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2511 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2514 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2515 eth_dev->process_private = (void *)dpni_dev;
2517 /* For secondary processes, the primary has done all the work */
2518 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2519 /* In case of secondary, only burst and ops API need to be
2522 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2523 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2524 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2525 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2526 else if (dpaa2_get_devargs(dev->devargs,
2527 DRIVER_NO_PREFETCH_MODE))
2528 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2530 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2531 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2535 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2537 hw_id = dpaa2_dev->object_id;
2538 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2541 "Failure in opening dpni@%d with err code %d",
2547 /* Clean the device first */
2548 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2550 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2555 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2558 "Failure in get dpni@%d attribute, err code %d",
2563 priv->num_rx_tc = attr.num_rx_tcs;
2564 priv->qos_entries = attr.qos_entries;
2565 priv->fs_entries = attr.fs_entries;
2566 priv->dist_queues = attr.num_queues;
2568 /* only if the custom CG is enabled */
2569 if (attr.options & DPNI_OPT_CUSTOM_CG)
2570 priv->max_cgs = attr.num_cgs;
2574 for (i = 0; i < priv->max_cgs; i++)
2575 priv->cgid_in_use[i] = 0;
2577 for (i = 0; i < attr.num_rx_tcs; i++)
2578 priv->nb_rx_queues += attr.num_queues;
2580 /* Using number of TX queues as number of TX TCs */
2581 priv->nb_tx_queues = attr.num_tx_tcs;
2583 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2584 priv->num_rx_tc, priv->nb_rx_queues,
2585 priv->nb_tx_queues, priv->max_cgs);
2587 priv->hw = dpni_dev;
2588 priv->hw_id = hw_id;
2589 priv->options = attr.options;
2590 priv->max_mac_filters = attr.mac_filter_entries;
2591 priv->max_vlan_filters = attr.vlan_filter_entries;
2593 #if defined(RTE_LIBRTE_IEEE1588)
2594 priv->tx_conf_en = 1;
2596 priv->tx_conf_en = 0;
2599 /* Allocate memory for hardware structure for queues */
2600 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2602 DPAA2_PMD_ERR("Queue allocation Failed");
2606 /* Allocate memory for storing MAC addresses.
2607 * Table of mac_filter_entries size is allocated so that RTE ether lib
2608 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2610 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2611 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2612 if (eth_dev->data->mac_addrs == NULL) {
2614 "Failed to allocate %d bytes needed to store MAC addresses",
2615 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2620 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2622 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2623 rte_free(eth_dev->data->mac_addrs);
2624 eth_dev->data->mac_addrs = NULL;
2628 /* ... tx buffer layout ... */
2629 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2630 if (priv->tx_conf_en) {
2631 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2632 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2633 layout.pass_timestamp = true;
2635 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2637 layout.pass_frame_status = 1;
2638 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2639 DPNI_QUEUE_TX, &layout);
2641 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2645 /* ... tx-conf and error buffer layout ... */
2646 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2647 if (priv->tx_conf_en) {
2648 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2649 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2650 layout.pass_timestamp = true;
2652 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2654 layout.pass_frame_status = 1;
2655 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2656 DPNI_QUEUE_TX_CONFIRM, &layout);
2658 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2663 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2665 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2666 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2667 DPAA2_PMD_INFO("Loopback mode");
2668 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2669 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2670 DPAA2_PMD_INFO("No Prefetch mode");
2672 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2674 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2676 /*Init fields w.r.t. classficaition*/
2677 memset(&priv->extract.qos_key_extract, 0,
2678 sizeof(struct dpaa2_key_extract));
2679 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2680 if (!priv->extract.qos_extract_param) {
2681 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2682 " classificaiton ", ret);
2685 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2686 IP_ADDRESS_OFFSET_INVALID;
2687 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2688 IP_ADDRESS_OFFSET_INVALID;
2689 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2690 IP_ADDRESS_OFFSET_INVALID;
2691 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2692 IP_ADDRESS_OFFSET_INVALID;
2694 for (i = 0; i < MAX_TCS; i++) {
2695 memset(&priv->extract.tc_key_extract[i], 0,
2696 sizeof(struct dpaa2_key_extract));
2697 priv->extract.tc_extract_param[i] =
2698 (size_t)rte_malloc(NULL, 256, 64);
2699 if (!priv->extract.tc_extract_param[i]) {
2700 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2704 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2705 IP_ADDRESS_OFFSET_INVALID;
2706 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2707 IP_ADDRESS_OFFSET_INVALID;
2708 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2709 IP_ADDRESS_OFFSET_INVALID;
2710 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2711 IP_ADDRESS_OFFSET_INVALID;
2714 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2715 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2718 DPAA2_PMD_ERR("Unable to set mtu. check config");
2722 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2723 * with external entity to receive byte code for software sequence
2724 * and same will be offload to the H/W using MC interface.
2725 * Currently it is assumed that DPAA2 driver has byte code by some
2726 * mean and same if offloaded to H/W.
2728 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2729 WRIOP_SS_INITIALIZER(priv);
2730 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2732 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2737 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2740 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2745 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2748 dpaa2_dev_close(eth_dev);
2754 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2755 struct rte_dpaa2_device *dpaa2_dev)
2757 struct rte_eth_dev *eth_dev;
2758 struct dpaa2_dev_priv *dev_priv;
2761 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2762 RTE_PKTMBUF_HEADROOM) {
2764 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2765 RTE_PKTMBUF_HEADROOM,
2766 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2771 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2772 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2775 dev_priv = rte_zmalloc("ethdev private structure",
2776 sizeof(struct dpaa2_dev_priv),
2777 RTE_CACHE_LINE_SIZE);
2778 if (dev_priv == NULL) {
2780 "Unable to allocate memory for private data");
2781 rte_eth_dev_release_port(eth_dev);
2784 eth_dev->data->dev_private = (void *)dev_priv;
2785 /* Store a pointer to eth_dev in dev_private */
2786 dev_priv->eth_dev = eth_dev;
2787 dev_priv->tx_conf_en = 0;
2789 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2791 DPAA2_PMD_DEBUG("returning enodev");
2796 eth_dev->device = &dpaa2_dev->device;
2798 dpaa2_dev->eth_dev = eth_dev;
2799 eth_dev->data->rx_mbuf_alloc_failed = 0;
2801 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2802 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2804 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2806 /* Invoke PMD device initialization function */
2807 diag = dpaa2_dev_init(eth_dev);
2809 rte_eth_dev_probing_finish(eth_dev);
2813 rte_eth_dev_release_port(eth_dev);
2818 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2820 struct rte_eth_dev *eth_dev;
2823 eth_dev = dpaa2_dev->eth_dev;
2824 dpaa2_dev_close(eth_dev);
2825 ret = rte_eth_dev_release_port(eth_dev);
2830 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2831 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2832 .drv_type = DPAA2_ETH,
2833 .probe = rte_dpaa2_probe,
2834 .remove = rte_dpaa2_remove,
2837 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2838 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2839 DRIVER_LOOPBACK_MODE "=<int> "
2840 DRIVER_NO_PREFETCH_MODE "=<int>");
2841 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);