1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2021 NXP
12 #include <ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
34 #define DRIVER_TX_CONF "drv_tx_conf"
35 #define DRIVER_ERROR_QUEUE "drv_err_queue"
36 #define CHECK_INTERVAL 100 /* 100ms */
37 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
39 /* Supported Rx offloads */
40 static uint64_t dev_rx_offloads_sup =
41 DEV_RX_OFFLOAD_CHECKSUM |
42 DEV_RX_OFFLOAD_SCTP_CKSUM |
43 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
44 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
45 DEV_RX_OFFLOAD_VLAN_STRIP |
46 DEV_RX_OFFLOAD_VLAN_FILTER |
47 DEV_RX_OFFLOAD_JUMBO_FRAME |
48 DEV_RX_OFFLOAD_TIMESTAMP;
50 /* Rx offloads which cannot be disabled */
51 static uint64_t dev_rx_offloads_nodis =
52 DEV_RX_OFFLOAD_RSS_HASH |
53 DEV_RX_OFFLOAD_SCATTER;
55 /* Supported Tx offloads */
56 static uint64_t dev_tx_offloads_sup =
57 DEV_TX_OFFLOAD_VLAN_INSERT |
58 DEV_TX_OFFLOAD_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_UDP_CKSUM |
60 DEV_TX_OFFLOAD_TCP_CKSUM |
61 DEV_TX_OFFLOAD_SCTP_CKSUM |
62 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
63 DEV_TX_OFFLOAD_MT_LOCKFREE |
64 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
66 /* Tx offloads which cannot be disabled */
67 static uint64_t dev_tx_offloads_nodis =
68 DEV_TX_OFFLOAD_MULTI_SEGS;
70 /* enable timestamp in mbuf */
71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
72 uint64_t dpaa2_timestamp_rx_dynflag;
73 int dpaa2_timestamp_dynfield_offset = -1;
75 /* Enable error queue */
76 bool dpaa2_enable_err_queue;
78 struct rte_dpaa2_xstats_name_off {
79 char name[RTE_ETH_XSTATS_NAME_SIZE];
80 uint8_t page_id; /* dpni statistics page id */
81 uint8_t stats_id; /* stats id in the given page */
84 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
85 {"ingress_multicast_frames", 0, 2},
86 {"ingress_multicast_bytes", 0, 3},
87 {"ingress_broadcast_frames", 0, 4},
88 {"ingress_broadcast_bytes", 0, 5},
89 {"egress_multicast_frames", 1, 2},
90 {"egress_multicast_bytes", 1, 3},
91 {"egress_broadcast_frames", 1, 4},
92 {"egress_broadcast_bytes", 1, 5},
93 {"ingress_filtered_frames", 2, 0},
94 {"ingress_discarded_frames", 2, 1},
95 {"ingress_nobuffer_discards", 2, 2},
96 {"egress_discarded_frames", 2, 3},
97 {"egress_confirmed_frames", 2, 4},
98 {"cgr_reject_frames", 4, 0},
99 {"cgr_reject_bytes", 4, 1},
102 static struct rte_dpaa2_driver rte_dpaa2_pmd;
103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
104 int wait_to_complete);
105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
113 struct dpaa2_dev_priv *priv = dev->data->dev_private;
114 struct fsl_mc_io *dpni = dev->process_private;
116 PMD_INIT_FUNC_TRACE();
119 DPAA2_PMD_ERR("dpni is NULL");
124 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
127 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
128 priv->token, vlan_id);
131 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
132 ret, vlan_id, priv->hw_id);
138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
140 struct dpaa2_dev_priv *priv = dev->data->dev_private;
141 struct fsl_mc_io *dpni = dev->process_private;
144 PMD_INIT_FUNC_TRACE();
146 if (mask & ETH_VLAN_FILTER_MASK) {
147 /* VLAN Filter not avaialble */
148 if (!priv->max_vlan_filters) {
149 DPAA2_PMD_INFO("VLAN filter not available");
153 if (dev->data->dev_conf.rxmode.offloads &
154 DEV_RX_OFFLOAD_VLAN_FILTER)
155 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
158 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
161 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
169 enum rte_vlan_type vlan_type __rte_unused,
172 struct dpaa2_dev_priv *priv = dev->data->dev_private;
173 struct fsl_mc_io *dpni = dev->process_private;
176 PMD_INIT_FUNC_TRACE();
178 /* nothing to be done for standard vlan tpids */
179 if (tpid == 0x8100 || tpid == 0x88A8)
182 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
185 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
186 /* if already configured tpids, remove them first */
188 struct dpni_custom_tpid_cfg tpid_list = {0};
190 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
191 priv->token, &tpid_list);
194 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
195 priv->token, tpid_list.tpid1);
198 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
206 dpaa2_fw_version_get(struct rte_eth_dev *dev,
211 struct fsl_mc_io *dpni = dev->process_private;
212 struct mc_soc_version mc_plat_info = {0};
213 struct mc_version mc_ver_info = {0};
215 PMD_INIT_FUNC_TRACE();
217 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
218 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
220 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
221 DPAA2_PMD_WARN("\tmc_get_version failed");
223 ret = snprintf(fw_version, fw_size,
228 mc_ver_info.revision);
232 ret += 1; /* add the size of '\0' */
233 if (fw_size < (size_t)ret)
240 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
242 struct dpaa2_dev_priv *priv = dev->data->dev_private;
244 PMD_INIT_FUNC_TRACE();
246 dev_info->max_mac_addrs = priv->max_mac_filters;
247 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
248 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
249 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
250 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
251 dev_info->rx_offload_capa = dev_rx_offloads_sup |
252 dev_rx_offloads_nodis;
253 dev_info->tx_offload_capa = dev_tx_offloads_sup |
254 dev_tx_offloads_nodis;
255 dev_info->speed_capa = ETH_LINK_SPEED_1G |
256 ETH_LINK_SPEED_2_5G |
259 dev_info->max_hash_mac_addrs = 0;
260 dev_info->max_vfs = 0;
261 dev_info->max_vmdq_pools = ETH_16_POOLS;
262 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
264 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
265 /* same is rx size for best perf */
266 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
268 dev_info->default_rxportconf.nb_queues = 1;
269 dev_info->default_txportconf.nb_queues = 1;
270 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
271 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
273 if (dpaa2_svr_family == SVR_LX2160A) {
274 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
284 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
285 __rte_unused uint16_t queue_id,
286 struct rte_eth_burst_mode *mode)
288 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
291 const struct burst_info {
294 } rx_offload_map[] = {
295 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
296 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
297 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
298 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
299 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
300 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
301 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
302 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
303 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
304 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
307 /* Update Rx offload info */
308 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
309 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
310 snprintf(mode->info, sizeof(mode->info), "%s",
311 rx_offload_map[i].output);
320 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
321 __rte_unused uint16_t queue_id,
322 struct rte_eth_burst_mode *mode)
324 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
327 const struct burst_info {
330 } tx_offload_map[] = {
331 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
332 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
333 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
334 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
335 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
336 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
337 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
338 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
339 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
342 /* Update Tx offload info */
343 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
344 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
345 snprintf(mode->info, sizeof(mode->info), "%s",
346 tx_offload_map[i].output);
355 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
357 struct dpaa2_dev_priv *priv = dev->data->dev_private;
360 uint8_t num_rxqueue_per_tc;
361 struct dpaa2_queue *mc_q, *mcq;
364 struct dpaa2_queue *dpaa2_q;
366 PMD_INIT_FUNC_TRACE();
368 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
369 if (priv->flags & DPAA2_TX_CONF_ENABLE)
370 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
372 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
373 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
374 RTE_CACHE_LINE_SIZE);
376 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
380 for (i = 0; i < priv->nb_rx_queues; i++) {
381 mc_q->eth_data = dev->data;
382 priv->rx_vq[i] = mc_q++;
383 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
384 dpaa2_q->q_storage = rte_malloc("dq_storage",
385 sizeof(struct queue_storage_info_t),
386 RTE_CACHE_LINE_SIZE);
387 if (!dpaa2_q->q_storage)
390 memset(dpaa2_q->q_storage, 0,
391 sizeof(struct queue_storage_info_t));
392 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
396 if (dpaa2_enable_err_queue) {
397 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
398 sizeof(struct dpaa2_queue), 0);
400 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
401 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
402 sizeof(struct queue_storage_info_t) *
404 RTE_CACHE_LINE_SIZE);
405 if (!dpaa2_q->q_storage)
408 memset(dpaa2_q->q_storage, 0,
409 sizeof(struct queue_storage_info_t));
410 for (i = 0; i < RTE_MAX_LCORE; i++)
411 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
415 for (i = 0; i < priv->nb_tx_queues; i++) {
416 mc_q->eth_data = dev->data;
417 mc_q->flow_id = 0xffff;
418 priv->tx_vq[i] = mc_q++;
419 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
420 dpaa2_q->cscn = rte_malloc(NULL,
421 sizeof(struct qbman_result), 16);
426 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
427 /*Setup tx confirmation queues*/
428 for (i = 0; i < priv->nb_tx_queues; i++) {
429 mc_q->eth_data = dev->data;
432 priv->tx_conf_vq[i] = mc_q++;
433 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
435 rte_malloc("dq_storage",
436 sizeof(struct queue_storage_info_t),
437 RTE_CACHE_LINE_SIZE);
438 if (!dpaa2_q->q_storage)
441 memset(dpaa2_q->q_storage, 0,
442 sizeof(struct queue_storage_info_t));
443 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
449 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
450 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
451 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
452 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
460 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
461 rte_free(dpaa2_q->q_storage);
462 priv->tx_conf_vq[i--] = NULL;
464 i = priv->nb_tx_queues;
468 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
469 rte_free(dpaa2_q->cscn);
470 priv->tx_vq[i--] = NULL;
472 i = priv->nb_rx_queues;
475 mc_q = priv->rx_vq[0];
477 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
478 dpaa2_free_dq_storage(dpaa2_q->q_storage);
479 rte_free(dpaa2_q->q_storage);
480 priv->rx_vq[i--] = NULL;
483 if (dpaa2_enable_err_queue) {
484 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
485 if (dpaa2_q->q_storage)
486 dpaa2_free_dq_storage(dpaa2_q->q_storage);
487 rte_free(dpaa2_q->q_storage);
495 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
497 struct dpaa2_dev_priv *priv = dev->data->dev_private;
498 struct dpaa2_queue *dpaa2_q;
501 PMD_INIT_FUNC_TRACE();
503 /* Queue allocation base */
504 if (priv->rx_vq[0]) {
505 /* cleaning up queue storage */
506 for (i = 0; i < priv->nb_rx_queues; i++) {
507 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
508 if (dpaa2_q->q_storage)
509 rte_free(dpaa2_q->q_storage);
511 /* cleanup tx queue cscn */
512 for (i = 0; i < priv->nb_tx_queues; i++) {
513 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
514 rte_free(dpaa2_q->cscn);
516 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
517 /* cleanup tx conf queue storage */
518 for (i = 0; i < priv->nb_tx_queues; i++) {
519 dpaa2_q = (struct dpaa2_queue *)
521 rte_free(dpaa2_q->q_storage);
524 /*free memory for all queues (RX+TX) */
525 rte_free(priv->rx_vq[0]);
526 priv->rx_vq[0] = NULL;
531 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
533 struct dpaa2_dev_priv *priv = dev->data->dev_private;
534 struct fsl_mc_io *dpni = dev->process_private;
535 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
536 uint64_t rx_offloads = eth_conf->rxmode.offloads;
537 uint64_t tx_offloads = eth_conf->txmode.offloads;
538 int rx_l3_csum_offload = false;
539 int rx_l4_csum_offload = false;
540 int tx_l3_csum_offload = false;
541 int tx_l4_csum_offload = false;
544 PMD_INIT_FUNC_TRACE();
546 /* Rx offloads which are enabled by default */
547 if (dev_rx_offloads_nodis & ~rx_offloads) {
549 "Some of rx offloads enabled by default - requested 0x%" PRIx64
550 " fixed are 0x%" PRIx64,
551 rx_offloads, dev_rx_offloads_nodis);
554 /* Tx offloads which are enabled by default */
555 if (dev_tx_offloads_nodis & ~tx_offloads) {
557 "Some of tx offloads enabled by default - requested 0x%" PRIx64
558 " fixed are 0x%" PRIx64,
559 tx_offloads, dev_tx_offloads_nodis);
562 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
563 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
564 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
565 priv->token, eth_conf->rxmode.max_rx_pkt_len
566 - RTE_ETHER_CRC_LEN);
569 "Unable to set mtu. check config");
573 dev->data->dev_conf.rxmode.max_rx_pkt_len -
574 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
581 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
582 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
583 ret = dpaa2_setup_flow_dist(dev,
584 eth_conf->rx_adv_conf.rss_conf.rss_hf,
588 "Unable to set flow distribution on tc%d."
589 "Check queue config", tc_index);
595 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
596 rx_l3_csum_offload = true;
598 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
599 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
600 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
601 rx_l4_csum_offload = true;
603 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
604 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
606 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
610 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
611 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
613 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
617 #if !defined(RTE_LIBRTE_IEEE1588)
618 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
621 ret = rte_mbuf_dyn_rx_timestamp_register(
622 &dpaa2_timestamp_dynfield_offset,
623 &dpaa2_timestamp_rx_dynflag);
625 DPAA2_PMD_ERR("Error to register timestamp field/flag");
628 dpaa2_enable_ts[dev->data->port_id] = true;
631 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
632 tx_l3_csum_offload = true;
634 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
635 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
636 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
637 tx_l4_csum_offload = true;
639 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
640 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
642 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
646 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
647 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
649 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
653 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
654 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
655 * to 0 for LS2 in the hardware thus disabling data/annotation
656 * stashing. For LX2 this is fixed in hardware and thus hash result and
657 * parse results can be received in FD using this option.
659 if (dpaa2_svr_family == SVR_LX2160A) {
660 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
661 DPNI_FLCTYPE_HASH, true);
663 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
668 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
669 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
676 /* Function to setup RX flow information. It contains traffic class ID,
677 * flow ID, destination configuration etc.
680 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
681 uint16_t rx_queue_id,
683 unsigned int socket_id __rte_unused,
684 const struct rte_eth_rxconf *rx_conf,
685 struct rte_mempool *mb_pool)
687 struct dpaa2_dev_priv *priv = dev->data->dev_private;
688 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
689 struct dpaa2_queue *dpaa2_q;
690 struct dpni_queue cfg;
696 PMD_INIT_FUNC_TRACE();
698 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
699 dev, rx_queue_id, mb_pool, rx_conf);
701 /* Rx deferred start is not supported */
702 if (rx_conf->rx_deferred_start) {
703 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
708 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
709 bpid = mempool_to_bpid(mb_pool);
710 ret = dpaa2_attach_bp_list(priv,
711 rte_dpaa2_bpid_info[bpid].bp_list);
715 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
716 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
717 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
718 dpaa2_q->nb_desc = UINT16_MAX;
719 dpaa2_q->offloads = rx_conf->offloads;
721 /*Get the flow id from given VQ id*/
722 flow_id = dpaa2_q->flow_id;
723 memset(&cfg, 0, sizeof(struct dpni_queue));
725 options = options | DPNI_QUEUE_OPT_USER_CTX;
726 cfg.user_context = (size_t)(dpaa2_q);
728 /* check if a private cgr available. */
729 for (i = 0; i < priv->max_cgs; i++) {
730 if (!priv->cgid_in_use[i]) {
731 priv->cgid_in_use[i] = 1;
736 if (i < priv->max_cgs) {
737 options |= DPNI_QUEUE_OPT_SET_CGID;
739 dpaa2_q->cgid = cfg.cgid;
741 dpaa2_q->cgid = 0xff;
744 /*if ls2088 or rev2 device, enable the stashing */
746 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
747 options |= DPNI_QUEUE_OPT_FLC;
748 cfg.flc.stash_control = true;
749 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
750 /* 00 00 00 - last 6 bit represent annotation, context stashing,
751 * data stashing setting 01 01 00 (0x14)
752 * (in following order ->DS AS CS)
753 * to enable 1 line data, 1 line annotation.
754 * For LX2, this setting should be 01 00 00 (0x10)
756 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
757 cfg.flc.value |= 0x10;
759 cfg.flc.value |= 0x14;
761 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
762 dpaa2_q->tc_index, flow_id, options, &cfg);
764 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
768 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
769 struct dpni_taildrop taildrop;
772 dpaa2_q->nb_desc = nb_rx_desc;
773 /* Private CGR will use tail drop length as nb_rx_desc.
774 * for rest cases we can use standard byte based tail drop.
775 * There is no HW restriction, but number of CGRs are limited,
776 * hence this restriction is placed.
778 if (dpaa2_q->cgid != 0xff) {
779 /*enabling per rx queue congestion control */
780 taildrop.threshold = nb_rx_desc;
781 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
783 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
785 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
786 DPNI_CP_CONGESTION_GROUP,
789 dpaa2_q->cgid, &taildrop);
791 /*enabling per rx queue congestion control */
792 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
793 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
794 taildrop.oal = CONG_RX_OAL;
795 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
797 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
798 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
799 dpaa2_q->tc_index, flow_id,
803 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
807 } else { /* Disable tail Drop */
808 struct dpni_taildrop taildrop = {0};
809 DPAA2_PMD_INFO("Tail drop is disabled on queue");
812 if (dpaa2_q->cgid != 0xff) {
813 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
814 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
816 dpaa2_q->cgid, &taildrop);
818 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
819 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
820 dpaa2_q->tc_index, flow_id, &taildrop);
823 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
829 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
834 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
835 uint16_t tx_queue_id,
837 unsigned int socket_id __rte_unused,
838 const struct rte_eth_txconf *tx_conf)
840 struct dpaa2_dev_priv *priv = dev->data->dev_private;
841 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
842 priv->tx_vq[tx_queue_id];
843 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
844 priv->tx_conf_vq[tx_queue_id];
845 struct fsl_mc_io *dpni = dev->process_private;
846 struct dpni_queue tx_conf_cfg;
847 struct dpni_queue tx_flow_cfg;
848 uint8_t options = 0, flow_id;
849 struct dpni_queue_id qid;
853 PMD_INIT_FUNC_TRACE();
855 /* Tx deferred start is not supported */
856 if (tx_conf->tx_deferred_start) {
857 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
862 dpaa2_q->nb_desc = UINT16_MAX;
863 dpaa2_q->offloads = tx_conf->offloads;
865 /* Return if queue already configured */
866 if (dpaa2_q->flow_id != 0xffff) {
867 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
871 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
872 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
877 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
878 tc_id, flow_id, options, &tx_flow_cfg);
880 DPAA2_PMD_ERR("Error in setting the tx flow: "
881 "tc_id=%d, flow=%d err=%d",
882 tc_id, flow_id, ret);
886 dpaa2_q->flow_id = flow_id;
888 if (tx_queue_id == 0) {
889 /*Set tx-conf and error configuration*/
890 if (priv->flags & DPAA2_TX_CONF_ENABLE)
891 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
895 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
899 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
904 dpaa2_q->tc_index = tc_id;
906 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
907 DPNI_QUEUE_TX, dpaa2_q->tc_index,
908 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
910 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
913 dpaa2_q->fqid = qid.fqid;
915 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
916 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
918 dpaa2_q->nb_desc = nb_tx_desc;
920 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
921 cong_notif_cfg.threshold_entry = nb_tx_desc;
922 /* Notify that the queue is not congested when the data in
923 * the queue is below this thershold.(90% of value)
925 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
926 cong_notif_cfg.message_ctx = 0;
927 cong_notif_cfg.message_iova =
928 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
929 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
930 cong_notif_cfg.notification_mode =
931 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
932 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
933 DPNI_CONG_OPT_COHERENT_WRITE;
934 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
936 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
943 "Error in setting tx congestion notification: "
948 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
949 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
951 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
952 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
953 options = options | DPNI_QUEUE_OPT_USER_CTX;
954 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
955 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
956 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
957 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
959 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
960 "tc_index=%d, flow=%d err=%d",
961 dpaa2_tx_conf_q->tc_index,
962 dpaa2_tx_conf_q->flow_id, ret);
966 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
967 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
968 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
970 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
973 dpaa2_tx_conf_q->fqid = qid.fqid;
979 dpaa2_dev_rx_queue_release(void *q __rte_unused)
981 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
982 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
983 struct fsl_mc_io *dpni =
984 (struct fsl_mc_io *)priv->eth_dev->process_private;
987 struct dpni_queue cfg;
989 memset(&cfg, 0, sizeof(struct dpni_queue));
990 PMD_INIT_FUNC_TRACE();
991 if (dpaa2_q->cgid != 0xff) {
992 options = DPNI_QUEUE_OPT_CLEAR_CGID;
993 cfg.cgid = dpaa2_q->cgid;
995 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
997 dpaa2_q->tc_index, dpaa2_q->flow_id,
1000 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1001 dpaa2_q->fqid, ret);
1002 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1003 dpaa2_q->cgid = 0xff;
1008 dpaa2_dev_tx_queue_release(void *q __rte_unused)
1010 PMD_INIT_FUNC_TRACE();
1014 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1017 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1018 struct dpaa2_queue *dpaa2_q;
1019 struct qbman_swp *swp;
1020 struct qbman_fq_query_np_rslt state;
1021 uint32_t frame_cnt = 0;
1023 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1024 ret = dpaa2_affine_qbman_swp();
1027 "Failed to allocate IO portal, tid: %d\n",
1032 swp = DPAA2_PER_LCORE_PORTAL;
1034 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
1036 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1037 frame_cnt = qbman_fq_state_frame_count(&state);
1038 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
1039 rx_queue_id, frame_cnt);
1044 static const uint32_t *
1045 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1047 static const uint32_t ptypes[] = {
1048 /*todo -= add more types */
1051 RTE_PTYPE_L3_IPV4_EXT,
1053 RTE_PTYPE_L3_IPV6_EXT,
1061 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1062 dev->rx_pkt_burst == dpaa2_dev_rx ||
1063 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1069 * Dpaa2 link Interrupt handler
1072 * The address of parameter (struct rte_eth_dev *) regsitered before.
1078 dpaa2_interrupt_handler(void *param)
1080 struct rte_eth_dev *dev = param;
1081 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1082 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1084 int irq_index = DPNI_IRQ_INDEX;
1085 unsigned int status = 0, clear = 0;
1087 PMD_INIT_FUNC_TRACE();
1090 DPAA2_PMD_ERR("dpni is NULL");
1094 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1095 irq_index, &status);
1096 if (unlikely(ret)) {
1097 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1102 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1103 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1104 dpaa2_dev_link_update(dev, 0);
1105 /* calling all the apps registered for link status event */
1106 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1109 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1112 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1116 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1119 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1120 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1121 int irq_index = DPNI_IRQ_INDEX;
1122 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1124 PMD_INIT_FUNC_TRACE();
1126 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1129 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1134 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1137 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1144 dpaa2_dev_start(struct rte_eth_dev *dev)
1146 struct rte_device *rdev = dev->device;
1147 struct rte_dpaa2_device *dpaa2_dev;
1148 struct rte_eth_dev_data *data = dev->data;
1149 struct dpaa2_dev_priv *priv = data->dev_private;
1150 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1151 struct dpni_queue cfg;
1152 struct dpni_error_cfg err_cfg;
1154 struct dpni_queue_id qid;
1155 struct dpaa2_queue *dpaa2_q;
1157 struct rte_intr_handle *intr_handle;
1159 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1160 intr_handle = &dpaa2_dev->intr_handle;
1162 PMD_INIT_FUNC_TRACE();
1164 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1166 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1171 /* Power up the phy. Needed to make the link go UP */
1172 dpaa2_dev_set_link_up(dev);
1174 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1175 DPNI_QUEUE_TX, &qdid);
1177 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1182 for (i = 0; i < data->nb_rx_queues; i++) {
1183 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1184 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1185 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1186 dpaa2_q->flow_id, &cfg, &qid);
1188 DPAA2_PMD_ERR("Error in getting flow information: "
1192 dpaa2_q->fqid = qid.fqid;
1195 if (dpaa2_enable_err_queue) {
1196 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1197 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1199 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1203 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1204 dpaa2_q->fqid = qid.fqid;
1205 dpaa2_q->eth_data = dev->data;
1207 err_cfg.errors = DPNI_ERROR_DISC;
1208 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1210 /* checksum errors, send them to normal path
1211 * and set it in annotation
1213 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1215 /* if packet with parse error are not to be dropped */
1216 err_cfg.errors |= DPNI_ERROR_PHE;
1218 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1220 err_cfg.set_frame_annotation = true;
1222 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1223 priv->token, &err_cfg);
1225 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1230 /* if the interrupts were configured on this devices*/
1231 if (intr_handle && (intr_handle->fd) &&
1232 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1233 /* Registering LSC interrupt handler */
1234 rte_intr_callback_register(intr_handle,
1235 dpaa2_interrupt_handler,
1238 /* enable vfio intr/eventfd mapping
1239 * Interrupt index 0 is required, so we can not use
1242 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1244 /* enable dpni_irqs */
1245 dpaa2_eth_setup_irqs(dev, 1);
1248 /* Change the tx burst function if ordered queues are used */
1249 if (priv->en_ordered)
1250 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1256 * This routine disables all traffic on the adapter by issuing a
1257 * global reset on the MAC.
1260 dpaa2_dev_stop(struct rte_eth_dev *dev)
1262 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1263 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1265 struct rte_eth_link link;
1266 struct rte_intr_handle *intr_handle = dev->intr_handle;
1268 PMD_INIT_FUNC_TRACE();
1270 /* reset interrupt callback */
1271 if (intr_handle && (intr_handle->fd) &&
1272 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1273 /*disable dpni irqs */
1274 dpaa2_eth_setup_irqs(dev, 0);
1276 /* disable vfio intr before callback unregister */
1277 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1279 /* Unregistering LSC interrupt handler */
1280 rte_intr_callback_unregister(intr_handle,
1281 dpaa2_interrupt_handler,
1285 dpaa2_dev_set_link_down(dev);
1287 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1289 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1294 /* clear the recorded link status */
1295 memset(&link, 0, sizeof(link));
1296 rte_eth_linkstatus_set(dev, &link);
1302 dpaa2_dev_close(struct rte_eth_dev *dev)
1304 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1305 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1307 struct rte_eth_link link;
1309 PMD_INIT_FUNC_TRACE();
1311 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1315 DPAA2_PMD_WARN("Already closed or not started");
1319 dpaa2_tm_deinit(dev);
1320 dpaa2_flow_clean(dev);
1321 /* Clean the device first */
1322 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1324 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1328 memset(&link, 0, sizeof(link));
1329 rte_eth_linkstatus_set(dev, &link);
1331 /* Free private queues memory */
1332 dpaa2_free_rx_tx_queues(dev);
1333 /* Close the device at underlying layer*/
1334 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1336 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1340 /* Free the allocated memory for ethernet private data and dpni*/
1342 dev->process_private = NULL;
1345 for (i = 0; i < MAX_TCS; i++)
1346 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1348 if (priv->extract.qos_extract_param)
1349 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1351 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1356 dpaa2_dev_promiscuous_enable(
1357 struct rte_eth_dev *dev)
1360 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1361 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1363 PMD_INIT_FUNC_TRACE();
1366 DPAA2_PMD_ERR("dpni is NULL");
1370 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1372 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1374 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1376 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1382 dpaa2_dev_promiscuous_disable(
1383 struct rte_eth_dev *dev)
1386 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1387 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1389 PMD_INIT_FUNC_TRACE();
1392 DPAA2_PMD_ERR("dpni is NULL");
1396 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1398 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1400 if (dev->data->all_multicast == 0) {
1401 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1402 priv->token, false);
1404 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1412 dpaa2_dev_allmulticast_enable(
1413 struct rte_eth_dev *dev)
1416 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1417 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1419 PMD_INIT_FUNC_TRACE();
1422 DPAA2_PMD_ERR("dpni is NULL");
1426 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1428 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1434 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1437 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1438 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1440 PMD_INIT_FUNC_TRACE();
1443 DPAA2_PMD_ERR("dpni is NULL");
1447 /* must remain on for all promiscuous */
1448 if (dev->data->promiscuous == 1)
1451 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1453 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1459 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1462 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1463 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1464 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1467 PMD_INIT_FUNC_TRACE();
1470 DPAA2_PMD_ERR("dpni is NULL");
1474 /* check that mtu is within the allowed range */
1475 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1478 if (frame_size > DPAA2_ETH_MAX_LEN)
1479 dev->data->dev_conf.rxmode.offloads |=
1480 DEV_RX_OFFLOAD_JUMBO_FRAME;
1482 dev->data->dev_conf.rxmode.offloads &=
1483 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1485 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1487 /* Set the Max Rx frame length as 'mtu' +
1488 * Maximum Ethernet header length
1490 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1491 frame_size - RTE_ETHER_CRC_LEN);
1493 DPAA2_PMD_ERR("Setting the max frame length failed");
1496 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1501 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1502 struct rte_ether_addr *addr,
1503 __rte_unused uint32_t index,
1504 __rte_unused uint32_t pool)
1507 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1508 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1510 PMD_INIT_FUNC_TRACE();
1513 DPAA2_PMD_ERR("dpni is NULL");
1517 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1518 addr->addr_bytes, 0, 0, 0);
1521 "error: Adding the MAC ADDR failed: err = %d", ret);
1526 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1530 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1531 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1532 struct rte_eth_dev_data *data = dev->data;
1533 struct rte_ether_addr *macaddr;
1535 PMD_INIT_FUNC_TRACE();
1537 macaddr = &data->mac_addrs[index];
1540 DPAA2_PMD_ERR("dpni is NULL");
1544 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1545 priv->token, macaddr->addr_bytes);
1548 "error: Removing the MAC ADDR failed: err = %d", ret);
1552 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1553 struct rte_ether_addr *addr)
1556 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1557 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1559 PMD_INIT_FUNC_TRACE();
1562 DPAA2_PMD_ERR("dpni is NULL");
1566 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1567 priv->token, addr->addr_bytes);
1571 "error: Setting the MAC ADDR failed %d", ret);
1577 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1578 struct rte_eth_stats *stats)
1580 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1581 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1583 uint8_t page0 = 0, page1 = 1, page2 = 2;
1584 union dpni_statistics value;
1586 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1588 memset(&value, 0, sizeof(union dpni_statistics));
1590 PMD_INIT_FUNC_TRACE();
1593 DPAA2_PMD_ERR("dpni is NULL");
1598 DPAA2_PMD_ERR("stats is NULL");
1602 /*Get Counters from page_0*/
1603 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1608 stats->ipackets = value.page_0.ingress_all_frames;
1609 stats->ibytes = value.page_0.ingress_all_bytes;
1611 /*Get Counters from page_1*/
1612 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1617 stats->opackets = value.page_1.egress_all_frames;
1618 stats->obytes = value.page_1.egress_all_bytes;
1620 /*Get Counters from page_2*/
1621 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1626 /* Ingress drop frame count due to configured rules */
1627 stats->ierrors = value.page_2.ingress_filtered_frames;
1628 /* Ingress drop frame count due to error */
1629 stats->ierrors += value.page_2.ingress_discarded_frames;
1631 stats->oerrors = value.page_2.egress_discarded_frames;
1632 stats->imissed = value.page_2.ingress_nobuffer_discards;
1634 /* Fill in per queue stats */
1635 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1636 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1637 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1638 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1640 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1642 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1644 /* Byte counting is not implemented */
1645 stats->q_ibytes[i] = 0;
1646 stats->q_obytes[i] = 0;
1652 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1657 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1660 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1661 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1663 union dpni_statistics value[5] = {};
1664 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1672 /* Get Counters from page_0*/
1673 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1678 /* Get Counters from page_1*/
1679 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1684 /* Get Counters from page_2*/
1685 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1690 for (i = 0; i < priv->max_cgs; i++) {
1691 if (!priv->cgid_in_use[i]) {
1692 /* Get Counters from page_4*/
1693 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1702 for (i = 0; i < num; i++) {
1704 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1705 raw.counter[dpaa2_xstats_strings[i].stats_id];
1709 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1714 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1715 struct rte_eth_xstat_name *xstats_names,
1718 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1720 if (limit < stat_cnt)
1723 if (xstats_names != NULL)
1724 for (i = 0; i < stat_cnt; i++)
1725 strlcpy(xstats_names[i].name,
1726 dpaa2_xstats_strings[i].name,
1727 sizeof(xstats_names[i].name));
1733 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1734 uint64_t *values, unsigned int n)
1736 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1737 uint64_t values_copy[stat_cnt];
1740 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1741 struct fsl_mc_io *dpni =
1742 (struct fsl_mc_io *)dev->process_private;
1744 union dpni_statistics value[5] = {};
1752 /* Get Counters from page_0*/
1753 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1758 /* Get Counters from page_1*/
1759 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1764 /* Get Counters from page_2*/
1765 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1770 /* Get Counters from page_4*/
1771 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1776 for (i = 0; i < stat_cnt; i++) {
1777 values[i] = value[dpaa2_xstats_strings[i].page_id].
1778 raw.counter[dpaa2_xstats_strings[i].stats_id];
1783 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1785 for (i = 0; i < n; i++) {
1786 if (ids[i] >= stat_cnt) {
1787 DPAA2_PMD_ERR("xstats id value isn't valid");
1790 values[i] = values_copy[ids[i]];
1796 dpaa2_xstats_get_names_by_id(
1797 struct rte_eth_dev *dev,
1798 struct rte_eth_xstat_name *xstats_names,
1799 const uint64_t *ids,
1802 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1803 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1806 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1808 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1810 for (i = 0; i < limit; i++) {
1811 if (ids[i] >= stat_cnt) {
1812 DPAA2_PMD_ERR("xstats id value isn't valid");
1815 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1821 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1823 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1824 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1827 struct dpaa2_queue *dpaa2_q;
1829 PMD_INIT_FUNC_TRACE();
1832 DPAA2_PMD_ERR("dpni is NULL");
1836 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1840 /* Reset the per queue stats in dpaa2_queue structure */
1841 for (i = 0; i < priv->nb_rx_queues; i++) {
1842 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1844 dpaa2_q->rx_pkts = 0;
1847 for (i = 0; i < priv->nb_tx_queues; i++) {
1848 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1850 dpaa2_q->tx_pkts = 0;
1856 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1860 /* return 0 means link status changed, -1 means not changed */
1862 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1863 int wait_to_complete)
1866 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1867 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1868 struct rte_eth_link link;
1869 struct dpni_link_state state = {0};
1873 DPAA2_PMD_ERR("dpni is NULL");
1877 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1878 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1881 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1884 if (state.up == ETH_LINK_DOWN &&
1886 rte_delay_ms(CHECK_INTERVAL);
1891 memset(&link, 0, sizeof(struct rte_eth_link));
1892 link.link_status = state.up;
1893 link.link_speed = state.rate;
1895 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1896 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1898 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1900 ret = rte_eth_linkstatus_set(dev, &link);
1902 DPAA2_PMD_DEBUG("No change in status");
1904 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1905 link.link_status ? "Up" : "Down");
1911 * Toggle the DPNI to enable, if not already enabled.
1912 * This is not strictly PHY up/down - it is more of logical toggling.
1915 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1918 struct dpaa2_dev_priv *priv;
1919 struct fsl_mc_io *dpni;
1921 struct dpni_link_state state = {0};
1923 priv = dev->data->dev_private;
1924 dpni = (struct fsl_mc_io *)dev->process_private;
1927 DPAA2_PMD_ERR("dpni is NULL");
1931 /* Check if DPNI is currently enabled */
1932 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1934 /* Unable to obtain dpni status; Not continuing */
1935 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1939 /* Enable link if not already enabled */
1941 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1943 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1947 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1949 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1953 /* changing tx burst function to start enqueues */
1954 dev->tx_pkt_burst = dpaa2_dev_tx;
1955 dev->data->dev_link.link_status = state.up;
1956 dev->data->dev_link.link_speed = state.rate;
1959 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1961 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1966 * Toggle the DPNI to disable, if not already disabled.
1967 * This is not strictly PHY up/down - it is more of logical toggling.
1970 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1973 struct dpaa2_dev_priv *priv;
1974 struct fsl_mc_io *dpni;
1975 int dpni_enabled = 0;
1978 PMD_INIT_FUNC_TRACE();
1980 priv = dev->data->dev_private;
1981 dpni = (struct fsl_mc_io *)dev->process_private;
1984 DPAA2_PMD_ERR("Device has not yet been configured");
1988 /*changing tx burst function to avoid any more enqueues */
1989 dev->tx_pkt_burst = dummy_dev_tx;
1991 /* Loop while dpni_disable() attempts to drain the egress FQs
1992 * and confirm them back to us.
1995 ret = dpni_disable(dpni, 0, priv->token);
1997 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
2000 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
2002 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
2006 /* Allow the MC some slack */
2007 rte_delay_us(100 * 1000);
2008 } while (dpni_enabled && --retries);
2011 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2012 /* todo- we may have to manually cleanup queues.
2015 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2016 dev->data->port_id);
2019 dev->data->dev_link.link_status = 0;
2025 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2028 struct dpaa2_dev_priv *priv;
2029 struct fsl_mc_io *dpni;
2030 struct dpni_link_state state = {0};
2032 PMD_INIT_FUNC_TRACE();
2034 priv = dev->data->dev_private;
2035 dpni = (struct fsl_mc_io *)dev->process_private;
2037 if (dpni == NULL || fc_conf == NULL) {
2038 DPAA2_PMD_ERR("device not configured");
2042 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2044 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2048 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2049 if (state.options & DPNI_LINK_OPT_PAUSE) {
2050 /* DPNI_LINK_OPT_PAUSE set
2051 * if ASYM_PAUSE not set,
2052 * RX Side flow control (handle received Pause frame)
2053 * TX side flow control (send Pause frame)
2054 * if ASYM_PAUSE set,
2055 * RX Side flow control (handle received Pause frame)
2056 * No TX side flow control (send Pause frame disabled)
2058 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2059 fc_conf->mode = RTE_FC_FULL;
2061 fc_conf->mode = RTE_FC_RX_PAUSE;
2063 /* DPNI_LINK_OPT_PAUSE not set
2064 * if ASYM_PAUSE set,
2065 * TX side flow control (send Pause frame)
2066 * No RX side flow control (No action on pause frame rx)
2067 * if ASYM_PAUSE not set,
2068 * Flow control disabled
2070 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2071 fc_conf->mode = RTE_FC_TX_PAUSE;
2073 fc_conf->mode = RTE_FC_NONE;
2080 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2083 struct dpaa2_dev_priv *priv;
2084 struct fsl_mc_io *dpni;
2085 struct dpni_link_state state = {0};
2086 struct dpni_link_cfg cfg = {0};
2088 PMD_INIT_FUNC_TRACE();
2090 priv = dev->data->dev_private;
2091 dpni = (struct fsl_mc_io *)dev->process_private;
2094 DPAA2_PMD_ERR("dpni is NULL");
2098 /* It is necessary to obtain the current state before setting fc_conf
2099 * as MC would return error in case rate, autoneg or duplex values are
2102 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2104 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2108 /* Disable link before setting configuration */
2109 dpaa2_dev_set_link_down(dev);
2111 /* Based on fc_conf, update cfg */
2112 cfg.rate = state.rate;
2113 cfg.options = state.options;
2115 /* update cfg with fc_conf */
2116 switch (fc_conf->mode) {
2118 /* Full flow control;
2119 * OPT_PAUSE set, ASYM_PAUSE not set
2121 cfg.options |= DPNI_LINK_OPT_PAUSE;
2122 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2124 case RTE_FC_TX_PAUSE:
2125 /* Enable RX flow control
2126 * OPT_PAUSE not set;
2129 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2130 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2132 case RTE_FC_RX_PAUSE:
2133 /* Enable TX Flow control
2137 cfg.options |= DPNI_LINK_OPT_PAUSE;
2138 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2141 /* Disable Flow control
2143 * ASYM_PAUSE not set
2145 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2146 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2149 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2154 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2156 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2160 dpaa2_dev_set_link_up(dev);
2166 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2167 struct rte_eth_rss_conf *rss_conf)
2169 struct rte_eth_dev_data *data = dev->data;
2170 struct dpaa2_dev_priv *priv = data->dev_private;
2171 struct rte_eth_conf *eth_conf = &data->dev_conf;
2174 PMD_INIT_FUNC_TRACE();
2176 if (rss_conf->rss_hf) {
2177 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2178 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2181 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2187 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2188 ret = dpaa2_remove_flow_dist(dev, tc_index);
2191 "Unable to remove flow dist on tc%d",
2197 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2202 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2203 struct rte_eth_rss_conf *rss_conf)
2205 struct rte_eth_dev_data *data = dev->data;
2206 struct rte_eth_conf *eth_conf = &data->dev_conf;
2208 /* dpaa2 does not support rss_key, so length should be 0*/
2209 rss_conf->rss_key_len = 0;
2210 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2214 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2215 int eth_rx_queue_id,
2216 struct dpaa2_dpcon_dev *dpcon,
2217 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2219 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2220 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2221 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2222 uint8_t flow_id = dpaa2_ethq->flow_id;
2223 struct dpni_queue cfg;
2224 uint8_t options, priority;
2227 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2228 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2229 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2230 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2231 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2232 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2236 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2237 (dpcon->num_priorities - 1);
2239 memset(&cfg, 0, sizeof(struct dpni_queue));
2240 options = DPNI_QUEUE_OPT_DEST;
2241 cfg.destination.type = DPNI_DEST_DPCON;
2242 cfg.destination.id = dpcon->dpcon_id;
2243 cfg.destination.priority = priority;
2245 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2246 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2247 cfg.destination.hold_active = 1;
2250 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2251 !eth_priv->en_ordered) {
2252 struct opr_cfg ocfg;
2254 /* Restoration window size = 256 frames */
2256 /* Restoration window size = 512 frames for LX2 */
2257 if (dpaa2_svr_family == SVR_LX2160A)
2259 /* Auto advance NESN window enabled */
2261 /* Late arrival window size disabled */
2263 /* ORL resource exhaustaion advance NESN disabled */
2265 /* Loose ordering enabled */
2267 eth_priv->en_loose_ordered = 1;
2268 /* Strict ordering enabled if explicitly set */
2269 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2271 eth_priv->en_loose_ordered = 0;
2274 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2275 dpaa2_ethq->tc_index, flow_id,
2276 OPR_OPT_CREATE, &ocfg);
2278 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2282 eth_priv->en_ordered = 1;
2285 options |= DPNI_QUEUE_OPT_USER_CTX;
2286 cfg.user_context = (size_t)(dpaa2_ethq);
2288 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2289 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2291 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2295 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2300 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2301 int eth_rx_queue_id)
2303 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2304 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2305 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2306 uint8_t flow_id = dpaa2_ethq->flow_id;
2307 struct dpni_queue cfg;
2311 memset(&cfg, 0, sizeof(struct dpni_queue));
2312 options = DPNI_QUEUE_OPT_DEST;
2313 cfg.destination.type = DPNI_DEST_NONE;
2315 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2316 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2318 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2324 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2325 const struct rte_flow_ops **ops)
2330 *ops = &dpaa2_flow_ops;
2335 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2336 struct rte_eth_rxq_info *qinfo)
2338 struct dpaa2_queue *rxq;
2339 struct dpaa2_dev_priv *priv = dev->data->dev_private;
2340 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2341 uint16_t max_frame_length;
2343 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2345 qinfo->mp = rxq->mb_pool;
2346 qinfo->scattered_rx = dev->data->scattered_rx;
2347 qinfo->nb_desc = rxq->nb_desc;
2348 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2349 &max_frame_length) == 0)
2350 qinfo->rx_buf_size = max_frame_length;
2352 qinfo->conf.rx_free_thresh = 1;
2353 qinfo->conf.rx_drop_en = 1;
2354 qinfo->conf.rx_deferred_start = 0;
2355 qinfo->conf.offloads = rxq->offloads;
2359 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2360 struct rte_eth_txq_info *qinfo)
2362 struct dpaa2_queue *txq;
2364 txq = dev->data->tx_queues[queue_id];
2366 qinfo->nb_desc = txq->nb_desc;
2367 qinfo->conf.tx_thresh.pthresh = 0;
2368 qinfo->conf.tx_thresh.hthresh = 0;
2369 qinfo->conf.tx_thresh.wthresh = 0;
2371 qinfo->conf.tx_free_thresh = 0;
2372 qinfo->conf.tx_rs_thresh = 0;
2373 qinfo->conf.offloads = txq->offloads;
2374 qinfo->conf.tx_deferred_start = 0;
2378 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2380 *(const void **)ops = &dpaa2_tm_ops;
2386 rte_pmd_dpaa2_thread_init(void)
2390 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2391 ret = dpaa2_affine_qbman_swp();
2394 "Failed to allocate IO portal, tid: %d\n",
2401 static struct eth_dev_ops dpaa2_ethdev_ops = {
2402 .dev_configure = dpaa2_eth_dev_configure,
2403 .dev_start = dpaa2_dev_start,
2404 .dev_stop = dpaa2_dev_stop,
2405 .dev_close = dpaa2_dev_close,
2406 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2407 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2408 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2409 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2410 .dev_set_link_up = dpaa2_dev_set_link_up,
2411 .dev_set_link_down = dpaa2_dev_set_link_down,
2412 .link_update = dpaa2_dev_link_update,
2413 .stats_get = dpaa2_dev_stats_get,
2414 .xstats_get = dpaa2_dev_xstats_get,
2415 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2416 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2417 .xstats_get_names = dpaa2_xstats_get_names,
2418 .stats_reset = dpaa2_dev_stats_reset,
2419 .xstats_reset = dpaa2_dev_stats_reset,
2420 .fw_version_get = dpaa2_fw_version_get,
2421 .dev_infos_get = dpaa2_dev_info_get,
2422 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2423 .mtu_set = dpaa2_dev_mtu_set,
2424 .vlan_filter_set = dpaa2_vlan_filter_set,
2425 .vlan_offload_set = dpaa2_vlan_offload_set,
2426 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2427 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2428 .rx_queue_release = dpaa2_dev_rx_queue_release,
2429 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2430 .tx_queue_release = dpaa2_dev_tx_queue_release,
2431 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2432 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2433 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2434 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2435 .mac_addr_add = dpaa2_dev_add_mac_addr,
2436 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2437 .mac_addr_set = dpaa2_dev_set_mac_addr,
2438 .rss_hash_update = dpaa2_dev_rss_hash_update,
2439 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2440 .flow_ops_get = dpaa2_dev_flow_ops_get,
2441 .rxq_info_get = dpaa2_rxq_info_get,
2442 .txq_info_get = dpaa2_txq_info_get,
2443 .tm_ops_get = dpaa2_tm_ops_get,
2444 #if defined(RTE_LIBRTE_IEEE1588)
2445 .timesync_enable = dpaa2_timesync_enable,
2446 .timesync_disable = dpaa2_timesync_disable,
2447 .timesync_read_time = dpaa2_timesync_read_time,
2448 .timesync_write_time = dpaa2_timesync_write_time,
2449 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2450 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2451 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2455 /* Populate the mac address from physically available (u-boot/firmware) and/or
2456 * one set by higher layers like MC (restool) etc.
2457 * Returns the table of MAC entries (multiple entries)
2460 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2461 struct rte_ether_addr *mac_entry)
2464 struct rte_ether_addr phy_mac, prime_mac;
2466 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2467 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2469 /* Get the physical device MAC address */
2470 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2471 phy_mac.addr_bytes);
2473 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2477 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2478 prime_mac.addr_bytes);
2480 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2484 /* Now that both MAC have been obtained, do:
2485 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2487 * If empty_mac(phy), return prime.
2488 * if both are empty, create random MAC, set as prime and return
2490 if (!rte_is_zero_ether_addr(&phy_mac)) {
2491 /* If the addresses are not same, overwrite prime */
2492 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2493 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2495 phy_mac.addr_bytes);
2497 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2501 memcpy(&prime_mac, &phy_mac,
2502 sizeof(struct rte_ether_addr));
2504 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2505 /* In case phys and prime, both are zero, create random MAC */
2506 rte_eth_random_addr(prime_mac.addr_bytes);
2507 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2509 prime_mac.addr_bytes);
2511 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2516 /* prime_mac the final MAC address */
2517 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2525 check_devargs_handler(__rte_unused const char *key, const char *value,
2526 __rte_unused void *opaque)
2528 if (strcmp(value, "1"))
2535 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2537 struct rte_kvargs *kvlist;
2542 kvlist = rte_kvargs_parse(devargs->args, NULL);
2546 if (!rte_kvargs_count(kvlist, key)) {
2547 rte_kvargs_free(kvlist);
2551 if (rte_kvargs_process(kvlist, key,
2552 check_devargs_handler, NULL) < 0) {
2553 rte_kvargs_free(kvlist);
2556 rte_kvargs_free(kvlist);
2562 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2564 struct rte_device *dev = eth_dev->device;
2565 struct rte_dpaa2_device *dpaa2_dev;
2566 struct fsl_mc_io *dpni_dev;
2567 struct dpni_attr attr;
2568 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2569 struct dpni_buffer_layout layout;
2572 PMD_INIT_FUNC_TRACE();
2574 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2576 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2579 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2580 eth_dev->process_private = (void *)dpni_dev;
2582 /* For secondary processes, the primary has done all the work */
2583 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2584 /* In case of secondary, only burst and ops API need to be
2587 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2588 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2589 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2590 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2591 else if (dpaa2_get_devargs(dev->devargs,
2592 DRIVER_NO_PREFETCH_MODE))
2593 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2595 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2596 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2600 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2602 hw_id = dpaa2_dev->object_id;
2603 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2606 "Failure in opening dpni@%d with err code %d",
2612 /* Clean the device first */
2613 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2615 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2620 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2623 "Failure in get dpni@%d attribute, err code %d",
2628 priv->num_rx_tc = attr.num_rx_tcs;
2629 priv->qos_entries = attr.qos_entries;
2630 priv->fs_entries = attr.fs_entries;
2631 priv->dist_queues = attr.num_queues;
2633 /* only if the custom CG is enabled */
2634 if (attr.options & DPNI_OPT_CUSTOM_CG)
2635 priv->max_cgs = attr.num_cgs;
2639 for (i = 0; i < priv->max_cgs; i++)
2640 priv->cgid_in_use[i] = 0;
2642 for (i = 0; i < attr.num_rx_tcs; i++)
2643 priv->nb_rx_queues += attr.num_queues;
2645 /* Using number of TX queues as number of TX TCs */
2646 priv->nb_tx_queues = attr.num_tx_tcs;
2648 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2649 priv->num_rx_tc, priv->nb_rx_queues,
2650 priv->nb_tx_queues, priv->max_cgs);
2652 priv->hw = dpni_dev;
2653 priv->hw_id = hw_id;
2654 priv->options = attr.options;
2655 priv->max_mac_filters = attr.mac_filter_entries;
2656 priv->max_vlan_filters = attr.vlan_filter_entries;
2658 #if defined(RTE_LIBRTE_IEEE1588)
2659 printf("DPDK IEEE1588 is enabled\n");
2660 priv->flags |= DPAA2_TX_CONF_ENABLE;
2662 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2663 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2664 priv->flags |= DPAA2_TX_CONF_ENABLE;
2665 DPAA2_PMD_INFO("TX_CONF Enabled");
2668 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2669 dpaa2_enable_err_queue = 1;
2670 DPAA2_PMD_INFO("Enable error queue");
2673 /* Allocate memory for hardware structure for queues */
2674 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2676 DPAA2_PMD_ERR("Queue allocation Failed");
2680 /* Allocate memory for storing MAC addresses.
2681 * Table of mac_filter_entries size is allocated so that RTE ether lib
2682 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2684 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2685 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2686 if (eth_dev->data->mac_addrs == NULL) {
2688 "Failed to allocate %d bytes needed to store MAC addresses",
2689 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2694 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2696 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2697 rte_free(eth_dev->data->mac_addrs);
2698 eth_dev->data->mac_addrs = NULL;
2702 /* ... tx buffer layout ... */
2703 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2704 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2705 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2706 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2707 layout.pass_timestamp = true;
2709 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2711 layout.pass_frame_status = 1;
2712 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2713 DPNI_QUEUE_TX, &layout);
2715 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2719 /* ... tx-conf and error buffer layout ... */
2720 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2721 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2722 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2723 layout.pass_timestamp = true;
2725 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2726 layout.pass_frame_status = 1;
2727 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2728 DPNI_QUEUE_TX_CONFIRM, &layout);
2730 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2735 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2737 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2738 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2739 DPAA2_PMD_INFO("Loopback mode");
2740 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2741 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2742 DPAA2_PMD_INFO("No Prefetch mode");
2744 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2746 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2748 /*Init fields w.r.t. classficaition*/
2749 memset(&priv->extract.qos_key_extract, 0,
2750 sizeof(struct dpaa2_key_extract));
2751 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2752 if (!priv->extract.qos_extract_param) {
2753 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2754 " classificaiton ", ret);
2757 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2758 IP_ADDRESS_OFFSET_INVALID;
2759 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2760 IP_ADDRESS_OFFSET_INVALID;
2761 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2762 IP_ADDRESS_OFFSET_INVALID;
2763 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2764 IP_ADDRESS_OFFSET_INVALID;
2766 for (i = 0; i < MAX_TCS; i++) {
2767 memset(&priv->extract.tc_key_extract[i], 0,
2768 sizeof(struct dpaa2_key_extract));
2769 priv->extract.tc_extract_param[i] =
2770 (size_t)rte_malloc(NULL, 256, 64);
2771 if (!priv->extract.tc_extract_param[i]) {
2772 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2776 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2777 IP_ADDRESS_OFFSET_INVALID;
2778 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2779 IP_ADDRESS_OFFSET_INVALID;
2780 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2781 IP_ADDRESS_OFFSET_INVALID;
2782 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2783 IP_ADDRESS_OFFSET_INVALID;
2786 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2787 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2790 DPAA2_PMD_ERR("Unable to set mtu. check config");
2794 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2795 * with external entity to receive byte code for software sequence
2796 * and same will be offload to the H/W using MC interface.
2797 * Currently it is assumed that DPAA2 driver has byte code by some
2798 * mean and same if offloaded to H/W.
2800 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2801 WRIOP_SS_INITIALIZER(priv);
2802 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2804 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2809 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2812 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2817 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2820 dpaa2_dev_close(eth_dev);
2826 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2827 struct rte_dpaa2_device *dpaa2_dev)
2829 struct rte_eth_dev *eth_dev;
2830 struct dpaa2_dev_priv *dev_priv;
2833 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2834 RTE_PKTMBUF_HEADROOM) {
2836 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2837 RTE_PKTMBUF_HEADROOM,
2838 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2843 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2844 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2847 dev_priv = rte_zmalloc("ethdev private structure",
2848 sizeof(struct dpaa2_dev_priv),
2849 RTE_CACHE_LINE_SIZE);
2850 if (dev_priv == NULL) {
2852 "Unable to allocate memory for private data");
2853 rte_eth_dev_release_port(eth_dev);
2856 eth_dev->data->dev_private = (void *)dev_priv;
2857 /* Store a pointer to eth_dev in dev_private */
2858 dev_priv->eth_dev = eth_dev;
2860 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2862 DPAA2_PMD_DEBUG("returning enodev");
2867 eth_dev->device = &dpaa2_dev->device;
2869 dpaa2_dev->eth_dev = eth_dev;
2870 eth_dev->data->rx_mbuf_alloc_failed = 0;
2872 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2873 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2875 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2877 /* Invoke PMD device initialization function */
2878 diag = dpaa2_dev_init(eth_dev);
2880 rte_eth_dev_probing_finish(eth_dev);
2884 rte_eth_dev_release_port(eth_dev);
2889 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2891 struct rte_eth_dev *eth_dev;
2894 eth_dev = dpaa2_dev->eth_dev;
2895 dpaa2_dev_close(eth_dev);
2896 ret = rte_eth_dev_release_port(eth_dev);
2901 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2902 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2903 .drv_type = DPAA2_ETH,
2904 .probe = rte_dpaa2_probe,
2905 .remove = rte_dpaa2_remove,
2908 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2909 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2910 DRIVER_LOOPBACK_MODE "=<int> "
2911 DRIVER_NO_PREFETCH_MODE "=<int>"
2912 DRIVER_TX_CONF "=<int>"
2913 DRIVER_ERROR_QUEUE "=<int>");
2914 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);