1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2020 NXP
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
35 /* Supported Rx offloads */
36 static uint64_t dev_rx_offloads_sup =
37 DEV_RX_OFFLOAD_CHECKSUM |
38 DEV_RX_OFFLOAD_SCTP_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
41 DEV_RX_OFFLOAD_VLAN_STRIP |
42 DEV_RX_OFFLOAD_VLAN_FILTER |
43 DEV_RX_OFFLOAD_JUMBO_FRAME |
44 DEV_RX_OFFLOAD_TIMESTAMP;
46 /* Rx offloads which cannot be disabled */
47 static uint64_t dev_rx_offloads_nodis =
48 DEV_RX_OFFLOAD_RSS_HASH |
49 DEV_RX_OFFLOAD_SCATTER;
51 /* Supported Tx offloads */
52 static uint64_t dev_tx_offloads_sup =
53 DEV_TX_OFFLOAD_VLAN_INSERT |
54 DEV_TX_OFFLOAD_IPV4_CKSUM |
55 DEV_TX_OFFLOAD_UDP_CKSUM |
56 DEV_TX_OFFLOAD_TCP_CKSUM |
57 DEV_TX_OFFLOAD_SCTP_CKSUM |
58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_MT_LOCKFREE |
60 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
62 /* Tx offloads which cannot be disabled */
63 static uint64_t dev_tx_offloads_nodis =
64 DEV_TX_OFFLOAD_MULTI_SEGS;
66 /* enable timestamp in mbuf */
67 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
69 struct rte_dpaa2_xstats_name_off {
70 char name[RTE_ETH_XSTATS_NAME_SIZE];
71 uint8_t page_id; /* dpni statistics page id */
72 uint8_t stats_id; /* stats id in the given page */
75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
76 {"ingress_multicast_frames", 0, 2},
77 {"ingress_multicast_bytes", 0, 3},
78 {"ingress_broadcast_frames", 0, 4},
79 {"ingress_broadcast_bytes", 0, 5},
80 {"egress_multicast_frames", 1, 2},
81 {"egress_multicast_bytes", 1, 3},
82 {"egress_broadcast_frames", 1, 4},
83 {"egress_broadcast_bytes", 1, 5},
84 {"ingress_filtered_frames", 2, 0},
85 {"ingress_discarded_frames", 2, 1},
86 {"ingress_nobuffer_discards", 2, 2},
87 {"egress_discarded_frames", 2, 3},
88 {"egress_confirmed_frames", 2, 4},
89 {"cgr_reject_frames", 4, 0},
90 {"cgr_reject_bytes", 4, 1},
93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
95 RTE_ETH_FILTER_DELETE,
96 RTE_ETH_FILTER_UPDATE,
101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
102 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
104 int wait_to_complete);
105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
113 struct dpaa2_dev_priv *priv = dev->data->dev_private;
114 struct fsl_mc_io *dpni = dev->process_private;
116 PMD_INIT_FUNC_TRACE();
119 DPAA2_PMD_ERR("dpni is NULL");
124 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
127 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
128 priv->token, vlan_id);
131 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
132 ret, vlan_id, priv->hw_id);
138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
140 struct dpaa2_dev_priv *priv = dev->data->dev_private;
141 struct fsl_mc_io *dpni = dev->process_private;
144 PMD_INIT_FUNC_TRACE();
146 if (mask & ETH_VLAN_FILTER_MASK) {
147 /* VLAN Filter not avaialble */
148 if (!priv->max_vlan_filters) {
149 DPAA2_PMD_INFO("VLAN filter not available");
153 if (dev->data->dev_conf.rxmode.offloads &
154 DEV_RX_OFFLOAD_VLAN_FILTER)
155 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
158 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
161 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
169 enum rte_vlan_type vlan_type __rte_unused,
172 struct dpaa2_dev_priv *priv = dev->data->dev_private;
173 struct fsl_mc_io *dpni = dev->process_private;
176 PMD_INIT_FUNC_TRACE();
178 /* nothing to be done for standard vlan tpids */
179 if (tpid == 0x8100 || tpid == 0x88A8)
182 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
185 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
186 /* if already configured tpids, remove them first */
188 struct dpni_custom_tpid_cfg tpid_list = {0};
190 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
191 priv->token, &tpid_list);
194 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
195 priv->token, tpid_list.tpid1);
198 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
206 dpaa2_fw_version_get(struct rte_eth_dev *dev,
211 struct fsl_mc_io *dpni = dev->process_private;
212 struct mc_soc_version mc_plat_info = {0};
213 struct mc_version mc_ver_info = {0};
215 PMD_INIT_FUNC_TRACE();
217 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
218 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
220 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
221 DPAA2_PMD_WARN("\tmc_get_version failed");
223 ret = snprintf(fw_version, fw_size,
228 mc_ver_info.revision);
230 ret += 1; /* add the size of '\0' */
231 if (fw_size < (uint32_t)ret)
238 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
240 struct dpaa2_dev_priv *priv = dev->data->dev_private;
242 PMD_INIT_FUNC_TRACE();
244 dev_info->if_index = priv->hw_id;
246 dev_info->max_mac_addrs = priv->max_mac_filters;
247 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
248 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
249 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
250 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
251 dev_info->rx_offload_capa = dev_rx_offloads_sup |
252 dev_rx_offloads_nodis;
253 dev_info->tx_offload_capa = dev_tx_offloads_sup |
254 dev_tx_offloads_nodis;
255 dev_info->speed_capa = ETH_LINK_SPEED_1G |
256 ETH_LINK_SPEED_2_5G |
259 dev_info->max_hash_mac_addrs = 0;
260 dev_info->max_vfs = 0;
261 dev_info->max_vmdq_pools = ETH_16_POOLS;
262 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
264 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
265 /* same is rx size for best perf */
266 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
268 dev_info->default_rxportconf.nb_queues = 1;
269 dev_info->default_txportconf.nb_queues = 1;
270 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
271 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
273 if (dpaa2_svr_family == SVR_LX2160A) {
274 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
284 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
285 __rte_unused uint16_t queue_id,
286 struct rte_eth_burst_mode *mode)
288 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
291 const struct burst_info {
294 } rx_offload_map[] = {
295 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
296 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
297 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
298 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
299 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
300 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
301 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
302 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
303 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
304 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
307 /* Update Rx offload info */
308 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
309 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
310 snprintf(mode->info, sizeof(mode->info), "%s",
311 rx_offload_map[i].output);
320 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
321 __rte_unused uint16_t queue_id,
322 struct rte_eth_burst_mode *mode)
324 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
327 const struct burst_info {
330 } tx_offload_map[] = {
331 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
332 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
333 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
334 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
335 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
336 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
337 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
338 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
339 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
342 /* Update Tx offload info */
343 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
344 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
345 snprintf(mode->info, sizeof(mode->info), "%s",
346 tx_offload_map[i].output);
355 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
357 struct dpaa2_dev_priv *priv = dev->data->dev_private;
360 uint8_t num_rxqueue_per_tc;
361 struct dpaa2_queue *mc_q, *mcq;
364 struct dpaa2_queue *dpaa2_q;
366 PMD_INIT_FUNC_TRACE();
368 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
369 if (priv->tx_conf_en)
370 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
372 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
373 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
374 RTE_CACHE_LINE_SIZE);
376 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
380 for (i = 0; i < priv->nb_rx_queues; i++) {
381 mc_q->eth_data = dev->data;
382 priv->rx_vq[i] = mc_q++;
383 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
384 dpaa2_q->q_storage = rte_malloc("dq_storage",
385 sizeof(struct queue_storage_info_t),
386 RTE_CACHE_LINE_SIZE);
387 if (!dpaa2_q->q_storage)
390 memset(dpaa2_q->q_storage, 0,
391 sizeof(struct queue_storage_info_t));
392 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
396 for (i = 0; i < priv->nb_tx_queues; i++) {
397 mc_q->eth_data = dev->data;
398 mc_q->flow_id = 0xffff;
399 priv->tx_vq[i] = mc_q++;
400 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
401 dpaa2_q->cscn = rte_malloc(NULL,
402 sizeof(struct qbman_result), 16);
407 if (priv->tx_conf_en) {
408 /*Setup tx confirmation queues*/
409 for (i = 0; i < priv->nb_tx_queues; i++) {
410 mc_q->eth_data = dev->data;
413 priv->tx_conf_vq[i] = mc_q++;
414 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
416 rte_malloc("dq_storage",
417 sizeof(struct queue_storage_info_t),
418 RTE_CACHE_LINE_SIZE);
419 if (!dpaa2_q->q_storage)
422 memset(dpaa2_q->q_storage, 0,
423 sizeof(struct queue_storage_info_t));
424 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
430 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
431 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
432 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
433 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
441 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
442 rte_free(dpaa2_q->q_storage);
443 priv->tx_conf_vq[i--] = NULL;
445 i = priv->nb_tx_queues;
449 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
450 rte_free(dpaa2_q->cscn);
451 priv->tx_vq[i--] = NULL;
453 i = priv->nb_rx_queues;
456 mc_q = priv->rx_vq[0];
458 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
459 dpaa2_free_dq_storage(dpaa2_q->q_storage);
460 rte_free(dpaa2_q->q_storage);
461 priv->rx_vq[i--] = NULL;
468 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
470 struct dpaa2_dev_priv *priv = dev->data->dev_private;
471 struct dpaa2_queue *dpaa2_q;
474 PMD_INIT_FUNC_TRACE();
476 /* Queue allocation base */
477 if (priv->rx_vq[0]) {
478 /* cleaning up queue storage */
479 for (i = 0; i < priv->nb_rx_queues; i++) {
480 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
481 if (dpaa2_q->q_storage)
482 rte_free(dpaa2_q->q_storage);
484 /* cleanup tx queue cscn */
485 for (i = 0; i < priv->nb_tx_queues; i++) {
486 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
487 rte_free(dpaa2_q->cscn);
489 if (priv->tx_conf_en) {
490 /* cleanup tx conf queue storage */
491 for (i = 0; i < priv->nb_tx_queues; i++) {
492 dpaa2_q = (struct dpaa2_queue *)
494 rte_free(dpaa2_q->q_storage);
497 /*free memory for all queues (RX+TX) */
498 rte_free(priv->rx_vq[0]);
499 priv->rx_vq[0] = NULL;
504 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
506 struct dpaa2_dev_priv *priv = dev->data->dev_private;
507 struct fsl_mc_io *dpni = dev->process_private;
508 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
509 uint64_t rx_offloads = eth_conf->rxmode.offloads;
510 uint64_t tx_offloads = eth_conf->txmode.offloads;
511 int rx_l3_csum_offload = false;
512 int rx_l4_csum_offload = false;
513 int tx_l3_csum_offload = false;
514 int tx_l4_csum_offload = false;
517 PMD_INIT_FUNC_TRACE();
519 /* Rx offloads which are enabled by default */
520 if (dev_rx_offloads_nodis & ~rx_offloads) {
522 "Some of rx offloads enabled by default - requested 0x%" PRIx64
523 " fixed are 0x%" PRIx64,
524 rx_offloads, dev_rx_offloads_nodis);
527 /* Tx offloads which are enabled by default */
528 if (dev_tx_offloads_nodis & ~tx_offloads) {
530 "Some of tx offloads enabled by default - requested 0x%" PRIx64
531 " fixed are 0x%" PRIx64,
532 tx_offloads, dev_tx_offloads_nodis);
535 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
536 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
537 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
538 priv->token, eth_conf->rxmode.max_rx_pkt_len
539 - RTE_ETHER_CRC_LEN);
542 "Unable to set mtu. check config");
546 dev->data->dev_conf.rxmode.max_rx_pkt_len -
547 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
554 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
555 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
556 ret = dpaa2_setup_flow_dist(dev,
557 eth_conf->rx_adv_conf.rss_conf.rss_hf,
561 "Unable to set flow distribution on tc%d."
562 "Check queue config", tc_index);
568 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
569 rx_l3_csum_offload = true;
571 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
572 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
573 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
574 rx_l4_csum_offload = true;
576 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
577 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
579 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
583 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
584 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
586 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
590 #if !defined(RTE_LIBRTE_IEEE1588)
591 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
593 dpaa2_enable_ts[dev->data->port_id] = true;
595 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
596 tx_l3_csum_offload = true;
598 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
599 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
600 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
601 tx_l4_csum_offload = true;
603 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
604 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
606 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
610 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
611 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
613 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
617 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
618 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
619 * to 0 for LS2 in the hardware thus disabling data/annotation
620 * stashing. For LX2 this is fixed in hardware and thus hash result and
621 * parse results can be received in FD using this option.
623 if (dpaa2_svr_family == SVR_LX2160A) {
624 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
625 DPNI_FLCTYPE_HASH, true);
627 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
632 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
633 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
638 /* Function to setup RX flow information. It contains traffic class ID,
639 * flow ID, destination configuration etc.
642 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
643 uint16_t rx_queue_id,
645 unsigned int socket_id __rte_unused,
646 const struct rte_eth_rxconf *rx_conf __rte_unused,
647 struct rte_mempool *mb_pool)
649 struct dpaa2_dev_priv *priv = dev->data->dev_private;
650 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
651 struct dpaa2_queue *dpaa2_q;
652 struct dpni_queue cfg;
658 PMD_INIT_FUNC_TRACE();
660 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
661 dev, rx_queue_id, mb_pool, rx_conf);
663 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
664 bpid = mempool_to_bpid(mb_pool);
665 ret = dpaa2_attach_bp_list(priv,
666 rte_dpaa2_bpid_info[bpid].bp_list);
670 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
671 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
672 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
674 /*Get the flow id from given VQ id*/
675 flow_id = dpaa2_q->flow_id;
676 memset(&cfg, 0, sizeof(struct dpni_queue));
678 options = options | DPNI_QUEUE_OPT_USER_CTX;
679 cfg.user_context = (size_t)(dpaa2_q);
681 /* check if a private cgr available. */
682 for (i = 0; i < priv->max_cgs; i++) {
683 if (!priv->cgid_in_use[i]) {
684 priv->cgid_in_use[i] = 1;
689 if (i < priv->max_cgs) {
690 options |= DPNI_QUEUE_OPT_SET_CGID;
692 dpaa2_q->cgid = cfg.cgid;
694 dpaa2_q->cgid = 0xff;
697 /*if ls2088 or rev2 device, enable the stashing */
699 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
700 options |= DPNI_QUEUE_OPT_FLC;
701 cfg.flc.stash_control = true;
702 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
703 /* 00 00 00 - last 6 bit represent annotation, context stashing,
704 * data stashing setting 01 01 00 (0x14)
705 * (in following order ->DS AS CS)
706 * to enable 1 line data, 1 line annotation.
707 * For LX2, this setting should be 01 00 00 (0x10)
709 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
710 cfg.flc.value |= 0x10;
712 cfg.flc.value |= 0x14;
714 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
715 dpaa2_q->tc_index, flow_id, options, &cfg);
717 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
721 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
722 struct dpni_taildrop taildrop;
726 /* Private CGR will use tail drop length as nb_rx_desc.
727 * for rest cases we can use standard byte based tail drop.
728 * There is no HW restriction, but number of CGRs are limited,
729 * hence this restriction is placed.
731 if (dpaa2_q->cgid != 0xff) {
732 /*enabling per rx queue congestion control */
733 taildrop.threshold = nb_rx_desc;
734 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
736 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
738 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
739 DPNI_CP_CONGESTION_GROUP,
742 dpaa2_q->cgid, &taildrop);
744 /*enabling per rx queue congestion control */
745 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
746 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
747 taildrop.oal = CONG_RX_OAL;
748 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
750 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
751 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
752 dpaa2_q->tc_index, flow_id,
756 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
760 } else { /* Disable tail Drop */
761 struct dpni_taildrop taildrop = {0};
762 DPAA2_PMD_INFO("Tail drop is disabled on queue");
765 if (dpaa2_q->cgid != 0xff) {
766 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
767 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
769 dpaa2_q->cgid, &taildrop);
771 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
772 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
773 dpaa2_q->tc_index, flow_id, &taildrop);
776 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
782 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
787 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
788 uint16_t tx_queue_id,
789 uint16_t nb_tx_desc __rte_unused,
790 unsigned int socket_id __rte_unused,
791 const struct rte_eth_txconf *tx_conf __rte_unused)
793 struct dpaa2_dev_priv *priv = dev->data->dev_private;
794 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
795 priv->tx_vq[tx_queue_id];
796 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
797 priv->tx_conf_vq[tx_queue_id];
798 struct fsl_mc_io *dpni = dev->process_private;
799 struct dpni_queue tx_conf_cfg;
800 struct dpni_queue tx_flow_cfg;
801 uint8_t options = 0, flow_id;
802 struct dpni_queue_id qid;
806 PMD_INIT_FUNC_TRACE();
808 /* Return if queue already configured */
809 if (dpaa2_q->flow_id != 0xffff) {
810 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
814 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
815 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
820 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
821 tc_id, flow_id, options, &tx_flow_cfg);
823 DPAA2_PMD_ERR("Error in setting the tx flow: "
824 "tc_id=%d, flow=%d err=%d",
825 tc_id, flow_id, ret);
829 dpaa2_q->flow_id = flow_id;
831 if (tx_queue_id == 0) {
832 /*Set tx-conf and error configuration*/
833 if (priv->tx_conf_en)
834 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
838 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
842 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
847 dpaa2_q->tc_index = tc_id;
849 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
850 DPNI_QUEUE_TX, dpaa2_q->tc_index,
851 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
853 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
856 dpaa2_q->fqid = qid.fqid;
858 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
859 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
861 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
862 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
863 /* Notify that the queue is not congested when the data in
864 * the queue is below this thershold.
866 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
867 cong_notif_cfg.message_ctx = 0;
868 cong_notif_cfg.message_iova =
869 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
870 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
871 cong_notif_cfg.notification_mode =
872 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
873 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
874 DPNI_CONG_OPT_COHERENT_WRITE;
875 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
877 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
884 "Error in setting tx congestion notification: "
889 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
890 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
892 if (priv->tx_conf_en) {
893 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
894 options = options | DPNI_QUEUE_OPT_USER_CTX;
895 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
896 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
897 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
898 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
900 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
901 "tc_index=%d, flow=%d err=%d",
902 dpaa2_tx_conf_q->tc_index,
903 dpaa2_tx_conf_q->flow_id, ret);
907 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
908 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
909 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
911 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
914 dpaa2_tx_conf_q->fqid = qid.fqid;
920 dpaa2_dev_rx_queue_release(void *q __rte_unused)
922 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
923 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
924 struct fsl_mc_io *dpni =
925 (struct fsl_mc_io *)priv->eth_dev->process_private;
928 struct dpni_queue cfg;
930 memset(&cfg, 0, sizeof(struct dpni_queue));
931 PMD_INIT_FUNC_TRACE();
932 if (dpaa2_q->cgid != 0xff) {
933 options = DPNI_QUEUE_OPT_CLEAR_CGID;
934 cfg.cgid = dpaa2_q->cgid;
936 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
938 dpaa2_q->tc_index, dpaa2_q->flow_id,
941 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
943 priv->cgid_in_use[dpaa2_q->cgid] = 0;
944 dpaa2_q->cgid = 0xff;
949 dpaa2_dev_tx_queue_release(void *q __rte_unused)
951 PMD_INIT_FUNC_TRACE();
955 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
958 struct dpaa2_dev_priv *priv = dev->data->dev_private;
959 struct dpaa2_queue *dpaa2_q;
960 struct qbman_swp *swp;
961 struct qbman_fq_query_np_rslt state;
962 uint32_t frame_cnt = 0;
964 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
965 ret = dpaa2_affine_qbman_swp();
968 "Failed to allocate IO portal, tid: %d\n",
973 swp = DPAA2_PER_LCORE_PORTAL;
975 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
977 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
978 frame_cnt = qbman_fq_state_frame_count(&state);
979 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
980 rx_queue_id, frame_cnt);
985 static const uint32_t *
986 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
988 static const uint32_t ptypes[] = {
989 /*todo -= add more types */
992 RTE_PTYPE_L3_IPV4_EXT,
994 RTE_PTYPE_L3_IPV6_EXT,
1002 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1003 dev->rx_pkt_burst == dpaa2_dev_rx ||
1004 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1010 * Dpaa2 link Interrupt handler
1013 * The address of parameter (struct rte_eth_dev *) regsitered before.
1019 dpaa2_interrupt_handler(void *param)
1021 struct rte_eth_dev *dev = param;
1022 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1023 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1025 int irq_index = DPNI_IRQ_INDEX;
1026 unsigned int status = 0, clear = 0;
1028 PMD_INIT_FUNC_TRACE();
1031 DPAA2_PMD_ERR("dpni is NULL");
1035 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1036 irq_index, &status);
1037 if (unlikely(ret)) {
1038 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1043 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1044 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1045 dpaa2_dev_link_update(dev, 0);
1046 /* calling all the apps registered for link status event */
1047 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
1051 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1054 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1058 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1061 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1062 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1063 int irq_index = DPNI_IRQ_INDEX;
1064 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1066 PMD_INIT_FUNC_TRACE();
1068 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1071 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1076 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1079 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1086 dpaa2_dev_start(struct rte_eth_dev *dev)
1088 struct rte_device *rdev = dev->device;
1089 struct rte_dpaa2_device *dpaa2_dev;
1090 struct rte_eth_dev_data *data = dev->data;
1091 struct dpaa2_dev_priv *priv = data->dev_private;
1092 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1093 struct dpni_queue cfg;
1094 struct dpni_error_cfg err_cfg;
1096 struct dpni_queue_id qid;
1097 struct dpaa2_queue *dpaa2_q;
1099 struct rte_intr_handle *intr_handle;
1101 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1102 intr_handle = &dpaa2_dev->intr_handle;
1104 PMD_INIT_FUNC_TRACE();
1106 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1108 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1113 /* Power up the phy. Needed to make the link go UP */
1114 dpaa2_dev_set_link_up(dev);
1116 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1117 DPNI_QUEUE_TX, &qdid);
1119 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1124 for (i = 0; i < data->nb_rx_queues; i++) {
1125 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1126 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1127 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1128 dpaa2_q->flow_id, &cfg, &qid);
1130 DPAA2_PMD_ERR("Error in getting flow information: "
1134 dpaa2_q->fqid = qid.fqid;
1137 /*checksum errors, send them to normal path and set it in annotation */
1138 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1139 err_cfg.errors |= DPNI_ERROR_PHE;
1141 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1142 err_cfg.set_frame_annotation = true;
1144 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1145 priv->token, &err_cfg);
1147 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1152 /* if the interrupts were configured on this devices*/
1153 if (intr_handle && (intr_handle->fd) &&
1154 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1155 /* Registering LSC interrupt handler */
1156 rte_intr_callback_register(intr_handle,
1157 dpaa2_interrupt_handler,
1160 /* enable vfio intr/eventfd mapping
1161 * Interrupt index 0 is required, so we can not use
1164 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1166 /* enable dpni_irqs */
1167 dpaa2_eth_setup_irqs(dev, 1);
1170 /* Change the tx burst function if ordered queues are used */
1171 if (priv->en_ordered)
1172 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1178 * This routine disables all traffic on the adapter by issuing a
1179 * global reset on the MAC.
1182 dpaa2_dev_stop(struct rte_eth_dev *dev)
1184 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1185 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1187 struct rte_eth_link link;
1188 struct rte_intr_handle *intr_handle = dev->intr_handle;
1190 PMD_INIT_FUNC_TRACE();
1192 /* reset interrupt callback */
1193 if (intr_handle && (intr_handle->fd) &&
1194 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1195 /*disable dpni irqs */
1196 dpaa2_eth_setup_irqs(dev, 0);
1198 /* disable vfio intr before callback unregister */
1199 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1201 /* Unregistering LSC interrupt handler */
1202 rte_intr_callback_unregister(intr_handle,
1203 dpaa2_interrupt_handler,
1207 dpaa2_dev_set_link_down(dev);
1209 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1211 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1216 /* clear the recorded link status */
1217 memset(&link, 0, sizeof(link));
1218 rte_eth_linkstatus_set(dev, &link);
1222 dpaa2_dev_close(struct rte_eth_dev *dev)
1224 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1225 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1227 struct rte_eth_link link;
1229 PMD_INIT_FUNC_TRACE();
1231 dpaa2_flow_clean(dev);
1233 /* Clean the device first */
1234 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1236 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1240 memset(&link, 0, sizeof(link));
1241 rte_eth_linkstatus_set(dev, &link);
1245 dpaa2_dev_promiscuous_enable(
1246 struct rte_eth_dev *dev)
1249 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1250 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1252 PMD_INIT_FUNC_TRACE();
1255 DPAA2_PMD_ERR("dpni is NULL");
1259 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1261 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1263 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1265 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1271 dpaa2_dev_promiscuous_disable(
1272 struct rte_eth_dev *dev)
1275 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1276 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1278 PMD_INIT_FUNC_TRACE();
1281 DPAA2_PMD_ERR("dpni is NULL");
1285 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1287 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1289 if (dev->data->all_multicast == 0) {
1290 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1291 priv->token, false);
1293 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1301 dpaa2_dev_allmulticast_enable(
1302 struct rte_eth_dev *dev)
1305 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1306 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1308 PMD_INIT_FUNC_TRACE();
1311 DPAA2_PMD_ERR("dpni is NULL");
1315 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1317 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1323 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1326 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1327 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1329 PMD_INIT_FUNC_TRACE();
1332 DPAA2_PMD_ERR("dpni is NULL");
1336 /* must remain on for all promiscuous */
1337 if (dev->data->promiscuous == 1)
1340 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1342 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1348 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1351 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1352 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1353 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1356 PMD_INIT_FUNC_TRACE();
1359 DPAA2_PMD_ERR("dpni is NULL");
1363 /* check that mtu is within the allowed range */
1364 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1367 if (frame_size > RTE_ETHER_MAX_LEN)
1368 dev->data->dev_conf.rxmode.offloads |=
1369 DEV_RX_OFFLOAD_JUMBO_FRAME;
1371 dev->data->dev_conf.rxmode.offloads &=
1372 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1374 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1376 /* Set the Max Rx frame length as 'mtu' +
1377 * Maximum Ethernet header length
1379 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1380 frame_size - RTE_ETHER_CRC_LEN);
1382 DPAA2_PMD_ERR("Setting the max frame length failed");
1385 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1390 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1391 struct rte_ether_addr *addr,
1392 __rte_unused uint32_t index,
1393 __rte_unused uint32_t pool)
1396 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1397 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1399 PMD_INIT_FUNC_TRACE();
1402 DPAA2_PMD_ERR("dpni is NULL");
1406 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1407 addr->addr_bytes, 0, 0, 0);
1410 "error: Adding the MAC ADDR failed: err = %d", ret);
1415 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1419 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1420 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1421 struct rte_eth_dev_data *data = dev->data;
1422 struct rte_ether_addr *macaddr;
1424 PMD_INIT_FUNC_TRACE();
1426 macaddr = &data->mac_addrs[index];
1429 DPAA2_PMD_ERR("dpni is NULL");
1433 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1434 priv->token, macaddr->addr_bytes);
1437 "error: Removing the MAC ADDR failed: err = %d", ret);
1441 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1442 struct rte_ether_addr *addr)
1445 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1446 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1448 PMD_INIT_FUNC_TRACE();
1451 DPAA2_PMD_ERR("dpni is NULL");
1455 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1456 priv->token, addr->addr_bytes);
1460 "error: Setting the MAC ADDR failed %d", ret);
1466 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1467 struct rte_eth_stats *stats)
1469 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1470 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1472 uint8_t page0 = 0, page1 = 1, page2 = 2;
1473 union dpni_statistics value;
1475 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1477 memset(&value, 0, sizeof(union dpni_statistics));
1479 PMD_INIT_FUNC_TRACE();
1482 DPAA2_PMD_ERR("dpni is NULL");
1487 DPAA2_PMD_ERR("stats is NULL");
1491 /*Get Counters from page_0*/
1492 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1497 stats->ipackets = value.page_0.ingress_all_frames;
1498 stats->ibytes = value.page_0.ingress_all_bytes;
1500 /*Get Counters from page_1*/
1501 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1506 stats->opackets = value.page_1.egress_all_frames;
1507 stats->obytes = value.page_1.egress_all_bytes;
1509 /*Get Counters from page_2*/
1510 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1515 /* Ingress drop frame count due to configured rules */
1516 stats->ierrors = value.page_2.ingress_filtered_frames;
1517 /* Ingress drop frame count due to error */
1518 stats->ierrors += value.page_2.ingress_discarded_frames;
1520 stats->oerrors = value.page_2.egress_discarded_frames;
1521 stats->imissed = value.page_2.ingress_nobuffer_discards;
1523 /* Fill in per queue stats */
1524 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1525 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1526 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1527 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1529 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1531 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1533 /* Byte counting is not implemented */
1534 stats->q_ibytes[i] = 0;
1535 stats->q_obytes[i] = 0;
1541 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1546 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1549 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1550 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1552 union dpni_statistics value[5] = {};
1553 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1561 /* Get Counters from page_0*/
1562 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1567 /* Get Counters from page_1*/
1568 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1573 /* Get Counters from page_2*/
1574 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1579 for (i = 0; i < priv->max_cgs; i++) {
1580 if (!priv->cgid_in_use[i]) {
1581 /* Get Counters from page_4*/
1582 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1591 for (i = 0; i < num; i++) {
1593 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1594 raw.counter[dpaa2_xstats_strings[i].stats_id];
1598 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1603 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1604 struct rte_eth_xstat_name *xstats_names,
1607 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1609 if (limit < stat_cnt)
1612 if (xstats_names != NULL)
1613 for (i = 0; i < stat_cnt; i++)
1614 strlcpy(xstats_names[i].name,
1615 dpaa2_xstats_strings[i].name,
1616 sizeof(xstats_names[i].name));
1622 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1623 uint64_t *values, unsigned int n)
1625 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1626 uint64_t values_copy[stat_cnt];
1629 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1630 struct fsl_mc_io *dpni =
1631 (struct fsl_mc_io *)dev->process_private;
1633 union dpni_statistics value[5] = {};
1641 /* Get Counters from page_0*/
1642 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1647 /* Get Counters from page_1*/
1648 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1653 /* Get Counters from page_2*/
1654 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1659 /* Get Counters from page_4*/
1660 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1665 for (i = 0; i < stat_cnt; i++) {
1666 values[i] = value[dpaa2_xstats_strings[i].page_id].
1667 raw.counter[dpaa2_xstats_strings[i].stats_id];
1672 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1674 for (i = 0; i < n; i++) {
1675 if (ids[i] >= stat_cnt) {
1676 DPAA2_PMD_ERR("xstats id value isn't valid");
1679 values[i] = values_copy[ids[i]];
1685 dpaa2_xstats_get_names_by_id(
1686 struct rte_eth_dev *dev,
1687 struct rte_eth_xstat_name *xstats_names,
1688 const uint64_t *ids,
1691 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1692 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1695 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1697 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1699 for (i = 0; i < limit; i++) {
1700 if (ids[i] >= stat_cnt) {
1701 DPAA2_PMD_ERR("xstats id value isn't valid");
1704 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1710 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1712 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1713 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1716 struct dpaa2_queue *dpaa2_q;
1718 PMD_INIT_FUNC_TRACE();
1721 DPAA2_PMD_ERR("dpni is NULL");
1725 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1729 /* Reset the per queue stats in dpaa2_queue structure */
1730 for (i = 0; i < priv->nb_rx_queues; i++) {
1731 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1733 dpaa2_q->rx_pkts = 0;
1736 for (i = 0; i < priv->nb_tx_queues; i++) {
1737 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1739 dpaa2_q->tx_pkts = 0;
1745 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1749 /* return 0 means link status changed, -1 means not changed */
1751 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1752 int wait_to_complete __rte_unused)
1755 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1756 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1757 struct rte_eth_link link;
1758 struct dpni_link_state state = {0};
1761 DPAA2_PMD_ERR("dpni is NULL");
1765 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1767 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1771 memset(&link, 0, sizeof(struct rte_eth_link));
1772 link.link_status = state.up;
1773 link.link_speed = state.rate;
1775 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1776 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1778 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1780 ret = rte_eth_linkstatus_set(dev, &link);
1782 DPAA2_PMD_DEBUG("No change in status");
1784 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1785 link.link_status ? "Up" : "Down");
1791 * Toggle the DPNI to enable, if not already enabled.
1792 * This is not strictly PHY up/down - it is more of logical toggling.
1795 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1798 struct dpaa2_dev_priv *priv;
1799 struct fsl_mc_io *dpni;
1801 struct dpni_link_state state = {0};
1803 priv = dev->data->dev_private;
1804 dpni = (struct fsl_mc_io *)dev->process_private;
1807 DPAA2_PMD_ERR("dpni is NULL");
1811 /* Check if DPNI is currently enabled */
1812 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1814 /* Unable to obtain dpni status; Not continuing */
1815 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1819 /* Enable link if not already enabled */
1821 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1823 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1827 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1829 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1833 /* changing tx burst function to start enqueues */
1834 dev->tx_pkt_burst = dpaa2_dev_tx;
1835 dev->data->dev_link.link_status = state.up;
1836 dev->data->dev_link.link_speed = state.rate;
1839 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1841 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1846 * Toggle the DPNI to disable, if not already disabled.
1847 * This is not strictly PHY up/down - it is more of logical toggling.
1850 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1853 struct dpaa2_dev_priv *priv;
1854 struct fsl_mc_io *dpni;
1855 int dpni_enabled = 0;
1858 PMD_INIT_FUNC_TRACE();
1860 priv = dev->data->dev_private;
1861 dpni = (struct fsl_mc_io *)dev->process_private;
1864 DPAA2_PMD_ERR("Device has not yet been configured");
1868 /*changing tx burst function to avoid any more enqueues */
1869 dev->tx_pkt_burst = dummy_dev_tx;
1871 /* Loop while dpni_disable() attempts to drain the egress FQs
1872 * and confirm them back to us.
1875 ret = dpni_disable(dpni, 0, priv->token);
1877 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1880 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1882 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1886 /* Allow the MC some slack */
1887 rte_delay_us(100 * 1000);
1888 } while (dpni_enabled && --retries);
1891 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1892 /* todo- we may have to manually cleanup queues.
1895 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1896 dev->data->port_id);
1899 dev->data->dev_link.link_status = 0;
1905 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1908 struct dpaa2_dev_priv *priv;
1909 struct fsl_mc_io *dpni;
1910 struct dpni_link_state state = {0};
1912 PMD_INIT_FUNC_TRACE();
1914 priv = dev->data->dev_private;
1915 dpni = (struct fsl_mc_io *)dev->process_private;
1917 if (dpni == NULL || fc_conf == NULL) {
1918 DPAA2_PMD_ERR("device not configured");
1922 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1924 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1928 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1929 if (state.options & DPNI_LINK_OPT_PAUSE) {
1930 /* DPNI_LINK_OPT_PAUSE set
1931 * if ASYM_PAUSE not set,
1932 * RX Side flow control (handle received Pause frame)
1933 * TX side flow control (send Pause frame)
1934 * if ASYM_PAUSE set,
1935 * RX Side flow control (handle received Pause frame)
1936 * No TX side flow control (send Pause frame disabled)
1938 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1939 fc_conf->mode = RTE_FC_FULL;
1941 fc_conf->mode = RTE_FC_RX_PAUSE;
1943 /* DPNI_LINK_OPT_PAUSE not set
1944 * if ASYM_PAUSE set,
1945 * TX side flow control (send Pause frame)
1946 * No RX side flow control (No action on pause frame rx)
1947 * if ASYM_PAUSE not set,
1948 * Flow control disabled
1950 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1951 fc_conf->mode = RTE_FC_TX_PAUSE;
1953 fc_conf->mode = RTE_FC_NONE;
1960 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1963 struct dpaa2_dev_priv *priv;
1964 struct fsl_mc_io *dpni;
1965 struct dpni_link_state state = {0};
1966 struct dpni_link_cfg cfg = {0};
1968 PMD_INIT_FUNC_TRACE();
1970 priv = dev->data->dev_private;
1971 dpni = (struct fsl_mc_io *)dev->process_private;
1974 DPAA2_PMD_ERR("dpni is NULL");
1978 /* It is necessary to obtain the current state before setting fc_conf
1979 * as MC would return error in case rate, autoneg or duplex values are
1982 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1984 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
1988 /* Disable link before setting configuration */
1989 dpaa2_dev_set_link_down(dev);
1991 /* Based on fc_conf, update cfg */
1992 cfg.rate = state.rate;
1993 cfg.options = state.options;
1995 /* update cfg with fc_conf */
1996 switch (fc_conf->mode) {
1998 /* Full flow control;
1999 * OPT_PAUSE set, ASYM_PAUSE not set
2001 cfg.options |= DPNI_LINK_OPT_PAUSE;
2002 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2004 case RTE_FC_TX_PAUSE:
2005 /* Enable RX flow control
2006 * OPT_PAUSE not set;
2009 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2010 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2012 case RTE_FC_RX_PAUSE:
2013 /* Enable TX Flow control
2017 cfg.options |= DPNI_LINK_OPT_PAUSE;
2018 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2021 /* Disable Flow control
2023 * ASYM_PAUSE not set
2025 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2026 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2029 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2034 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2036 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2040 dpaa2_dev_set_link_up(dev);
2046 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2047 struct rte_eth_rss_conf *rss_conf)
2049 struct rte_eth_dev_data *data = dev->data;
2050 struct dpaa2_dev_priv *priv = data->dev_private;
2051 struct rte_eth_conf *eth_conf = &data->dev_conf;
2054 PMD_INIT_FUNC_TRACE();
2056 if (rss_conf->rss_hf) {
2057 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2058 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2061 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2067 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2068 ret = dpaa2_remove_flow_dist(dev, tc_index);
2071 "Unable to remove flow dist on tc%d",
2077 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2082 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2083 struct rte_eth_rss_conf *rss_conf)
2085 struct rte_eth_dev_data *data = dev->data;
2086 struct rte_eth_conf *eth_conf = &data->dev_conf;
2088 /* dpaa2 does not support rss_key, so length should be 0*/
2089 rss_conf->rss_key_len = 0;
2090 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2094 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2095 int eth_rx_queue_id,
2096 struct dpaa2_dpcon_dev *dpcon,
2097 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2099 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2100 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2101 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2102 uint8_t flow_id = dpaa2_ethq->flow_id;
2103 struct dpni_queue cfg;
2104 uint8_t options, priority;
2107 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2108 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2109 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2110 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2111 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2112 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2116 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2117 (dpcon->num_priorities - 1);
2119 memset(&cfg, 0, sizeof(struct dpni_queue));
2120 options = DPNI_QUEUE_OPT_DEST;
2121 cfg.destination.type = DPNI_DEST_DPCON;
2122 cfg.destination.id = dpcon->dpcon_id;
2123 cfg.destination.priority = priority;
2125 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2126 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2127 cfg.destination.hold_active = 1;
2130 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2131 !eth_priv->en_ordered) {
2132 struct opr_cfg ocfg;
2134 /* Restoration window size = 256 frames */
2136 /* Restoration window size = 512 frames for LX2 */
2137 if (dpaa2_svr_family == SVR_LX2160A)
2139 /* Auto advance NESN window enabled */
2141 /* Late arrival window size disabled */
2143 /* ORL resource exhaustaion advance NESN disabled */
2145 /* Loose ordering enabled */
2147 eth_priv->en_loose_ordered = 1;
2148 /* Strict ordering enabled if explicitly set */
2149 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2151 eth_priv->en_loose_ordered = 0;
2154 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2155 dpaa2_ethq->tc_index, flow_id,
2156 OPR_OPT_CREATE, &ocfg);
2158 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2162 eth_priv->en_ordered = 1;
2165 options |= DPNI_QUEUE_OPT_USER_CTX;
2166 cfg.user_context = (size_t)(dpaa2_ethq);
2168 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2169 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2171 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2175 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2180 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2181 int eth_rx_queue_id)
2183 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2184 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2185 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2186 uint8_t flow_id = dpaa2_ethq->flow_id;
2187 struct dpni_queue cfg;
2191 memset(&cfg, 0, sizeof(struct dpni_queue));
2192 options = DPNI_QUEUE_OPT_DEST;
2193 cfg.destination.type = DPNI_DEST_NONE;
2195 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2196 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2198 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2204 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2208 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2209 if (dpaa2_supported_filter_ops[i] == filter_op)
2216 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2217 enum rte_filter_type filter_type,
2218 enum rte_filter_op filter_op,
2226 switch (filter_type) {
2227 case RTE_ETH_FILTER_GENERIC:
2228 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2232 *(const void **)arg = &dpaa2_flow_ops;
2233 dpaa2_filter_type |= filter_type;
2236 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2244 static struct eth_dev_ops dpaa2_ethdev_ops = {
2245 .dev_configure = dpaa2_eth_dev_configure,
2246 .dev_start = dpaa2_dev_start,
2247 .dev_stop = dpaa2_dev_stop,
2248 .dev_close = dpaa2_dev_close,
2249 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2250 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2251 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2252 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2253 .dev_set_link_up = dpaa2_dev_set_link_up,
2254 .dev_set_link_down = dpaa2_dev_set_link_down,
2255 .link_update = dpaa2_dev_link_update,
2256 .stats_get = dpaa2_dev_stats_get,
2257 .xstats_get = dpaa2_dev_xstats_get,
2258 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2259 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2260 .xstats_get_names = dpaa2_xstats_get_names,
2261 .stats_reset = dpaa2_dev_stats_reset,
2262 .xstats_reset = dpaa2_dev_stats_reset,
2263 .fw_version_get = dpaa2_fw_version_get,
2264 .dev_infos_get = dpaa2_dev_info_get,
2265 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2266 .mtu_set = dpaa2_dev_mtu_set,
2267 .vlan_filter_set = dpaa2_vlan_filter_set,
2268 .vlan_offload_set = dpaa2_vlan_offload_set,
2269 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2270 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2271 .rx_queue_release = dpaa2_dev_rx_queue_release,
2272 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2273 .tx_queue_release = dpaa2_dev_tx_queue_release,
2274 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2275 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2276 .rx_queue_count = dpaa2_dev_rx_queue_count,
2277 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2278 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2279 .mac_addr_add = dpaa2_dev_add_mac_addr,
2280 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2281 .mac_addr_set = dpaa2_dev_set_mac_addr,
2282 .rss_hash_update = dpaa2_dev_rss_hash_update,
2283 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2284 .filter_ctrl = dpaa2_dev_flow_ctrl,
2285 #if defined(RTE_LIBRTE_IEEE1588)
2286 .timesync_enable = dpaa2_timesync_enable,
2287 .timesync_disable = dpaa2_timesync_disable,
2288 .timesync_read_time = dpaa2_timesync_read_time,
2289 .timesync_write_time = dpaa2_timesync_write_time,
2290 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2291 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2292 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2296 /* Populate the mac address from physically available (u-boot/firmware) and/or
2297 * one set by higher layers like MC (restool) etc.
2298 * Returns the table of MAC entries (multiple entries)
2301 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2302 struct rte_ether_addr *mac_entry)
2305 struct rte_ether_addr phy_mac, prime_mac;
2307 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2308 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2310 /* Get the physical device MAC address */
2311 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2312 phy_mac.addr_bytes);
2314 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2318 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2319 prime_mac.addr_bytes);
2321 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2325 /* Now that both MAC have been obtained, do:
2326 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2328 * If empty_mac(phy), return prime.
2329 * if both are empty, create random MAC, set as prime and return
2331 if (!rte_is_zero_ether_addr(&phy_mac)) {
2332 /* If the addresses are not same, overwrite prime */
2333 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2334 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2336 phy_mac.addr_bytes);
2338 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2342 memcpy(&prime_mac, &phy_mac,
2343 sizeof(struct rte_ether_addr));
2345 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2346 /* In case phys and prime, both are zero, create random MAC */
2347 rte_eth_random_addr(prime_mac.addr_bytes);
2348 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2350 prime_mac.addr_bytes);
2352 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2357 /* prime_mac the final MAC address */
2358 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2366 check_devargs_handler(__rte_unused const char *key, const char *value,
2367 __rte_unused void *opaque)
2369 if (strcmp(value, "1"))
2376 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2378 struct rte_kvargs *kvlist;
2383 kvlist = rte_kvargs_parse(devargs->args, NULL);
2387 if (!rte_kvargs_count(kvlist, key)) {
2388 rte_kvargs_free(kvlist);
2392 if (rte_kvargs_process(kvlist, key,
2393 check_devargs_handler, NULL) < 0) {
2394 rte_kvargs_free(kvlist);
2397 rte_kvargs_free(kvlist);
2403 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2405 struct rte_device *dev = eth_dev->device;
2406 struct rte_dpaa2_device *dpaa2_dev;
2407 struct fsl_mc_io *dpni_dev;
2408 struct dpni_attr attr;
2409 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2410 struct dpni_buffer_layout layout;
2413 PMD_INIT_FUNC_TRACE();
2415 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2417 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2420 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2421 eth_dev->process_private = (void *)dpni_dev;
2423 /* For secondary processes, the primary has done all the work */
2424 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2425 /* In case of secondary, only burst and ops API need to be
2428 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2429 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2430 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2431 else if (dpaa2_get_devargs(dev->devargs,
2432 DRIVER_NO_PREFETCH_MODE))
2433 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2435 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2436 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2440 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2442 hw_id = dpaa2_dev->object_id;
2443 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2446 "Failure in opening dpni@%d with err code %d",
2452 /* Clean the device first */
2453 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2455 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2460 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2463 "Failure in get dpni@%d attribute, err code %d",
2468 priv->num_rx_tc = attr.num_rx_tcs;
2469 priv->qos_entries = attr.qos_entries;
2470 priv->fs_entries = attr.fs_entries;
2471 priv->dist_queues = attr.num_queues;
2473 /* only if the custom CG is enabled */
2474 if (attr.options & DPNI_OPT_CUSTOM_CG)
2475 priv->max_cgs = attr.num_cgs;
2479 for (i = 0; i < priv->max_cgs; i++)
2480 priv->cgid_in_use[i] = 0;
2482 for (i = 0; i < attr.num_rx_tcs; i++)
2483 priv->nb_rx_queues += attr.num_queues;
2485 /* Using number of TX queues as number of TX TCs */
2486 priv->nb_tx_queues = attr.num_tx_tcs;
2488 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2489 priv->num_rx_tc, priv->nb_rx_queues,
2490 priv->nb_tx_queues, priv->max_cgs);
2492 priv->hw = dpni_dev;
2493 priv->hw_id = hw_id;
2494 priv->options = attr.options;
2495 priv->max_mac_filters = attr.mac_filter_entries;
2496 priv->max_vlan_filters = attr.vlan_filter_entries;
2498 #if defined(RTE_LIBRTE_IEEE1588)
2499 priv->tx_conf_en = 1;
2501 priv->tx_conf_en = 0;
2504 /* Allocate memory for hardware structure for queues */
2505 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2507 DPAA2_PMD_ERR("Queue allocation Failed");
2511 /* Allocate memory for storing MAC addresses.
2512 * Table of mac_filter_entries size is allocated so that RTE ether lib
2513 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2515 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2516 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2517 if (eth_dev->data->mac_addrs == NULL) {
2519 "Failed to allocate %d bytes needed to store MAC addresses",
2520 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2525 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2527 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2528 rte_free(eth_dev->data->mac_addrs);
2529 eth_dev->data->mac_addrs = NULL;
2533 /* ... tx buffer layout ... */
2534 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2535 if (priv->tx_conf_en) {
2536 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2537 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2538 layout.pass_timestamp = true;
2540 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2542 layout.pass_frame_status = 1;
2543 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2544 DPNI_QUEUE_TX, &layout);
2546 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2550 /* ... tx-conf and error buffer layout ... */
2551 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2552 if (priv->tx_conf_en) {
2553 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2554 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2555 layout.pass_timestamp = true;
2557 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2559 layout.pass_frame_status = 1;
2560 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2561 DPNI_QUEUE_TX_CONFIRM, &layout);
2563 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2568 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2570 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2571 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2572 DPAA2_PMD_INFO("Loopback mode");
2573 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2574 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2575 DPAA2_PMD_INFO("No Prefetch mode");
2577 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2579 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2581 /*Init fields w.r.t. classficaition*/
2582 memset(&priv->extract.qos_key_extract, 0,
2583 sizeof(struct dpaa2_key_extract));
2584 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2585 if (!priv->extract.qos_extract_param) {
2586 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2587 " classificaiton ", ret);
2590 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2591 IP_ADDRESS_OFFSET_INVALID;
2592 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2593 IP_ADDRESS_OFFSET_INVALID;
2594 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2595 IP_ADDRESS_OFFSET_INVALID;
2596 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2597 IP_ADDRESS_OFFSET_INVALID;
2599 for (i = 0; i < MAX_TCS; i++) {
2600 memset(&priv->extract.tc_key_extract[i], 0,
2601 sizeof(struct dpaa2_key_extract));
2602 priv->extract.tc_extract_param[i] =
2603 (size_t)rte_malloc(NULL, 256, 64);
2604 if (!priv->extract.tc_extract_param[i]) {
2605 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2609 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2610 IP_ADDRESS_OFFSET_INVALID;
2611 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2612 IP_ADDRESS_OFFSET_INVALID;
2613 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2614 IP_ADDRESS_OFFSET_INVALID;
2615 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2616 IP_ADDRESS_OFFSET_INVALID;
2619 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2620 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2623 DPAA2_PMD_ERR("Unable to set mtu. check config");
2627 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2628 * with external entity to receive byte code for software sequence
2629 * and same will be offload to the H/W using MC interface.
2630 * Currently it is assumed that DPAA2 driver has byte code by some
2631 * mean and same if offloaded to H/W.
2633 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2634 WRIOP_SS_INITIALIZER(priv);
2635 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2637 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2642 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2645 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2650 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2653 dpaa2_dev_uninit(eth_dev);
2658 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2660 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2661 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_dev->process_private;
2664 PMD_INIT_FUNC_TRACE();
2666 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2670 DPAA2_PMD_WARN("Already closed or not started");
2674 dpaa2_dev_close(eth_dev);
2676 dpaa2_free_rx_tx_queues(eth_dev);
2678 /* Close the device at underlying layer*/
2679 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2682 "Failure closing dpni device with err code %d",
2686 /* Free the allocated memory for ethernet private data and dpni*/
2688 eth_dev->process_private = NULL;
2691 for (i = 0; i < MAX_TCS; i++)
2692 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
2694 if (priv->extract.qos_extract_param)
2695 rte_free((void *)(size_t)priv->extract.qos_extract_param);
2697 eth_dev->dev_ops = NULL;
2698 eth_dev->rx_pkt_burst = NULL;
2699 eth_dev->tx_pkt_burst = NULL;
2701 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2706 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2707 struct rte_dpaa2_device *dpaa2_dev)
2709 struct rte_eth_dev *eth_dev;
2710 struct dpaa2_dev_priv *dev_priv;
2713 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2714 RTE_PKTMBUF_HEADROOM) {
2716 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2717 RTE_PKTMBUF_HEADROOM,
2718 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2723 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2724 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2727 dev_priv = rte_zmalloc("ethdev private structure",
2728 sizeof(struct dpaa2_dev_priv),
2729 RTE_CACHE_LINE_SIZE);
2730 if (dev_priv == NULL) {
2732 "Unable to allocate memory for private data");
2733 rte_eth_dev_release_port(eth_dev);
2736 eth_dev->data->dev_private = (void *)dev_priv;
2737 /* Store a pointer to eth_dev in dev_private */
2738 dev_priv->eth_dev = eth_dev;
2739 dev_priv->tx_conf_en = 0;
2741 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2743 DPAA2_PMD_DEBUG("returning enodev");
2748 eth_dev->device = &dpaa2_dev->device;
2750 dpaa2_dev->eth_dev = eth_dev;
2751 eth_dev->data->rx_mbuf_alloc_failed = 0;
2753 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2754 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2756 /* Invoke PMD device initialization function */
2757 diag = dpaa2_dev_init(eth_dev);
2759 rte_eth_dev_probing_finish(eth_dev);
2763 rte_eth_dev_release_port(eth_dev);
2768 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2770 struct rte_eth_dev *eth_dev;
2772 eth_dev = dpaa2_dev->eth_dev;
2773 dpaa2_dev_uninit(eth_dev);
2775 rte_eth_dev_release_port(eth_dev);
2780 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2781 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2782 .drv_type = DPAA2_ETH,
2783 .probe = rte_dpaa2_probe,
2784 .remove = rte_dpaa2_remove,
2787 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2788 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2789 DRIVER_LOOPBACK_MODE "=<int> "
2790 DRIVER_NO_PREFETCH_MODE "=<int>");
2791 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);