1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
21 #include "dpaa2_pmd_logs.h"
22 #include <fslmc_vfio.h>
23 #include <dpaa2_hw_pvt.h>
24 #include <dpaa2_hw_mempool.h>
25 #include <dpaa2_hw_dpio.h>
26 #include <mc/fsl_dpmng.h>
27 #include "dpaa2_ethdev.h"
28 #include <fsl_qbman_debug.h>
30 /* Supported Rx offloads */
31 static uint64_t dev_rx_offloads_sup =
32 DEV_RX_OFFLOAD_VLAN_STRIP |
33 DEV_RX_OFFLOAD_IPV4_CKSUM |
34 DEV_RX_OFFLOAD_UDP_CKSUM |
35 DEV_RX_OFFLOAD_TCP_CKSUM |
36 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
37 DEV_RX_OFFLOAD_VLAN_FILTER |
38 DEV_RX_OFFLOAD_JUMBO_FRAME;
40 /* Rx offloads which cannot be disabled */
41 static uint64_t dev_rx_offloads_nodis =
42 DEV_RX_OFFLOAD_SCATTER;
44 /* Supported Tx offloads */
45 static uint64_t dev_tx_offloads_sup =
46 DEV_TX_OFFLOAD_VLAN_INSERT |
47 DEV_TX_OFFLOAD_IPV4_CKSUM |
48 DEV_TX_OFFLOAD_UDP_CKSUM |
49 DEV_TX_OFFLOAD_TCP_CKSUM |
50 DEV_TX_OFFLOAD_SCTP_CKSUM |
51 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
53 /* Tx offloads which cannot be disabled */
54 static uint64_t dev_tx_offloads_nodis =
55 DEV_TX_OFFLOAD_MULTI_SEGS |
56 DEV_TX_OFFLOAD_MT_LOCKFREE |
57 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
59 struct rte_dpaa2_xstats_name_off {
60 char name[RTE_ETH_XSTATS_NAME_SIZE];
61 uint8_t page_id; /* dpni statistics page id */
62 uint8_t stats_id; /* stats id in the given page */
65 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
66 {"ingress_multicast_frames", 0, 2},
67 {"ingress_multicast_bytes", 0, 3},
68 {"ingress_broadcast_frames", 0, 4},
69 {"ingress_broadcast_bytes", 0, 5},
70 {"egress_multicast_frames", 1, 2},
71 {"egress_multicast_bytes", 1, 3},
72 {"egress_broadcast_frames", 1, 4},
73 {"egress_broadcast_bytes", 1, 5},
74 {"ingress_filtered_frames", 2, 0},
75 {"ingress_discarded_frames", 2, 1},
76 {"ingress_nobuffer_discards", 2, 2},
77 {"egress_discarded_frames", 2, 3},
78 {"egress_confirmed_frames", 2, 4},
81 static struct rte_dpaa2_driver rte_dpaa2_pmd;
82 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
83 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
84 int wait_to_complete);
85 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
86 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
87 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
89 int dpaa2_logtype_pmd;
92 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
95 struct dpaa2_dev_priv *priv = dev->data->dev_private;
96 struct fsl_mc_io *dpni = priv->hw;
98 PMD_INIT_FUNC_TRACE();
101 DPAA2_PMD_ERR("dpni is NULL");
106 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW,
107 priv->token, vlan_id);
109 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
110 priv->token, vlan_id);
113 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
114 ret, vlan_id, priv->hw_id);
120 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
122 struct dpaa2_dev_priv *priv = dev->data->dev_private;
123 struct fsl_mc_io *dpni = priv->hw;
126 PMD_INIT_FUNC_TRACE();
128 if (mask & ETH_VLAN_FILTER_MASK) {
129 /* VLAN Filter not avaialble */
130 if (!priv->max_vlan_filters) {
131 DPAA2_PMD_INFO("VLAN filter not available");
135 if (dev->data->dev_conf.rxmode.offloads &
136 DEV_RX_OFFLOAD_VLAN_FILTER)
137 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
140 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
143 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
146 if (mask & ETH_VLAN_EXTEND_MASK) {
147 if (dev->data->dev_conf.rxmode.offloads &
148 DEV_RX_OFFLOAD_VLAN_EXTEND)
149 DPAA2_PMD_INFO("VLAN extend offload not supported");
156 dpaa2_fw_version_get(struct rte_eth_dev *dev,
161 struct dpaa2_dev_priv *priv = dev->data->dev_private;
162 struct fsl_mc_io *dpni = priv->hw;
163 struct mc_soc_version mc_plat_info = {0};
164 struct mc_version mc_ver_info = {0};
166 PMD_INIT_FUNC_TRACE();
168 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
169 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
171 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
172 DPAA2_PMD_WARN("\tmc_get_version failed");
174 ret = snprintf(fw_version, fw_size,
179 mc_ver_info.revision);
181 ret += 1; /* add the size of '\0' */
182 if (fw_size < (uint32_t)ret)
189 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
191 struct dpaa2_dev_priv *priv = dev->data->dev_private;
193 PMD_INIT_FUNC_TRACE();
195 dev_info->if_index = priv->hw_id;
197 dev_info->max_mac_addrs = priv->max_mac_filters;
198 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
199 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
200 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
201 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
202 dev_info->rx_offload_capa = dev_rx_offloads_sup |
203 dev_rx_offloads_nodis;
204 dev_info->tx_offload_capa = dev_tx_offloads_sup |
205 dev_tx_offloads_nodis;
206 dev_info->speed_capa = ETH_LINK_SPEED_1G |
207 ETH_LINK_SPEED_2_5G |
210 dev_info->max_hash_mac_addrs = 0;
211 dev_info->max_vfs = 0;
212 dev_info->max_vmdq_pools = ETH_16_POOLS;
213 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
217 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
219 struct dpaa2_dev_priv *priv = dev->data->dev_private;
222 struct dpaa2_queue *mc_q, *mcq;
225 struct dpaa2_queue *dpaa2_q;
227 PMD_INIT_FUNC_TRACE();
229 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
230 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
231 RTE_CACHE_LINE_SIZE);
233 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
237 for (i = 0; i < priv->nb_rx_queues; i++) {
239 priv->rx_vq[i] = mc_q++;
240 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
241 dpaa2_q->q_storage = rte_malloc("dq_storage",
242 sizeof(struct queue_storage_info_t),
243 RTE_CACHE_LINE_SIZE);
244 if (!dpaa2_q->q_storage)
247 memset(dpaa2_q->q_storage, 0,
248 sizeof(struct queue_storage_info_t));
249 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
253 for (i = 0; i < priv->nb_tx_queues; i++) {
255 mc_q->flow_id = 0xffff;
256 priv->tx_vq[i] = mc_q++;
257 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
258 dpaa2_q->cscn = rte_malloc(NULL,
259 sizeof(struct qbman_result), 16);
265 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
266 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
267 mcq->tc_index = DPAA2_DEF_TC;
268 mcq->flow_id = dist_idx;
276 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
277 rte_free(dpaa2_q->cscn);
278 priv->tx_vq[i--] = NULL;
280 i = priv->nb_rx_queues;
283 mc_q = priv->rx_vq[0];
285 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
286 dpaa2_free_dq_storage(dpaa2_q->q_storage);
287 rte_free(dpaa2_q->q_storage);
288 priv->rx_vq[i--] = NULL;
295 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
297 struct dpaa2_dev_priv *priv = dev->data->dev_private;
298 struct dpaa2_queue *dpaa2_q;
301 PMD_INIT_FUNC_TRACE();
303 /* Queue allocation base */
304 if (priv->rx_vq[0]) {
305 /* cleaning up queue storage */
306 for (i = 0; i < priv->nb_rx_queues; i++) {
307 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
308 if (dpaa2_q->q_storage)
309 rte_free(dpaa2_q->q_storage);
311 /* cleanup tx queue cscn */
312 for (i = 0; i < priv->nb_tx_queues; i++) {
313 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
315 rte_free(dpaa2_q->cscn);
317 /*free memory for all queues (RX+TX) */
318 rte_free(priv->rx_vq[0]);
319 priv->rx_vq[0] = NULL;
324 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
326 struct dpaa2_dev_priv *priv = dev->data->dev_private;
327 struct fsl_mc_io *dpni = priv->hw;
328 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
329 uint64_t rx_offloads = eth_conf->rxmode.offloads;
330 uint64_t tx_offloads = eth_conf->txmode.offloads;
331 int rx_l3_csum_offload = false;
332 int rx_l4_csum_offload = false;
333 int tx_l3_csum_offload = false;
334 int tx_l4_csum_offload = false;
337 PMD_INIT_FUNC_TRACE();
339 /* Rx offloads validation */
340 if (dev_rx_offloads_nodis & ~rx_offloads) {
342 "Rx offloads non configurable - requested 0x%" PRIx64
343 " ignored 0x%" PRIx64,
344 rx_offloads, dev_rx_offloads_nodis);
347 /* Tx offloads validation */
348 if (dev_tx_offloads_nodis & ~tx_offloads) {
350 "Tx offloads non configurable - requested 0x%" PRIx64
351 " ignored 0x%" PRIx64,
352 tx_offloads, dev_tx_offloads_nodis);
355 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
356 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
357 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
358 priv->token, eth_conf->rxmode.max_rx_pkt_len);
361 "Unable to set mtu. check config");
369 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
370 ret = dpaa2_setup_flow_dist(dev,
371 eth_conf->rx_adv_conf.rss_conf.rss_hf);
373 DPAA2_PMD_ERR("Unable to set flow distribution."
374 "Check queue config");
379 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
380 rx_l3_csum_offload = true;
382 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
383 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM))
384 rx_l4_csum_offload = true;
386 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
387 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
389 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
393 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
394 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
396 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
400 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
401 tx_l3_csum_offload = true;
403 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
404 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
405 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
406 tx_l4_csum_offload = true;
408 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
409 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
411 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
415 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
416 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
418 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
422 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
423 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
424 * to 0 for LS2 in the hardware thus disabling data/annotation
425 * stashing. For LX2 this is fixed in hardware and thus hash result and
426 * parse results can be received in FD using this option.
428 if (dpaa2_svr_family == SVR_LX2160A) {
429 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
430 DPNI_FLCTYPE_HASH, true);
432 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
437 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
438 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
440 /* update the current status */
441 dpaa2_dev_link_update(dev, 0);
446 /* Function to setup RX flow information. It contains traffic class ID,
447 * flow ID, destination configuration etc.
450 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
451 uint16_t rx_queue_id,
452 uint16_t nb_rx_desc __rte_unused,
453 unsigned int socket_id __rte_unused,
454 const struct rte_eth_rxconf *rx_conf __rte_unused,
455 struct rte_mempool *mb_pool)
457 struct dpaa2_dev_priv *priv = dev->data->dev_private;
458 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
459 struct dpaa2_queue *dpaa2_q;
460 struct dpni_queue cfg;
466 PMD_INIT_FUNC_TRACE();
468 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
469 dev, rx_queue_id, mb_pool, rx_conf);
471 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
472 bpid = mempool_to_bpid(mb_pool);
473 ret = dpaa2_attach_bp_list(priv,
474 rte_dpaa2_bpid_info[bpid].bp_list);
478 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
479 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
481 /*Get the flow id from given VQ id*/
482 flow_id = rx_queue_id % priv->nb_rx_queues;
483 memset(&cfg, 0, sizeof(struct dpni_queue));
485 options = options | DPNI_QUEUE_OPT_USER_CTX;
486 cfg.user_context = (size_t)(dpaa2_q);
488 /*if ls2088 or rev2 device, enable the stashing */
490 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
491 options |= DPNI_QUEUE_OPT_FLC;
492 cfg.flc.stash_control = true;
493 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
494 /* 00 00 00 - last 6 bit represent annotation, context stashing,
495 * data stashing setting 01 01 00 (0x14)
496 * (in following order ->DS AS CS)
497 * to enable 1 line data, 1 line annotation.
498 * For LX2, this setting should be 01 00 00 (0x10)
500 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
501 cfg.flc.value |= 0x10;
503 cfg.flc.value |= 0x14;
505 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
506 dpaa2_q->tc_index, flow_id, options, &cfg);
508 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
512 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
513 struct dpni_taildrop taildrop;
516 /*enabling per rx queue congestion control */
517 taildrop.threshold = CONG_THRESHOLD_RX_Q;
518 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
519 taildrop.oal = CONG_RX_OAL;
520 DPAA2_PMD_DEBUG("Enabling Early Drop on queue = %d",
522 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
523 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
524 dpaa2_q->tc_index, flow_id, &taildrop);
526 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
532 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
537 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
538 uint16_t tx_queue_id,
539 uint16_t nb_tx_desc __rte_unused,
540 unsigned int socket_id __rte_unused,
541 const struct rte_eth_txconf *tx_conf __rte_unused)
543 struct dpaa2_dev_priv *priv = dev->data->dev_private;
544 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
545 priv->tx_vq[tx_queue_id];
546 struct fsl_mc_io *dpni = priv->hw;
547 struct dpni_queue tx_conf_cfg;
548 struct dpni_queue tx_flow_cfg;
549 uint8_t options = 0, flow_id;
553 PMD_INIT_FUNC_TRACE();
555 /* Return if queue already configured */
556 if (dpaa2_q->flow_id != 0xffff) {
557 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
561 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
562 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
567 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
568 tc_id, flow_id, options, &tx_flow_cfg);
570 DPAA2_PMD_ERR("Error in setting the tx flow: "
571 "tc_id=%d, flow=%d err=%d",
572 tc_id, flow_id, ret);
576 dpaa2_q->flow_id = flow_id;
578 if (tx_queue_id == 0) {
579 /*Set tx-conf and error configuration*/
580 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
584 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
589 dpaa2_q->tc_index = tc_id;
591 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
592 struct dpni_congestion_notification_cfg cong_notif_cfg;
594 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
595 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
596 /* Notify that the queue is not congested when the data in
597 * the queue is below this thershold.
599 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
600 cong_notif_cfg.message_ctx = 0;
601 cong_notif_cfg.message_iova =
602 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
603 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
604 cong_notif_cfg.notification_mode =
605 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
606 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
607 DPNI_CONG_OPT_COHERENT_WRITE;
609 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
616 "Error in setting tx congestion notification: "
621 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
626 dpaa2_dev_rx_queue_release(void *q __rte_unused)
628 PMD_INIT_FUNC_TRACE();
632 dpaa2_dev_tx_queue_release(void *q __rte_unused)
634 PMD_INIT_FUNC_TRACE();
638 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
641 struct dpaa2_dev_priv *priv = dev->data->dev_private;
642 struct dpaa2_queue *dpaa2_q;
643 struct qbman_swp *swp;
644 struct qbman_fq_query_np_rslt state;
645 uint32_t frame_cnt = 0;
647 PMD_INIT_FUNC_TRACE();
649 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
650 ret = dpaa2_affine_qbman_swp();
652 DPAA2_PMD_ERR("Failure in affining portal");
656 swp = DPAA2_PER_LCORE_PORTAL;
658 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
660 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
661 frame_cnt = qbman_fq_state_frame_count(&state);
662 DPAA2_PMD_DEBUG("RX frame count for q(%d) is %u",
663 rx_queue_id, frame_cnt);
668 static const uint32_t *
669 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
671 static const uint32_t ptypes[] = {
672 /*todo -= add more types */
675 RTE_PTYPE_L3_IPV4_EXT,
677 RTE_PTYPE_L3_IPV6_EXT,
685 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx)
691 * Dpaa2 link Interrupt handler
694 * The address of parameter (struct rte_eth_dev *) regsitered before.
700 dpaa2_interrupt_handler(void *param)
702 struct rte_eth_dev *dev = param;
703 struct dpaa2_dev_priv *priv = dev->data->dev_private;
704 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
706 int irq_index = DPNI_IRQ_INDEX;
707 unsigned int status = 0, clear = 0;
709 PMD_INIT_FUNC_TRACE();
712 DPAA2_PMD_ERR("dpni is NULL");
716 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
719 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
724 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
725 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
726 dpaa2_dev_link_update(dev, 0);
727 /* calling all the apps registered for link status event */
728 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
732 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
735 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
739 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
742 struct dpaa2_dev_priv *priv = dev->data->dev_private;
743 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
744 int irq_index = DPNI_IRQ_INDEX;
745 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
747 PMD_INIT_FUNC_TRACE();
749 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
752 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
757 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
760 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
767 dpaa2_dev_start(struct rte_eth_dev *dev)
769 struct rte_device *rdev = dev->device;
770 struct rte_dpaa2_device *dpaa2_dev;
771 struct rte_eth_dev_data *data = dev->data;
772 struct dpaa2_dev_priv *priv = data->dev_private;
773 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
774 struct dpni_queue cfg;
775 struct dpni_error_cfg err_cfg;
777 struct dpni_queue_id qid;
778 struct dpaa2_queue *dpaa2_q;
780 struct rte_intr_handle *intr_handle;
782 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
783 intr_handle = &dpaa2_dev->intr_handle;
785 PMD_INIT_FUNC_TRACE();
787 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
789 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
794 /* Power up the phy. Needed to make the link go UP */
795 dpaa2_dev_set_link_up(dev);
797 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
798 DPNI_QUEUE_TX, &qdid);
800 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
805 for (i = 0; i < data->nb_rx_queues; i++) {
806 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
807 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
808 DPNI_QUEUE_RX, dpaa2_q->tc_index,
809 dpaa2_q->flow_id, &cfg, &qid);
811 DPAA2_PMD_ERR("Error in getting flow information: "
815 dpaa2_q->fqid = qid.fqid;
818 /*checksum errors, send them to normal path and set it in annotation */
819 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
821 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
822 err_cfg.set_frame_annotation = true;
824 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
825 priv->token, &err_cfg);
827 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
832 /* if the interrupts were configured on this devices*/
833 if (intr_handle && (intr_handle->fd) &&
834 (dev->data->dev_conf.intr_conf.lsc != 0)) {
835 /* Registering LSC interrupt handler */
836 rte_intr_callback_register(intr_handle,
837 dpaa2_interrupt_handler,
840 /* enable vfio intr/eventfd mapping
841 * Interrupt index 0 is required, so we can not use
844 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
846 /* enable dpni_irqs */
847 dpaa2_eth_setup_irqs(dev, 1);
854 * This routine disables all traffic on the adapter by issuing a
855 * global reset on the MAC.
858 dpaa2_dev_stop(struct rte_eth_dev *dev)
860 struct dpaa2_dev_priv *priv = dev->data->dev_private;
861 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
863 struct rte_eth_link link;
864 struct rte_intr_handle *intr_handle = dev->intr_handle;
866 PMD_INIT_FUNC_TRACE();
868 /* reset interrupt callback */
869 if (intr_handle && (intr_handle->fd) &&
870 (dev->data->dev_conf.intr_conf.lsc != 0)) {
871 /*disable dpni irqs */
872 dpaa2_eth_setup_irqs(dev, 0);
874 /* disable vfio intr before callback unregister */
875 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
877 /* Unregistering LSC interrupt handler */
878 rte_intr_callback_unregister(intr_handle,
879 dpaa2_interrupt_handler,
883 dpaa2_dev_set_link_down(dev);
885 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
887 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
892 /* clear the recorded link status */
893 memset(&link, 0, sizeof(link));
894 rte_eth_linkstatus_set(dev, &link);
898 dpaa2_dev_close(struct rte_eth_dev *dev)
900 struct dpaa2_dev_priv *priv = dev->data->dev_private;
901 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
903 struct rte_eth_link link;
905 PMD_INIT_FUNC_TRACE();
907 /* Clean the device first */
908 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
910 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
914 memset(&link, 0, sizeof(link));
915 rte_eth_linkstatus_set(dev, &link);
919 dpaa2_dev_promiscuous_enable(
920 struct rte_eth_dev *dev)
923 struct dpaa2_dev_priv *priv = dev->data->dev_private;
924 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
926 PMD_INIT_FUNC_TRACE();
929 DPAA2_PMD_ERR("dpni is NULL");
933 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
935 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
937 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
939 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
943 dpaa2_dev_promiscuous_disable(
944 struct rte_eth_dev *dev)
947 struct dpaa2_dev_priv *priv = dev->data->dev_private;
948 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
950 PMD_INIT_FUNC_TRACE();
953 DPAA2_PMD_ERR("dpni is NULL");
957 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
959 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
961 if (dev->data->all_multicast == 0) {
962 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
965 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
971 dpaa2_dev_allmulticast_enable(
972 struct rte_eth_dev *dev)
975 struct dpaa2_dev_priv *priv = dev->data->dev_private;
976 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
978 PMD_INIT_FUNC_TRACE();
981 DPAA2_PMD_ERR("dpni is NULL");
985 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
987 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
991 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
994 struct dpaa2_dev_priv *priv = dev->data->dev_private;
995 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
997 PMD_INIT_FUNC_TRACE();
1000 DPAA2_PMD_ERR("dpni is NULL");
1004 /* must remain on for all promiscuous */
1005 if (dev->data->promiscuous == 1)
1008 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1010 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1014 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1017 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1018 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1019 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
1022 PMD_INIT_FUNC_TRACE();
1025 DPAA2_PMD_ERR("dpni is NULL");
1029 /* check that mtu is within the allowed range */
1030 if ((mtu < ETHER_MIN_MTU) || (frame_size > DPAA2_MAX_RX_PKT_LEN))
1033 if (frame_size > ETHER_MAX_LEN)
1034 dev->data->dev_conf.rxmode.offloads &=
1035 DEV_RX_OFFLOAD_JUMBO_FRAME;
1037 dev->data->dev_conf.rxmode.offloads &=
1038 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1040 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1042 /* Set the Max Rx frame length as 'mtu' +
1043 * Maximum Ethernet header length
1045 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1048 DPAA2_PMD_ERR("Setting the max frame length failed");
1051 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1056 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1057 struct ether_addr *addr,
1058 __rte_unused uint32_t index,
1059 __rte_unused uint32_t pool)
1062 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1063 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1065 PMD_INIT_FUNC_TRACE();
1068 DPAA2_PMD_ERR("dpni is NULL");
1072 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW,
1073 priv->token, addr->addr_bytes);
1076 "error: Adding the MAC ADDR failed: err = %d", ret);
1081 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1085 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1086 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1087 struct rte_eth_dev_data *data = dev->data;
1088 struct ether_addr *macaddr;
1090 PMD_INIT_FUNC_TRACE();
1092 macaddr = &data->mac_addrs[index];
1095 DPAA2_PMD_ERR("dpni is NULL");
1099 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1100 priv->token, macaddr->addr_bytes);
1103 "error: Removing the MAC ADDR failed: err = %d", ret);
1107 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1108 struct ether_addr *addr)
1111 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1112 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1114 PMD_INIT_FUNC_TRACE();
1117 DPAA2_PMD_ERR("dpni is NULL");
1121 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1122 priv->token, addr->addr_bytes);
1126 "error: Setting the MAC ADDR failed %d", ret);
1132 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1133 struct rte_eth_stats *stats)
1135 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1136 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1138 uint8_t page0 = 0, page1 = 1, page2 = 2;
1139 union dpni_statistics value;
1141 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1143 memset(&value, 0, sizeof(union dpni_statistics));
1145 PMD_INIT_FUNC_TRACE();
1148 DPAA2_PMD_ERR("dpni is NULL");
1153 DPAA2_PMD_ERR("stats is NULL");
1157 /*Get Counters from page_0*/
1158 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1163 stats->ipackets = value.page_0.ingress_all_frames;
1164 stats->ibytes = value.page_0.ingress_all_bytes;
1166 /*Get Counters from page_1*/
1167 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1172 stats->opackets = value.page_1.egress_all_frames;
1173 stats->obytes = value.page_1.egress_all_bytes;
1175 /*Get Counters from page_2*/
1176 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1181 /* Ingress drop frame count due to configured rules */
1182 stats->ierrors = value.page_2.ingress_filtered_frames;
1183 /* Ingress drop frame count due to error */
1184 stats->ierrors += value.page_2.ingress_discarded_frames;
1186 stats->oerrors = value.page_2.egress_discarded_frames;
1187 stats->imissed = value.page_2.ingress_nobuffer_discards;
1189 /* Fill in per queue stats */
1190 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1191 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1192 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1193 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1195 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1197 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1199 /* Byte counting is not implemented */
1200 stats->q_ibytes[i] = 0;
1201 stats->q_obytes[i] = 0;
1207 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1212 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1215 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1216 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1218 union dpni_statistics value[3] = {};
1219 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1227 /* Get Counters from page_0*/
1228 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1233 /* Get Counters from page_1*/
1234 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1239 /* Get Counters from page_2*/
1240 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1245 for (i = 0; i < num; i++) {
1247 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1248 raw.counter[dpaa2_xstats_strings[i].stats_id];
1252 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1257 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1258 struct rte_eth_xstat_name *xstats_names,
1261 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1263 if (limit < stat_cnt)
1266 if (xstats_names != NULL)
1267 for (i = 0; i < stat_cnt; i++)
1268 snprintf(xstats_names[i].name,
1269 sizeof(xstats_names[i].name),
1271 dpaa2_xstats_strings[i].name);
1277 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1278 uint64_t *values, unsigned int n)
1280 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1281 uint64_t values_copy[stat_cnt];
1284 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1285 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1287 union dpni_statistics value[3] = {};
1295 /* Get Counters from page_0*/
1296 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1301 /* Get Counters from page_1*/
1302 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1307 /* Get Counters from page_2*/
1308 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1313 for (i = 0; i < stat_cnt; i++) {
1314 values[i] = value[dpaa2_xstats_strings[i].page_id].
1315 raw.counter[dpaa2_xstats_strings[i].stats_id];
1320 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1322 for (i = 0; i < n; i++) {
1323 if (ids[i] >= stat_cnt) {
1324 DPAA2_PMD_ERR("xstats id value isn't valid");
1327 values[i] = values_copy[ids[i]];
1333 dpaa2_xstats_get_names_by_id(
1334 struct rte_eth_dev *dev,
1335 struct rte_eth_xstat_name *xstats_names,
1336 const uint64_t *ids,
1339 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1340 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1343 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1345 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1347 for (i = 0; i < limit; i++) {
1348 if (ids[i] >= stat_cnt) {
1349 DPAA2_PMD_ERR("xstats id value isn't valid");
1352 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1358 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1360 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1361 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1364 struct dpaa2_queue *dpaa2_q;
1366 PMD_INIT_FUNC_TRACE();
1369 DPAA2_PMD_ERR("dpni is NULL");
1373 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1377 /* Reset the per queue stats in dpaa2_queue structure */
1378 for (i = 0; i < priv->nb_rx_queues; i++) {
1379 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1381 dpaa2_q->rx_pkts = 0;
1384 for (i = 0; i < priv->nb_tx_queues; i++) {
1385 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1387 dpaa2_q->tx_pkts = 0;
1393 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1397 /* return 0 means link status changed, -1 means not changed */
1399 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1400 int wait_to_complete __rte_unused)
1403 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1404 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1405 struct rte_eth_link link;
1406 struct dpni_link_state state = {0};
1409 DPAA2_PMD_ERR("dpni is NULL");
1413 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1415 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1419 memset(&link, 0, sizeof(struct rte_eth_link));
1420 link.link_status = state.up;
1421 link.link_speed = state.rate;
1423 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1424 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1426 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1428 ret = rte_eth_linkstatus_set(dev, &link);
1430 DPAA2_PMD_DEBUG("No change in status");
1432 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1433 link.link_status ? "Up" : "Down");
1439 * Toggle the DPNI to enable, if not already enabled.
1440 * This is not strictly PHY up/down - it is more of logical toggling.
1443 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1446 struct dpaa2_dev_priv *priv;
1447 struct fsl_mc_io *dpni;
1449 struct dpni_link_state state = {0};
1451 priv = dev->data->dev_private;
1452 dpni = (struct fsl_mc_io *)priv->hw;
1455 DPAA2_PMD_ERR("dpni is NULL");
1459 /* Check if DPNI is currently enabled */
1460 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1462 /* Unable to obtain dpni status; Not continuing */
1463 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1467 /* Enable link if not already enabled */
1469 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1471 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1475 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1477 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1481 /* changing tx burst function to start enqueues */
1482 dev->tx_pkt_burst = dpaa2_dev_tx;
1483 dev->data->dev_link.link_status = state.up;
1486 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1488 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1493 * Toggle the DPNI to disable, if not already disabled.
1494 * This is not strictly PHY up/down - it is more of logical toggling.
1497 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1500 struct dpaa2_dev_priv *priv;
1501 struct fsl_mc_io *dpni;
1502 int dpni_enabled = 0;
1505 PMD_INIT_FUNC_TRACE();
1507 priv = dev->data->dev_private;
1508 dpni = (struct fsl_mc_io *)priv->hw;
1511 DPAA2_PMD_ERR("Device has not yet been configured");
1515 /*changing tx burst function to avoid any more enqueues */
1516 dev->tx_pkt_burst = dummy_dev_tx;
1518 /* Loop while dpni_disable() attempts to drain the egress FQs
1519 * and confirm them back to us.
1522 ret = dpni_disable(dpni, 0, priv->token);
1524 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1527 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1529 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1533 /* Allow the MC some slack */
1534 rte_delay_us(100 * 1000);
1535 } while (dpni_enabled && --retries);
1538 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1539 /* todo- we may have to manually cleanup queues.
1542 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1543 dev->data->port_id);
1546 dev->data->dev_link.link_status = 0;
1552 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1555 struct dpaa2_dev_priv *priv;
1556 struct fsl_mc_io *dpni;
1557 struct dpni_link_state state = {0};
1559 PMD_INIT_FUNC_TRACE();
1561 priv = dev->data->dev_private;
1562 dpni = (struct fsl_mc_io *)priv->hw;
1564 if (dpni == NULL || fc_conf == NULL) {
1565 DPAA2_PMD_ERR("device not configured");
1569 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1571 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1575 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1576 if (state.options & DPNI_LINK_OPT_PAUSE) {
1577 /* DPNI_LINK_OPT_PAUSE set
1578 * if ASYM_PAUSE not set,
1579 * RX Side flow control (handle received Pause frame)
1580 * TX side flow control (send Pause frame)
1581 * if ASYM_PAUSE set,
1582 * RX Side flow control (handle received Pause frame)
1583 * No TX side flow control (send Pause frame disabled)
1585 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1586 fc_conf->mode = RTE_FC_FULL;
1588 fc_conf->mode = RTE_FC_RX_PAUSE;
1590 /* DPNI_LINK_OPT_PAUSE not set
1591 * if ASYM_PAUSE set,
1592 * TX side flow control (send Pause frame)
1593 * No RX side flow control (No action on pause frame rx)
1594 * if ASYM_PAUSE not set,
1595 * Flow control disabled
1597 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1598 fc_conf->mode = RTE_FC_TX_PAUSE;
1600 fc_conf->mode = RTE_FC_NONE;
1607 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1610 struct dpaa2_dev_priv *priv;
1611 struct fsl_mc_io *dpni;
1612 struct dpni_link_state state = {0};
1613 struct dpni_link_cfg cfg = {0};
1615 PMD_INIT_FUNC_TRACE();
1617 priv = dev->data->dev_private;
1618 dpni = (struct fsl_mc_io *)priv->hw;
1621 DPAA2_PMD_ERR("dpni is NULL");
1625 /* It is necessary to obtain the current state before setting fc_conf
1626 * as MC would return error in case rate, autoneg or duplex values are
1629 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1631 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
1635 /* Disable link before setting configuration */
1636 dpaa2_dev_set_link_down(dev);
1638 /* Based on fc_conf, update cfg */
1639 cfg.rate = state.rate;
1640 cfg.options = state.options;
1642 /* update cfg with fc_conf */
1643 switch (fc_conf->mode) {
1645 /* Full flow control;
1646 * OPT_PAUSE set, ASYM_PAUSE not set
1648 cfg.options |= DPNI_LINK_OPT_PAUSE;
1649 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1651 case RTE_FC_TX_PAUSE:
1652 /* Enable RX flow control
1653 * OPT_PAUSE not set;
1656 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1657 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1659 case RTE_FC_RX_PAUSE:
1660 /* Enable TX Flow control
1664 cfg.options |= DPNI_LINK_OPT_PAUSE;
1665 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1668 /* Disable Flow control
1670 * ASYM_PAUSE not set
1672 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1673 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1676 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
1681 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
1683 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
1687 dpaa2_dev_set_link_up(dev);
1693 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
1694 struct rte_eth_rss_conf *rss_conf)
1696 struct rte_eth_dev_data *data = dev->data;
1697 struct rte_eth_conf *eth_conf = &data->dev_conf;
1700 PMD_INIT_FUNC_TRACE();
1702 if (rss_conf->rss_hf) {
1703 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf);
1705 DPAA2_PMD_ERR("Unable to set flow dist");
1709 ret = dpaa2_remove_flow_dist(dev, 0);
1711 DPAA2_PMD_ERR("Unable to remove flow dist");
1715 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1720 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1721 struct rte_eth_rss_conf *rss_conf)
1723 struct rte_eth_dev_data *data = dev->data;
1724 struct rte_eth_conf *eth_conf = &data->dev_conf;
1726 /* dpaa2 does not support rss_key, so length should be 0*/
1727 rss_conf->rss_key_len = 0;
1728 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1732 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
1733 int eth_rx_queue_id,
1735 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1737 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
1738 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw;
1739 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
1740 uint8_t flow_id = dpaa2_ethq->flow_id;
1741 struct dpni_queue cfg;
1745 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
1746 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
1747 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
1748 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
1752 memset(&cfg, 0, sizeof(struct dpni_queue));
1753 options = DPNI_QUEUE_OPT_DEST;
1754 cfg.destination.type = DPNI_DEST_DPCON;
1755 cfg.destination.id = dpcon_id;
1756 cfg.destination.priority = queue_conf->ev.priority;
1758 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
1759 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
1760 cfg.destination.hold_active = 1;
1763 options |= DPNI_QUEUE_OPT_USER_CTX;
1764 cfg.user_context = (size_t)(dpaa2_ethq);
1766 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
1767 dpaa2_ethq->tc_index, flow_id, options, &cfg);
1769 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
1773 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
1778 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
1779 int eth_rx_queue_id)
1781 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
1782 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw;
1783 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
1784 uint8_t flow_id = dpaa2_ethq->flow_id;
1785 struct dpni_queue cfg;
1789 memset(&cfg, 0, sizeof(struct dpni_queue));
1790 options = DPNI_QUEUE_OPT_DEST;
1791 cfg.destination.type = DPNI_DEST_NONE;
1793 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
1794 dpaa2_ethq->tc_index, flow_id, options, &cfg);
1796 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
1801 static struct eth_dev_ops dpaa2_ethdev_ops = {
1802 .dev_configure = dpaa2_eth_dev_configure,
1803 .dev_start = dpaa2_dev_start,
1804 .dev_stop = dpaa2_dev_stop,
1805 .dev_close = dpaa2_dev_close,
1806 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
1807 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
1808 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
1809 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
1810 .dev_set_link_up = dpaa2_dev_set_link_up,
1811 .dev_set_link_down = dpaa2_dev_set_link_down,
1812 .link_update = dpaa2_dev_link_update,
1813 .stats_get = dpaa2_dev_stats_get,
1814 .xstats_get = dpaa2_dev_xstats_get,
1815 .xstats_get_by_id = dpaa2_xstats_get_by_id,
1816 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
1817 .xstats_get_names = dpaa2_xstats_get_names,
1818 .stats_reset = dpaa2_dev_stats_reset,
1819 .xstats_reset = dpaa2_dev_stats_reset,
1820 .fw_version_get = dpaa2_fw_version_get,
1821 .dev_infos_get = dpaa2_dev_info_get,
1822 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
1823 .mtu_set = dpaa2_dev_mtu_set,
1824 .vlan_filter_set = dpaa2_vlan_filter_set,
1825 .vlan_offload_set = dpaa2_vlan_offload_set,
1826 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
1827 .rx_queue_release = dpaa2_dev_rx_queue_release,
1828 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
1829 .tx_queue_release = dpaa2_dev_tx_queue_release,
1830 .rx_queue_count = dpaa2_dev_rx_queue_count,
1831 .flow_ctrl_get = dpaa2_flow_ctrl_get,
1832 .flow_ctrl_set = dpaa2_flow_ctrl_set,
1833 .mac_addr_add = dpaa2_dev_add_mac_addr,
1834 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
1835 .mac_addr_set = dpaa2_dev_set_mac_addr,
1836 .rss_hash_update = dpaa2_dev_rss_hash_update,
1837 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
1840 /* Populate the mac address from physically available (u-boot/firmware) and/or
1841 * one set by higher layers like MC (restool) etc.
1842 * Returns the table of MAC entries (multiple entries)
1845 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
1846 struct ether_addr *mac_entry)
1849 struct ether_addr phy_mac, prime_mac;
1851 memset(&phy_mac, 0, sizeof(struct ether_addr));
1852 memset(&prime_mac, 0, sizeof(struct ether_addr));
1854 /* Get the physical device MAC address */
1855 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
1856 phy_mac.addr_bytes);
1858 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
1862 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
1863 prime_mac.addr_bytes);
1865 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
1869 /* Now that both MAC have been obtained, do:
1870 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
1872 * If empty_mac(phy), return prime.
1873 * if both are empty, create random MAC, set as prime and return
1875 if (!is_zero_ether_addr(&phy_mac)) {
1876 /* If the addresses are not same, overwrite prime */
1877 if (!is_same_ether_addr(&phy_mac, &prime_mac)) {
1878 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
1880 phy_mac.addr_bytes);
1882 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
1886 memcpy(&prime_mac, &phy_mac, sizeof(struct ether_addr));
1888 } else if (is_zero_ether_addr(&prime_mac)) {
1889 /* In case phys and prime, both are zero, create random MAC */
1890 eth_random_addr(prime_mac.addr_bytes);
1891 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
1893 prime_mac.addr_bytes);
1895 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
1900 /* prime_mac the final MAC address */
1901 memcpy(mac_entry, &prime_mac, sizeof(struct ether_addr));
1909 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
1911 struct rte_device *dev = eth_dev->device;
1912 struct rte_dpaa2_device *dpaa2_dev;
1913 struct fsl_mc_io *dpni_dev;
1914 struct dpni_attr attr;
1915 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
1916 struct dpni_buffer_layout layout;
1919 PMD_INIT_FUNC_TRACE();
1921 /* For secondary processes, the primary has done all the work */
1922 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1925 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
1927 hw_id = dpaa2_dev->object_id;
1929 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
1931 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
1935 dpni_dev->regs = rte_mcp_ptr_list[0];
1936 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
1939 "Failure in opening dpni@%d with err code %d",
1945 /* Clean the device first */
1946 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
1948 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
1953 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
1956 "Failure in get dpni@%d attribute, err code %d",
1961 priv->num_rx_tc = attr.num_rx_tcs;
1963 /* Resetting the "num_rx_queues" to equal number of queues in first TC
1964 * as only one TC is supported on Rx Side. Once Multiple TCs will be
1965 * in use for Rx processing then this will be changed or removed.
1967 priv->nb_rx_queues = attr.num_queues;
1969 /* Using number of TX queues as number of TX TCs */
1970 priv->nb_tx_queues = attr.num_tx_tcs;
1972 DPAA2_PMD_DEBUG("RX-TC= %d, nb_rx_queues= %d, nb_tx_queues=%d",
1973 priv->num_rx_tc, priv->nb_rx_queues,
1974 priv->nb_tx_queues);
1976 priv->hw = dpni_dev;
1977 priv->hw_id = hw_id;
1978 priv->options = attr.options;
1979 priv->max_mac_filters = attr.mac_filter_entries;
1980 priv->max_vlan_filters = attr.vlan_filter_entries;
1983 /* Allocate memory for hardware structure for queues */
1984 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
1986 DPAA2_PMD_ERR("Queue allocation Failed");
1990 /* Allocate memory for storing MAC addresses.
1991 * Table of mac_filter_entries size is allocated so that RTE ether lib
1992 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
1994 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
1995 ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
1996 if (eth_dev->data->mac_addrs == NULL) {
1998 "Failed to allocate %d bytes needed to store MAC addresses",
1999 ETHER_ADDR_LEN * attr.mac_filter_entries);
2004 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2006 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2007 rte_free(eth_dev->data->mac_addrs);
2008 eth_dev->data->mac_addrs = NULL;
2012 /* ... tx buffer layout ... */
2013 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2014 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2015 layout.pass_frame_status = 1;
2016 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2017 DPNI_QUEUE_TX, &layout);
2019 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2023 /* ... tx-conf and error buffer layout ... */
2024 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2025 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2026 layout.pass_frame_status = 1;
2027 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2028 DPNI_QUEUE_TX_CONFIRM, &layout);
2030 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2035 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2037 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2038 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2040 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2043 dpaa2_dev_uninit(eth_dev);
2048 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2050 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2051 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
2054 PMD_INIT_FUNC_TRACE();
2056 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2060 DPAA2_PMD_WARN("Already closed or not started");
2064 dpaa2_dev_close(eth_dev);
2066 dpaa2_free_rx_tx_queues(eth_dev);
2068 /* Close the device at underlying layer*/
2069 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2072 "Failure closing dpni device with err code %d",
2076 /* Free the allocated memory for ethernet private data and dpni*/
2080 eth_dev->dev_ops = NULL;
2081 eth_dev->rx_pkt_burst = NULL;
2082 eth_dev->tx_pkt_burst = NULL;
2084 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2089 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2090 struct rte_dpaa2_device *dpaa2_dev)
2092 struct rte_eth_dev *eth_dev;
2095 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2096 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2099 eth_dev->data->dev_private = rte_zmalloc(
2100 "ethdev private structure",
2101 sizeof(struct dpaa2_dev_priv),
2102 RTE_CACHE_LINE_SIZE);
2103 if (eth_dev->data->dev_private == NULL) {
2105 "Unable to allocate memory for private data");
2106 rte_eth_dev_release_port(eth_dev);
2110 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2115 eth_dev->device = &dpaa2_dev->device;
2117 dpaa2_dev->eth_dev = eth_dev;
2118 eth_dev->data->rx_mbuf_alloc_failed = 0;
2120 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2121 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2123 /* Invoke PMD device initialization function */
2124 diag = dpaa2_dev_init(eth_dev);
2126 rte_eth_dev_probing_finish(eth_dev);
2130 rte_eth_dev_release_port(eth_dev);
2135 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2137 struct rte_eth_dev *eth_dev;
2139 eth_dev = dpaa2_dev->eth_dev;
2140 dpaa2_dev_uninit(eth_dev);
2142 rte_eth_dev_release_port(eth_dev);
2147 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2148 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2149 .drv_type = DPAA2_ETH,
2150 .probe = rte_dpaa2_probe,
2151 .remove = rte_dpaa2_remove,
2154 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2156 RTE_INIT(dpaa2_pmd_init_log)
2158 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2");
2159 if (dpaa2_logtype_pmd >= 0)
2160 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE);