1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2020 NXP
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
35 /* Supported Rx offloads */
36 static uint64_t dev_rx_offloads_sup =
37 DEV_RX_OFFLOAD_CHECKSUM |
38 DEV_RX_OFFLOAD_SCTP_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
41 DEV_RX_OFFLOAD_VLAN_STRIP |
42 DEV_RX_OFFLOAD_VLAN_FILTER |
43 DEV_RX_OFFLOAD_JUMBO_FRAME |
44 DEV_RX_OFFLOAD_TIMESTAMP;
46 /* Rx offloads which cannot be disabled */
47 static uint64_t dev_rx_offloads_nodis =
48 DEV_RX_OFFLOAD_RSS_HASH |
49 DEV_RX_OFFLOAD_SCATTER;
51 /* Supported Tx offloads */
52 static uint64_t dev_tx_offloads_sup =
53 DEV_TX_OFFLOAD_VLAN_INSERT |
54 DEV_TX_OFFLOAD_IPV4_CKSUM |
55 DEV_TX_OFFLOAD_UDP_CKSUM |
56 DEV_TX_OFFLOAD_TCP_CKSUM |
57 DEV_TX_OFFLOAD_SCTP_CKSUM |
58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_MT_LOCKFREE |
60 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
62 /* Tx offloads which cannot be disabled */
63 static uint64_t dev_tx_offloads_nodis =
64 DEV_TX_OFFLOAD_MULTI_SEGS;
66 /* enable timestamp in mbuf */
67 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
69 struct rte_dpaa2_xstats_name_off {
70 char name[RTE_ETH_XSTATS_NAME_SIZE];
71 uint8_t page_id; /* dpni statistics page id */
72 uint8_t stats_id; /* stats id in the given page */
75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
76 {"ingress_multicast_frames", 0, 2},
77 {"ingress_multicast_bytes", 0, 3},
78 {"ingress_broadcast_frames", 0, 4},
79 {"ingress_broadcast_bytes", 0, 5},
80 {"egress_multicast_frames", 1, 2},
81 {"egress_multicast_bytes", 1, 3},
82 {"egress_broadcast_frames", 1, 4},
83 {"egress_broadcast_bytes", 1, 5},
84 {"ingress_filtered_frames", 2, 0},
85 {"ingress_discarded_frames", 2, 1},
86 {"ingress_nobuffer_discards", 2, 2},
87 {"egress_discarded_frames", 2, 3},
88 {"egress_confirmed_frames", 2, 4},
89 {"cgr_reject_frames", 4, 0},
90 {"cgr_reject_bytes", 4, 1},
93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
95 RTE_ETH_FILTER_DELETE,
96 RTE_ETH_FILTER_UPDATE,
101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
102 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
104 int wait_to_complete);
105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
113 struct dpaa2_dev_priv *priv = dev->data->dev_private;
114 struct fsl_mc_io *dpni = dev->process_private;
116 PMD_INIT_FUNC_TRACE();
119 DPAA2_PMD_ERR("dpni is NULL");
124 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
127 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
128 priv->token, vlan_id);
131 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
132 ret, vlan_id, priv->hw_id);
138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
140 struct dpaa2_dev_priv *priv = dev->data->dev_private;
141 struct fsl_mc_io *dpni = dev->process_private;
144 PMD_INIT_FUNC_TRACE();
146 if (mask & ETH_VLAN_FILTER_MASK) {
147 /* VLAN Filter not avaialble */
148 if (!priv->max_vlan_filters) {
149 DPAA2_PMD_INFO("VLAN filter not available");
153 if (dev->data->dev_conf.rxmode.offloads &
154 DEV_RX_OFFLOAD_VLAN_FILTER)
155 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
158 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
161 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
169 enum rte_vlan_type vlan_type __rte_unused,
172 struct dpaa2_dev_priv *priv = dev->data->dev_private;
173 struct fsl_mc_io *dpni = dev->process_private;
176 PMD_INIT_FUNC_TRACE();
178 /* nothing to be done for standard vlan tpids */
179 if (tpid == 0x8100 || tpid == 0x88A8)
182 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
185 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
186 /* if already configured tpids, remove them first */
188 struct dpni_custom_tpid_cfg tpid_list = {0};
190 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
191 priv->token, &tpid_list);
194 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
195 priv->token, tpid_list.tpid1);
198 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
206 dpaa2_fw_version_get(struct rte_eth_dev *dev,
211 struct fsl_mc_io *dpni = dev->process_private;
212 struct mc_soc_version mc_plat_info = {0};
213 struct mc_version mc_ver_info = {0};
215 PMD_INIT_FUNC_TRACE();
217 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
218 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
220 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
221 DPAA2_PMD_WARN("\tmc_get_version failed");
223 ret = snprintf(fw_version, fw_size,
228 mc_ver_info.revision);
230 ret += 1; /* add the size of '\0' */
231 if (fw_size < (uint32_t)ret)
238 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
240 struct dpaa2_dev_priv *priv = dev->data->dev_private;
242 PMD_INIT_FUNC_TRACE();
244 dev_info->max_mac_addrs = priv->max_mac_filters;
245 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
246 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
247 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
248 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
249 dev_info->rx_offload_capa = dev_rx_offloads_sup |
250 dev_rx_offloads_nodis;
251 dev_info->tx_offload_capa = dev_tx_offloads_sup |
252 dev_tx_offloads_nodis;
253 dev_info->speed_capa = ETH_LINK_SPEED_1G |
254 ETH_LINK_SPEED_2_5G |
257 dev_info->max_hash_mac_addrs = 0;
258 dev_info->max_vfs = 0;
259 dev_info->max_vmdq_pools = ETH_16_POOLS;
260 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
262 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
263 /* same is rx size for best perf */
264 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
266 dev_info->default_rxportconf.nb_queues = 1;
267 dev_info->default_txportconf.nb_queues = 1;
268 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
269 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
271 if (dpaa2_svr_family == SVR_LX2160A) {
272 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
282 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
283 __rte_unused uint16_t queue_id,
284 struct rte_eth_burst_mode *mode)
286 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
289 const struct burst_info {
292 } rx_offload_map[] = {
293 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
294 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
295 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
296 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
297 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
298 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
299 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
300 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
301 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
302 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
305 /* Update Rx offload info */
306 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
307 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
308 snprintf(mode->info, sizeof(mode->info), "%s",
309 rx_offload_map[i].output);
318 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
319 __rte_unused uint16_t queue_id,
320 struct rte_eth_burst_mode *mode)
322 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
325 const struct burst_info {
328 } tx_offload_map[] = {
329 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
330 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
331 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
332 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
333 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
334 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
335 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
336 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
337 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
340 /* Update Tx offload info */
341 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
342 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
343 snprintf(mode->info, sizeof(mode->info), "%s",
344 tx_offload_map[i].output);
353 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
355 struct dpaa2_dev_priv *priv = dev->data->dev_private;
358 uint8_t num_rxqueue_per_tc;
359 struct dpaa2_queue *mc_q, *mcq;
362 struct dpaa2_queue *dpaa2_q;
364 PMD_INIT_FUNC_TRACE();
366 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
367 if (priv->tx_conf_en)
368 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
370 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
371 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
372 RTE_CACHE_LINE_SIZE);
374 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
378 for (i = 0; i < priv->nb_rx_queues; i++) {
379 mc_q->eth_data = dev->data;
380 priv->rx_vq[i] = mc_q++;
381 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
382 dpaa2_q->q_storage = rte_malloc("dq_storage",
383 sizeof(struct queue_storage_info_t),
384 RTE_CACHE_LINE_SIZE);
385 if (!dpaa2_q->q_storage)
388 memset(dpaa2_q->q_storage, 0,
389 sizeof(struct queue_storage_info_t));
390 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
394 for (i = 0; i < priv->nb_tx_queues; i++) {
395 mc_q->eth_data = dev->data;
396 mc_q->flow_id = 0xffff;
397 priv->tx_vq[i] = mc_q++;
398 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
399 dpaa2_q->cscn = rte_malloc(NULL,
400 sizeof(struct qbman_result), 16);
405 if (priv->tx_conf_en) {
406 /*Setup tx confirmation queues*/
407 for (i = 0; i < priv->nb_tx_queues; i++) {
408 mc_q->eth_data = dev->data;
411 priv->tx_conf_vq[i] = mc_q++;
412 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
414 rte_malloc("dq_storage",
415 sizeof(struct queue_storage_info_t),
416 RTE_CACHE_LINE_SIZE);
417 if (!dpaa2_q->q_storage)
420 memset(dpaa2_q->q_storage, 0,
421 sizeof(struct queue_storage_info_t));
422 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
428 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
429 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
430 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
431 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
439 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
440 rte_free(dpaa2_q->q_storage);
441 priv->tx_conf_vq[i--] = NULL;
443 i = priv->nb_tx_queues;
447 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
448 rte_free(dpaa2_q->cscn);
449 priv->tx_vq[i--] = NULL;
451 i = priv->nb_rx_queues;
454 mc_q = priv->rx_vq[0];
456 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
457 dpaa2_free_dq_storage(dpaa2_q->q_storage);
458 rte_free(dpaa2_q->q_storage);
459 priv->rx_vq[i--] = NULL;
466 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
468 struct dpaa2_dev_priv *priv = dev->data->dev_private;
469 struct dpaa2_queue *dpaa2_q;
472 PMD_INIT_FUNC_TRACE();
474 /* Queue allocation base */
475 if (priv->rx_vq[0]) {
476 /* cleaning up queue storage */
477 for (i = 0; i < priv->nb_rx_queues; i++) {
478 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
479 if (dpaa2_q->q_storage)
480 rte_free(dpaa2_q->q_storage);
482 /* cleanup tx queue cscn */
483 for (i = 0; i < priv->nb_tx_queues; i++) {
484 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
485 rte_free(dpaa2_q->cscn);
487 if (priv->tx_conf_en) {
488 /* cleanup tx conf queue storage */
489 for (i = 0; i < priv->nb_tx_queues; i++) {
490 dpaa2_q = (struct dpaa2_queue *)
492 rte_free(dpaa2_q->q_storage);
495 /*free memory for all queues (RX+TX) */
496 rte_free(priv->rx_vq[0]);
497 priv->rx_vq[0] = NULL;
502 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
504 struct dpaa2_dev_priv *priv = dev->data->dev_private;
505 struct fsl_mc_io *dpni = dev->process_private;
506 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
507 uint64_t rx_offloads = eth_conf->rxmode.offloads;
508 uint64_t tx_offloads = eth_conf->txmode.offloads;
509 int rx_l3_csum_offload = false;
510 int rx_l4_csum_offload = false;
511 int tx_l3_csum_offload = false;
512 int tx_l4_csum_offload = false;
515 PMD_INIT_FUNC_TRACE();
517 /* Rx offloads which are enabled by default */
518 if (dev_rx_offloads_nodis & ~rx_offloads) {
520 "Some of rx offloads enabled by default - requested 0x%" PRIx64
521 " fixed are 0x%" PRIx64,
522 rx_offloads, dev_rx_offloads_nodis);
525 /* Tx offloads which are enabled by default */
526 if (dev_tx_offloads_nodis & ~tx_offloads) {
528 "Some of tx offloads enabled by default - requested 0x%" PRIx64
529 " fixed are 0x%" PRIx64,
530 tx_offloads, dev_tx_offloads_nodis);
533 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
534 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
535 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
536 priv->token, eth_conf->rxmode.max_rx_pkt_len
537 - RTE_ETHER_CRC_LEN);
540 "Unable to set mtu. check config");
544 dev->data->dev_conf.rxmode.max_rx_pkt_len -
545 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
552 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
553 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
554 ret = dpaa2_setup_flow_dist(dev,
555 eth_conf->rx_adv_conf.rss_conf.rss_hf,
559 "Unable to set flow distribution on tc%d."
560 "Check queue config", tc_index);
566 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
567 rx_l3_csum_offload = true;
569 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
570 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
571 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
572 rx_l4_csum_offload = true;
574 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
575 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
577 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
581 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
582 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
584 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
588 #if !defined(RTE_LIBRTE_IEEE1588)
589 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
591 dpaa2_enable_ts[dev->data->port_id] = true;
593 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
594 tx_l3_csum_offload = true;
596 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
597 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
598 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
599 tx_l4_csum_offload = true;
601 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
602 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
604 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
608 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
609 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
611 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
615 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
616 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
617 * to 0 for LS2 in the hardware thus disabling data/annotation
618 * stashing. For LX2 this is fixed in hardware and thus hash result and
619 * parse results can be received in FD using this option.
621 if (dpaa2_svr_family == SVR_LX2160A) {
622 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
623 DPNI_FLCTYPE_HASH, true);
625 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
630 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
631 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
636 /* Function to setup RX flow information. It contains traffic class ID,
637 * flow ID, destination configuration etc.
640 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
641 uint16_t rx_queue_id,
643 unsigned int socket_id __rte_unused,
644 const struct rte_eth_rxconf *rx_conf,
645 struct rte_mempool *mb_pool)
647 struct dpaa2_dev_priv *priv = dev->data->dev_private;
648 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
649 struct dpaa2_queue *dpaa2_q;
650 struct dpni_queue cfg;
656 PMD_INIT_FUNC_TRACE();
658 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
659 dev, rx_queue_id, mb_pool, rx_conf);
661 /* Rx deferred start is not supported */
662 if (rx_conf->rx_deferred_start) {
663 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
668 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
669 bpid = mempool_to_bpid(mb_pool);
670 ret = dpaa2_attach_bp_list(priv,
671 rte_dpaa2_bpid_info[bpid].bp_list);
675 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
676 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
677 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
678 dpaa2_q->nb_desc = UINT16_MAX;
679 dpaa2_q->offloads = rx_conf->offloads;
681 /*Get the flow id from given VQ id*/
682 flow_id = dpaa2_q->flow_id;
683 memset(&cfg, 0, sizeof(struct dpni_queue));
685 options = options | DPNI_QUEUE_OPT_USER_CTX;
686 cfg.user_context = (size_t)(dpaa2_q);
688 /* check if a private cgr available. */
689 for (i = 0; i < priv->max_cgs; i++) {
690 if (!priv->cgid_in_use[i]) {
691 priv->cgid_in_use[i] = 1;
696 if (i < priv->max_cgs) {
697 options |= DPNI_QUEUE_OPT_SET_CGID;
699 dpaa2_q->cgid = cfg.cgid;
701 dpaa2_q->cgid = 0xff;
704 /*if ls2088 or rev2 device, enable the stashing */
706 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
707 options |= DPNI_QUEUE_OPT_FLC;
708 cfg.flc.stash_control = true;
709 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
710 /* 00 00 00 - last 6 bit represent annotation, context stashing,
711 * data stashing setting 01 01 00 (0x14)
712 * (in following order ->DS AS CS)
713 * to enable 1 line data, 1 line annotation.
714 * For LX2, this setting should be 01 00 00 (0x10)
716 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
717 cfg.flc.value |= 0x10;
719 cfg.flc.value |= 0x14;
721 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
722 dpaa2_q->tc_index, flow_id, options, &cfg);
724 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
728 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
729 struct dpni_taildrop taildrop;
732 dpaa2_q->nb_desc = nb_rx_desc;
733 /* Private CGR will use tail drop length as nb_rx_desc.
734 * for rest cases we can use standard byte based tail drop.
735 * There is no HW restriction, but number of CGRs are limited,
736 * hence this restriction is placed.
738 if (dpaa2_q->cgid != 0xff) {
739 /*enabling per rx queue congestion control */
740 taildrop.threshold = nb_rx_desc;
741 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
743 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
745 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
746 DPNI_CP_CONGESTION_GROUP,
749 dpaa2_q->cgid, &taildrop);
751 /*enabling per rx queue congestion control */
752 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
753 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
754 taildrop.oal = CONG_RX_OAL;
755 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
757 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
758 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
759 dpaa2_q->tc_index, flow_id,
763 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
767 } else { /* Disable tail Drop */
768 struct dpni_taildrop taildrop = {0};
769 DPAA2_PMD_INFO("Tail drop is disabled on queue");
772 if (dpaa2_q->cgid != 0xff) {
773 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
774 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
776 dpaa2_q->cgid, &taildrop);
778 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
779 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
780 dpaa2_q->tc_index, flow_id, &taildrop);
783 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
789 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
794 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
795 uint16_t tx_queue_id,
797 unsigned int socket_id __rte_unused,
798 const struct rte_eth_txconf *tx_conf)
800 struct dpaa2_dev_priv *priv = dev->data->dev_private;
801 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
802 priv->tx_vq[tx_queue_id];
803 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
804 priv->tx_conf_vq[tx_queue_id];
805 struct fsl_mc_io *dpni = dev->process_private;
806 struct dpni_queue tx_conf_cfg;
807 struct dpni_queue tx_flow_cfg;
808 uint8_t options = 0, flow_id;
809 struct dpni_queue_id qid;
813 PMD_INIT_FUNC_TRACE();
815 /* Tx deferred start is not supported */
816 if (tx_conf->tx_deferred_start) {
817 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
822 dpaa2_q->nb_desc = UINT16_MAX;
823 dpaa2_q->offloads = tx_conf->offloads;
825 /* Return if queue already configured */
826 if (dpaa2_q->flow_id != 0xffff) {
827 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
831 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
832 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
837 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
838 tc_id, flow_id, options, &tx_flow_cfg);
840 DPAA2_PMD_ERR("Error in setting the tx flow: "
841 "tc_id=%d, flow=%d err=%d",
842 tc_id, flow_id, ret);
846 dpaa2_q->flow_id = flow_id;
848 if (tx_queue_id == 0) {
849 /*Set tx-conf and error configuration*/
850 if (priv->tx_conf_en)
851 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
855 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
859 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
864 dpaa2_q->tc_index = tc_id;
866 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
867 DPNI_QUEUE_TX, dpaa2_q->tc_index,
868 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
870 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
873 dpaa2_q->fqid = qid.fqid;
875 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
876 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
878 dpaa2_q->nb_desc = nb_tx_desc;
880 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
881 cong_notif_cfg.threshold_entry = nb_tx_desc;
882 /* Notify that the queue is not congested when the data in
883 * the queue is below this thershold.
885 cong_notif_cfg.threshold_exit = nb_tx_desc - 24;
886 cong_notif_cfg.message_ctx = 0;
887 cong_notif_cfg.message_iova =
888 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
889 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
890 cong_notif_cfg.notification_mode =
891 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
892 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
893 DPNI_CONG_OPT_COHERENT_WRITE;
894 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
896 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
903 "Error in setting tx congestion notification: "
908 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
909 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
911 if (priv->tx_conf_en) {
912 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
913 options = options | DPNI_QUEUE_OPT_USER_CTX;
914 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
915 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
916 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
917 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
919 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
920 "tc_index=%d, flow=%d err=%d",
921 dpaa2_tx_conf_q->tc_index,
922 dpaa2_tx_conf_q->flow_id, ret);
926 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
927 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
928 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
930 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
933 dpaa2_tx_conf_q->fqid = qid.fqid;
939 dpaa2_dev_rx_queue_release(void *q __rte_unused)
941 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
942 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
943 struct fsl_mc_io *dpni =
944 (struct fsl_mc_io *)priv->eth_dev->process_private;
947 struct dpni_queue cfg;
949 memset(&cfg, 0, sizeof(struct dpni_queue));
950 PMD_INIT_FUNC_TRACE();
951 if (dpaa2_q->cgid != 0xff) {
952 options = DPNI_QUEUE_OPT_CLEAR_CGID;
953 cfg.cgid = dpaa2_q->cgid;
955 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
957 dpaa2_q->tc_index, dpaa2_q->flow_id,
960 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
962 priv->cgid_in_use[dpaa2_q->cgid] = 0;
963 dpaa2_q->cgid = 0xff;
968 dpaa2_dev_tx_queue_release(void *q __rte_unused)
970 PMD_INIT_FUNC_TRACE();
974 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
977 struct dpaa2_dev_priv *priv = dev->data->dev_private;
978 struct dpaa2_queue *dpaa2_q;
979 struct qbman_swp *swp;
980 struct qbman_fq_query_np_rslt state;
981 uint32_t frame_cnt = 0;
983 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
984 ret = dpaa2_affine_qbman_swp();
987 "Failed to allocate IO portal, tid: %d\n",
992 swp = DPAA2_PER_LCORE_PORTAL;
994 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
996 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
997 frame_cnt = qbman_fq_state_frame_count(&state);
998 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
999 rx_queue_id, frame_cnt);
1004 static const uint32_t *
1005 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1007 static const uint32_t ptypes[] = {
1008 /*todo -= add more types */
1011 RTE_PTYPE_L3_IPV4_EXT,
1013 RTE_PTYPE_L3_IPV6_EXT,
1021 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1022 dev->rx_pkt_burst == dpaa2_dev_rx ||
1023 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1029 * Dpaa2 link Interrupt handler
1032 * The address of parameter (struct rte_eth_dev *) regsitered before.
1038 dpaa2_interrupt_handler(void *param)
1040 struct rte_eth_dev *dev = param;
1041 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1042 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1044 int irq_index = DPNI_IRQ_INDEX;
1045 unsigned int status = 0, clear = 0;
1047 PMD_INIT_FUNC_TRACE();
1050 DPAA2_PMD_ERR("dpni is NULL");
1054 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1055 irq_index, &status);
1056 if (unlikely(ret)) {
1057 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1062 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1063 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1064 dpaa2_dev_link_update(dev, 0);
1065 /* calling all the apps registered for link status event */
1066 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1069 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1072 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1076 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1079 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1080 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1081 int irq_index = DPNI_IRQ_INDEX;
1082 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1084 PMD_INIT_FUNC_TRACE();
1086 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1089 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1094 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1097 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1104 dpaa2_dev_start(struct rte_eth_dev *dev)
1106 struct rte_device *rdev = dev->device;
1107 struct rte_dpaa2_device *dpaa2_dev;
1108 struct rte_eth_dev_data *data = dev->data;
1109 struct dpaa2_dev_priv *priv = data->dev_private;
1110 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1111 struct dpni_queue cfg;
1112 struct dpni_error_cfg err_cfg;
1114 struct dpni_queue_id qid;
1115 struct dpaa2_queue *dpaa2_q;
1117 struct rte_intr_handle *intr_handle;
1119 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1120 intr_handle = &dpaa2_dev->intr_handle;
1122 PMD_INIT_FUNC_TRACE();
1124 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1126 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1131 /* Power up the phy. Needed to make the link go UP */
1132 dpaa2_dev_set_link_up(dev);
1134 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1135 DPNI_QUEUE_TX, &qdid);
1137 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1142 for (i = 0; i < data->nb_rx_queues; i++) {
1143 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1144 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1145 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1146 dpaa2_q->flow_id, &cfg, &qid);
1148 DPAA2_PMD_ERR("Error in getting flow information: "
1152 dpaa2_q->fqid = qid.fqid;
1155 /*checksum errors, send them to normal path and set it in annotation */
1156 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1157 err_cfg.errors |= DPNI_ERROR_PHE;
1159 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1160 err_cfg.set_frame_annotation = true;
1162 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1163 priv->token, &err_cfg);
1165 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1170 /* if the interrupts were configured on this devices*/
1171 if (intr_handle && (intr_handle->fd) &&
1172 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1173 /* Registering LSC interrupt handler */
1174 rte_intr_callback_register(intr_handle,
1175 dpaa2_interrupt_handler,
1178 /* enable vfio intr/eventfd mapping
1179 * Interrupt index 0 is required, so we can not use
1182 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1184 /* enable dpni_irqs */
1185 dpaa2_eth_setup_irqs(dev, 1);
1188 /* Change the tx burst function if ordered queues are used */
1189 if (priv->en_ordered)
1190 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1196 * This routine disables all traffic on the adapter by issuing a
1197 * global reset on the MAC.
1200 dpaa2_dev_stop(struct rte_eth_dev *dev)
1202 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1203 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1205 struct rte_eth_link link;
1206 struct rte_intr_handle *intr_handle = dev->intr_handle;
1208 PMD_INIT_FUNC_TRACE();
1210 /* reset interrupt callback */
1211 if (intr_handle && (intr_handle->fd) &&
1212 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1213 /*disable dpni irqs */
1214 dpaa2_eth_setup_irqs(dev, 0);
1216 /* disable vfio intr before callback unregister */
1217 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1219 /* Unregistering LSC interrupt handler */
1220 rte_intr_callback_unregister(intr_handle,
1221 dpaa2_interrupt_handler,
1225 dpaa2_dev_set_link_down(dev);
1227 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1229 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1234 /* clear the recorded link status */
1235 memset(&link, 0, sizeof(link));
1236 rte_eth_linkstatus_set(dev, &link);
1240 dpaa2_dev_close(struct rte_eth_dev *dev)
1242 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1243 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1245 struct rte_eth_link link;
1247 PMD_INIT_FUNC_TRACE();
1249 dpaa2_flow_clean(dev);
1251 /* Clean the device first */
1252 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1254 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1258 memset(&link, 0, sizeof(link));
1259 rte_eth_linkstatus_set(dev, &link);
1265 dpaa2_dev_promiscuous_enable(
1266 struct rte_eth_dev *dev)
1269 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1270 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1272 PMD_INIT_FUNC_TRACE();
1275 DPAA2_PMD_ERR("dpni is NULL");
1279 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1281 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1283 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1285 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1291 dpaa2_dev_promiscuous_disable(
1292 struct rte_eth_dev *dev)
1295 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1296 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1298 PMD_INIT_FUNC_TRACE();
1301 DPAA2_PMD_ERR("dpni is NULL");
1305 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1307 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1309 if (dev->data->all_multicast == 0) {
1310 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1311 priv->token, false);
1313 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1321 dpaa2_dev_allmulticast_enable(
1322 struct rte_eth_dev *dev)
1325 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1326 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1328 PMD_INIT_FUNC_TRACE();
1331 DPAA2_PMD_ERR("dpni is NULL");
1335 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1337 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1343 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1346 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1347 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1349 PMD_INIT_FUNC_TRACE();
1352 DPAA2_PMD_ERR("dpni is NULL");
1356 /* must remain on for all promiscuous */
1357 if (dev->data->promiscuous == 1)
1360 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1362 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1368 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1371 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1372 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1373 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1376 PMD_INIT_FUNC_TRACE();
1379 DPAA2_PMD_ERR("dpni is NULL");
1383 /* check that mtu is within the allowed range */
1384 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1387 if (frame_size > RTE_ETHER_MAX_LEN)
1388 dev->data->dev_conf.rxmode.offloads |=
1389 DEV_RX_OFFLOAD_JUMBO_FRAME;
1391 dev->data->dev_conf.rxmode.offloads &=
1392 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1394 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1396 /* Set the Max Rx frame length as 'mtu' +
1397 * Maximum Ethernet header length
1399 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1400 frame_size - RTE_ETHER_CRC_LEN);
1402 DPAA2_PMD_ERR("Setting the max frame length failed");
1405 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1410 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1411 struct rte_ether_addr *addr,
1412 __rte_unused uint32_t index,
1413 __rte_unused uint32_t pool)
1416 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1417 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1419 PMD_INIT_FUNC_TRACE();
1422 DPAA2_PMD_ERR("dpni is NULL");
1426 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1427 addr->addr_bytes, 0, 0, 0);
1430 "error: Adding the MAC ADDR failed: err = %d", ret);
1435 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1439 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1440 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1441 struct rte_eth_dev_data *data = dev->data;
1442 struct rte_ether_addr *macaddr;
1444 PMD_INIT_FUNC_TRACE();
1446 macaddr = &data->mac_addrs[index];
1449 DPAA2_PMD_ERR("dpni is NULL");
1453 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1454 priv->token, macaddr->addr_bytes);
1457 "error: Removing the MAC ADDR failed: err = %d", ret);
1461 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1462 struct rte_ether_addr *addr)
1465 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1466 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1468 PMD_INIT_FUNC_TRACE();
1471 DPAA2_PMD_ERR("dpni is NULL");
1475 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1476 priv->token, addr->addr_bytes);
1480 "error: Setting the MAC ADDR failed %d", ret);
1486 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1487 struct rte_eth_stats *stats)
1489 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1490 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1492 uint8_t page0 = 0, page1 = 1, page2 = 2;
1493 union dpni_statistics value;
1495 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1497 memset(&value, 0, sizeof(union dpni_statistics));
1499 PMD_INIT_FUNC_TRACE();
1502 DPAA2_PMD_ERR("dpni is NULL");
1507 DPAA2_PMD_ERR("stats is NULL");
1511 /*Get Counters from page_0*/
1512 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1517 stats->ipackets = value.page_0.ingress_all_frames;
1518 stats->ibytes = value.page_0.ingress_all_bytes;
1520 /*Get Counters from page_1*/
1521 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1526 stats->opackets = value.page_1.egress_all_frames;
1527 stats->obytes = value.page_1.egress_all_bytes;
1529 /*Get Counters from page_2*/
1530 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1535 /* Ingress drop frame count due to configured rules */
1536 stats->ierrors = value.page_2.ingress_filtered_frames;
1537 /* Ingress drop frame count due to error */
1538 stats->ierrors += value.page_2.ingress_discarded_frames;
1540 stats->oerrors = value.page_2.egress_discarded_frames;
1541 stats->imissed = value.page_2.ingress_nobuffer_discards;
1543 /* Fill in per queue stats */
1544 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1545 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1546 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1547 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1549 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1551 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1553 /* Byte counting is not implemented */
1554 stats->q_ibytes[i] = 0;
1555 stats->q_obytes[i] = 0;
1561 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1566 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1569 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1570 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1572 union dpni_statistics value[5] = {};
1573 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1581 /* Get Counters from page_0*/
1582 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1587 /* Get Counters from page_1*/
1588 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1593 /* Get Counters from page_2*/
1594 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1599 for (i = 0; i < priv->max_cgs; i++) {
1600 if (!priv->cgid_in_use[i]) {
1601 /* Get Counters from page_4*/
1602 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1611 for (i = 0; i < num; i++) {
1613 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1614 raw.counter[dpaa2_xstats_strings[i].stats_id];
1618 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1623 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1624 struct rte_eth_xstat_name *xstats_names,
1627 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1629 if (limit < stat_cnt)
1632 if (xstats_names != NULL)
1633 for (i = 0; i < stat_cnt; i++)
1634 strlcpy(xstats_names[i].name,
1635 dpaa2_xstats_strings[i].name,
1636 sizeof(xstats_names[i].name));
1642 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1643 uint64_t *values, unsigned int n)
1645 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1646 uint64_t values_copy[stat_cnt];
1649 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1650 struct fsl_mc_io *dpni =
1651 (struct fsl_mc_io *)dev->process_private;
1653 union dpni_statistics value[5] = {};
1661 /* Get Counters from page_0*/
1662 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1667 /* Get Counters from page_1*/
1668 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1673 /* Get Counters from page_2*/
1674 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1679 /* Get Counters from page_4*/
1680 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1685 for (i = 0; i < stat_cnt; i++) {
1686 values[i] = value[dpaa2_xstats_strings[i].page_id].
1687 raw.counter[dpaa2_xstats_strings[i].stats_id];
1692 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1694 for (i = 0; i < n; i++) {
1695 if (ids[i] >= stat_cnt) {
1696 DPAA2_PMD_ERR("xstats id value isn't valid");
1699 values[i] = values_copy[ids[i]];
1705 dpaa2_xstats_get_names_by_id(
1706 struct rte_eth_dev *dev,
1707 struct rte_eth_xstat_name *xstats_names,
1708 const uint64_t *ids,
1711 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1712 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1715 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1717 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1719 for (i = 0; i < limit; i++) {
1720 if (ids[i] >= stat_cnt) {
1721 DPAA2_PMD_ERR("xstats id value isn't valid");
1724 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1730 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1732 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1733 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1736 struct dpaa2_queue *dpaa2_q;
1738 PMD_INIT_FUNC_TRACE();
1741 DPAA2_PMD_ERR("dpni is NULL");
1745 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1749 /* Reset the per queue stats in dpaa2_queue structure */
1750 for (i = 0; i < priv->nb_rx_queues; i++) {
1751 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1753 dpaa2_q->rx_pkts = 0;
1756 for (i = 0; i < priv->nb_tx_queues; i++) {
1757 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1759 dpaa2_q->tx_pkts = 0;
1765 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1769 /* return 0 means link status changed, -1 means not changed */
1771 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1772 int wait_to_complete __rte_unused)
1775 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1776 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1777 struct rte_eth_link link;
1778 struct dpni_link_state state = {0};
1781 DPAA2_PMD_ERR("dpni is NULL");
1785 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1787 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1791 memset(&link, 0, sizeof(struct rte_eth_link));
1792 link.link_status = state.up;
1793 link.link_speed = state.rate;
1795 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1796 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1798 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1800 ret = rte_eth_linkstatus_set(dev, &link);
1802 DPAA2_PMD_DEBUG("No change in status");
1804 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1805 link.link_status ? "Up" : "Down");
1811 * Toggle the DPNI to enable, if not already enabled.
1812 * This is not strictly PHY up/down - it is more of logical toggling.
1815 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1818 struct dpaa2_dev_priv *priv;
1819 struct fsl_mc_io *dpni;
1821 struct dpni_link_state state = {0};
1823 priv = dev->data->dev_private;
1824 dpni = (struct fsl_mc_io *)dev->process_private;
1827 DPAA2_PMD_ERR("dpni is NULL");
1831 /* Check if DPNI is currently enabled */
1832 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1834 /* Unable to obtain dpni status; Not continuing */
1835 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1839 /* Enable link if not already enabled */
1841 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1843 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1847 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1849 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1853 /* changing tx burst function to start enqueues */
1854 dev->tx_pkt_burst = dpaa2_dev_tx;
1855 dev->data->dev_link.link_status = state.up;
1856 dev->data->dev_link.link_speed = state.rate;
1859 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1861 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1866 * Toggle the DPNI to disable, if not already disabled.
1867 * This is not strictly PHY up/down - it is more of logical toggling.
1870 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1873 struct dpaa2_dev_priv *priv;
1874 struct fsl_mc_io *dpni;
1875 int dpni_enabled = 0;
1878 PMD_INIT_FUNC_TRACE();
1880 priv = dev->data->dev_private;
1881 dpni = (struct fsl_mc_io *)dev->process_private;
1884 DPAA2_PMD_ERR("Device has not yet been configured");
1888 /*changing tx burst function to avoid any more enqueues */
1889 dev->tx_pkt_burst = dummy_dev_tx;
1891 /* Loop while dpni_disable() attempts to drain the egress FQs
1892 * and confirm them back to us.
1895 ret = dpni_disable(dpni, 0, priv->token);
1897 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1900 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1902 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1906 /* Allow the MC some slack */
1907 rte_delay_us(100 * 1000);
1908 } while (dpni_enabled && --retries);
1911 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1912 /* todo- we may have to manually cleanup queues.
1915 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1916 dev->data->port_id);
1919 dev->data->dev_link.link_status = 0;
1925 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1928 struct dpaa2_dev_priv *priv;
1929 struct fsl_mc_io *dpni;
1930 struct dpni_link_state state = {0};
1932 PMD_INIT_FUNC_TRACE();
1934 priv = dev->data->dev_private;
1935 dpni = (struct fsl_mc_io *)dev->process_private;
1937 if (dpni == NULL || fc_conf == NULL) {
1938 DPAA2_PMD_ERR("device not configured");
1942 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1944 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1948 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1949 if (state.options & DPNI_LINK_OPT_PAUSE) {
1950 /* DPNI_LINK_OPT_PAUSE set
1951 * if ASYM_PAUSE not set,
1952 * RX Side flow control (handle received Pause frame)
1953 * TX side flow control (send Pause frame)
1954 * if ASYM_PAUSE set,
1955 * RX Side flow control (handle received Pause frame)
1956 * No TX side flow control (send Pause frame disabled)
1958 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1959 fc_conf->mode = RTE_FC_FULL;
1961 fc_conf->mode = RTE_FC_RX_PAUSE;
1963 /* DPNI_LINK_OPT_PAUSE not set
1964 * if ASYM_PAUSE set,
1965 * TX side flow control (send Pause frame)
1966 * No RX side flow control (No action on pause frame rx)
1967 * if ASYM_PAUSE not set,
1968 * Flow control disabled
1970 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1971 fc_conf->mode = RTE_FC_TX_PAUSE;
1973 fc_conf->mode = RTE_FC_NONE;
1980 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1983 struct dpaa2_dev_priv *priv;
1984 struct fsl_mc_io *dpni;
1985 struct dpni_link_state state = {0};
1986 struct dpni_link_cfg cfg = {0};
1988 PMD_INIT_FUNC_TRACE();
1990 priv = dev->data->dev_private;
1991 dpni = (struct fsl_mc_io *)dev->process_private;
1994 DPAA2_PMD_ERR("dpni is NULL");
1998 /* It is necessary to obtain the current state before setting fc_conf
1999 * as MC would return error in case rate, autoneg or duplex values are
2002 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2004 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2008 /* Disable link before setting configuration */
2009 dpaa2_dev_set_link_down(dev);
2011 /* Based on fc_conf, update cfg */
2012 cfg.rate = state.rate;
2013 cfg.options = state.options;
2015 /* update cfg with fc_conf */
2016 switch (fc_conf->mode) {
2018 /* Full flow control;
2019 * OPT_PAUSE set, ASYM_PAUSE not set
2021 cfg.options |= DPNI_LINK_OPT_PAUSE;
2022 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2024 case RTE_FC_TX_PAUSE:
2025 /* Enable RX flow control
2026 * OPT_PAUSE not set;
2029 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2030 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2032 case RTE_FC_RX_PAUSE:
2033 /* Enable TX Flow control
2037 cfg.options |= DPNI_LINK_OPT_PAUSE;
2038 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2041 /* Disable Flow control
2043 * ASYM_PAUSE not set
2045 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2046 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2049 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2054 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2056 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2060 dpaa2_dev_set_link_up(dev);
2066 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2067 struct rte_eth_rss_conf *rss_conf)
2069 struct rte_eth_dev_data *data = dev->data;
2070 struct dpaa2_dev_priv *priv = data->dev_private;
2071 struct rte_eth_conf *eth_conf = &data->dev_conf;
2074 PMD_INIT_FUNC_TRACE();
2076 if (rss_conf->rss_hf) {
2077 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2078 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2081 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2087 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2088 ret = dpaa2_remove_flow_dist(dev, tc_index);
2091 "Unable to remove flow dist on tc%d",
2097 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2102 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2103 struct rte_eth_rss_conf *rss_conf)
2105 struct rte_eth_dev_data *data = dev->data;
2106 struct rte_eth_conf *eth_conf = &data->dev_conf;
2108 /* dpaa2 does not support rss_key, so length should be 0*/
2109 rss_conf->rss_key_len = 0;
2110 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2114 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2115 int eth_rx_queue_id,
2116 struct dpaa2_dpcon_dev *dpcon,
2117 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2119 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2120 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2121 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2122 uint8_t flow_id = dpaa2_ethq->flow_id;
2123 struct dpni_queue cfg;
2124 uint8_t options, priority;
2127 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2128 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2129 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2130 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2131 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2132 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2136 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2137 (dpcon->num_priorities - 1);
2139 memset(&cfg, 0, sizeof(struct dpni_queue));
2140 options = DPNI_QUEUE_OPT_DEST;
2141 cfg.destination.type = DPNI_DEST_DPCON;
2142 cfg.destination.id = dpcon->dpcon_id;
2143 cfg.destination.priority = priority;
2145 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2146 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2147 cfg.destination.hold_active = 1;
2150 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2151 !eth_priv->en_ordered) {
2152 struct opr_cfg ocfg;
2154 /* Restoration window size = 256 frames */
2156 /* Restoration window size = 512 frames for LX2 */
2157 if (dpaa2_svr_family == SVR_LX2160A)
2159 /* Auto advance NESN window enabled */
2161 /* Late arrival window size disabled */
2163 /* ORL resource exhaustaion advance NESN disabled */
2165 /* Loose ordering enabled */
2167 eth_priv->en_loose_ordered = 1;
2168 /* Strict ordering enabled if explicitly set */
2169 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2171 eth_priv->en_loose_ordered = 0;
2174 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2175 dpaa2_ethq->tc_index, flow_id,
2176 OPR_OPT_CREATE, &ocfg);
2178 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2182 eth_priv->en_ordered = 1;
2185 options |= DPNI_QUEUE_OPT_USER_CTX;
2186 cfg.user_context = (size_t)(dpaa2_ethq);
2188 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2189 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2191 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2195 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2200 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2201 int eth_rx_queue_id)
2203 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2204 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2205 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2206 uint8_t flow_id = dpaa2_ethq->flow_id;
2207 struct dpni_queue cfg;
2211 memset(&cfg, 0, sizeof(struct dpni_queue));
2212 options = DPNI_QUEUE_OPT_DEST;
2213 cfg.destination.type = DPNI_DEST_NONE;
2215 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2216 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2218 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2224 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2228 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2229 if (dpaa2_supported_filter_ops[i] == filter_op)
2236 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2237 enum rte_filter_type filter_type,
2238 enum rte_filter_op filter_op,
2246 switch (filter_type) {
2247 case RTE_ETH_FILTER_GENERIC:
2248 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2252 *(const void **)arg = &dpaa2_flow_ops;
2253 dpaa2_filter_type |= filter_type;
2256 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2265 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2266 struct rte_eth_rxq_info *qinfo)
2268 struct dpaa2_queue *rxq;
2270 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2272 qinfo->mp = rxq->mb_pool;
2273 qinfo->scattered_rx = dev->data->scattered_rx;
2274 qinfo->nb_desc = rxq->nb_desc;
2276 qinfo->conf.rx_free_thresh = 1;
2277 qinfo->conf.rx_drop_en = 1;
2278 qinfo->conf.rx_deferred_start = 0;
2279 qinfo->conf.offloads = rxq->offloads;
2283 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2284 struct rte_eth_txq_info *qinfo)
2286 struct dpaa2_queue *txq;
2288 txq = dev->data->tx_queues[queue_id];
2290 qinfo->nb_desc = txq->nb_desc;
2291 qinfo->conf.tx_thresh.pthresh = 0;
2292 qinfo->conf.tx_thresh.hthresh = 0;
2293 qinfo->conf.tx_thresh.wthresh = 0;
2295 qinfo->conf.tx_free_thresh = 0;
2296 qinfo->conf.tx_rs_thresh = 0;
2297 qinfo->conf.offloads = txq->offloads;
2298 qinfo->conf.tx_deferred_start = 0;
2301 static struct eth_dev_ops dpaa2_ethdev_ops = {
2302 .dev_configure = dpaa2_eth_dev_configure,
2303 .dev_start = dpaa2_dev_start,
2304 .dev_stop = dpaa2_dev_stop,
2305 .dev_close = dpaa2_dev_close,
2306 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2307 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2308 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2309 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2310 .dev_set_link_up = dpaa2_dev_set_link_up,
2311 .dev_set_link_down = dpaa2_dev_set_link_down,
2312 .link_update = dpaa2_dev_link_update,
2313 .stats_get = dpaa2_dev_stats_get,
2314 .xstats_get = dpaa2_dev_xstats_get,
2315 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2316 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2317 .xstats_get_names = dpaa2_xstats_get_names,
2318 .stats_reset = dpaa2_dev_stats_reset,
2319 .xstats_reset = dpaa2_dev_stats_reset,
2320 .fw_version_get = dpaa2_fw_version_get,
2321 .dev_infos_get = dpaa2_dev_info_get,
2322 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2323 .mtu_set = dpaa2_dev_mtu_set,
2324 .vlan_filter_set = dpaa2_vlan_filter_set,
2325 .vlan_offload_set = dpaa2_vlan_offload_set,
2326 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2327 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2328 .rx_queue_release = dpaa2_dev_rx_queue_release,
2329 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2330 .tx_queue_release = dpaa2_dev_tx_queue_release,
2331 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2332 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2333 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2334 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2335 .mac_addr_add = dpaa2_dev_add_mac_addr,
2336 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2337 .mac_addr_set = dpaa2_dev_set_mac_addr,
2338 .rss_hash_update = dpaa2_dev_rss_hash_update,
2339 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2340 .filter_ctrl = dpaa2_dev_flow_ctrl,
2341 .rxq_info_get = dpaa2_rxq_info_get,
2342 .txq_info_get = dpaa2_txq_info_get,
2343 #if defined(RTE_LIBRTE_IEEE1588)
2344 .timesync_enable = dpaa2_timesync_enable,
2345 .timesync_disable = dpaa2_timesync_disable,
2346 .timesync_read_time = dpaa2_timesync_read_time,
2347 .timesync_write_time = dpaa2_timesync_write_time,
2348 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2349 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2350 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2354 /* Populate the mac address from physically available (u-boot/firmware) and/or
2355 * one set by higher layers like MC (restool) etc.
2356 * Returns the table of MAC entries (multiple entries)
2359 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2360 struct rte_ether_addr *mac_entry)
2363 struct rte_ether_addr phy_mac, prime_mac;
2365 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2366 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2368 /* Get the physical device MAC address */
2369 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2370 phy_mac.addr_bytes);
2372 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2376 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2377 prime_mac.addr_bytes);
2379 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2383 /* Now that both MAC have been obtained, do:
2384 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2386 * If empty_mac(phy), return prime.
2387 * if both are empty, create random MAC, set as prime and return
2389 if (!rte_is_zero_ether_addr(&phy_mac)) {
2390 /* If the addresses are not same, overwrite prime */
2391 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2392 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2394 phy_mac.addr_bytes);
2396 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2400 memcpy(&prime_mac, &phy_mac,
2401 sizeof(struct rte_ether_addr));
2403 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2404 /* In case phys and prime, both are zero, create random MAC */
2405 rte_eth_random_addr(prime_mac.addr_bytes);
2406 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2408 prime_mac.addr_bytes);
2410 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2415 /* prime_mac the final MAC address */
2416 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2424 check_devargs_handler(__rte_unused const char *key, const char *value,
2425 __rte_unused void *opaque)
2427 if (strcmp(value, "1"))
2434 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2436 struct rte_kvargs *kvlist;
2441 kvlist = rte_kvargs_parse(devargs->args, NULL);
2445 if (!rte_kvargs_count(kvlist, key)) {
2446 rte_kvargs_free(kvlist);
2450 if (rte_kvargs_process(kvlist, key,
2451 check_devargs_handler, NULL) < 0) {
2452 rte_kvargs_free(kvlist);
2455 rte_kvargs_free(kvlist);
2461 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2463 struct rte_device *dev = eth_dev->device;
2464 struct rte_dpaa2_device *dpaa2_dev;
2465 struct fsl_mc_io *dpni_dev;
2466 struct dpni_attr attr;
2467 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2468 struct dpni_buffer_layout layout;
2471 PMD_INIT_FUNC_TRACE();
2473 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2475 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2478 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2479 eth_dev->process_private = (void *)dpni_dev;
2481 /* For secondary processes, the primary has done all the work */
2482 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2483 /* In case of secondary, only burst and ops API need to be
2486 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2487 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2488 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2489 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2490 else if (dpaa2_get_devargs(dev->devargs,
2491 DRIVER_NO_PREFETCH_MODE))
2492 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2494 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2495 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2499 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2501 hw_id = dpaa2_dev->object_id;
2502 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2505 "Failure in opening dpni@%d with err code %d",
2511 /* Clean the device first */
2512 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2514 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2519 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2522 "Failure in get dpni@%d attribute, err code %d",
2527 priv->num_rx_tc = attr.num_rx_tcs;
2528 priv->qos_entries = attr.qos_entries;
2529 priv->fs_entries = attr.fs_entries;
2530 priv->dist_queues = attr.num_queues;
2532 /* only if the custom CG is enabled */
2533 if (attr.options & DPNI_OPT_CUSTOM_CG)
2534 priv->max_cgs = attr.num_cgs;
2538 for (i = 0; i < priv->max_cgs; i++)
2539 priv->cgid_in_use[i] = 0;
2541 for (i = 0; i < attr.num_rx_tcs; i++)
2542 priv->nb_rx_queues += attr.num_queues;
2544 /* Using number of TX queues as number of TX TCs */
2545 priv->nb_tx_queues = attr.num_tx_tcs;
2547 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2548 priv->num_rx_tc, priv->nb_rx_queues,
2549 priv->nb_tx_queues, priv->max_cgs);
2551 priv->hw = dpni_dev;
2552 priv->hw_id = hw_id;
2553 priv->options = attr.options;
2554 priv->max_mac_filters = attr.mac_filter_entries;
2555 priv->max_vlan_filters = attr.vlan_filter_entries;
2557 #if defined(RTE_LIBRTE_IEEE1588)
2558 priv->tx_conf_en = 1;
2560 priv->tx_conf_en = 0;
2563 /* Allocate memory for hardware structure for queues */
2564 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2566 DPAA2_PMD_ERR("Queue allocation Failed");
2570 /* Allocate memory for storing MAC addresses.
2571 * Table of mac_filter_entries size is allocated so that RTE ether lib
2572 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2574 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2575 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2576 if (eth_dev->data->mac_addrs == NULL) {
2578 "Failed to allocate %d bytes needed to store MAC addresses",
2579 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2584 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2586 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2587 rte_free(eth_dev->data->mac_addrs);
2588 eth_dev->data->mac_addrs = NULL;
2592 /* ... tx buffer layout ... */
2593 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2594 if (priv->tx_conf_en) {
2595 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2596 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2597 layout.pass_timestamp = true;
2599 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2601 layout.pass_frame_status = 1;
2602 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2603 DPNI_QUEUE_TX, &layout);
2605 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2609 /* ... tx-conf and error buffer layout ... */
2610 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2611 if (priv->tx_conf_en) {
2612 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2613 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2614 layout.pass_timestamp = true;
2616 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2618 layout.pass_frame_status = 1;
2619 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2620 DPNI_QUEUE_TX_CONFIRM, &layout);
2622 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2627 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2629 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2630 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2631 DPAA2_PMD_INFO("Loopback mode");
2632 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2633 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2634 DPAA2_PMD_INFO("No Prefetch mode");
2636 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2638 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2640 /*Init fields w.r.t. classficaition*/
2641 memset(&priv->extract.qos_key_extract, 0,
2642 sizeof(struct dpaa2_key_extract));
2643 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2644 if (!priv->extract.qos_extract_param) {
2645 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2646 " classificaiton ", ret);
2649 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2650 IP_ADDRESS_OFFSET_INVALID;
2651 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2652 IP_ADDRESS_OFFSET_INVALID;
2653 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2654 IP_ADDRESS_OFFSET_INVALID;
2655 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2656 IP_ADDRESS_OFFSET_INVALID;
2658 for (i = 0; i < MAX_TCS; i++) {
2659 memset(&priv->extract.tc_key_extract[i], 0,
2660 sizeof(struct dpaa2_key_extract));
2661 priv->extract.tc_extract_param[i] =
2662 (size_t)rte_malloc(NULL, 256, 64);
2663 if (!priv->extract.tc_extract_param[i]) {
2664 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2668 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2669 IP_ADDRESS_OFFSET_INVALID;
2670 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2671 IP_ADDRESS_OFFSET_INVALID;
2672 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2673 IP_ADDRESS_OFFSET_INVALID;
2674 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2675 IP_ADDRESS_OFFSET_INVALID;
2678 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2679 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2682 DPAA2_PMD_ERR("Unable to set mtu. check config");
2686 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2687 * with external entity to receive byte code for software sequence
2688 * and same will be offload to the H/W using MC interface.
2689 * Currently it is assumed that DPAA2 driver has byte code by some
2690 * mean and same if offloaded to H/W.
2692 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2693 WRIOP_SS_INITIALIZER(priv);
2694 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2696 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2701 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2704 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2709 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2712 dpaa2_dev_uninit(eth_dev);
2717 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2719 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2720 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_dev->process_private;
2723 PMD_INIT_FUNC_TRACE();
2725 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2729 DPAA2_PMD_WARN("Already closed or not started");
2733 dpaa2_dev_close(eth_dev);
2735 dpaa2_free_rx_tx_queues(eth_dev);
2737 /* Close the device at underlying layer*/
2738 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2741 "Failure closing dpni device with err code %d",
2745 /* Free the allocated memory for ethernet private data and dpni*/
2747 eth_dev->process_private = NULL;
2750 for (i = 0; i < MAX_TCS; i++)
2751 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
2753 if (priv->extract.qos_extract_param)
2754 rte_free((void *)(size_t)priv->extract.qos_extract_param);
2756 eth_dev->dev_ops = NULL;
2757 eth_dev->rx_pkt_burst = NULL;
2758 eth_dev->tx_pkt_burst = NULL;
2760 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2765 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2766 struct rte_dpaa2_device *dpaa2_dev)
2768 struct rte_eth_dev *eth_dev;
2769 struct dpaa2_dev_priv *dev_priv;
2772 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2773 RTE_PKTMBUF_HEADROOM) {
2775 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2776 RTE_PKTMBUF_HEADROOM,
2777 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2782 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2783 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2786 dev_priv = rte_zmalloc("ethdev private structure",
2787 sizeof(struct dpaa2_dev_priv),
2788 RTE_CACHE_LINE_SIZE);
2789 if (dev_priv == NULL) {
2791 "Unable to allocate memory for private data");
2792 rte_eth_dev_release_port(eth_dev);
2795 eth_dev->data->dev_private = (void *)dev_priv;
2796 /* Store a pointer to eth_dev in dev_private */
2797 dev_priv->eth_dev = eth_dev;
2798 dev_priv->tx_conf_en = 0;
2800 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2802 DPAA2_PMD_DEBUG("returning enodev");
2807 eth_dev->device = &dpaa2_dev->device;
2809 dpaa2_dev->eth_dev = eth_dev;
2810 eth_dev->data->rx_mbuf_alloc_failed = 0;
2812 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2813 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2815 /* Invoke PMD device initialization function */
2816 diag = dpaa2_dev_init(eth_dev);
2818 rte_eth_dev_probing_finish(eth_dev);
2822 rte_eth_dev_release_port(eth_dev);
2827 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2829 struct rte_eth_dev *eth_dev;
2831 eth_dev = dpaa2_dev->eth_dev;
2832 dpaa2_dev_uninit(eth_dev);
2834 rte_eth_dev_release_port(eth_dev);
2839 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2840 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2841 .drv_type = DPAA2_ETH,
2842 .probe = rte_dpaa2_probe,
2843 .remove = rte_dpaa2_remove,
2846 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2847 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2848 DRIVER_LOOPBACK_MODE "=<int> "
2849 DRIVER_NO_PREFETCH_MODE "=<int>");
2850 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);