1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include <fsl_qbman_debug.h>
31 #define DRIVER_LOOPBACK_MODE "drv_loopback"
32 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
34 /* Supported Rx offloads */
35 static uint64_t dev_rx_offloads_sup =
36 DEV_RX_OFFLOAD_CHECKSUM |
37 DEV_RX_OFFLOAD_SCTP_CKSUM |
38 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
40 DEV_RX_OFFLOAD_VLAN_STRIP |
41 DEV_RX_OFFLOAD_VLAN_FILTER |
42 DEV_RX_OFFLOAD_JUMBO_FRAME |
43 DEV_RX_OFFLOAD_TIMESTAMP;
45 /* Rx offloads which cannot be disabled */
46 static uint64_t dev_rx_offloads_nodis =
47 DEV_RX_OFFLOAD_SCATTER;
49 /* Supported Tx offloads */
50 static uint64_t dev_tx_offloads_sup =
51 DEV_TX_OFFLOAD_VLAN_INSERT |
52 DEV_TX_OFFLOAD_IPV4_CKSUM |
53 DEV_TX_OFFLOAD_UDP_CKSUM |
54 DEV_TX_OFFLOAD_TCP_CKSUM |
55 DEV_TX_OFFLOAD_SCTP_CKSUM |
56 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
57 DEV_TX_OFFLOAD_MT_LOCKFREE |
58 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
60 /* Tx offloads which cannot be disabled */
61 static uint64_t dev_tx_offloads_nodis =
62 DEV_TX_OFFLOAD_MULTI_SEGS;
64 /* enable timestamp in mbuf */
65 enum pmd_dpaa2_ts dpaa2_enable_ts;
67 struct rte_dpaa2_xstats_name_off {
68 char name[RTE_ETH_XSTATS_NAME_SIZE];
69 uint8_t page_id; /* dpni statistics page id */
70 uint8_t stats_id; /* stats id in the given page */
73 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
74 {"ingress_multicast_frames", 0, 2},
75 {"ingress_multicast_bytes", 0, 3},
76 {"ingress_broadcast_frames", 0, 4},
77 {"ingress_broadcast_bytes", 0, 5},
78 {"egress_multicast_frames", 1, 2},
79 {"egress_multicast_bytes", 1, 3},
80 {"egress_broadcast_frames", 1, 4},
81 {"egress_broadcast_bytes", 1, 5},
82 {"ingress_filtered_frames", 2, 0},
83 {"ingress_discarded_frames", 2, 1},
84 {"ingress_nobuffer_discards", 2, 2},
85 {"egress_discarded_frames", 2, 3},
86 {"egress_confirmed_frames", 2, 4},
89 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
91 RTE_ETH_FILTER_DELETE,
92 RTE_ETH_FILTER_UPDATE,
97 static struct rte_dpaa2_driver rte_dpaa2_pmd;
98 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
99 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
100 int wait_to_complete);
101 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
102 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
103 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
105 int dpaa2_logtype_pmd;
108 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable)
110 dpaa2_enable_ts = enable;
114 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
117 struct dpaa2_dev_priv *priv = dev->data->dev_private;
118 struct fsl_mc_io *dpni = priv->hw;
120 PMD_INIT_FUNC_TRACE();
123 DPAA2_PMD_ERR("dpni is NULL");
128 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW,
129 priv->token, vlan_id);
131 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
132 priv->token, vlan_id);
135 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
136 ret, vlan_id, priv->hw_id);
142 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
144 struct dpaa2_dev_priv *priv = dev->data->dev_private;
145 struct fsl_mc_io *dpni = priv->hw;
148 PMD_INIT_FUNC_TRACE();
150 if (mask & ETH_VLAN_FILTER_MASK) {
151 /* VLAN Filter not avaialble */
152 if (!priv->max_vlan_filters) {
153 DPAA2_PMD_INFO("VLAN filter not available");
157 if (dev->data->dev_conf.rxmode.offloads &
158 DEV_RX_OFFLOAD_VLAN_FILTER)
159 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
162 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
165 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
168 if (mask & ETH_VLAN_EXTEND_MASK) {
169 if (dev->data->dev_conf.rxmode.offloads &
170 DEV_RX_OFFLOAD_VLAN_EXTEND)
171 DPAA2_PMD_INFO("VLAN extend offload not supported");
178 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
179 enum rte_vlan_type vlan_type __rte_unused,
182 struct dpaa2_dev_priv *priv = dev->data->dev_private;
183 struct fsl_mc_io *dpni = priv->hw;
186 PMD_INIT_FUNC_TRACE();
188 /* nothing to be done for standard vlan tpids */
189 if (tpid == 0x8100 || tpid == 0x88A8)
192 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
195 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
196 /* if already configured tpids, remove them first */
198 struct dpni_custom_tpid_cfg tpid_list = {0};
200 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
201 priv->token, &tpid_list);
204 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
205 priv->token, tpid_list.tpid1);
208 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
216 dpaa2_fw_version_get(struct rte_eth_dev *dev,
221 struct dpaa2_dev_priv *priv = dev->data->dev_private;
222 struct fsl_mc_io *dpni = priv->hw;
223 struct mc_soc_version mc_plat_info = {0};
224 struct mc_version mc_ver_info = {0};
226 PMD_INIT_FUNC_TRACE();
228 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
229 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
231 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
232 DPAA2_PMD_WARN("\tmc_get_version failed");
234 ret = snprintf(fw_version, fw_size,
239 mc_ver_info.revision);
241 ret += 1; /* add the size of '\0' */
242 if (fw_size < (uint32_t)ret)
249 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
251 struct dpaa2_dev_priv *priv = dev->data->dev_private;
253 PMD_INIT_FUNC_TRACE();
255 dev_info->if_index = priv->hw_id;
257 dev_info->max_mac_addrs = priv->max_mac_filters;
258 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
259 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
260 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
261 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
262 dev_info->rx_offload_capa = dev_rx_offloads_sup |
263 dev_rx_offloads_nodis;
264 dev_info->tx_offload_capa = dev_tx_offloads_sup |
265 dev_tx_offloads_nodis;
266 dev_info->speed_capa = ETH_LINK_SPEED_1G |
267 ETH_LINK_SPEED_2_5G |
270 dev_info->max_hash_mac_addrs = 0;
271 dev_info->max_vfs = 0;
272 dev_info->max_vmdq_pools = ETH_16_POOLS;
273 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
279 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
281 struct dpaa2_dev_priv *priv = dev->data->dev_private;
284 uint8_t num_rxqueue_per_tc;
285 struct dpaa2_queue *mc_q, *mcq;
288 struct dpaa2_queue *dpaa2_q;
290 PMD_INIT_FUNC_TRACE();
292 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
293 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
294 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
295 RTE_CACHE_LINE_SIZE);
297 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
301 for (i = 0; i < priv->nb_rx_queues; i++) {
302 mc_q->eth_data = dev->data;
303 priv->rx_vq[i] = mc_q++;
304 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
305 dpaa2_q->q_storage = rte_malloc("dq_storage",
306 sizeof(struct queue_storage_info_t),
307 RTE_CACHE_LINE_SIZE);
308 if (!dpaa2_q->q_storage)
311 memset(dpaa2_q->q_storage, 0,
312 sizeof(struct queue_storage_info_t));
313 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
317 for (i = 0; i < priv->nb_tx_queues; i++) {
318 mc_q->eth_data = dev->data;
319 mc_q->flow_id = 0xffff;
320 priv->tx_vq[i] = mc_q++;
321 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
322 dpaa2_q->cscn = rte_malloc(NULL,
323 sizeof(struct qbman_result), 16);
329 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
330 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
331 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
332 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
340 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
341 rte_free(dpaa2_q->cscn);
342 priv->tx_vq[i--] = NULL;
344 i = priv->nb_rx_queues;
347 mc_q = priv->rx_vq[0];
349 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
350 dpaa2_free_dq_storage(dpaa2_q->q_storage);
351 rte_free(dpaa2_q->q_storage);
352 priv->rx_vq[i--] = NULL;
359 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
361 struct dpaa2_dev_priv *priv = dev->data->dev_private;
362 struct dpaa2_queue *dpaa2_q;
365 PMD_INIT_FUNC_TRACE();
367 /* Queue allocation base */
368 if (priv->rx_vq[0]) {
369 /* cleaning up queue storage */
370 for (i = 0; i < priv->nb_rx_queues; i++) {
371 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
372 if (dpaa2_q->q_storage)
373 rte_free(dpaa2_q->q_storage);
375 /* cleanup tx queue cscn */
376 for (i = 0; i < priv->nb_tx_queues; i++) {
377 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
378 rte_free(dpaa2_q->cscn);
380 /*free memory for all queues (RX+TX) */
381 rte_free(priv->rx_vq[0]);
382 priv->rx_vq[0] = NULL;
387 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
389 struct dpaa2_dev_priv *priv = dev->data->dev_private;
390 struct fsl_mc_io *dpni = priv->hw;
391 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
392 uint64_t rx_offloads = eth_conf->rxmode.offloads;
393 uint64_t tx_offloads = eth_conf->txmode.offloads;
394 int rx_l3_csum_offload = false;
395 int rx_l4_csum_offload = false;
396 int tx_l3_csum_offload = false;
397 int tx_l4_csum_offload = false;
400 PMD_INIT_FUNC_TRACE();
402 /* Rx offloads which are enabled by default */
403 if (dev_rx_offloads_nodis & ~rx_offloads) {
405 "Some of rx offloads enabled by default - requested 0x%" PRIx64
406 " fixed are 0x%" PRIx64,
407 rx_offloads, dev_rx_offloads_nodis);
410 /* Tx offloads which are enabled by default */
411 if (dev_tx_offloads_nodis & ~tx_offloads) {
413 "Some of tx offloads enabled by default - requested 0x%" PRIx64
414 " fixed are 0x%" PRIx64,
415 tx_offloads, dev_tx_offloads_nodis);
418 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
419 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
420 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
421 priv->token, eth_conf->rxmode.max_rx_pkt_len);
424 "Unable to set mtu. check config");
432 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
433 ret = dpaa2_setup_flow_dist(dev,
434 eth_conf->rx_adv_conf.rss_conf.rss_hf);
436 DPAA2_PMD_ERR("Unable to set flow distribution."
437 "Check queue config");
442 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
443 rx_l3_csum_offload = true;
445 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
446 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
447 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
448 rx_l4_csum_offload = true;
450 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
451 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
453 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
457 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
458 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
460 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
464 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
465 dpaa2_enable_ts = true;
467 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
468 tx_l3_csum_offload = true;
470 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
471 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
472 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
473 tx_l4_csum_offload = true;
475 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
476 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
478 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
482 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
483 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
485 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
489 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
490 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
491 * to 0 for LS2 in the hardware thus disabling data/annotation
492 * stashing. For LX2 this is fixed in hardware and thus hash result and
493 * parse results can be received in FD using this option.
495 if (dpaa2_svr_family == SVR_LX2160A) {
496 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
497 DPNI_FLCTYPE_HASH, true);
499 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
504 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
505 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
507 /* update the current status */
508 dpaa2_dev_link_update(dev, 0);
513 /* Function to setup RX flow information. It contains traffic class ID,
514 * flow ID, destination configuration etc.
517 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
518 uint16_t rx_queue_id,
519 uint16_t nb_rx_desc __rte_unused,
520 unsigned int socket_id __rte_unused,
521 const struct rte_eth_rxconf *rx_conf __rte_unused,
522 struct rte_mempool *mb_pool)
524 struct dpaa2_dev_priv *priv = dev->data->dev_private;
525 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
526 struct dpaa2_queue *dpaa2_q;
527 struct dpni_queue cfg;
533 PMD_INIT_FUNC_TRACE();
535 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
536 dev, rx_queue_id, mb_pool, rx_conf);
538 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
539 bpid = mempool_to_bpid(mb_pool);
540 ret = dpaa2_attach_bp_list(priv,
541 rte_dpaa2_bpid_info[bpid].bp_list);
545 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
546 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
547 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
549 /*Get the flow id from given VQ id*/
550 flow_id = rx_queue_id % priv->nb_rx_queues;
551 memset(&cfg, 0, sizeof(struct dpni_queue));
553 options = options | DPNI_QUEUE_OPT_USER_CTX;
554 cfg.user_context = (size_t)(dpaa2_q);
556 /*if ls2088 or rev2 device, enable the stashing */
558 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
559 options |= DPNI_QUEUE_OPT_FLC;
560 cfg.flc.stash_control = true;
561 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
562 /* 00 00 00 - last 6 bit represent annotation, context stashing,
563 * data stashing setting 01 01 00 (0x14)
564 * (in following order ->DS AS CS)
565 * to enable 1 line data, 1 line annotation.
566 * For LX2, this setting should be 01 00 00 (0x10)
568 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
569 cfg.flc.value |= 0x10;
571 cfg.flc.value |= 0x14;
573 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
574 dpaa2_q->tc_index, flow_id, options, &cfg);
576 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
580 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
581 struct dpni_taildrop taildrop;
584 /*enabling per rx queue congestion control */
585 taildrop.threshold = CONG_THRESHOLD_RX_Q;
586 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
587 taildrop.oal = CONG_RX_OAL;
588 DPAA2_PMD_DEBUG("Enabling Early Drop on queue = %d",
590 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
591 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
592 dpaa2_q->tc_index, flow_id, &taildrop);
594 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
600 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
605 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
606 uint16_t tx_queue_id,
607 uint16_t nb_tx_desc __rte_unused,
608 unsigned int socket_id __rte_unused,
609 const struct rte_eth_txconf *tx_conf __rte_unused)
611 struct dpaa2_dev_priv *priv = dev->data->dev_private;
612 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
613 priv->tx_vq[tx_queue_id];
614 struct fsl_mc_io *dpni = priv->hw;
615 struct dpni_queue tx_conf_cfg;
616 struct dpni_queue tx_flow_cfg;
617 uint8_t options = 0, flow_id;
621 PMD_INIT_FUNC_TRACE();
623 /* Return if queue already configured */
624 if (dpaa2_q->flow_id != 0xffff) {
625 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
629 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
630 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
635 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
636 tc_id, flow_id, options, &tx_flow_cfg);
638 DPAA2_PMD_ERR("Error in setting the tx flow: "
639 "tc_id=%d, flow=%d err=%d",
640 tc_id, flow_id, ret);
644 dpaa2_q->flow_id = flow_id;
646 if (tx_queue_id == 0) {
647 /*Set tx-conf and error configuration*/
648 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
652 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
657 dpaa2_q->tc_index = tc_id;
659 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
660 struct dpni_congestion_notification_cfg cong_notif_cfg;
662 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
663 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
664 /* Notify that the queue is not congested when the data in
665 * the queue is below this thershold.
667 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
668 cong_notif_cfg.message_ctx = 0;
669 cong_notif_cfg.message_iova =
670 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
671 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
672 cong_notif_cfg.notification_mode =
673 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
674 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
675 DPNI_CONG_OPT_COHERENT_WRITE;
676 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
678 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
685 "Error in setting tx congestion notification: "
690 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
691 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
696 dpaa2_dev_rx_queue_release(void *q __rte_unused)
698 PMD_INIT_FUNC_TRACE();
702 dpaa2_dev_tx_queue_release(void *q __rte_unused)
704 PMD_INIT_FUNC_TRACE();
708 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
711 struct dpaa2_dev_priv *priv = dev->data->dev_private;
712 struct dpaa2_queue *dpaa2_q;
713 struct qbman_swp *swp;
714 struct qbman_fq_query_np_rslt state;
715 uint32_t frame_cnt = 0;
717 PMD_INIT_FUNC_TRACE();
719 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
720 ret = dpaa2_affine_qbman_swp();
722 DPAA2_PMD_ERR("Failure in affining portal");
726 swp = DPAA2_PER_LCORE_PORTAL;
728 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
730 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
731 frame_cnt = qbman_fq_state_frame_count(&state);
732 DPAA2_PMD_DEBUG("RX frame count for q(%d) is %u",
733 rx_queue_id, frame_cnt);
738 static const uint32_t *
739 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
741 static const uint32_t ptypes[] = {
742 /*todo -= add more types */
745 RTE_PTYPE_L3_IPV4_EXT,
747 RTE_PTYPE_L3_IPV6_EXT,
755 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
756 dev->rx_pkt_burst == dpaa2_dev_rx ||
757 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
763 * Dpaa2 link Interrupt handler
766 * The address of parameter (struct rte_eth_dev *) regsitered before.
772 dpaa2_interrupt_handler(void *param)
774 struct rte_eth_dev *dev = param;
775 struct dpaa2_dev_priv *priv = dev->data->dev_private;
776 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
778 int irq_index = DPNI_IRQ_INDEX;
779 unsigned int status = 0, clear = 0;
781 PMD_INIT_FUNC_TRACE();
784 DPAA2_PMD_ERR("dpni is NULL");
788 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
791 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
796 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
797 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
798 dpaa2_dev_link_update(dev, 0);
799 /* calling all the apps registered for link status event */
800 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
804 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
807 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
811 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
814 struct dpaa2_dev_priv *priv = dev->data->dev_private;
815 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
816 int irq_index = DPNI_IRQ_INDEX;
817 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
819 PMD_INIT_FUNC_TRACE();
821 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
824 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
829 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
832 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
839 dpaa2_dev_start(struct rte_eth_dev *dev)
841 struct rte_device *rdev = dev->device;
842 struct rte_dpaa2_device *dpaa2_dev;
843 struct rte_eth_dev_data *data = dev->data;
844 struct dpaa2_dev_priv *priv = data->dev_private;
845 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
846 struct dpni_queue cfg;
847 struct dpni_error_cfg err_cfg;
849 struct dpni_queue_id qid;
850 struct dpaa2_queue *dpaa2_q;
852 struct rte_intr_handle *intr_handle;
854 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
855 intr_handle = &dpaa2_dev->intr_handle;
857 PMD_INIT_FUNC_TRACE();
859 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
861 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
866 /* Power up the phy. Needed to make the link go UP */
867 dpaa2_dev_set_link_up(dev);
869 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
870 DPNI_QUEUE_TX, &qdid);
872 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
877 for (i = 0; i < data->nb_rx_queues; i++) {
878 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
879 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
880 DPNI_QUEUE_RX, dpaa2_q->tc_index,
881 dpaa2_q->flow_id, &cfg, &qid);
883 DPAA2_PMD_ERR("Error in getting flow information: "
887 dpaa2_q->fqid = qid.fqid;
890 /*checksum errors, send them to normal path and set it in annotation */
891 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
892 err_cfg.errors |= DPNI_ERROR_PHE;
894 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
895 err_cfg.set_frame_annotation = true;
897 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
898 priv->token, &err_cfg);
900 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
905 /* if the interrupts were configured on this devices*/
906 if (intr_handle && (intr_handle->fd) &&
907 (dev->data->dev_conf.intr_conf.lsc != 0)) {
908 /* Registering LSC interrupt handler */
909 rte_intr_callback_register(intr_handle,
910 dpaa2_interrupt_handler,
913 /* enable vfio intr/eventfd mapping
914 * Interrupt index 0 is required, so we can not use
917 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
919 /* enable dpni_irqs */
920 dpaa2_eth_setup_irqs(dev, 1);
923 /* Change the tx burst function if ordered queues are used */
924 if (priv->en_ordered)
925 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
931 * This routine disables all traffic on the adapter by issuing a
932 * global reset on the MAC.
935 dpaa2_dev_stop(struct rte_eth_dev *dev)
937 struct dpaa2_dev_priv *priv = dev->data->dev_private;
938 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
940 struct rte_eth_link link;
941 struct rte_intr_handle *intr_handle = dev->intr_handle;
943 PMD_INIT_FUNC_TRACE();
945 /* reset interrupt callback */
946 if (intr_handle && (intr_handle->fd) &&
947 (dev->data->dev_conf.intr_conf.lsc != 0)) {
948 /*disable dpni irqs */
949 dpaa2_eth_setup_irqs(dev, 0);
951 /* disable vfio intr before callback unregister */
952 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
954 /* Unregistering LSC interrupt handler */
955 rte_intr_callback_unregister(intr_handle,
956 dpaa2_interrupt_handler,
960 dpaa2_dev_set_link_down(dev);
962 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
964 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
969 /* clear the recorded link status */
970 memset(&link, 0, sizeof(link));
971 rte_eth_linkstatus_set(dev, &link);
975 dpaa2_dev_close(struct rte_eth_dev *dev)
977 struct dpaa2_dev_priv *priv = dev->data->dev_private;
978 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
980 struct rte_eth_link link;
982 PMD_INIT_FUNC_TRACE();
984 dpaa2_flow_clean(dev);
986 /* Clean the device first */
987 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
989 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
993 memset(&link, 0, sizeof(link));
994 rte_eth_linkstatus_set(dev, &link);
998 dpaa2_dev_promiscuous_enable(
999 struct rte_eth_dev *dev)
1002 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1003 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1005 PMD_INIT_FUNC_TRACE();
1008 DPAA2_PMD_ERR("dpni is NULL");
1012 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1014 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1016 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1018 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1024 dpaa2_dev_promiscuous_disable(
1025 struct rte_eth_dev *dev)
1028 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1029 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1031 PMD_INIT_FUNC_TRACE();
1034 DPAA2_PMD_ERR("dpni is NULL");
1038 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1040 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1042 if (dev->data->all_multicast == 0) {
1043 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1044 priv->token, false);
1046 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1054 dpaa2_dev_allmulticast_enable(
1055 struct rte_eth_dev *dev)
1058 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1059 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1061 PMD_INIT_FUNC_TRACE();
1064 DPAA2_PMD_ERR("dpni is NULL");
1068 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1070 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1076 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1079 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1080 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1082 PMD_INIT_FUNC_TRACE();
1085 DPAA2_PMD_ERR("dpni is NULL");
1089 /* must remain on for all promiscuous */
1090 if (dev->data->promiscuous == 1)
1093 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1095 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1101 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1104 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1105 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1106 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1109 PMD_INIT_FUNC_TRACE();
1112 DPAA2_PMD_ERR("dpni is NULL");
1116 /* check that mtu is within the allowed range */
1117 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1120 if (frame_size > RTE_ETHER_MAX_LEN)
1121 dev->data->dev_conf.rxmode.offloads &=
1122 DEV_RX_OFFLOAD_JUMBO_FRAME;
1124 dev->data->dev_conf.rxmode.offloads &=
1125 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1127 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1129 /* Set the Max Rx frame length as 'mtu' +
1130 * Maximum Ethernet header length
1132 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1135 DPAA2_PMD_ERR("Setting the max frame length failed");
1138 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1143 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1144 struct rte_ether_addr *addr,
1145 __rte_unused uint32_t index,
1146 __rte_unused uint32_t pool)
1149 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1150 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1152 PMD_INIT_FUNC_TRACE();
1155 DPAA2_PMD_ERR("dpni is NULL");
1159 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW,
1160 priv->token, addr->addr_bytes);
1163 "error: Adding the MAC ADDR failed: err = %d", ret);
1168 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1172 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1173 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1174 struct rte_eth_dev_data *data = dev->data;
1175 struct rte_ether_addr *macaddr;
1177 PMD_INIT_FUNC_TRACE();
1179 macaddr = &data->mac_addrs[index];
1182 DPAA2_PMD_ERR("dpni is NULL");
1186 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1187 priv->token, macaddr->addr_bytes);
1190 "error: Removing the MAC ADDR failed: err = %d", ret);
1194 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1195 struct rte_ether_addr *addr)
1198 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1199 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1201 PMD_INIT_FUNC_TRACE();
1204 DPAA2_PMD_ERR("dpni is NULL");
1208 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1209 priv->token, addr->addr_bytes);
1213 "error: Setting the MAC ADDR failed %d", ret);
1219 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1220 struct rte_eth_stats *stats)
1222 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1223 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1225 uint8_t page0 = 0, page1 = 1, page2 = 2;
1226 union dpni_statistics value;
1228 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1230 memset(&value, 0, sizeof(union dpni_statistics));
1232 PMD_INIT_FUNC_TRACE();
1235 DPAA2_PMD_ERR("dpni is NULL");
1240 DPAA2_PMD_ERR("stats is NULL");
1244 /*Get Counters from page_0*/
1245 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1250 stats->ipackets = value.page_0.ingress_all_frames;
1251 stats->ibytes = value.page_0.ingress_all_bytes;
1253 /*Get Counters from page_1*/
1254 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1259 stats->opackets = value.page_1.egress_all_frames;
1260 stats->obytes = value.page_1.egress_all_bytes;
1262 /*Get Counters from page_2*/
1263 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1268 /* Ingress drop frame count due to configured rules */
1269 stats->ierrors = value.page_2.ingress_filtered_frames;
1270 /* Ingress drop frame count due to error */
1271 stats->ierrors += value.page_2.ingress_discarded_frames;
1273 stats->oerrors = value.page_2.egress_discarded_frames;
1274 stats->imissed = value.page_2.ingress_nobuffer_discards;
1276 /* Fill in per queue stats */
1277 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1278 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1279 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1280 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1282 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1284 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1286 /* Byte counting is not implemented */
1287 stats->q_ibytes[i] = 0;
1288 stats->q_obytes[i] = 0;
1294 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1299 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1302 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1303 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1305 union dpni_statistics value[3] = {};
1306 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1314 /* Get Counters from page_0*/
1315 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1320 /* Get Counters from page_1*/
1321 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1326 /* Get Counters from page_2*/
1327 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1332 for (i = 0; i < num; i++) {
1334 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1335 raw.counter[dpaa2_xstats_strings[i].stats_id];
1339 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1344 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1345 struct rte_eth_xstat_name *xstats_names,
1348 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1350 if (limit < stat_cnt)
1353 if (xstats_names != NULL)
1354 for (i = 0; i < stat_cnt; i++)
1355 strlcpy(xstats_names[i].name,
1356 dpaa2_xstats_strings[i].name,
1357 sizeof(xstats_names[i].name));
1363 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1364 uint64_t *values, unsigned int n)
1366 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1367 uint64_t values_copy[stat_cnt];
1370 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1371 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1373 union dpni_statistics value[3] = {};
1381 /* Get Counters from page_0*/
1382 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1387 /* Get Counters from page_1*/
1388 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1393 /* Get Counters from page_2*/
1394 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1399 for (i = 0; i < stat_cnt; i++) {
1400 values[i] = value[dpaa2_xstats_strings[i].page_id].
1401 raw.counter[dpaa2_xstats_strings[i].stats_id];
1406 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1408 for (i = 0; i < n; i++) {
1409 if (ids[i] >= stat_cnt) {
1410 DPAA2_PMD_ERR("xstats id value isn't valid");
1413 values[i] = values_copy[ids[i]];
1419 dpaa2_xstats_get_names_by_id(
1420 struct rte_eth_dev *dev,
1421 struct rte_eth_xstat_name *xstats_names,
1422 const uint64_t *ids,
1425 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1426 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1429 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1431 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1433 for (i = 0; i < limit; i++) {
1434 if (ids[i] >= stat_cnt) {
1435 DPAA2_PMD_ERR("xstats id value isn't valid");
1438 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1444 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1446 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1447 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1450 struct dpaa2_queue *dpaa2_q;
1452 PMD_INIT_FUNC_TRACE();
1455 DPAA2_PMD_ERR("dpni is NULL");
1459 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1463 /* Reset the per queue stats in dpaa2_queue structure */
1464 for (i = 0; i < priv->nb_rx_queues; i++) {
1465 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1467 dpaa2_q->rx_pkts = 0;
1470 for (i = 0; i < priv->nb_tx_queues; i++) {
1471 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1473 dpaa2_q->tx_pkts = 0;
1479 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1483 /* return 0 means link status changed, -1 means not changed */
1485 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1486 int wait_to_complete __rte_unused)
1489 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1490 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
1491 struct rte_eth_link link;
1492 struct dpni_link_state state = {0};
1495 DPAA2_PMD_ERR("dpni is NULL");
1499 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1501 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1505 memset(&link, 0, sizeof(struct rte_eth_link));
1506 link.link_status = state.up;
1507 link.link_speed = state.rate;
1509 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1510 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1512 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1514 ret = rte_eth_linkstatus_set(dev, &link);
1516 DPAA2_PMD_DEBUG("No change in status");
1518 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1519 link.link_status ? "Up" : "Down");
1525 * Toggle the DPNI to enable, if not already enabled.
1526 * This is not strictly PHY up/down - it is more of logical toggling.
1529 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1532 struct dpaa2_dev_priv *priv;
1533 struct fsl_mc_io *dpni;
1535 struct dpni_link_state state = {0};
1537 priv = dev->data->dev_private;
1538 dpni = (struct fsl_mc_io *)priv->hw;
1541 DPAA2_PMD_ERR("dpni is NULL");
1545 /* Check if DPNI is currently enabled */
1546 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1548 /* Unable to obtain dpni status; Not continuing */
1549 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1553 /* Enable link if not already enabled */
1555 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1557 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1561 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1563 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1567 /* changing tx burst function to start enqueues */
1568 dev->tx_pkt_burst = dpaa2_dev_tx;
1569 dev->data->dev_link.link_status = state.up;
1572 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1574 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1579 * Toggle the DPNI to disable, if not already disabled.
1580 * This is not strictly PHY up/down - it is more of logical toggling.
1583 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1586 struct dpaa2_dev_priv *priv;
1587 struct fsl_mc_io *dpni;
1588 int dpni_enabled = 0;
1591 PMD_INIT_FUNC_TRACE();
1593 priv = dev->data->dev_private;
1594 dpni = (struct fsl_mc_io *)priv->hw;
1597 DPAA2_PMD_ERR("Device has not yet been configured");
1601 /*changing tx burst function to avoid any more enqueues */
1602 dev->tx_pkt_burst = dummy_dev_tx;
1604 /* Loop while dpni_disable() attempts to drain the egress FQs
1605 * and confirm them back to us.
1608 ret = dpni_disable(dpni, 0, priv->token);
1610 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1613 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1615 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1619 /* Allow the MC some slack */
1620 rte_delay_us(100 * 1000);
1621 } while (dpni_enabled && --retries);
1624 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1625 /* todo- we may have to manually cleanup queues.
1628 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1629 dev->data->port_id);
1632 dev->data->dev_link.link_status = 0;
1638 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1641 struct dpaa2_dev_priv *priv;
1642 struct fsl_mc_io *dpni;
1643 struct dpni_link_state state = {0};
1645 PMD_INIT_FUNC_TRACE();
1647 priv = dev->data->dev_private;
1648 dpni = (struct fsl_mc_io *)priv->hw;
1650 if (dpni == NULL || fc_conf == NULL) {
1651 DPAA2_PMD_ERR("device not configured");
1655 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1657 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1661 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1662 if (state.options & DPNI_LINK_OPT_PAUSE) {
1663 /* DPNI_LINK_OPT_PAUSE set
1664 * if ASYM_PAUSE not set,
1665 * RX Side flow control (handle received Pause frame)
1666 * TX side flow control (send Pause frame)
1667 * if ASYM_PAUSE set,
1668 * RX Side flow control (handle received Pause frame)
1669 * No TX side flow control (send Pause frame disabled)
1671 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1672 fc_conf->mode = RTE_FC_FULL;
1674 fc_conf->mode = RTE_FC_RX_PAUSE;
1676 /* DPNI_LINK_OPT_PAUSE not set
1677 * if ASYM_PAUSE set,
1678 * TX side flow control (send Pause frame)
1679 * No RX side flow control (No action on pause frame rx)
1680 * if ASYM_PAUSE not set,
1681 * Flow control disabled
1683 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1684 fc_conf->mode = RTE_FC_TX_PAUSE;
1686 fc_conf->mode = RTE_FC_NONE;
1693 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1696 struct dpaa2_dev_priv *priv;
1697 struct fsl_mc_io *dpni;
1698 struct dpni_link_state state = {0};
1699 struct dpni_link_cfg cfg = {0};
1701 PMD_INIT_FUNC_TRACE();
1703 priv = dev->data->dev_private;
1704 dpni = (struct fsl_mc_io *)priv->hw;
1707 DPAA2_PMD_ERR("dpni is NULL");
1711 /* It is necessary to obtain the current state before setting fc_conf
1712 * as MC would return error in case rate, autoneg or duplex values are
1715 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1717 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
1721 /* Disable link before setting configuration */
1722 dpaa2_dev_set_link_down(dev);
1724 /* Based on fc_conf, update cfg */
1725 cfg.rate = state.rate;
1726 cfg.options = state.options;
1728 /* update cfg with fc_conf */
1729 switch (fc_conf->mode) {
1731 /* Full flow control;
1732 * OPT_PAUSE set, ASYM_PAUSE not set
1734 cfg.options |= DPNI_LINK_OPT_PAUSE;
1735 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1737 case RTE_FC_TX_PAUSE:
1738 /* Enable RX flow control
1739 * OPT_PAUSE not set;
1742 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1743 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1745 case RTE_FC_RX_PAUSE:
1746 /* Enable TX Flow control
1750 cfg.options |= DPNI_LINK_OPT_PAUSE;
1751 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1754 /* Disable Flow control
1756 * ASYM_PAUSE not set
1758 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1759 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1762 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
1767 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
1769 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
1773 dpaa2_dev_set_link_up(dev);
1779 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
1780 struct rte_eth_rss_conf *rss_conf)
1782 struct rte_eth_dev_data *data = dev->data;
1783 struct rte_eth_conf *eth_conf = &data->dev_conf;
1786 PMD_INIT_FUNC_TRACE();
1788 if (rss_conf->rss_hf) {
1789 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf);
1791 DPAA2_PMD_ERR("Unable to set flow dist");
1795 ret = dpaa2_remove_flow_dist(dev, 0);
1797 DPAA2_PMD_ERR("Unable to remove flow dist");
1801 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1806 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1807 struct rte_eth_rss_conf *rss_conf)
1809 struct rte_eth_dev_data *data = dev->data;
1810 struct rte_eth_conf *eth_conf = &data->dev_conf;
1812 /* dpaa2 does not support rss_key, so length should be 0*/
1813 rss_conf->rss_key_len = 0;
1814 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1818 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
1819 int eth_rx_queue_id,
1821 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1823 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
1824 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw;
1825 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
1826 uint8_t flow_id = dpaa2_ethq->flow_id;
1827 struct dpni_queue cfg;
1831 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
1832 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
1833 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
1834 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
1835 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
1836 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
1840 memset(&cfg, 0, sizeof(struct dpni_queue));
1841 options = DPNI_QUEUE_OPT_DEST;
1842 cfg.destination.type = DPNI_DEST_DPCON;
1843 cfg.destination.id = dpcon_id;
1844 cfg.destination.priority = queue_conf->ev.priority;
1846 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
1847 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
1848 cfg.destination.hold_active = 1;
1851 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
1852 !eth_priv->en_ordered) {
1853 struct opr_cfg ocfg;
1855 /* Restoration window size = 256 frames */
1857 /* Restoration window size = 512 frames for LX2 */
1858 if (dpaa2_svr_family == SVR_LX2160A)
1860 /* Auto advance NESN window enabled */
1862 /* Late arrival window size disabled */
1864 /* ORL resource exhaustaion advance NESN disabled */
1866 /* Loose ordering enabled */
1868 eth_priv->en_loose_ordered = 1;
1869 /* Strict ordering enabled if explicitly set */
1870 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
1872 eth_priv->en_loose_ordered = 0;
1875 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
1876 dpaa2_ethq->tc_index, flow_id,
1877 OPR_OPT_CREATE, &ocfg);
1879 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
1883 eth_priv->en_ordered = 1;
1886 options |= DPNI_QUEUE_OPT_USER_CTX;
1887 cfg.user_context = (size_t)(dpaa2_ethq);
1889 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
1890 dpaa2_ethq->tc_index, flow_id, options, &cfg);
1892 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
1896 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
1901 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
1902 int eth_rx_queue_id)
1904 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
1905 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw;
1906 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
1907 uint8_t flow_id = dpaa2_ethq->flow_id;
1908 struct dpni_queue cfg;
1912 memset(&cfg, 0, sizeof(struct dpni_queue));
1913 options = DPNI_QUEUE_OPT_DEST;
1914 cfg.destination.type = DPNI_DEST_NONE;
1916 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
1917 dpaa2_ethq->tc_index, flow_id, options, &cfg);
1919 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
1925 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
1929 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
1930 if (dpaa2_supported_filter_ops[i] == filter_op)
1937 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
1938 enum rte_filter_type filter_type,
1939 enum rte_filter_op filter_op,
1947 switch (filter_type) {
1948 case RTE_ETH_FILTER_GENERIC:
1949 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
1953 *(const void **)arg = &dpaa2_flow_ops;
1954 dpaa2_filter_type |= filter_type;
1957 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
1965 static struct eth_dev_ops dpaa2_ethdev_ops = {
1966 .dev_configure = dpaa2_eth_dev_configure,
1967 .dev_start = dpaa2_dev_start,
1968 .dev_stop = dpaa2_dev_stop,
1969 .dev_close = dpaa2_dev_close,
1970 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
1971 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
1972 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
1973 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
1974 .dev_set_link_up = dpaa2_dev_set_link_up,
1975 .dev_set_link_down = dpaa2_dev_set_link_down,
1976 .link_update = dpaa2_dev_link_update,
1977 .stats_get = dpaa2_dev_stats_get,
1978 .xstats_get = dpaa2_dev_xstats_get,
1979 .xstats_get_by_id = dpaa2_xstats_get_by_id,
1980 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
1981 .xstats_get_names = dpaa2_xstats_get_names,
1982 .stats_reset = dpaa2_dev_stats_reset,
1983 .xstats_reset = dpaa2_dev_stats_reset,
1984 .fw_version_get = dpaa2_fw_version_get,
1985 .dev_infos_get = dpaa2_dev_info_get,
1986 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
1987 .mtu_set = dpaa2_dev_mtu_set,
1988 .vlan_filter_set = dpaa2_vlan_filter_set,
1989 .vlan_offload_set = dpaa2_vlan_offload_set,
1990 .vlan_tpid_set = dpaa2_vlan_tpid_set,
1991 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
1992 .rx_queue_release = dpaa2_dev_rx_queue_release,
1993 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
1994 .tx_queue_release = dpaa2_dev_tx_queue_release,
1995 .rx_queue_count = dpaa2_dev_rx_queue_count,
1996 .flow_ctrl_get = dpaa2_flow_ctrl_get,
1997 .flow_ctrl_set = dpaa2_flow_ctrl_set,
1998 .mac_addr_add = dpaa2_dev_add_mac_addr,
1999 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2000 .mac_addr_set = dpaa2_dev_set_mac_addr,
2001 .rss_hash_update = dpaa2_dev_rss_hash_update,
2002 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2003 .filter_ctrl = dpaa2_dev_flow_ctrl,
2006 /* Populate the mac address from physically available (u-boot/firmware) and/or
2007 * one set by higher layers like MC (restool) etc.
2008 * Returns the table of MAC entries (multiple entries)
2011 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2012 struct rte_ether_addr *mac_entry)
2015 struct rte_ether_addr phy_mac, prime_mac;
2017 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2018 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2020 /* Get the physical device MAC address */
2021 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2022 phy_mac.addr_bytes);
2024 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2028 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2029 prime_mac.addr_bytes);
2031 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2035 /* Now that both MAC have been obtained, do:
2036 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2038 * If empty_mac(phy), return prime.
2039 * if both are empty, create random MAC, set as prime and return
2041 if (!rte_is_zero_ether_addr(&phy_mac)) {
2042 /* If the addresses are not same, overwrite prime */
2043 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2044 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2046 phy_mac.addr_bytes);
2048 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2052 memcpy(&prime_mac, &phy_mac,
2053 sizeof(struct rte_ether_addr));
2055 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2056 /* In case phys and prime, both are zero, create random MAC */
2057 rte_eth_random_addr(prime_mac.addr_bytes);
2058 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2060 prime_mac.addr_bytes);
2062 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2067 /* prime_mac the final MAC address */
2068 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2076 check_devargs_handler(__rte_unused const char *key, const char *value,
2077 __rte_unused void *opaque)
2079 if (strcmp(value, "1"))
2086 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2088 struct rte_kvargs *kvlist;
2093 kvlist = rte_kvargs_parse(devargs->args, NULL);
2097 if (!rte_kvargs_count(kvlist, key)) {
2098 rte_kvargs_free(kvlist);
2102 if (rte_kvargs_process(kvlist, key,
2103 check_devargs_handler, NULL) < 0) {
2104 rte_kvargs_free(kvlist);
2107 rte_kvargs_free(kvlist);
2113 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2115 struct rte_device *dev = eth_dev->device;
2116 struct rte_dpaa2_device *dpaa2_dev;
2117 struct fsl_mc_io *dpni_dev;
2118 struct dpni_attr attr;
2119 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2120 struct dpni_buffer_layout layout;
2123 PMD_INIT_FUNC_TRACE();
2125 /* For secondary processes, the primary has done all the work */
2126 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2127 /* In case of secondary, only burst and ops API need to be
2130 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2131 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2132 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2133 else if (dpaa2_get_devargs(dev->devargs,
2134 DRIVER_NO_PREFETCH_MODE))
2135 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2137 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2138 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2142 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2144 hw_id = dpaa2_dev->object_id;
2146 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2148 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2152 dpni_dev->regs = rte_mcp_ptr_list[0];
2153 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2156 "Failure in opening dpni@%d with err code %d",
2162 /* Clean the device first */
2163 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2165 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2170 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2173 "Failure in get dpni@%d attribute, err code %d",
2178 priv->num_rx_tc = attr.num_rx_tcs;
2180 for (i = 0; i < attr.num_rx_tcs; i++)
2181 priv->nb_rx_queues += attr.num_queues;
2183 /* Using number of TX queues as number of TX TCs */
2184 priv->nb_tx_queues = attr.num_tx_tcs;
2186 DPAA2_PMD_DEBUG("RX-TC= %d, nb_rx_queues= %d, nb_tx_queues=%d",
2187 priv->num_rx_tc, priv->nb_rx_queues,
2188 priv->nb_tx_queues);
2190 priv->hw = dpni_dev;
2191 priv->hw_id = hw_id;
2192 priv->options = attr.options;
2193 priv->max_mac_filters = attr.mac_filter_entries;
2194 priv->max_vlan_filters = attr.vlan_filter_entries;
2197 /* Allocate memory for hardware structure for queues */
2198 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2200 DPAA2_PMD_ERR("Queue allocation Failed");
2204 /* Allocate memory for storing MAC addresses.
2205 * Table of mac_filter_entries size is allocated so that RTE ether lib
2206 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2208 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2209 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2210 if (eth_dev->data->mac_addrs == NULL) {
2212 "Failed to allocate %d bytes needed to store MAC addresses",
2213 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2218 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2220 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2221 rte_free(eth_dev->data->mac_addrs);
2222 eth_dev->data->mac_addrs = NULL;
2226 /* ... tx buffer layout ... */
2227 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2228 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2229 layout.pass_frame_status = 1;
2230 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2231 DPNI_QUEUE_TX, &layout);
2233 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2237 /* ... tx-conf and error buffer layout ... */
2238 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2239 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2240 layout.pass_frame_status = 1;
2241 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2242 DPNI_QUEUE_TX_CONFIRM, &layout);
2244 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2249 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2251 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2252 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2253 DPAA2_PMD_INFO("Loopback mode");
2254 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2255 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2256 DPAA2_PMD_INFO("No Prefetch mode");
2258 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2260 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2262 /*Init fields w.r.t. classficaition*/
2263 memset(&priv->extract.qos_key_cfg, 0, sizeof(struct dpkg_profile_cfg));
2264 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2265 if (!priv->extract.qos_extract_param) {
2266 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2267 " classificaiton ", ret);
2270 for (i = 0; i < MAX_TCS; i++) {
2271 memset(&priv->extract.fs_key_cfg[i], 0,
2272 sizeof(struct dpkg_profile_cfg));
2273 priv->extract.fs_extract_param[i] =
2274 (size_t)rte_malloc(NULL, 256, 64);
2275 if (!priv->extract.fs_extract_param[i]) {
2276 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2282 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2285 dpaa2_dev_uninit(eth_dev);
2290 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2292 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2293 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;
2296 PMD_INIT_FUNC_TRACE();
2298 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2302 DPAA2_PMD_WARN("Already closed or not started");
2306 dpaa2_dev_close(eth_dev);
2308 dpaa2_free_rx_tx_queues(eth_dev);
2310 /* Close the device at underlying layer*/
2311 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2314 "Failure closing dpni device with err code %d",
2318 /* Free the allocated memory for ethernet private data and dpni*/
2322 for (i = 0; i < MAX_TCS; i++) {
2323 if (priv->extract.fs_extract_param[i])
2324 rte_free((void *)(size_t)priv->extract.fs_extract_param[i]);
2327 if (priv->extract.qos_extract_param)
2328 rte_free((void *)(size_t)priv->extract.qos_extract_param);
2330 eth_dev->dev_ops = NULL;
2331 eth_dev->rx_pkt_burst = NULL;
2332 eth_dev->tx_pkt_burst = NULL;
2334 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2339 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2340 struct rte_dpaa2_device *dpaa2_dev)
2342 struct rte_eth_dev *eth_dev;
2345 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2346 RTE_PKTMBUF_HEADROOM) {
2348 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2349 RTE_PKTMBUF_HEADROOM,
2350 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2355 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2356 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2359 eth_dev->data->dev_private = rte_zmalloc(
2360 "ethdev private structure",
2361 sizeof(struct dpaa2_dev_priv),
2362 RTE_CACHE_LINE_SIZE);
2363 if (eth_dev->data->dev_private == NULL) {
2365 "Unable to allocate memory for private data");
2366 rte_eth_dev_release_port(eth_dev);
2370 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2375 eth_dev->device = &dpaa2_dev->device;
2377 dpaa2_dev->eth_dev = eth_dev;
2378 eth_dev->data->rx_mbuf_alloc_failed = 0;
2380 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2381 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2383 /* Invoke PMD device initialization function */
2384 diag = dpaa2_dev_init(eth_dev);
2386 rte_eth_dev_probing_finish(eth_dev);
2390 rte_eth_dev_release_port(eth_dev);
2395 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2397 struct rte_eth_dev *eth_dev;
2399 eth_dev = dpaa2_dev->eth_dev;
2400 dpaa2_dev_uninit(eth_dev);
2402 rte_eth_dev_release_port(eth_dev);
2407 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2408 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2409 .drv_type = DPAA2_ETH,
2410 .probe = rte_dpaa2_probe,
2411 .remove = rte_dpaa2_remove,
2414 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2415 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2416 DRIVER_LOOPBACK_MODE "=<int> "
2417 DRIVER_NO_PREFETCH_MODE "=<int>");
2418 RTE_INIT(dpaa2_pmd_init_log)
2420 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2");
2421 if (dpaa2_logtype_pmd >= 0)
2422 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE);