drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21 #include "rte_dpaa2_mempool.h"
  22
  23 #include "dpaa2_pmd_logs.h"
  24 #include <fslmc_vfio.h>
  25 #include <dpaa2_hw_pvt.h>
  26 #include <dpaa2_hw_mempool.h>
  27 #include <dpaa2_hw_dpio.h>
  28 #include <mc/fsl_dpmng.h>
  29 #include "dpaa2_ethdev.h"
  30 #include "dpaa2_sparser.h"
  31 #include <fsl_qbman_debug.h>
  32
  33 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  34 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  35 #define DRIVER_TX_CONF "drv_tx_conf"
  36 #define DRIVER_ERROR_QUEUE  "drv_err_queue"
  37 #define CHECK_INTERVAL         100  /* 100ms */
  38 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  39
  40 /* Supported Rx offloads */
  41 static uint64_t dev_rx_offloads_sup =
  42                 RTE_ETH_RX_OFFLOAD_CHECKSUM |
  43                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
  44                 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  45                 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
  46                 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
  47                 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
  48                 RTE_ETH_RX_OFFLOAD_TIMESTAMP;
  49
  50 /* Rx offloads which cannot be disabled */
  51 static uint64_t dev_rx_offloads_nodis =
  52                 RTE_ETH_RX_OFFLOAD_RSS_HASH |
  53                 RTE_ETH_RX_OFFLOAD_SCATTER;
  54
  55 /* Supported Tx offloads */
  56 static uint64_t dev_tx_offloads_sup =
  57                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
  58                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
  59                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
  60                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
  61                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
  62                 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  63                 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
  64                 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
  65
  66 /* Tx offloads which cannot be disabled */
  67 static uint64_t dev_tx_offloads_nodis =
  68                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
  69
  70 /* enable timestamp in mbuf */
  71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  72 uint64_t dpaa2_timestamp_rx_dynflag;
  73 int dpaa2_timestamp_dynfield_offset = -1;
  74
  75 /* Enable error queue */
  76 bool dpaa2_enable_err_queue;
  77
  78 #define MAX_NB_RX_DESC          11264
  79 int total_nb_rx_desc;
  80
  81 struct rte_dpaa2_xstats_name_off {
  82         char name[RTE_ETH_XSTATS_NAME_SIZE];
  83         uint8_t page_id; /* dpni statistics page id */
  84         uint8_t stats_id; /* stats id in the given page */
  85 };
  86
  87 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  88         {"ingress_multicast_frames", 0, 2},
  89         {"ingress_multicast_bytes", 0, 3},
  90         {"ingress_broadcast_frames", 0, 4},
  91         {"ingress_broadcast_bytes", 0, 5},
  92         {"egress_multicast_frames", 1, 2},
  93         {"egress_multicast_bytes", 1, 3},
  94         {"egress_broadcast_frames", 1, 4},
  95         {"egress_broadcast_bytes", 1, 5},
  96         {"ingress_filtered_frames", 2, 0},
  97         {"ingress_discarded_frames", 2, 1},
  98         {"ingress_nobuffer_discards", 2, 2},
  99         {"egress_discarded_frames", 2, 3},
 100         {"egress_confirmed_frames", 2, 4},
 101         {"cgr_reject_frames", 4, 0},
 102         {"cgr_reject_bytes", 4, 1},
 103 };
 104
 105 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 106 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 107                                  int wait_to_complete);
 108 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 109 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 110 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 111
 112 static int
 113 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 114 {
 115         int ret;
 116         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 117         struct fsl_mc_io *dpni = dev->process_private;
 118
 119         PMD_INIT_FUNC_TRACE();
 120
 121         if (dpni == NULL) {
 122                 DPAA2_PMD_ERR("dpni is NULL");
 123                 return -1;
 124         }
 125
 126         if (on)
 127                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 128                                        vlan_id, 0, 0, 0);
 129         else
 130                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 131                                           priv->token, vlan_id);
 132
 133         if (ret < 0)
 134                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 135                               ret, vlan_id, priv->hw_id);
 136
 137         return ret;
 138 }
 139
 140 static int
 141 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 142 {
 143         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 144         struct fsl_mc_io *dpni = dev->process_private;
 145         int ret = 0;
 146
 147         PMD_INIT_FUNC_TRACE();
 148
 149         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
 150                 /* VLAN Filter not available */
 151                 if (!priv->max_vlan_filters) {
 152                         DPAA2_PMD_INFO("VLAN filter not available");
 153                         return -ENOTSUP;
 154                 }
 155
 156                 if (dev->data->dev_conf.rxmode.offloads &
 157                         RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 158                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 159                                                       priv->token, true);
 160                 else
 161                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 162                                                       priv->token, false);
 163                 if (ret < 0)
 164                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 165         }
 166
 167         return ret;
 168 }
 169
 170 static int
 171 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 172                       enum rte_vlan_type vlan_type __rte_unused,
 173                       uint16_t tpid)
 174 {
 175         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 176         struct fsl_mc_io *dpni = dev->process_private;
 177         int ret = -ENOTSUP;
 178
 179         PMD_INIT_FUNC_TRACE();
 180
 181         /* nothing to be done for standard vlan tpids */
 182         if (tpid == 0x8100 || tpid == 0x88A8)
 183                 return 0;
 184
 185         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 186                                    priv->token, tpid);
 187         if (ret < 0)
 188                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 189         /* if already configured tpids, remove them first */
 190         if (ret == -EBUSY) {
 191                 struct dpni_custom_tpid_cfg tpid_list = {0};
 192
 193                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 194                                    priv->token, &tpid_list);
 195                 if (ret < 0)
 196                         goto fail;
 197                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 198                                    priv->token, tpid_list.tpid1);
 199                 if (ret < 0)
 200                         goto fail;
 201                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 202                                            priv->token, tpid);
 203         }
 204 fail:
 205         return ret;
 206 }
 207
 208 static int
 209 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 210                      char *fw_version,
 211                      size_t fw_size)
 212 {
 213         int ret;
 214         struct fsl_mc_io *dpni = dev->process_private;
 215         struct mc_soc_version mc_plat_info = {0};
 216         struct mc_version mc_ver_info = {0};
 217
 218         PMD_INIT_FUNC_TRACE();
 219
 220         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 221                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 222
 223         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 224                 DPAA2_PMD_WARN("\tmc_get_version failed");
 225
 226         ret = snprintf(fw_version, fw_size,
 227                        "%x-%d.%d.%d",
 228                        mc_plat_info.svr,
 229                        mc_ver_info.major,
 230                        mc_ver_info.minor,
 231                        mc_ver_info.revision);
 232         if (ret < 0)
 233                 return -EINVAL;
 234
 235         ret += 1; /* add the size of '\0' */
 236         if (fw_size < (size_t)ret)
 237                 return ret;
 238         else
 239                 return 0;
 240 }
 241
 242 static int
 243 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 244 {
 245         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 246
 247         PMD_INIT_FUNC_TRACE();
 248
 249         dev_info->max_mac_addrs = priv->max_mac_filters;
 250         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 251         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 252         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 253         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 254         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 255                                         dev_rx_offloads_nodis;
 256         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 257                                         dev_tx_offloads_nodis;
 258         dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
 259                         RTE_ETH_LINK_SPEED_2_5G |
 260                         RTE_ETH_LINK_SPEED_10G;
 261         dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 262
 263         dev_info->max_hash_mac_addrs = 0;
 264         dev_info->max_vfs = 0;
 265         dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
 266         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 267
 268         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 269         /* same is rx size for best perf */
 270         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 271
 272         dev_info->default_rxportconf.nb_queues = 1;
 273         dev_info->default_txportconf.nb_queues = 1;
 274         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 275         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 276
 277         if (dpaa2_svr_family == SVR_LX2160A) {
 278                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G |
 279                                 RTE_ETH_LINK_SPEED_40G |
 280                                 RTE_ETH_LINK_SPEED_50G |
 281                                 RTE_ETH_LINK_SPEED_100G;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static int
 288 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 289                         __rte_unused uint16_t queue_id,
 290                         struct rte_eth_burst_mode *mode)
 291 {
 292         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 293         int ret = -EINVAL;
 294         unsigned int i;
 295         const struct burst_info {
 296                 uint64_t flags;
 297                 const char *output;
 298         } rx_offload_map[] = {
 299                         {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 300                         {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 301                         {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 302                         {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 303                         {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 304                         {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 305                         {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 306                         {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"},
 307                         {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}
 308         };
 309
 310         /* Update Rx offload info */
 311         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 312                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 313                         snprintf(mode->info, sizeof(mode->info), "%s",
 314                                 rx_offload_map[i].output);
 315                         ret = 0;
 316                         break;
 317                 }
 318         }
 319         return ret;
 320 }
 321
 322 static int
 323 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 324                         __rte_unused uint16_t queue_id,
 325                         struct rte_eth_burst_mode *mode)
 326 {
 327         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 328         int ret = -EINVAL;
 329         unsigned int i;
 330         const struct burst_info {
 331                 uint64_t flags;
 332                 const char *output;
 333         } tx_offload_map[] = {
 334                         {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 335                         {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 336                         {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 337                         {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 338                         {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 339                         {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 340                         {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 341                         {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 342                         {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 343         };
 344
 345         /* Update Tx offload info */
 346         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 347                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 348                         snprintf(mode->info, sizeof(mode->info), "%s",
 349                                 tx_offload_map[i].output);
 350                         ret = 0;
 351                         break;
 352                 }
 353         }
 354         return ret;
 355 }
 356
 357 static int
 358 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 359 {
 360         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 361         uint16_t dist_idx;
 362         uint32_t vq_id;
 363         uint8_t num_rxqueue_per_tc;
 364         struct dpaa2_queue *mc_q, *mcq;
 365         uint32_t tot_queues;
 366         int i;
 367         struct dpaa2_queue *dpaa2_q;
 368
 369         PMD_INIT_FUNC_TRACE();
 370
 371         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 372         if (priv->flags & DPAA2_TX_CONF_ENABLE)
 373                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 374         else
 375                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 376         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 377                           RTE_CACHE_LINE_SIZE);
 378         if (!mc_q) {
 379                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 380                 return -1;
 381         }
 382
 383         for (i = 0; i < priv->nb_rx_queues; i++) {
 384                 mc_q->eth_data = dev->data;
 385                 priv->rx_vq[i] = mc_q++;
 386                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 387                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 388                                         sizeof(struct queue_storage_info_t),
 389                                         RTE_CACHE_LINE_SIZE);
 390                 if (!dpaa2_q->q_storage)
 391                         goto fail;
 392
 393                 memset(dpaa2_q->q_storage, 0,
 394                        sizeof(struct queue_storage_info_t));
 395                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 396                         goto fail;
 397         }
 398
 399         if (dpaa2_enable_err_queue) {
 400                 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
 401                         sizeof(struct dpaa2_queue), 0);
 402
 403                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 404                 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
 405                                         sizeof(struct queue_storage_info_t) *
 406                                         RTE_MAX_LCORE,
 407                                         RTE_CACHE_LINE_SIZE);
 408                 if (!dpaa2_q->q_storage)
 409                         goto fail;
 410
 411                 memset(dpaa2_q->q_storage, 0,
 412                        sizeof(struct queue_storage_info_t));
 413                 for (i = 0; i < RTE_MAX_LCORE; i++)
 414                         if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
 415                                 goto fail;
 416         }
 417
 418         for (i = 0; i < priv->nb_tx_queues; i++) {
 419                 mc_q->eth_data = dev->data;
 420                 mc_q->flow_id = 0xffff;
 421                 priv->tx_vq[i] = mc_q++;
 422                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 423                 dpaa2_q->cscn = rte_malloc(NULL,
 424                                            sizeof(struct qbman_result), 16);
 425                 if (!dpaa2_q->cscn)
 426                         goto fail_tx;
 427         }
 428
 429         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 430                 /*Setup tx confirmation queues*/
 431                 for (i = 0; i < priv->nb_tx_queues; i++) {
 432                         mc_q->eth_data = dev->data;
 433                         mc_q->tc_index = i;
 434                         mc_q->flow_id = 0;
 435                         priv->tx_conf_vq[i] = mc_q++;
 436                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 437                         dpaa2_q->q_storage =
 438                                 rte_malloc("dq_storage",
 439                                         sizeof(struct queue_storage_info_t),
 440                                         RTE_CACHE_LINE_SIZE);
 441                         if (!dpaa2_q->q_storage)
 442                                 goto fail_tx_conf;
 443
 444                         memset(dpaa2_q->q_storage, 0,
 445                                sizeof(struct queue_storage_info_t));
 446                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 447                                 goto fail_tx_conf;
 448                 }
 449         }
 450
 451         vq_id = 0;
 452         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 453                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 454                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 455                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 456                 vq_id++;
 457         }
 458
 459         return 0;
 460 fail_tx_conf:
 461         i -= 1;
 462         while (i >= 0) {
 463                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 464                 rte_free(dpaa2_q->q_storage);
 465                 priv->tx_conf_vq[i--] = NULL;
 466         }
 467         i = priv->nb_tx_queues;
 468 fail_tx:
 469         i -= 1;
 470         while (i >= 0) {
 471                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 472                 rte_free(dpaa2_q->cscn);
 473                 priv->tx_vq[i--] = NULL;
 474         }
 475         i = priv->nb_rx_queues;
 476 fail:
 477         i -= 1;
 478         mc_q = priv->rx_vq[0];
 479         while (i >= 0) {
 480                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 481                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 482                 rte_free(dpaa2_q->q_storage);
 483                 priv->rx_vq[i--] = NULL;
 484         }
 485
 486         if (dpaa2_enable_err_queue) {
 487                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 488                 if (dpaa2_q->q_storage)
 489                         dpaa2_free_dq_storage(dpaa2_q->q_storage);
 490                 rte_free(dpaa2_q->q_storage);
 491         }
 492
 493         rte_free(mc_q);
 494         return -1;
 495 }
 496
 497 static void
 498 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 499 {
 500         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 501         struct dpaa2_queue *dpaa2_q;
 502         int i;
 503
 504         PMD_INIT_FUNC_TRACE();
 505
 506         /* Queue allocation base */
 507         if (priv->rx_vq[0]) {
 508                 /* cleaning up queue storage */
 509                 for (i = 0; i < priv->nb_rx_queues; i++) {
 510                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 511                         if (dpaa2_q->q_storage)
 512                                 rte_free(dpaa2_q->q_storage);
 513                 }
 514                 /* cleanup tx queue cscn */
 515                 for (i = 0; i < priv->nb_tx_queues; i++) {
 516                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 517                         rte_free(dpaa2_q->cscn);
 518                 }
 519                 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 520                         /* cleanup tx conf queue storage */
 521                         for (i = 0; i < priv->nb_tx_queues; i++) {
 522                                 dpaa2_q = (struct dpaa2_queue *)
 523                                                 priv->tx_conf_vq[i];
 524                                 rte_free(dpaa2_q->q_storage);
 525                         }
 526                 }
 527                 /*free memory for all queues (RX+TX) */
 528                 rte_free(priv->rx_vq[0]);
 529                 priv->rx_vq[0] = NULL;
 530         }
 531 }
 532
 533 static int
 534 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 535 {
 536         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 537         struct fsl_mc_io *dpni = dev->process_private;
 538         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 539         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 540         uint64_t tx_offloads = eth_conf->txmode.offloads;
 541         int rx_l3_csum_offload = false;
 542         int rx_l4_csum_offload = false;
 543         int tx_l3_csum_offload = false;
 544         int tx_l4_csum_offload = false;
 545         int ret, tc_index;
 546         uint32_t max_rx_pktlen;
 547
 548         PMD_INIT_FUNC_TRACE();
 549
 550         /* Rx offloads which are enabled by default */
 551         if (dev_rx_offloads_nodis & ~rx_offloads) {
 552                 DPAA2_PMD_INFO(
 553                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 554                 " fixed are 0x%" PRIx64,
 555                 rx_offloads, dev_rx_offloads_nodis);
 556         }
 557
 558         /* Tx offloads which are enabled by default */
 559         if (dev_tx_offloads_nodis & ~tx_offloads) {
 560                 DPAA2_PMD_INFO(
 561                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 562                 " fixed are 0x%" PRIx64,
 563                 tx_offloads, dev_tx_offloads_nodis);
 564         }
 565
 566         max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
 567                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
 568         if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) {
 569                 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 570                         priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN);
 571                 if (ret != 0) {
 572                         DPAA2_PMD_ERR("Unable to set mtu. check config");
 573                         return ret;
 574                 }
 575                 DPAA2_PMD_INFO("MTU configured for the device: %d",
 576                                 dev->data->mtu);
 577         } else {
 578                 return -1;
 579         }
 580
 581         if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
 582                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 583                         ret = dpaa2_setup_flow_dist(dev,
 584                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 585                                         tc_index);
 586                         if (ret) {
 587                                 DPAA2_PMD_ERR(
 588                                         "Unable to set flow distribution on tc%d."
 589                                         "Check queue config", tc_index);
 590                                 return ret;
 591                         }
 592                 }
 593         }
 594
 595         if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM)
 596                 rx_l3_csum_offload = true;
 597
 598         if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) ||
 599                 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) ||
 600                 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM))
 601                 rx_l4_csum_offload = true;
 602
 603         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 604                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 605         if (ret) {
 606                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 607                 return ret;
 608         }
 609
 610         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 611                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 612         if (ret) {
 613                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 614                 return ret;
 615         }
 616
 617 #if !defined(RTE_LIBRTE_IEEE1588)
 618         if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 619 #endif
 620         {
 621                 ret = rte_mbuf_dyn_rx_timestamp_register(
 622                                 &dpaa2_timestamp_dynfield_offset,
 623                                 &dpaa2_timestamp_rx_dynflag);
 624                 if (ret != 0) {
 625                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 626                         return -rte_errno;
 627                 }
 628                 dpaa2_enable_ts[dev->data->port_id] = true;
 629         }
 630
 631         if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
 632                 tx_l3_csum_offload = true;
 633
 634         if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) ||
 635                 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) ||
 636                 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM))
 637                 tx_l4_csum_offload = true;
 638
 639         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 640                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 641         if (ret) {
 642                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 643                 return ret;
 644         }
 645
 646         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 647                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 648         if (ret) {
 649                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 650                 return ret;
 651         }
 652
 653         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 654          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 655          * to 0 for LS2 in the hardware thus disabling data/annotation
 656          * stashing. For LX2 this is fixed in hardware and thus hash result and
 657          * parse results can be received in FD using this option.
 658          */
 659         if (dpaa2_svr_family == SVR_LX2160A) {
 660                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 661                                        DPNI_FLCTYPE_HASH, true);
 662                 if (ret) {
 663                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 664                         return ret;
 665                 }
 666         }
 667
 668         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 669                 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK);
 670
 671         dpaa2_tm_init(dev);
 672
 673         return 0;
 674 }
 675
 676 /* Function to setup RX flow information. It contains traffic class ID,
 677  * flow ID, destination configuration etc.
 678  */
 679 static int
 680 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 681                          uint16_t rx_queue_id,
 682                          uint16_t nb_rx_desc,
 683                          unsigned int socket_id __rte_unused,
 684                          const struct rte_eth_rxconf *rx_conf,
 685                          struct rte_mempool *mb_pool)
 686 {
 687         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 688         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 689         struct dpaa2_queue *dpaa2_q;
 690         struct dpni_queue cfg;
 691         uint8_t options = 0;
 692         uint8_t flow_id;
 693         uint32_t bpid;
 694         int i, ret;
 695
 696         PMD_INIT_FUNC_TRACE();
 697
 698         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 699                         dev, rx_queue_id, mb_pool, rx_conf);
 700
 701         total_nb_rx_desc += nb_rx_desc;
 702         if (total_nb_rx_desc > MAX_NB_RX_DESC) {
 703                 DPAA2_PMD_WARN("\nTotal nb_rx_desc exceeds %d limit. Please use Normal buffers",
 704                                MAX_NB_RX_DESC);
 705                 DPAA2_PMD_WARN("To use Normal buffers, run 'export DPNI_NORMAL_BUF=1' before running dynamic_dpl.sh script");
 706         }
 707
 708         /* Rx deferred start is not supported */
 709         if (rx_conf->rx_deferred_start) {
 710                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 711                                 (void *)dev);
 712                 return -EINVAL;
 713         }
 714
 715         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 716                 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 717                         ret = rte_dpaa2_bpid_info_init(mb_pool);
 718                         if (ret)
 719                                 return ret;
 720                 }
 721                 bpid = mempool_to_bpid(mb_pool);
 722                 ret = dpaa2_attach_bp_list(priv, dpni,
 723                                 rte_dpaa2_bpid_info[bpid].bp_list);
 724                 if (ret)
 725                         return ret;
 726         }
 727         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 728         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 729         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 730         dpaa2_q->nb_desc = UINT16_MAX;
 731         dpaa2_q->offloads = rx_conf->offloads;
 732
 733         /*Get the flow id from given VQ id*/
 734         flow_id = dpaa2_q->flow_id;
 735         memset(&cfg, 0, sizeof(struct dpni_queue));
 736
 737         options = options | DPNI_QUEUE_OPT_USER_CTX;
 738         cfg.user_context = (size_t)(dpaa2_q);
 739
 740         /* check if a private cgr available. */
 741         for (i = 0; i < priv->max_cgs; i++) {
 742                 if (!priv->cgid_in_use[i]) {
 743                         priv->cgid_in_use[i] = 1;
 744                         break;
 745                 }
 746         }
 747
 748         if (i < priv->max_cgs) {
 749                 options |= DPNI_QUEUE_OPT_SET_CGID;
 750                 cfg.cgid = i;
 751                 dpaa2_q->cgid = cfg.cgid;
 752         } else {
 753                 dpaa2_q->cgid = 0xff;
 754         }
 755
 756         /*if ls2088 or rev2 device, enable the stashing */
 757
 758         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 759                 options |= DPNI_QUEUE_OPT_FLC;
 760                 cfg.flc.stash_control = true;
 761                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 762                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 763                  * data stashing setting 01 01 00 (0x14)
 764                  * (in following order ->DS AS CS)
 765                  * to enable 1 line data, 1 line annotation.
 766                  * For LX2, this setting should be 01 00 00 (0x10)
 767                  */
 768                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 769                         cfg.flc.value |= 0x10;
 770                 else
 771                         cfg.flc.value |= 0x14;
 772         }
 773         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 774                              dpaa2_q->tc_index, flow_id, options, &cfg);
 775         if (ret) {
 776                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 777                 return -1;
 778         }
 779
 780         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 781                 struct dpni_taildrop taildrop;
 782
 783                 taildrop.enable = 1;
 784                 dpaa2_q->nb_desc = nb_rx_desc;
 785                 /* Private CGR will use tail drop length as nb_rx_desc.
 786                  * for rest cases we can use standard byte based tail drop.
 787                  * There is no HW restriction, but number of CGRs are limited,
 788                  * hence this restriction is placed.
 789                  */
 790                 if (dpaa2_q->cgid != 0xff) {
 791                         /*enabling per rx queue congestion control */
 792                         taildrop.threshold = nb_rx_desc;
 793                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 794                         taildrop.oal = 0;
 795                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 796                                         rx_queue_id);
 797                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 798                                                 DPNI_CP_CONGESTION_GROUP,
 799                                                 DPNI_QUEUE_RX,
 800                                                 dpaa2_q->tc_index,
 801                                                 dpaa2_q->cgid, &taildrop);
 802                 } else {
 803                         /*enabling per rx queue congestion control */
 804                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 805                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 806                         taildrop.oal = CONG_RX_OAL;
 807                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 808                                         rx_queue_id);
 809                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 810                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 811                                                 dpaa2_q->tc_index, flow_id,
 812                                                 &taildrop);
 813                 }
 814                 if (ret) {
 815                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 816                                       ret);
 817                         return -1;
 818                 }
 819         } else { /* Disable tail Drop */
 820                 struct dpni_taildrop taildrop = {0};
 821                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 822
 823                 taildrop.enable = 0;
 824                 if (dpaa2_q->cgid != 0xff) {
 825                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 826                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 827                                         dpaa2_q->tc_index,
 828                                         dpaa2_q->cgid, &taildrop);
 829                 } else {
 830                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 831                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 832                                         dpaa2_q->tc_index, flow_id, &taildrop);
 833                 }
 834                 if (ret) {
 835                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 836                                       ret);
 837                         return -1;
 838                 }
 839         }
 840
 841         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 842         return 0;
 843 }
 844
 845 static int
 846 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 847                          uint16_t tx_queue_id,
 848                          uint16_t nb_tx_desc,
 849                          unsigned int socket_id __rte_unused,
 850                          const struct rte_eth_txconf *tx_conf)
 851 {
 852         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 853         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 854                 priv->tx_vq[tx_queue_id];
 855         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 856                 priv->tx_conf_vq[tx_queue_id];
 857         struct fsl_mc_io *dpni = dev->process_private;
 858         struct dpni_queue tx_conf_cfg;
 859         struct dpni_queue tx_flow_cfg;
 860         uint8_t options = 0, flow_id;
 861         uint16_t channel_id;
 862         struct dpni_queue_id qid;
 863         uint32_t tc_id;
 864         int ret;
 865
 866         PMD_INIT_FUNC_TRACE();
 867
 868         /* Tx deferred start is not supported */
 869         if (tx_conf->tx_deferred_start) {
 870                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 871                                 (void *)dev);
 872                 return -EINVAL;
 873         }
 874
 875         dpaa2_q->nb_desc = UINT16_MAX;
 876         dpaa2_q->offloads = tx_conf->offloads;
 877
 878         /* Return if queue already configured */
 879         if (dpaa2_q->flow_id != 0xffff) {
 880                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 881                 return 0;
 882         }
 883
 884         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 885         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 886
 887         if (tx_queue_id == 0) {
 888                 /*Set tx-conf and error configuration*/
 889                 if (priv->flags & DPAA2_TX_CONF_ENABLE)
 890                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 891                                                             priv->token,
 892                                                             DPNI_CONF_AFFINE);
 893                 else
 894                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 895                                                             priv->token,
 896                                                             DPNI_CONF_DISABLE);
 897                 if (ret) {
 898                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 899                                       "err=%d", ret);
 900                         return -1;
 901                 }
 902         }
 903
 904         tc_id = tx_queue_id % priv->num_tx_tc;
 905         channel_id = (uint8_t)(tx_queue_id / priv->num_tx_tc) % priv->num_channels;
 906         flow_id = 0;
 907
 908         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 909                         ((channel_id << 8) | tc_id), flow_id, options, &tx_flow_cfg);
 910         if (ret) {
 911                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 912                         "tc_id=%d, flow=%d err=%d",
 913                         tc_id, flow_id, ret);
 914                         return -1;
 915         }
 916
 917         dpaa2_q->flow_id = flow_id;
 918
 919         dpaa2_q->tc_index = tc_id;
 920
 921         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 922                              DPNI_QUEUE_TX, ((channel_id << 8) | dpaa2_q->tc_index),
 923                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 924         if (ret) {
 925                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 926                 return -1;
 927         }
 928         dpaa2_q->fqid = qid.fqid;
 929
 930         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 931                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 932
 933                 dpaa2_q->nb_desc = nb_tx_desc;
 934
 935                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 936                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 937                 /* Notify that the queue is not congested when the data in
 938                  * the queue is below this threshold.(90% of value)
 939                  */
 940                 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
 941                 cong_notif_cfg.message_ctx = 0;
 942                 cong_notif_cfg.message_iova =
 943                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 944                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 945                 cong_notif_cfg.notification_mode =
 946                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 947                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 948                                          DPNI_CONG_OPT_COHERENT_WRITE;
 949                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 950
 951                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 952                                                        priv->token,
 953                                                        DPNI_QUEUE_TX,
 954                                                        ((channel_id << 8) | tc_id),
 955                                                        &cong_notif_cfg);
 956                 if (ret) {
 957                         DPAA2_PMD_ERR(
 958                            "Error in setting tx congestion notification: "
 959                            "err=%d", ret);
 960                         return -ret;
 961                 }
 962         }
 963         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 964         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 965
 966         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 967                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 968                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 969                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 970                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 971                              DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index),
 972                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 973                 if (ret) {
 974                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 975                               "tc_index=%d, flow=%d err=%d",
 976                               dpaa2_tx_conf_q->tc_index,
 977                               dpaa2_tx_conf_q->flow_id, ret);
 978                         return -1;
 979                 }
 980
 981                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 982                              DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index),
 983                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 984                 if (ret) {
 985                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 986                         return -1;
 987                 }
 988                 dpaa2_tx_conf_q->fqid = qid.fqid;
 989         }
 990         return 0;
 991 }
 992
 993 static void
 994 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 995 {
 996         struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id];
 997         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 998         struct fsl_mc_io *dpni =
 999                 (struct fsl_mc_io *)priv->eth_dev->process_private;
1000         uint8_t options = 0;
1001         int ret;
1002         struct dpni_queue cfg;
1003
1004         memset(&cfg, 0, sizeof(struct dpni_queue));
1005         PMD_INIT_FUNC_TRACE();
1006
1007         total_nb_rx_desc -= dpaa2_q->nb_desc;
1008
1009         if (dpaa2_q->cgid != 0xff) {
1010                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
1011                 cfg.cgid = dpaa2_q->cgid;
1012
1013                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
1014                                      DPNI_QUEUE_RX,
1015                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
1016                                      options, &cfg);
1017                 if (ret)
1018                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1019                                         dpaa2_q->fqid, ret);
1020                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1021                 dpaa2_q->cgid = 0xff;
1022         }
1023 }
1024
1025 static uint32_t
1026 dpaa2_dev_rx_queue_count(void *rx_queue)
1027 {
1028         int32_t ret;
1029         struct dpaa2_queue *dpaa2_q;
1030         struct qbman_swp *swp;
1031         struct qbman_fq_query_np_rslt state;
1032         uint32_t frame_cnt = 0;
1033
1034         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1035                 ret = dpaa2_affine_qbman_swp();
1036                 if (ret) {
1037                         DPAA2_PMD_ERR(
1038                                 "Failed to allocate IO portal, tid: %d\n",
1039                                 rte_gettid());
1040                         return -EINVAL;
1041                 }
1042         }
1043         swp = DPAA2_PER_LCORE_PORTAL;
1044
1045         dpaa2_q = rx_queue;
1046
1047         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1048                 frame_cnt = qbman_fq_state_frame_count(&state);
1049                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u",
1050                                 rx_queue, frame_cnt);
1051         }
1052         return frame_cnt;
1053 }
1054
1055 static const uint32_t *
1056 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1057 {
1058         static const uint32_t ptypes[] = {
1059                 /*todo -= add more types */
1060                 RTE_PTYPE_L2_ETHER,
1061                 RTE_PTYPE_L3_IPV4,
1062                 RTE_PTYPE_L3_IPV4_EXT,
1063                 RTE_PTYPE_L3_IPV6,
1064                 RTE_PTYPE_L3_IPV6_EXT,
1065                 RTE_PTYPE_L4_TCP,
1066                 RTE_PTYPE_L4_UDP,
1067                 RTE_PTYPE_L4_SCTP,
1068                 RTE_PTYPE_L4_ICMP,
1069                 RTE_PTYPE_UNKNOWN
1070         };
1071
1072         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1073                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1074                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1075                 return ptypes;
1076         return NULL;
1077 }
1078
1079 /**
1080  * Dpaa2 link Interrupt handler
1081  *
1082  * @param param
1083  *  The address of parameter (struct rte_eth_dev *) registered before.
1084  *
1085  * @return
1086  *  void
1087  */
1088 static void
1089 dpaa2_interrupt_handler(void *param)
1090 {
1091         struct rte_eth_dev *dev = param;
1092         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1093         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1094         int ret;
1095         int irq_index = DPNI_IRQ_INDEX;
1096         unsigned int status = 0, clear = 0;
1097
1098         PMD_INIT_FUNC_TRACE();
1099
1100         if (dpni == NULL) {
1101                 DPAA2_PMD_ERR("dpni is NULL");
1102                 return;
1103         }
1104
1105         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1106                                   irq_index, &status);
1107         if (unlikely(ret)) {
1108                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1109                 clear = 0xffffffff;
1110                 goto out;
1111         }
1112
1113         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1114                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1115                 dpaa2_dev_link_update(dev, 0);
1116                 /* calling all the apps registered for link status event */
1117                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1118         }
1119 out:
1120         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1121                                     irq_index, clear);
1122         if (unlikely(ret))
1123                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1124 }
1125
1126 static int
1127 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1128 {
1129         int err = 0;
1130         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1131         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1132         int irq_index = DPNI_IRQ_INDEX;
1133         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1134
1135         PMD_INIT_FUNC_TRACE();
1136
1137         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1138                                 irq_index, mask);
1139         if (err < 0) {
1140                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1141                               strerror(-err));
1142                 return err;
1143         }
1144
1145         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1146                                   irq_index, enable);
1147         if (err < 0)
1148                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1149                               strerror(-err));
1150
1151         return err;
1152 }
1153
1154 static int
1155 dpaa2_dev_start(struct rte_eth_dev *dev)
1156 {
1157         struct rte_device *rdev = dev->device;
1158         struct rte_dpaa2_device *dpaa2_dev;
1159         struct rte_eth_dev_data *data = dev->data;
1160         struct dpaa2_dev_priv *priv = data->dev_private;
1161         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1162         struct dpni_queue cfg;
1163         struct dpni_error_cfg   err_cfg;
1164         struct dpni_queue_id qid;
1165         struct dpaa2_queue *dpaa2_q;
1166         int ret, i;
1167         struct rte_intr_handle *intr_handle;
1168
1169         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1170         intr_handle = dpaa2_dev->intr_handle;
1171
1172         PMD_INIT_FUNC_TRACE();
1173         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1174         if (ret) {
1175                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1176                               priv->hw_id, ret);
1177                 return ret;
1178         }
1179
1180         /* Power up the phy. Needed to make the link go UP */
1181         dpaa2_dev_set_link_up(dev);
1182
1183         for (i = 0; i < data->nb_rx_queues; i++) {
1184                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1185                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1186                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1187                                        dpaa2_q->flow_id, &cfg, &qid);
1188                 if (ret) {
1189                         DPAA2_PMD_ERR("Error in getting flow information: "
1190                                       "err=%d", ret);
1191                         return ret;
1192                 }
1193                 dpaa2_q->fqid = qid.fqid;
1194         }
1195
1196         if (dpaa2_enable_err_queue) {
1197                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1198                                      DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1199                 if (ret) {
1200                         DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1201                                                 ret);
1202                         return ret;
1203                 }
1204                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1205                 dpaa2_q->fqid = qid.fqid;
1206                 dpaa2_q->eth_data = dev->data;
1207
1208                 err_cfg.errors =  DPNI_ERROR_DISC;
1209                 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1210         } else {
1211                 /* checksum errors, send them to normal path
1212                  * and set it in annotation
1213                  */
1214                 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1215
1216                 /* if packet with parse error are not to be dropped */
1217                 err_cfg.errors |= DPNI_ERROR_PHE;
1218
1219                 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1220         }
1221         err_cfg.set_frame_annotation = true;
1222
1223         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1224                                        priv->token, &err_cfg);
1225         if (ret) {
1226                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1227                               ret);
1228                 return ret;
1229         }
1230
1231         /* if the interrupts were configured on this devices*/
1232         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1233             dev->data->dev_conf.intr_conf.lsc != 0) {
1234                 /* Registering LSC interrupt handler */
1235                 rte_intr_callback_register(intr_handle,
1236                                            dpaa2_interrupt_handler,
1237                                            (void *)dev);
1238
1239                 /* enable vfio intr/eventfd mapping
1240                  * Interrupt index 0 is required, so we can not use
1241                  * rte_intr_enable.
1242                  */
1243                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1244
1245                 /* enable dpni_irqs */
1246                 dpaa2_eth_setup_irqs(dev, 1);
1247         }
1248
1249         /* Change the tx burst function if ordered queues are used */
1250         if (priv->en_ordered)
1251                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1252
1253         return 0;
1254 }
1255
1256 /**
1257  *  This routine disables all traffic on the adapter by issuing a
1258  *  global reset on the MAC.
1259  */
1260 static int
1261 dpaa2_dev_stop(struct rte_eth_dev *dev)
1262 {
1263         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1264         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1265         int ret;
1266         struct rte_eth_link link;
1267         struct rte_device *rdev = dev->device;
1268         struct rte_intr_handle *intr_handle;
1269         struct rte_dpaa2_device *dpaa2_dev;
1270
1271         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1272         intr_handle = dpaa2_dev->intr_handle;
1273
1274         PMD_INIT_FUNC_TRACE();
1275
1276         /* reset interrupt callback  */
1277         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1278             dev->data->dev_conf.intr_conf.lsc != 0) {
1279                 /*disable dpni irqs */
1280                 dpaa2_eth_setup_irqs(dev, 0);
1281
1282                 /* disable vfio intr before callback unregister */
1283                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1284
1285                 /* Unregistering LSC interrupt handler */
1286                 rte_intr_callback_unregister(intr_handle,
1287                                              dpaa2_interrupt_handler,
1288                                              (void *)dev);
1289         }
1290
1291         dpaa2_dev_set_link_down(dev);
1292
1293         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1294         if (ret) {
1295                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1296                               ret, priv->hw_id);
1297                 return ret;
1298         }
1299
1300         /* clear the recorded link status */
1301         memset(&link, 0, sizeof(link));
1302         rte_eth_linkstatus_set(dev, &link);
1303
1304         return 0;
1305 }
1306
1307 static int
1308 dpaa2_dev_close(struct rte_eth_dev *dev)
1309 {
1310         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1311         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1312         int i, ret;
1313         struct rte_eth_link link;
1314
1315         PMD_INIT_FUNC_TRACE();
1316
1317         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1318                 return 0;
1319
1320         if (!dpni) {
1321                 DPAA2_PMD_WARN("Already closed or not started");
1322                 return -1;
1323         }
1324
1325         dpaa2_tm_deinit(dev);
1326         dpaa2_flow_clean(dev);
1327         /* Clean the device first */
1328         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1329         if (ret) {
1330                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1331                 return -1;
1332         }
1333
1334         memset(&link, 0, sizeof(link));
1335         rte_eth_linkstatus_set(dev, &link);
1336
1337         /* Free private queues memory */
1338         dpaa2_free_rx_tx_queues(dev);
1339         /* Close the device at underlying layer*/
1340         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1341         if (ret) {
1342                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1343                               ret);
1344         }
1345
1346         /* Free the allocated memory for ethernet private data and dpni*/
1347         priv->hw = NULL;
1348         dev->process_private = NULL;
1349         rte_free(dpni);
1350
1351         for (i = 0; i < MAX_TCS; i++)
1352                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1353
1354         if (priv->extract.qos_extract_param)
1355                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1356
1357         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1358         return 0;
1359 }
1360
1361 static int
1362 dpaa2_dev_promiscuous_enable(
1363                 struct rte_eth_dev *dev)
1364 {
1365         int ret;
1366         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1367         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1368
1369         PMD_INIT_FUNC_TRACE();
1370
1371         if (dpni == NULL) {
1372                 DPAA2_PMD_ERR("dpni is NULL");
1373                 return -ENODEV;
1374         }
1375
1376         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1377         if (ret < 0)
1378                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1379
1380         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1381         if (ret < 0)
1382                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1383
1384         return ret;
1385 }
1386
1387 static int
1388 dpaa2_dev_promiscuous_disable(
1389                 struct rte_eth_dev *dev)
1390 {
1391         int ret;
1392         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1393         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1394
1395         PMD_INIT_FUNC_TRACE();
1396
1397         if (dpni == NULL) {
1398                 DPAA2_PMD_ERR("dpni is NULL");
1399                 return -ENODEV;
1400         }
1401
1402         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1403         if (ret < 0)
1404                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1405
1406         if (dev->data->all_multicast == 0) {
1407                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1408                                                  priv->token, false);
1409                 if (ret < 0)
1410                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1411                                       ret);
1412         }
1413
1414         return ret;
1415 }
1416
1417 static int
1418 dpaa2_dev_allmulticast_enable(
1419                 struct rte_eth_dev *dev)
1420 {
1421         int ret;
1422         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1423         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1424
1425         PMD_INIT_FUNC_TRACE();
1426
1427         if (dpni == NULL) {
1428                 DPAA2_PMD_ERR("dpni is NULL");
1429                 return -ENODEV;
1430         }
1431
1432         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1433         if (ret < 0)
1434                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1435
1436         return ret;
1437 }
1438
1439 static int
1440 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1441 {
1442         int ret;
1443         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1444         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1445
1446         PMD_INIT_FUNC_TRACE();
1447
1448         if (dpni == NULL) {
1449                 DPAA2_PMD_ERR("dpni is NULL");
1450                 return -ENODEV;
1451         }
1452
1453         /* must remain on for all promiscuous */
1454         if (dev->data->promiscuous == 1)
1455                 return 0;
1456
1457         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1458         if (ret < 0)
1459                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1460
1461         return ret;
1462 }
1463
1464 static int
1465 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1466 {
1467         int ret;
1468         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1469         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1470         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1471                                 + VLAN_TAG_SIZE;
1472
1473         PMD_INIT_FUNC_TRACE();
1474
1475         if (dpni == NULL) {
1476                 DPAA2_PMD_ERR("dpni is NULL");
1477                 return -EINVAL;
1478         }
1479
1480         /* Set the Max Rx frame length as 'mtu' +
1481          * Maximum Ethernet header length
1482          */
1483         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1484                                         frame_size - RTE_ETHER_CRC_LEN);
1485         if (ret) {
1486                 DPAA2_PMD_ERR("Setting the max frame length failed");
1487                 return -1;
1488         }
1489         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1490         return 0;
1491 }
1492
1493 static int
1494 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1495                        struct rte_ether_addr *addr,
1496                        __rte_unused uint32_t index,
1497                        __rte_unused uint32_t pool)
1498 {
1499         int ret;
1500         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1501         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1502
1503         PMD_INIT_FUNC_TRACE();
1504
1505         if (dpni == NULL) {
1506                 DPAA2_PMD_ERR("dpni is NULL");
1507                 return -1;
1508         }
1509
1510         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1511                                 addr->addr_bytes, 0, 0, 0);
1512         if (ret)
1513                 DPAA2_PMD_ERR(
1514                         "error: Adding the MAC ADDR failed: err = %d", ret);
1515         return 0;
1516 }
1517
1518 static void
1519 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1520                           uint32_t index)
1521 {
1522         int ret;
1523         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1524         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1525         struct rte_eth_dev_data *data = dev->data;
1526         struct rte_ether_addr *macaddr;
1527
1528         PMD_INIT_FUNC_TRACE();
1529
1530         macaddr = &data->mac_addrs[index];
1531
1532         if (dpni == NULL) {
1533                 DPAA2_PMD_ERR("dpni is NULL");
1534                 return;
1535         }
1536
1537         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1538                                    priv->token, macaddr->addr_bytes);
1539         if (ret)
1540                 DPAA2_PMD_ERR(
1541                         "error: Removing the MAC ADDR failed: err = %d", ret);
1542 }
1543
1544 static int
1545 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1546                        struct rte_ether_addr *addr)
1547 {
1548         int ret;
1549         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1550         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1551
1552         PMD_INIT_FUNC_TRACE();
1553
1554         if (dpni == NULL) {
1555                 DPAA2_PMD_ERR("dpni is NULL");
1556                 return -EINVAL;
1557         }
1558
1559         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1560                                         priv->token, addr->addr_bytes);
1561
1562         if (ret)
1563                 DPAA2_PMD_ERR(
1564                         "error: Setting the MAC ADDR failed %d", ret);
1565
1566         return ret;
1567 }
1568
1569 static
1570 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1571                          struct rte_eth_stats *stats)
1572 {
1573         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1574         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1575         int32_t  retcode;
1576         uint8_t page0 = 0, page1 = 1, page2 = 2;
1577         union dpni_statistics value;
1578         int i;
1579         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1580
1581         memset(&value, 0, sizeof(union dpni_statistics));
1582
1583         PMD_INIT_FUNC_TRACE();
1584
1585         if (!dpni) {
1586                 DPAA2_PMD_ERR("dpni is NULL");
1587                 return -EINVAL;
1588         }
1589
1590         if (!stats) {
1591                 DPAA2_PMD_ERR("stats is NULL");
1592                 return -EINVAL;
1593         }
1594
1595         /*Get Counters from page_0*/
1596         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1597                                       page0, 0, &value);
1598         if (retcode)
1599                 goto err;
1600
1601         stats->ipackets = value.page_0.ingress_all_frames;
1602         stats->ibytes = value.page_0.ingress_all_bytes;
1603
1604         /*Get Counters from page_1*/
1605         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1606                                       page1, 0, &value);
1607         if (retcode)
1608                 goto err;
1609
1610         stats->opackets = value.page_1.egress_all_frames;
1611         stats->obytes = value.page_1.egress_all_bytes;
1612
1613         /*Get Counters from page_2*/
1614         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1615                                       page2, 0, &value);
1616         if (retcode)
1617                 goto err;
1618
1619         /* Ingress drop frame count due to configured rules */
1620         stats->ierrors = value.page_2.ingress_filtered_frames;
1621         /* Ingress drop frame count due to error */
1622         stats->ierrors += value.page_2.ingress_discarded_frames;
1623
1624         stats->oerrors = value.page_2.egress_discarded_frames;
1625         stats->imissed = value.page_2.ingress_nobuffer_discards;
1626
1627         /* Fill in per queue stats */
1628         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1629                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1630                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1631                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1632                 if (dpaa2_rxq)
1633                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1634                 if (dpaa2_txq)
1635                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1636
1637                 /* Byte counting is not implemented */
1638                 stats->q_ibytes[i]   = 0;
1639                 stats->q_obytes[i]   = 0;
1640         }
1641
1642         return 0;
1643
1644 err:
1645         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1646         return retcode;
1647 };
1648
1649 static int
1650 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1651                      unsigned int n)
1652 {
1653         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1654         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1655         int32_t  retcode;
1656         union dpni_statistics value[5] = {};
1657         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1658
1659         if (n < num)
1660                 return num;
1661
1662         if (xstats == NULL)
1663                 return 0;
1664
1665         /* Get Counters from page_0*/
1666         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1667                                       0, 0, &value[0]);
1668         if (retcode)
1669                 goto err;
1670
1671         /* Get Counters from page_1*/
1672         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1673                                       1, 0, &value[1]);
1674         if (retcode)
1675                 goto err;
1676
1677         /* Get Counters from page_2*/
1678         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1679                                       2, 0, &value[2]);
1680         if (retcode)
1681                 goto err;
1682
1683         for (i = 0; i < priv->max_cgs; i++) {
1684                 if (!priv->cgid_in_use[i]) {
1685                         /* Get Counters from page_4*/
1686                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1687                                                       priv->token,
1688                                                       4, 0, &value[4]);
1689                         if (retcode)
1690                                 goto err;
1691                         break;
1692                 }
1693         }
1694
1695         for (i = 0; i < num; i++) {
1696                 xstats[i].id = i;
1697                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1698                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1699         }
1700         return i;
1701 err:
1702         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1703         return retcode;
1704 }
1705
1706 static int
1707 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1708                        struct rte_eth_xstat_name *xstats_names,
1709                        unsigned int limit)
1710 {
1711         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1712
1713         if (limit < stat_cnt)
1714                 return stat_cnt;
1715
1716         if (xstats_names != NULL)
1717                 for (i = 0; i < stat_cnt; i++)
1718                         strlcpy(xstats_names[i].name,
1719                                 dpaa2_xstats_strings[i].name,
1720                                 sizeof(xstats_names[i].name));
1721
1722         return stat_cnt;
1723 }
1724
1725 static int
1726 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1727                        uint64_t *values, unsigned int n)
1728 {
1729         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1730         uint64_t values_copy[stat_cnt];
1731
1732         if (!ids) {
1733                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1734                 struct fsl_mc_io *dpni =
1735                         (struct fsl_mc_io *)dev->process_private;
1736                 int32_t  retcode;
1737                 union dpni_statistics value[5] = {};
1738
1739                 if (n < stat_cnt)
1740                         return stat_cnt;
1741
1742                 if (!values)
1743                         return 0;
1744
1745                 /* Get Counters from page_0*/
1746                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1747                                               0, 0, &value[0]);
1748                 if (retcode)
1749                         return 0;
1750
1751                 /* Get Counters from page_1*/
1752                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1753                                               1, 0, &value[1]);
1754                 if (retcode)
1755                         return 0;
1756
1757                 /* Get Counters from page_2*/
1758                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1759                                               2, 0, &value[2]);
1760                 if (retcode)
1761                         return 0;
1762
1763                 /* Get Counters from page_4*/
1764                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1765                                               4, 0, &value[4]);
1766                 if (retcode)
1767                         return 0;
1768
1769                 for (i = 0; i < stat_cnt; i++) {
1770                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1771                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1772                 }
1773                 return stat_cnt;
1774         }
1775
1776         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1777
1778         for (i = 0; i < n; i++) {
1779                 if (ids[i] >= stat_cnt) {
1780                         DPAA2_PMD_ERR("xstats id value isn't valid");
1781                         return -1;
1782                 }
1783                 values[i] = values_copy[ids[i]];
1784         }
1785         return n;
1786 }
1787
1788 static int
1789 dpaa2_xstats_get_names_by_id(
1790         struct rte_eth_dev *dev,
1791         const uint64_t *ids,
1792         struct rte_eth_xstat_name *xstats_names,
1793         unsigned int limit)
1794 {
1795         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1796         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1797
1798         if (!ids)
1799                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1800
1801         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1802
1803         for (i = 0; i < limit; i++) {
1804                 if (ids[i] >= stat_cnt) {
1805                         DPAA2_PMD_ERR("xstats id value isn't valid");
1806                         return -1;
1807                 }
1808                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1809         }
1810         return limit;
1811 }
1812
1813 static int
1814 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1815 {
1816         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1817         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1818         int retcode;
1819         int i;
1820         struct dpaa2_queue *dpaa2_q;
1821
1822         PMD_INIT_FUNC_TRACE();
1823
1824         if (dpni == NULL) {
1825                 DPAA2_PMD_ERR("dpni is NULL");
1826                 return -EINVAL;
1827         }
1828
1829         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1830         if (retcode)
1831                 goto error;
1832
1833         /* Reset the per queue stats in dpaa2_queue structure */
1834         for (i = 0; i < priv->nb_rx_queues; i++) {
1835                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1836                 if (dpaa2_q)
1837                         dpaa2_q->rx_pkts = 0;
1838         }
1839
1840         for (i = 0; i < priv->nb_tx_queues; i++) {
1841                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1842                 if (dpaa2_q)
1843                         dpaa2_q->tx_pkts = 0;
1844         }
1845
1846         return 0;
1847
1848 error:
1849         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1850         return retcode;
1851 };
1852
1853 /* return 0 means link status changed, -1 means not changed */
1854 static int
1855 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1856                       int wait_to_complete)
1857 {
1858         int ret;
1859         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1860         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1861         struct rte_eth_link link;
1862         struct dpni_link_state state = {0};
1863         uint8_t count;
1864
1865         if (dpni == NULL) {
1866                 DPAA2_PMD_ERR("dpni is NULL");
1867                 return 0;
1868         }
1869
1870         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1871                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1872                                           &state);
1873                 if (ret < 0) {
1874                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1875                         return -1;
1876                 }
1877                 if (state.up == RTE_ETH_LINK_DOWN &&
1878                     wait_to_complete)
1879                         rte_delay_ms(CHECK_INTERVAL);
1880                 else
1881                         break;
1882         }
1883
1884         memset(&link, 0, sizeof(struct rte_eth_link));
1885         link.link_status = state.up;
1886         link.link_speed = state.rate;
1887
1888         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1889                 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
1890         else
1891                 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1892
1893         ret = rte_eth_linkstatus_set(dev, &link);
1894         if (ret == -1)
1895                 DPAA2_PMD_DEBUG("No change in status");
1896         else
1897                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1898                                link.link_status ? "Up" : "Down");
1899
1900         return ret;
1901 }
1902
1903 /**
1904  * Toggle the DPNI to enable, if not already enabled.
1905  * This is not strictly PHY up/down - it is more of logical toggling.
1906  */
1907 static int
1908 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1909 {
1910         int ret = -EINVAL;
1911         struct dpaa2_dev_priv *priv;
1912         struct fsl_mc_io *dpni;
1913         int en = 0;
1914         struct dpni_link_state state = {0};
1915
1916         priv = dev->data->dev_private;
1917         dpni = (struct fsl_mc_io *)dev->process_private;
1918
1919         if (dpni == NULL) {
1920                 DPAA2_PMD_ERR("dpni is NULL");
1921                 return ret;
1922         }
1923
1924         /* Check if DPNI is currently enabled */
1925         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1926         if (ret) {
1927                 /* Unable to obtain dpni status; Not continuing */
1928                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1929                 return -EINVAL;
1930         }
1931
1932         /* Enable link if not already enabled */
1933         if (!en) {
1934                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1935                 if (ret) {
1936                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1937                         return -EINVAL;
1938                 }
1939         }
1940         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1941         if (ret < 0) {
1942                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1943                 return -1;
1944         }
1945
1946         /* changing tx burst function to start enqueues */
1947         dev->tx_pkt_burst = dpaa2_dev_tx;
1948         dev->data->dev_link.link_status = state.up;
1949         dev->data->dev_link.link_speed = state.rate;
1950
1951         if (state.up)
1952                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1953         else
1954                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1955         return ret;
1956 }
1957
1958 /**
1959  * Toggle the DPNI to disable, if not already disabled.
1960  * This is not strictly PHY up/down - it is more of logical toggling.
1961  */
1962 static int
1963 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1964 {
1965         int ret = -EINVAL;
1966         struct dpaa2_dev_priv *priv;
1967         struct fsl_mc_io *dpni;
1968         int dpni_enabled = 0;
1969         int retries = 10;
1970
1971         PMD_INIT_FUNC_TRACE();
1972
1973         priv = dev->data->dev_private;
1974         dpni = (struct fsl_mc_io *)dev->process_private;
1975
1976         if (dpni == NULL) {
1977                 DPAA2_PMD_ERR("Device has not yet been configured");
1978                 return ret;
1979         }
1980
1981         /*changing  tx burst function to avoid any more enqueues */
1982         dev->tx_pkt_burst = dummy_dev_tx;
1983
1984         /* Loop while dpni_disable() attempts to drain the egress FQs
1985          * and confirm them back to us.
1986          */
1987         do {
1988                 ret = dpni_disable(dpni, 0, priv->token);
1989                 if (ret) {
1990                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1991                         return ret;
1992                 }
1993                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1994                 if (ret) {
1995                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1996                         return ret;
1997                 }
1998                 if (dpni_enabled)
1999                         /* Allow the MC some slack */
2000                         rte_delay_us(100 * 1000);
2001         } while (dpni_enabled && --retries);
2002
2003         if (!retries) {
2004                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2005                 /* todo- we may have to manually cleanup queues.
2006                  */
2007         } else {
2008                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2009                                dev->data->port_id);
2010         }
2011
2012         dev->data->dev_link.link_status = 0;
2013
2014         return ret;
2015 }
2016
2017 static int
2018 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2019 {
2020         int ret = -EINVAL;
2021         struct dpaa2_dev_priv *priv;
2022         struct fsl_mc_io *dpni;
2023         struct dpni_link_state state = {0};
2024
2025         PMD_INIT_FUNC_TRACE();
2026
2027         priv = dev->data->dev_private;
2028         dpni = (struct fsl_mc_io *)dev->process_private;
2029
2030         if (dpni == NULL || fc_conf == NULL) {
2031                 DPAA2_PMD_ERR("device not configured");
2032                 return ret;
2033         }
2034
2035         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2036         if (ret) {
2037                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2038                 return ret;
2039         }
2040
2041         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2042         if (state.options & DPNI_LINK_OPT_PAUSE) {
2043                 /* DPNI_LINK_OPT_PAUSE set
2044                  *  if ASYM_PAUSE not set,
2045                  *      RX Side flow control (handle received Pause frame)
2046                  *      TX side flow control (send Pause frame)
2047                  *  if ASYM_PAUSE set,
2048                  *      RX Side flow control (handle received Pause frame)
2049                  *      No TX side flow control (send Pause frame disabled)
2050                  */
2051                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2052                         fc_conf->mode = RTE_ETH_FC_FULL;
2053                 else
2054                         fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2055         } else {
2056                 /* DPNI_LINK_OPT_PAUSE not set
2057                  *  if ASYM_PAUSE set,
2058                  *      TX side flow control (send Pause frame)
2059                  *      No RX side flow control (No action on pause frame rx)
2060                  *  if ASYM_PAUSE not set,
2061                  *      Flow control disabled
2062                  */
2063                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2064                         fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2065                 else
2066                         fc_conf->mode = RTE_ETH_FC_NONE;
2067         }
2068
2069         return ret;
2070 }
2071
2072 static int
2073 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2074 {
2075         int ret = -EINVAL;
2076         struct dpaa2_dev_priv *priv;
2077         struct fsl_mc_io *dpni;
2078         struct dpni_link_state state = {0};
2079         struct dpni_link_cfg cfg = {0};
2080
2081         PMD_INIT_FUNC_TRACE();
2082
2083         priv = dev->data->dev_private;
2084         dpni = (struct fsl_mc_io *)dev->process_private;
2085
2086         if (dpni == NULL) {
2087                 DPAA2_PMD_ERR("dpni is NULL");
2088                 return ret;
2089         }
2090
2091         /* It is necessary to obtain the current state before setting fc_conf
2092          * as MC would return error in case rate, autoneg or duplex values are
2093          * different.
2094          */
2095         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2096         if (ret) {
2097                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2098                 return -1;
2099         }
2100
2101         /* Disable link before setting configuration */
2102         dpaa2_dev_set_link_down(dev);
2103
2104         /* Based on fc_conf, update cfg */
2105         cfg.rate = state.rate;
2106         cfg.options = state.options;
2107
2108         /* update cfg with fc_conf */
2109         switch (fc_conf->mode) {
2110         case RTE_ETH_FC_FULL:
2111                 /* Full flow control;
2112                  * OPT_PAUSE set, ASYM_PAUSE not set
2113                  */
2114                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2115                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2116                 break;
2117         case RTE_ETH_FC_TX_PAUSE:
2118                 /* Enable RX flow control
2119                  * OPT_PAUSE not set;
2120                  * ASYM_PAUSE set;
2121                  */
2122                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2123                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2124                 break;
2125         case RTE_ETH_FC_RX_PAUSE:
2126                 /* Enable TX Flow control
2127                  * OPT_PAUSE set
2128                  * ASYM_PAUSE set
2129                  */
2130                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2131                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2132                 break;
2133         case RTE_ETH_FC_NONE:
2134                 /* Disable Flow control
2135                  * OPT_PAUSE not set
2136                  * ASYM_PAUSE not set
2137                  */
2138                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2139                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2140                 break;
2141         default:
2142                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2143                               fc_conf->mode);
2144                 return -1;
2145         }
2146
2147         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2148         if (ret)
2149                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2150                               ret);
2151
2152         /* Enable link */
2153         dpaa2_dev_set_link_up(dev);
2154
2155         return ret;
2156 }
2157
2158 static int
2159 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2160                           struct rte_eth_rss_conf *rss_conf)
2161 {
2162         struct rte_eth_dev_data *data = dev->data;
2163         struct dpaa2_dev_priv *priv = data->dev_private;
2164         struct rte_eth_conf *eth_conf = &data->dev_conf;
2165         int ret, tc_index;
2166
2167         PMD_INIT_FUNC_TRACE();
2168
2169         if (rss_conf->rss_hf) {
2170                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2171                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2172                                 tc_index);
2173                         if (ret) {
2174                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2175                                         tc_index);
2176                                 return ret;
2177                         }
2178                 }
2179         } else {
2180                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2181                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2182                         if (ret) {
2183                                 DPAA2_PMD_ERR(
2184                                         "Unable to remove flow dist on tc%d",
2185                                         tc_index);
2186                                 return ret;
2187                         }
2188                 }
2189         }
2190         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2191         return 0;
2192 }
2193
2194 static int
2195 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2196                             struct rte_eth_rss_conf *rss_conf)
2197 {
2198         struct rte_eth_dev_data *data = dev->data;
2199         struct rte_eth_conf *eth_conf = &data->dev_conf;
2200
2201         /* dpaa2 does not support rss_key, so length should be 0*/
2202         rss_conf->rss_key_len = 0;
2203         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2204         return 0;
2205 }
2206
2207 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2208                 int eth_rx_queue_id,
2209                 struct dpaa2_dpcon_dev *dpcon,
2210                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2211 {
2212         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2213         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2214         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2215         uint8_t flow_id = dpaa2_ethq->flow_id;
2216         struct dpni_queue cfg;
2217         uint8_t options, priority;
2218         int ret;
2219
2220         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2221                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2222         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2223                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2224         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2225                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2226         else
2227                 return -EINVAL;
2228
2229         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2230                    (dpcon->num_priorities - 1);
2231
2232         memset(&cfg, 0, sizeof(struct dpni_queue));
2233         options = DPNI_QUEUE_OPT_DEST;
2234         cfg.destination.type = DPNI_DEST_DPCON;
2235         cfg.destination.id = dpcon->dpcon_id;
2236         cfg.destination.priority = priority;
2237
2238         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2239                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2240                 cfg.destination.hold_active = 1;
2241         }
2242
2243         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2244                         !eth_priv->en_ordered) {
2245                 struct opr_cfg ocfg;
2246
2247                 /* Restoration window size = 256 frames */
2248                 ocfg.oprrws = 3;
2249                 /* Restoration window size = 512 frames for LX2 */
2250                 if (dpaa2_svr_family == SVR_LX2160A)
2251                         ocfg.oprrws = 4;
2252                 /* Auto advance NESN window enabled */
2253                 ocfg.oa = 1;
2254                 /* Late arrival window size disabled */
2255                 ocfg.olws = 0;
2256                 /* ORL resource exhaustion advance NESN disabled */
2257                 ocfg.oeane = 0;
2258                 /* Loose ordering enabled */
2259                 ocfg.oloe = 1;
2260                 eth_priv->en_loose_ordered = 1;
2261                 /* Strict ordering enabled if explicitly set */
2262                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2263                         ocfg.oloe = 0;
2264                         eth_priv->en_loose_ordered = 0;
2265                 }
2266
2267                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2268                                    dpaa2_ethq->tc_index, flow_id,
2269                                    OPR_OPT_CREATE, &ocfg, 0);
2270                 if (ret) {
2271                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2272                         return ret;
2273                 }
2274
2275                 eth_priv->en_ordered = 1;
2276         }
2277
2278         options |= DPNI_QUEUE_OPT_USER_CTX;
2279         cfg.user_context = (size_t)(dpaa2_ethq);
2280
2281         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2282                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2283         if (ret) {
2284                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2285                 return ret;
2286         }
2287
2288         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2289
2290         return 0;
2291 }
2292
2293 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2294                 int eth_rx_queue_id)
2295 {
2296         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2297         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2298         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2299         uint8_t flow_id = dpaa2_ethq->flow_id;
2300         struct dpni_queue cfg;
2301         uint8_t options;
2302         int ret;
2303
2304         memset(&cfg, 0, sizeof(struct dpni_queue));
2305         options = DPNI_QUEUE_OPT_DEST;
2306         cfg.destination.type = DPNI_DEST_NONE;
2307
2308         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2309                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2310         if (ret)
2311                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2312
2313         return ret;
2314 }
2315
2316 static int
2317 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2318                        const struct rte_flow_ops **ops)
2319 {
2320         if (!dev)
2321                 return -ENODEV;
2322
2323         *ops = &dpaa2_flow_ops;
2324         return 0;
2325 }
2326
2327 static void
2328 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2329         struct rte_eth_rxq_info *qinfo)
2330 {
2331         struct dpaa2_queue *rxq;
2332         struct dpaa2_dev_priv *priv = dev->data->dev_private;
2333         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2334         uint16_t max_frame_length;
2335
2336         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2337
2338         qinfo->mp = rxq->mb_pool;
2339         qinfo->scattered_rx = dev->data->scattered_rx;
2340         qinfo->nb_desc = rxq->nb_desc;
2341         if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2342                                 &max_frame_length) == 0)
2343                 qinfo->rx_buf_size = max_frame_length;
2344
2345         qinfo->conf.rx_free_thresh = 1;
2346         qinfo->conf.rx_drop_en = 1;
2347         qinfo->conf.rx_deferred_start = 0;
2348         qinfo->conf.offloads = rxq->offloads;
2349 }
2350
2351 static void
2352 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2353         struct rte_eth_txq_info *qinfo)
2354 {
2355         struct dpaa2_queue *txq;
2356
2357         txq = dev->data->tx_queues[queue_id];
2358
2359         qinfo->nb_desc = txq->nb_desc;
2360         qinfo->conf.tx_thresh.pthresh = 0;
2361         qinfo->conf.tx_thresh.hthresh = 0;
2362         qinfo->conf.tx_thresh.wthresh = 0;
2363
2364         qinfo->conf.tx_free_thresh = 0;
2365         qinfo->conf.tx_rs_thresh = 0;
2366         qinfo->conf.offloads = txq->offloads;
2367         qinfo->conf.tx_deferred_start = 0;
2368 }
2369
2370 static int
2371 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2372 {
2373         *(const void **)ops = &dpaa2_tm_ops;
2374
2375         return 0;
2376 }
2377
2378 void
2379 rte_pmd_dpaa2_thread_init(void)
2380 {
2381         int ret;
2382
2383         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2384                 ret = dpaa2_affine_qbman_swp();
2385                 if (ret) {
2386                         DPAA2_PMD_ERR(
2387                                 "Failed to allocate IO portal, tid: %d\n",
2388                                 rte_gettid());
2389                         return;
2390                 }
2391         }
2392 }
2393
2394 static struct eth_dev_ops dpaa2_ethdev_ops = {
2395         .dev_configure    = dpaa2_eth_dev_configure,
2396         .dev_start            = dpaa2_dev_start,
2397         .dev_stop             = dpaa2_dev_stop,
2398         .dev_close            = dpaa2_dev_close,
2399         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2400         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2401         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2402         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2403         .dev_set_link_up      = dpaa2_dev_set_link_up,
2404         .dev_set_link_down    = dpaa2_dev_set_link_down,
2405         .link_update       = dpaa2_dev_link_update,
2406         .stats_get             = dpaa2_dev_stats_get,
2407         .xstats_get            = dpaa2_dev_xstats_get,
2408         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2409         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2410         .xstats_get_names      = dpaa2_xstats_get_names,
2411         .stats_reset       = dpaa2_dev_stats_reset,
2412         .xstats_reset         = dpaa2_dev_stats_reset,
2413         .fw_version_get    = dpaa2_fw_version_get,
2414         .dev_infos_get     = dpaa2_dev_info_get,
2415         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2416         .mtu_set           = dpaa2_dev_mtu_set,
2417         .vlan_filter_set      = dpaa2_vlan_filter_set,
2418         .vlan_offload_set     = dpaa2_vlan_offload_set,
2419         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2420         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2421         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2422         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2423         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2424         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2425         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2426         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2427         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2428         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2429         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2430         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2431         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2432         .flow_ops_get         = dpaa2_dev_flow_ops_get,
2433         .rxq_info_get         = dpaa2_rxq_info_get,
2434         .txq_info_get         = dpaa2_txq_info_get,
2435         .tm_ops_get           = dpaa2_tm_ops_get,
2436 #if defined(RTE_LIBRTE_IEEE1588)
2437         .timesync_enable      = dpaa2_timesync_enable,
2438         .timesync_disable     = dpaa2_timesync_disable,
2439         .timesync_read_time   = dpaa2_timesync_read_time,
2440         .timesync_write_time  = dpaa2_timesync_write_time,
2441         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2442         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2443         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2444 #endif
2445 };
2446
2447 /* Populate the mac address from physically available (u-boot/firmware) and/or
2448  * one set by higher layers like MC (restool) etc.
2449  * Returns the table of MAC entries (multiple entries)
2450  */
2451 static int
2452 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2453                   struct rte_ether_addr *mac_entry)
2454 {
2455         int ret;
2456         struct rte_ether_addr phy_mac, prime_mac;
2457
2458         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2459         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2460
2461         /* Get the physical device MAC address */
2462         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2463                                      phy_mac.addr_bytes);
2464         if (ret) {
2465                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2466                 goto cleanup;
2467         }
2468
2469         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2470                                         prime_mac.addr_bytes);
2471         if (ret) {
2472                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2473                 goto cleanup;
2474         }
2475
2476         /* Now that both MAC have been obtained, do:
2477          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2478          *     and return phy
2479          *  If empty_mac(phy), return prime.
2480          *  if both are empty, create random MAC, set as prime and return
2481          */
2482         if (!rte_is_zero_ether_addr(&phy_mac)) {
2483                 /* If the addresses are not same, overwrite prime */
2484                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2485                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2486                                                         priv->token,
2487                                                         phy_mac.addr_bytes);
2488                         if (ret) {
2489                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2490                                               ret);
2491                                 goto cleanup;
2492                         }
2493                         memcpy(&prime_mac, &phy_mac,
2494                                 sizeof(struct rte_ether_addr));
2495                 }
2496         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2497                 /* In case phys and prime, both are zero, create random MAC */
2498                 rte_eth_random_addr(prime_mac.addr_bytes);
2499                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2500                                                 priv->token,
2501                                                 prime_mac.addr_bytes);
2502                 if (ret) {
2503                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2504                         goto cleanup;
2505                 }
2506         }
2507
2508         /* prime_mac the final MAC address */
2509         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2510         return 0;
2511
2512 cleanup:
2513         return -1;
2514 }
2515
2516 static int
2517 check_devargs_handler(__rte_unused const char *key, const char *value,
2518                       __rte_unused void *opaque)
2519 {
2520         if (strcmp(value, "1"))
2521                 return -1;
2522
2523         return 0;
2524 }
2525
2526 static int
2527 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2528 {
2529         struct rte_kvargs *kvlist;
2530
2531         if (!devargs)
2532                 return 0;
2533
2534         kvlist = rte_kvargs_parse(devargs->args, NULL);
2535         if (!kvlist)
2536                 return 0;
2537
2538         if (!rte_kvargs_count(kvlist, key)) {
2539                 rte_kvargs_free(kvlist);
2540                 return 0;
2541         }
2542
2543         if (rte_kvargs_process(kvlist, key,
2544                                check_devargs_handler, NULL) < 0) {
2545                 rte_kvargs_free(kvlist);
2546                 return 0;
2547         }
2548         rte_kvargs_free(kvlist);
2549
2550         return 1;
2551 }
2552
2553 static int
2554 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2555 {
2556         struct rte_device *dev = eth_dev->device;
2557         struct rte_dpaa2_device *dpaa2_dev;
2558         struct fsl_mc_io *dpni_dev;
2559         struct dpni_attr attr;
2560         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2561         struct dpni_buffer_layout layout;
2562         int ret, hw_id, i;
2563
2564         PMD_INIT_FUNC_TRACE();
2565
2566         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2567         if (!dpni_dev) {
2568                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2569                 return -1;
2570         }
2571         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2572         eth_dev->process_private = (void *)dpni_dev;
2573
2574         /* For secondary processes, the primary has done all the work */
2575         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2576                 /* In case of secondary, only burst and ops API need to be
2577                  * plugged.
2578                  */
2579                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2580                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2581                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2582                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2583                 else if (dpaa2_get_devargs(dev->devargs,
2584                                         DRIVER_NO_PREFETCH_MODE))
2585                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2586                 else
2587                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2588                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2589                 return 0;
2590         }
2591
2592         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2593
2594         hw_id = dpaa2_dev->object_id;
2595         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2596         if (ret) {
2597                 DPAA2_PMD_ERR(
2598                              "Failure in opening dpni@%d with err code %d",
2599                              hw_id, ret);
2600                 rte_free(dpni_dev);
2601                 return -1;
2602         }
2603
2604         /* Clean the device first */
2605         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2606         if (ret) {
2607                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2608                               hw_id, ret);
2609                 goto init_err;
2610         }
2611
2612         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2613         if (ret) {
2614                 DPAA2_PMD_ERR(
2615                              "Failure in get dpni@%d attribute, err code %d",
2616                              hw_id, ret);
2617                 goto init_err;
2618         }
2619
2620         priv->num_rx_tc = attr.num_rx_tcs;
2621         priv->num_tx_tc = attr.num_tx_tcs;
2622         priv->qos_entries = attr.qos_entries;
2623         priv->fs_entries = attr.fs_entries;
2624         priv->dist_queues = attr.num_queues;
2625         priv->num_channels = attr.num_channels;
2626         priv->channel_inuse = 0;
2627
2628         /* only if the custom CG is enabled */
2629         if (attr.options & DPNI_OPT_CUSTOM_CG)
2630                 priv->max_cgs = attr.num_cgs;
2631         else
2632                 priv->max_cgs = 0;
2633
2634         for (i = 0; i < priv->max_cgs; i++)
2635                 priv->cgid_in_use[i] = 0;
2636
2637         for (i = 0; i < attr.num_rx_tcs; i++)
2638                 priv->nb_rx_queues += attr.num_queues;
2639
2640         priv->nb_tx_queues = attr.num_tx_tcs * attr.num_channels;
2641
2642         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2643                         priv->num_rx_tc, priv->nb_rx_queues,
2644                         priv->nb_tx_queues, priv->max_cgs);
2645
2646         priv->hw = dpni_dev;
2647         priv->hw_id = hw_id;
2648         priv->options = attr.options;
2649         priv->max_mac_filters = attr.mac_filter_entries;
2650         priv->max_vlan_filters = attr.vlan_filter_entries;
2651         priv->flags = 0;
2652 #if defined(RTE_LIBRTE_IEEE1588)
2653         printf("DPDK IEEE1588 is enabled\n");
2654         priv->flags |= DPAA2_TX_CONF_ENABLE;
2655 #endif
2656         /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2657         if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2658                 priv->flags |= DPAA2_TX_CONF_ENABLE;
2659                 DPAA2_PMD_INFO("TX_CONF Enabled");
2660         }
2661
2662         if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2663                 dpaa2_enable_err_queue = 1;
2664                 DPAA2_PMD_INFO("Enable error queue");
2665         }
2666
2667         /* Allocate memory for hardware structure for queues */
2668         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2669         if (ret) {
2670                 DPAA2_PMD_ERR("Queue allocation Failed");
2671                 goto init_err;
2672         }
2673
2674         /* Allocate memory for storing MAC addresses.
2675          * Table of mac_filter_entries size is allocated so that RTE ether lib
2676          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2677          */
2678         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2679                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2680         if (eth_dev->data->mac_addrs == NULL) {
2681                 DPAA2_PMD_ERR(
2682                    "Failed to allocate %d bytes needed to store MAC addresses",
2683                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2684                 ret = -ENOMEM;
2685                 goto init_err;
2686         }
2687
2688         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2689         if (ret) {
2690                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2691                 rte_free(eth_dev->data->mac_addrs);
2692                 eth_dev->data->mac_addrs = NULL;
2693                 goto init_err;
2694         }
2695
2696         /* ... tx buffer layout ... */
2697         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2698         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2699                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2700                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2701                 layout.pass_timestamp = true;
2702         } else {
2703                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2704         }
2705         layout.pass_frame_status = 1;
2706         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2707                                      DPNI_QUEUE_TX, &layout);
2708         if (ret) {
2709                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2710                 goto init_err;
2711         }
2712
2713         /* ... tx-conf and error buffer layout ... */
2714         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2715         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2716                 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2717                 layout.pass_timestamp = true;
2718         }
2719         layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2720         layout.pass_frame_status = 1;
2721         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2722                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2723         if (ret) {
2724                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2725                              ret);
2726                 goto init_err;
2727         }
2728
2729         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2730
2731         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2732                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2733                 DPAA2_PMD_INFO("Loopback mode");
2734         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2735                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2736                 DPAA2_PMD_INFO("No Prefetch mode");
2737         } else {
2738                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2739         }
2740         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2741
2742         /* Init fields w.r.t. classification */
2743         memset(&priv->extract.qos_key_extract, 0,
2744                 sizeof(struct dpaa2_key_extract));
2745         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2746         if (!priv->extract.qos_extract_param) {
2747                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2748                             " classification ", ret);
2749                 goto init_err;
2750         }
2751         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2752                 IP_ADDRESS_OFFSET_INVALID;
2753         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2754                 IP_ADDRESS_OFFSET_INVALID;
2755         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2756                 IP_ADDRESS_OFFSET_INVALID;
2757         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2758                 IP_ADDRESS_OFFSET_INVALID;
2759
2760         for (i = 0; i < MAX_TCS; i++) {
2761                 memset(&priv->extract.tc_key_extract[i], 0,
2762                         sizeof(struct dpaa2_key_extract));
2763                 priv->extract.tc_extract_param[i] =
2764                         (size_t)rte_malloc(NULL, 256, 64);
2765                 if (!priv->extract.tc_extract_param[i]) {
2766                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classification",
2767                                      ret);
2768                         goto init_err;
2769                 }
2770                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2771                         IP_ADDRESS_OFFSET_INVALID;
2772                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2773                         IP_ADDRESS_OFFSET_INVALID;
2774                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2775                         IP_ADDRESS_OFFSET_INVALID;
2776                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2777                         IP_ADDRESS_OFFSET_INVALID;
2778         }
2779
2780         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2781                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2782                                         + VLAN_TAG_SIZE);
2783         if (ret) {
2784                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2785                 goto init_err;
2786         }
2787
2788         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2789          * with external entity to receive byte code for software sequence
2790          * and same will be offload to the H/W using MC interface.
2791          * Currently it is assumed that DPAA2 driver has byte code by some
2792          * mean and same if offloaded to H/W.
2793          */
2794         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2795                 WRIOP_SS_INITIALIZER(priv);
2796                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2797                 if (ret < 0) {
2798                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2799                                       ret);
2800                         return ret;
2801                 }
2802
2803                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2804                                                          DPNI_SS_INGRESS);
2805                 if (ret < 0) {
2806                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2807                                       ret);
2808                         return ret;
2809                 }
2810         }
2811         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2812         return 0;
2813 init_err:
2814         dpaa2_dev_close(eth_dev);
2815
2816         return ret;
2817 }
2818
2819 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2820 {
2821         return dev->device->driver == &rte_dpaa2_pmd.driver;
2822 }
2823
2824 static int
2825 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2826                 struct rte_dpaa2_device *dpaa2_dev)
2827 {
2828         struct rte_eth_dev *eth_dev;
2829         struct dpaa2_dev_priv *dev_priv;
2830         int diag;
2831
2832         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2833                 RTE_PKTMBUF_HEADROOM) {
2834                 DPAA2_PMD_ERR(
2835                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2836                 RTE_PKTMBUF_HEADROOM,
2837                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2838
2839                 return -1;
2840         }
2841
2842         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2843                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2844                 if (!eth_dev)
2845                         return -ENODEV;
2846                 dev_priv = rte_zmalloc("ethdev private structure",
2847                                        sizeof(struct dpaa2_dev_priv),
2848                                        RTE_CACHE_LINE_SIZE);
2849                 if (dev_priv == NULL) {
2850                         DPAA2_PMD_CRIT(
2851                                 "Unable to allocate memory for private data");
2852                         rte_eth_dev_release_port(eth_dev);
2853                         return -ENOMEM;
2854                 }
2855                 eth_dev->data->dev_private = (void *)dev_priv;
2856                 /* Store a pointer to eth_dev in dev_private */
2857                 dev_priv->eth_dev = eth_dev;
2858         } else {
2859                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2860                 if (!eth_dev) {
2861                         DPAA2_PMD_DEBUG("returning enodev");
2862                         return -ENODEV;
2863                 }
2864         }
2865
2866         eth_dev->device = &dpaa2_dev->device;
2867
2868         dpaa2_dev->eth_dev = eth_dev;
2869         eth_dev->data->rx_mbuf_alloc_failed = 0;
2870
2871         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2872                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2873
2874         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2875
2876         /* Invoke PMD device initialization function */
2877         diag = dpaa2_dev_init(eth_dev);
2878         if (diag == 0) {
2879                 rte_eth_dev_probing_finish(eth_dev);
2880                 return 0;
2881         }
2882
2883         rte_eth_dev_release_port(eth_dev);
2884         return diag;
2885 }
2886
2887 static int
2888 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2889 {
2890         struct rte_eth_dev *eth_dev;
2891         int ret;
2892
2893         eth_dev = dpaa2_dev->eth_dev;
2894         dpaa2_dev_close(eth_dev);
2895         ret = rte_eth_dev_release_port(eth_dev);
2896
2897         return ret;
2898 }
2899
2900 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2901         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2902         .drv_type = DPAA2_ETH,
2903         .probe = rte_dpaa2_probe,
2904         .remove = rte_dpaa2_remove,
2905 };
2906
2907 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2908 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2909                 DRIVER_LOOPBACK_MODE "=<int> "
2910                 DRIVER_NO_PREFETCH_MODE "=<int>"
2911                 DRIVER_TX_CONF "=<int>"
2912                 DRIVER_ERROR_QUEUE "=<int>");
2913 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);