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34 #ifndef _DPAA2_ETHDEV_H
35 #define _DPAA2_ETHDEV_H
37 #include <mc/fsl_dpni.h>
38 #include <mc/fsl_mc_sys.h>
40 #define DPAA2_MIN_RX_BUF_SIZE 512
41 #define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/
43 #define MAX_TCS DPNI_MAX_TC
44 #define MAX_RX_QUEUES 16
45 #define MAX_TX_QUEUES 16
47 /*default tc to be used for ,congestion, distribution etc configuration. */
48 #define DPAA2_DEF_TC 0
50 /* Threshold for a Tx queue to *Enter* Congestion state.
52 #define CONG_ENTER_TX_THRESHOLD 512
54 /* Threshold for a queue to *Exit* Congestion state.
56 #define CONG_EXIT_TX_THRESHOLD 480
58 #define CONG_RETRY_COUNT 18000
60 /* RX queue tail drop threshold
61 * currently considering 32 KB packets
63 #define CONG_THRESHOLD_RX_Q (64 * 1024)
65 /* Size of the input SMMU mapped memory required by MC */
66 #define DIST_PARAM_IOVA_SIZE 256
68 /* Enable TX Congestion control support
71 #define DPAA2_TX_CGR_OFF 0x01
73 /* Disable RX tail drop, default is enable */
74 #define DPAA2_RX_TAILDROP_OFF 0x04
76 struct dpaa2_dev_priv {
83 void *rx_vq[MAX_RX_QUEUES];
84 void *tx_vq[MAX_TX_QUEUES];
86 struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
88 uint8_t max_mac_filters;
89 uint8_t max_vlan_filters;
91 uint8_t flags; /*dpaa2 config flags */
94 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
95 uint32_t req_dist_set);
97 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
100 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
102 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
104 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
105 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
106 #endif /* _DPAA2_ETHDEV_H */