1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
8 #ifndef _DPAA2_ETHDEV_H
9 #define _DPAA2_ETHDEV_H
11 #include <rte_event_eth_rx_adapter.h>
12 #include <rte_pmd_dpaa2.h>
14 #include <dpaa2_hw_pvt.h>
16 #include <mc/fsl_dpni.h>
17 #include <mc/fsl_mc_sys.h>
19 #define DPAA2_MIN_RX_BUF_SIZE 512
20 #define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/
22 #define MAX_TCS DPNI_MAX_TC
23 #define MAX_RX_QUEUES 128
24 #define MAX_TX_QUEUES 16
26 /*default tc to be used for ,congestion, distribution etc configuration. */
27 #define DPAA2_DEF_TC 0
29 /* Threshold for a Tx queue to *Enter* Congestion state.
31 #define CONG_ENTER_TX_THRESHOLD 512
33 /* Threshold for a queue to *Exit* Congestion state.
35 #define CONG_EXIT_TX_THRESHOLD 480
37 #define CONG_RETRY_COUNT 18000
39 /* RX queue tail drop threshold
40 * currently considering 32 KB packets
42 #define CONG_THRESHOLD_RX_Q (64 * 1024)
43 #define CONG_RX_OAL 128
45 /* Size of the input SMMU mapped memory required by MC */
46 #define DIST_PARAM_IOVA_SIZE 256
48 /* Enable TX Congestion control support
51 #define DPAA2_TX_CGR_OFF 0x01
53 /* Disable RX tail drop, default is enable */
54 #define DPAA2_RX_TAILDROP_OFF 0x04
56 #define DPAA2_RSS_OFFLOAD_ALL ( \
62 /* LX2 FRC Parsed values (Little Endian) */
63 #define DPAA2_PKT_TYPE_ETHER 0x0060
64 #define DPAA2_PKT_TYPE_IPV4 0x0000
65 #define DPAA2_PKT_TYPE_IPV6 0x0020
66 #define DPAA2_PKT_TYPE_IPV4_EXT \
67 (0x0001 | DPAA2_PKT_TYPE_IPV4)
68 #define DPAA2_PKT_TYPE_IPV6_EXT \
69 (0x0001 | DPAA2_PKT_TYPE_IPV6)
70 #define DPAA2_PKT_TYPE_IPV4_TCP \
71 (0x000e | DPAA2_PKT_TYPE_IPV4)
72 #define DPAA2_PKT_TYPE_IPV6_TCP \
73 (0x000e | DPAA2_PKT_TYPE_IPV6)
74 #define DPAA2_PKT_TYPE_IPV4_UDP \
75 (0x0010 | DPAA2_PKT_TYPE_IPV4)
76 #define DPAA2_PKT_TYPE_IPV6_UDP \
77 (0x0010 | DPAA2_PKT_TYPE_IPV6)
78 #define DPAA2_PKT_TYPE_IPV4_SCTP \
79 (0x000f | DPAA2_PKT_TYPE_IPV4)
80 #define DPAA2_PKT_TYPE_IPV6_SCTP \
81 (0x000f | DPAA2_PKT_TYPE_IPV6)
82 #define DPAA2_PKT_TYPE_IPV4_ICMP \
83 (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT)
84 #define DPAA2_PKT_TYPE_IPV6_ICMP \
85 (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT)
86 #define DPAA2_PKT_TYPE_VLAN_1 0x0160
87 #define DPAA2_PKT_TYPE_VLAN_2 0x0260
89 /* enable timestamp in mbuf*/
90 extern enum pmd_dpaa2_ts dpaa2_enable_ts;
92 #define DPAA2_QOS_TABLE_RECONFIGURE 1
93 #define DPAA2_FS_TABLE_RECONFIGURE 2
96 extern const struct rte_flow_ops dpaa2_flow_ops;
97 extern enum rte_filter_type dpaa2_filter_type;
99 struct dpaa2_dev_priv {
104 uint8_t nb_tx_queues;
105 uint8_t nb_rx_queues;
107 void *rx_vq[MAX_RX_QUEUES];
108 void *tx_vq[MAX_TX_QUEUES];
110 struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
111 uint8_t max_mac_filters;
112 uint8_t max_vlan_filters;
114 uint8_t flags; /*dpaa2 config flags */
116 uint8_t en_loose_ordered;
120 uint8_t pattern_type[DPKG_MAX_NUM_OF_EXTRACTS];
121 } pattern[MAX_TCS + 1];
124 struct dpkg_profile_cfg qos_key_cfg;
125 struct dpkg_profile_cfg fs_key_cfg[MAX_TCS];
126 uint64_t qos_extract_param;
127 uint64_t fs_extract_param[MAX_TCS];
131 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
132 struct dpkg_profile_cfg *kg_cfg);
134 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
135 uint64_t req_dist_set);
137 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
140 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
142 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
145 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
147 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
148 int eth_rx_queue_id);
150 uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs,
153 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
155 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
156 const struct qbman_fd *fd,
157 const struct qbman_result *dq,
158 struct dpaa2_queue *rxq,
159 struct rte_event *ev);
160 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp,
161 const struct qbman_fd *fd,
162 const struct qbman_result *dq,
163 struct dpaa2_queue *rxq,
164 struct rte_event *ev);
165 void dpaa2_dev_process_ordered_event(struct qbman_swp *swp,
166 const struct qbman_fd *fd,
167 const struct qbman_result *dq,
168 struct dpaa2_queue *rxq,
169 struct rte_event *ev);
170 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
171 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,
173 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
174 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
176 #endif /* _DPAA2_ETHDEV_H */