1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2019 NXP
8 #ifndef _DPAA2_ETHDEV_H
9 #define _DPAA2_ETHDEV_H
11 #include <rte_event_eth_rx_adapter.h>
12 #include <rte_pmd_dpaa2.h>
14 #include <dpaa2_hw_pvt.h>
16 #include <mc/fsl_dpni.h>
17 #include <mc/fsl_mc_sys.h>
19 #define DPAA2_MIN_RX_BUF_SIZE 512
20 #define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/
22 #define MAX_TCS DPNI_MAX_TC
23 #define MAX_RX_QUEUES 128
24 #define MAX_TX_QUEUES 16
26 /*default tc to be used for ,congestion, distribution etc configuration. */
27 #define DPAA2_DEF_TC 0
29 /* Threshold for a Tx queue to *Enter* Congestion state.
31 #define CONG_ENTER_TX_THRESHOLD 512
33 /* Threshold for a queue to *Exit* Congestion state.
35 #define CONG_EXIT_TX_THRESHOLD 480
37 #define CONG_RETRY_COUNT 18000
39 /* RX queue tail drop threshold
40 * currently considering 64 KB packets
42 #define CONG_THRESHOLD_RX_BYTES_Q (64 * 1024)
43 #define CONG_RX_OAL 128
45 /* Size of the input SMMU mapped memory required by MC */
46 #define DIST_PARAM_IOVA_SIZE 256
48 /* Enable TX Congestion control support
51 #define DPAA2_TX_CGR_OFF 0x01
53 /* Disable RX tail drop, default is enable */
54 #define DPAA2_RX_TAILDROP_OFF 0x04
56 #define DPAA2_RSS_OFFLOAD_ALL ( \
57 ETH_RSS_L2_PAYLOAD | \
63 /* LX2 FRC Parsed values (Little Endian) */
64 #define DPAA2_PKT_TYPE_ETHER 0x0060
65 #define DPAA2_PKT_TYPE_IPV4 0x0000
66 #define DPAA2_PKT_TYPE_IPV6 0x0020
67 #define DPAA2_PKT_TYPE_IPV4_EXT \
68 (0x0001 | DPAA2_PKT_TYPE_IPV4)
69 #define DPAA2_PKT_TYPE_IPV6_EXT \
70 (0x0001 | DPAA2_PKT_TYPE_IPV6)
71 #define DPAA2_PKT_TYPE_IPV4_TCP \
72 (0x000e | DPAA2_PKT_TYPE_IPV4)
73 #define DPAA2_PKT_TYPE_IPV6_TCP \
74 (0x000e | DPAA2_PKT_TYPE_IPV6)
75 #define DPAA2_PKT_TYPE_IPV4_UDP \
76 (0x0010 | DPAA2_PKT_TYPE_IPV4)
77 #define DPAA2_PKT_TYPE_IPV6_UDP \
78 (0x0010 | DPAA2_PKT_TYPE_IPV6)
79 #define DPAA2_PKT_TYPE_IPV4_SCTP \
80 (0x000f | DPAA2_PKT_TYPE_IPV4)
81 #define DPAA2_PKT_TYPE_IPV6_SCTP \
82 (0x000f | DPAA2_PKT_TYPE_IPV6)
83 #define DPAA2_PKT_TYPE_IPV4_ICMP \
84 (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT)
85 #define DPAA2_PKT_TYPE_IPV6_ICMP \
86 (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT)
87 #define DPAA2_PKT_TYPE_VLAN_1 0x0160
88 #define DPAA2_PKT_TYPE_VLAN_2 0x0260
90 /* enable timestamp in mbuf*/
91 extern enum pmd_dpaa2_ts dpaa2_enable_ts;
93 #define DPAA2_QOS_TABLE_RECONFIGURE 1
94 #define DPAA2_FS_TABLE_RECONFIGURE 2
97 extern const struct rte_flow_ops dpaa2_flow_ops;
98 extern enum rte_filter_type dpaa2_filter_type;
100 struct dpaa2_dev_priv {
105 uint8_t nb_tx_queues;
106 uint8_t nb_rx_queues;
108 void *rx_vq[MAX_RX_QUEUES];
109 void *tx_vq[MAX_TX_QUEUES];
110 struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
111 void *tx_conf_vq[MAX_TX_QUEUES];
113 uint8_t max_mac_filters;
114 uint8_t max_vlan_filters;
116 uint8_t flags; /*dpaa2 config flags */
118 uint8_t en_loose_ordered;
120 uint8_t cgid_in_use[MAX_RX_QUEUES];
124 uint8_t pattern_type[DPKG_MAX_NUM_OF_EXTRACTS];
125 } pattern[MAX_TCS + 1];
128 struct dpkg_profile_cfg qos_key_cfg;
129 struct dpkg_profile_cfg fs_key_cfg[MAX_TCS];
130 uint64_t qos_extract_param;
131 uint64_t fs_extract_param[MAX_TCS];
134 #if defined(RTE_LIBRTE_IEEE1588)
135 /*stores timestamp of last received packet on dev*/
136 uint64_t rx_timestamp;
137 /*stores timestamp of last received tx confirmation packet on dev*/
138 uint64_t tx_timestamp;
139 /* stores pointer to next tx_conf queue that should be processed,
140 * it corresponds to last packet transmitted
142 struct dpaa2_queue *next_tx_conf_queue;
144 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
147 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
148 struct dpkg_profile_cfg *kg_cfg);
150 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
151 uint64_t req_dist_set);
153 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
156 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
158 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
161 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
163 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
164 int eth_rx_queue_id);
166 uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
168 uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs,
171 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
173 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
174 const struct qbman_fd *fd,
175 const struct qbman_result *dq,
176 struct dpaa2_queue *rxq,
177 struct rte_event *ev);
178 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp,
179 const struct qbman_fd *fd,
180 const struct qbman_result *dq,
181 struct dpaa2_queue *rxq,
182 struct rte_event *ev);
183 void dpaa2_dev_process_ordered_event(struct qbman_swp *swp,
184 const struct qbman_fd *fd,
185 const struct qbman_result *dq,
186 struct dpaa2_queue *rxq,
187 struct rte_event *ev);
188 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
189 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,
191 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
192 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
193 void dpaa2_flow_clean(struct rte_eth_dev *dev);
194 uint16_t dpaa2_dev_tx_conf(void *queue) __attribute__((unused));
196 #if defined(RTE_LIBRTE_IEEE1588)
197 int dpaa2_timesync_enable(struct rte_eth_dev *dev);
198 int dpaa2_timesync_disable(struct rte_eth_dev *dev);
199 int dpaa2_timesync_read_time(struct rte_eth_dev *dev,
200 struct timespec *timestamp);
201 int dpaa2_timesync_write_time(struct rte_eth_dev *dev,
202 const struct timespec *timestamp);
203 int dpaa2_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
204 int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
205 struct timespec *timestamp,
206 uint32_t flags __rte_unused);
207 int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
208 struct timespec *timestamp);
210 #endif /* _DPAA2_ETHDEV_H */