1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2020 NXP
8 #ifndef _DPAA2_ETHDEV_H
9 #define _DPAA2_ETHDEV_H
11 #include <rte_event_eth_rx_adapter.h>
12 #include <rte_pmd_dpaa2.h>
14 #include <dpaa2_hw_pvt.h>
16 #include <mc/fsl_dpni.h>
17 #include <mc/fsl_mc_sys.h>
19 #define DPAA2_MIN_RX_BUF_SIZE 512
20 #define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/
22 #define MAX_TCS DPNI_MAX_TC
23 #define MAX_RX_QUEUES 128
24 #define MAX_TX_QUEUES 16
27 #define DPAA2_RX_DEFAULT_NBDESC 512
29 #define DPAA2_ETH_MAX_LEN (RTE_ETHER_MTU + \
30 RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
33 /*default tc to be used for ,congestion, distribution etc configuration. */
34 #define DPAA2_DEF_TC 0
36 /* Threshold for a Tx queue to *Enter* Congestion state.
38 #define CONG_ENTER_TX_THRESHOLD 512
40 /* Threshold for a queue to *Exit* Congestion state.
42 #define CONG_EXIT_TX_THRESHOLD 480
44 #define CONG_RETRY_COUNT 18000
46 /* RX queue tail drop threshold
47 * currently considering 64 KB packets
49 #define CONG_THRESHOLD_RX_BYTES_Q (64 * 1024)
50 #define CONG_RX_OAL 128
52 /* Size of the input SMMU mapped memory required by MC */
53 #define DIST_PARAM_IOVA_SIZE 256
55 /* Enable TX Congestion control support
58 #define DPAA2_TX_CGR_OFF 0x01
60 /* Disable RX tail drop, default is enable */
61 #define DPAA2_RX_TAILDROP_OFF 0x04
63 #define DPAA2_RSS_OFFLOAD_ALL ( \
64 ETH_RSS_L2_PAYLOAD | \
70 /* LX2 FRC Parsed values (Little Endian) */
71 #define DPAA2_PKT_TYPE_ETHER 0x0060
72 #define DPAA2_PKT_TYPE_IPV4 0x0000
73 #define DPAA2_PKT_TYPE_IPV6 0x0020
74 #define DPAA2_PKT_TYPE_IPV4_EXT \
75 (0x0001 | DPAA2_PKT_TYPE_IPV4)
76 #define DPAA2_PKT_TYPE_IPV6_EXT \
77 (0x0001 | DPAA2_PKT_TYPE_IPV6)
78 #define DPAA2_PKT_TYPE_IPV4_TCP \
79 (0x000e | DPAA2_PKT_TYPE_IPV4)
80 #define DPAA2_PKT_TYPE_IPV6_TCP \
81 (0x000e | DPAA2_PKT_TYPE_IPV6)
82 #define DPAA2_PKT_TYPE_IPV4_UDP \
83 (0x0010 | DPAA2_PKT_TYPE_IPV4)
84 #define DPAA2_PKT_TYPE_IPV6_UDP \
85 (0x0010 | DPAA2_PKT_TYPE_IPV6)
86 #define DPAA2_PKT_TYPE_IPV4_SCTP \
87 (0x000f | DPAA2_PKT_TYPE_IPV4)
88 #define DPAA2_PKT_TYPE_IPV6_SCTP \
89 (0x000f | DPAA2_PKT_TYPE_IPV6)
90 #define DPAA2_PKT_TYPE_IPV4_ICMP \
91 (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT)
92 #define DPAA2_PKT_TYPE_IPV6_ICMP \
93 (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT)
94 #define DPAA2_PKT_TYPE_VLAN_1 0x0160
95 #define DPAA2_PKT_TYPE_VLAN_2 0x0260
97 /* enable timestamp in mbuf*/
98 extern bool dpaa2_enable_ts[];
99 extern uint64_t dpaa2_timestamp_rx_dynflag;
100 extern int dpaa2_timestamp_dynfield_offset;
102 #define DPAA2_QOS_TABLE_RECONFIGURE 1
103 #define DPAA2_FS_TABLE_RECONFIGURE 2
105 #define DPAA2_QOS_TABLE_IPADDR_EXTRACT 4
106 #define DPAA2_FS_TABLE_IPADDR_EXTRACT 8
108 #define DPAA2_FLOW_MAX_KEY_SIZE 16
110 /*Externaly defined*/
111 extern const struct rte_flow_ops dpaa2_flow_ops;
112 extern enum rte_filter_type dpaa2_filter_type;
114 #define IP_ADDRESS_OFFSET_INVALID (-1)
116 struct dpaa2_key_info {
117 uint8_t key_offset[DPKG_MAX_NUM_OF_EXTRACTS];
118 uint8_t key_size[DPKG_MAX_NUM_OF_EXTRACTS];
119 /* Special for IP address. */
124 uint8_t key_total_size;
127 struct dpaa2_key_extract {
128 struct dpkg_profile_cfg dpkg;
129 struct dpaa2_key_info key_info;
133 struct dpaa2_key_extract qos_key_extract;
134 struct dpaa2_key_extract tc_key_extract[MAX_TCS];
135 uint64_t qos_extract_param;
136 uint64_t tc_extract_param[MAX_TCS];
139 struct dpaa2_dev_priv {
144 uint8_t nb_tx_queues;
145 uint8_t nb_rx_queues;
147 void *rx_vq[MAX_RX_QUEUES];
148 void *tx_vq[MAX_TX_QUEUES];
149 struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
150 void *tx_conf_vq[MAX_TX_QUEUES];
152 uint8_t max_mac_filters;
153 uint8_t max_vlan_filters;
155 uint16_t qos_entries;
158 uint8_t flags; /*dpaa2 config flags */
160 uint8_t en_loose_ordered;
162 uint8_t cgid_in_use[MAX_RX_QUEUES];
164 struct extract_s extract;
168 uint64_t ss_param_iova;
169 /*stores timestamp of last received packet on dev*/
170 uint64_t rx_timestamp;
171 /*stores timestamp of last received tx confirmation packet on dev*/
172 uint64_t tx_timestamp;
173 /* stores pointer to next tx_conf queue that should be processed,
174 * it corresponds to last packet transmitted
176 struct dpaa2_queue *next_tx_conf_queue;
178 struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */
180 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
183 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set,
184 struct dpkg_profile_cfg *kg_cfg);
186 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
187 uint64_t req_dist_set, int tc_index);
189 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
192 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
195 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
197 struct dpaa2_dpcon_dev *dpcon,
198 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
201 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
202 int eth_rx_queue_id);
204 uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
206 uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs,
209 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
211 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
212 const struct qbman_fd *fd,
213 const struct qbman_result *dq,
214 struct dpaa2_queue *rxq,
215 struct rte_event *ev);
216 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp,
217 const struct qbman_fd *fd,
218 const struct qbman_result *dq,
219 struct dpaa2_queue *rxq,
220 struct rte_event *ev);
221 void dpaa2_dev_process_ordered_event(struct qbman_swp *swp,
222 const struct qbman_fd *fd,
223 const struct qbman_result *dq,
224 struct dpaa2_queue *rxq,
225 struct rte_event *ev);
226 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
227 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,
229 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
230 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
231 void dpaa2_flow_clean(struct rte_eth_dev *dev);
232 uint16_t dpaa2_dev_tx_conf(void *queue) __rte_unused;
234 int dpaa2_timesync_enable(struct rte_eth_dev *dev);
235 int dpaa2_timesync_disable(struct rte_eth_dev *dev);
236 int dpaa2_timesync_read_time(struct rte_eth_dev *dev,
237 struct timespec *timestamp);
238 int dpaa2_timesync_write_time(struct rte_eth_dev *dev,
239 const struct timespec *timestamp);
240 int dpaa2_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
241 int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
242 struct timespec *timestamp,
243 uint32_t flags __rte_unused);
244 int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
245 struct timespec *timestamp);
246 #endif /* _DPAA2_ETHDEV_H */