drivers/net/dpaa2/dpaa2_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016 NXP
   5  *
   6  */
   7
   8 #ifndef _DPAA2_ETHDEV_H
   9 #define _DPAA2_ETHDEV_H
  10
  11 #include <rte_event_eth_rx_adapter.h>
  12
  13 #include <mc/fsl_dpni.h>
  14 #include <mc/fsl_mc_sys.h>
  15
  16 #define DPAA2_MIN_RX_BUF_SIZE 512
  17 #define DPAA2_MAX_RX_PKT_LEN  10240 /*WRIOP support*/
  18
  19 #define MAX_TCS                 DPNI_MAX_TC
  20 #define MAX_RX_QUEUES           16
  21 #define MAX_TX_QUEUES           16
  22
  23 /*default tc to be used for ,congestion, distribution etc configuration. */
  24 #define DPAA2_DEF_TC            0
  25
  26 /* Threshold for a Tx queue to *Enter* Congestion state.
  27  */
  28 #define CONG_ENTER_TX_THRESHOLD   512
  29
  30 /* Threshold for a queue to *Exit* Congestion state.
  31  */
  32 #define CONG_EXIT_TX_THRESHOLD    480
  33
  34 #define CONG_RETRY_COUNT 18000
  35
  36 /* RX queue tail drop threshold
  37  * currently considering 32 KB packets
  38  */
  39 #define CONG_THRESHOLD_RX_Q  (64 * 1024)
  40 #define CONG_RX_OAL     128
  41
  42 /* Size of the input SMMU mapped memory required by MC */
  43 #define DIST_PARAM_IOVA_SIZE 256
  44
  45 /* Enable TX Congestion control support
  46  * default is disable
  47  */
  48 #define DPAA2_TX_CGR_OFF        0x01
  49
  50 /* Disable RX tail drop, default is enable */
  51 #define DPAA2_RX_TAILDROP_OFF   0x04
  52
  53 struct dpaa2_dev_priv {
  54         void *hw;
  55         int32_t hw_id;
  56         int32_t qdid;
  57         uint16_t token;
  58         uint8_t nb_tx_queues;
  59         uint8_t nb_rx_queues;
  60         void *rx_vq[MAX_RX_QUEUES];
  61         void *tx_vq[MAX_TX_QUEUES];
  62
  63         struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
  64         uint32_t options;
  65         uint8_t max_mac_filters;
  66         uint8_t max_vlan_filters;
  67         uint8_t num_rx_tc;
  68         uint8_t flags; /*dpaa2 config flags */
  69 };
  70
  71 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
  72                           uint64_t req_dist_set);
  73
  74 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
  75                            uint8_t tc_index);
  76
  77 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
  78
  79 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
  80                 int eth_rx_queue_id,
  81                 uint16_t dpcon_id,
  82                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
  83
  84 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
  85                 int eth_rx_queue_id);
  86
  87 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
  88                                uint16_t nb_pkts);
  89 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
  90                                       const struct qbman_fd *fd,
  91                                       const struct qbman_result *dq,
  92                                       struct dpaa2_queue *rxq,
  93                                       struct rte_event *ev);
  94 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
  95 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
  96 #endif /* _DPAA2_ETHDEV_H */