drivers/net/dpaa2/dpaa2_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016 NXP
   5  *
   6  */
   7
   8 #ifndef _DPAA2_ETHDEV_H
   9 #define _DPAA2_ETHDEV_H
  10
  11 #include <rte_event_eth_rx_adapter.h>
  12 #include <rte_pmd_dpaa2.h>
  13
  14 #include <mc/fsl_dpni.h>
  15 #include <mc/fsl_mc_sys.h>
  16
  17 #define DPAA2_MIN_RX_BUF_SIZE 512
  18 #define DPAA2_MAX_RX_PKT_LEN  10240 /*WRIOP support*/
  19
  20 #define MAX_TCS                 DPNI_MAX_TC
  21 #define MAX_RX_QUEUES           16
  22 #define MAX_TX_QUEUES           16
  23
  24 /*default tc to be used for ,congestion, distribution etc configuration. */
  25 #define DPAA2_DEF_TC            0
  26
  27 /* Threshold for a Tx queue to *Enter* Congestion state.
  28  */
  29 #define CONG_ENTER_TX_THRESHOLD   512
  30
  31 /* Threshold for a queue to *Exit* Congestion state.
  32  */
  33 #define CONG_EXIT_TX_THRESHOLD    480
  34
  35 #define CONG_RETRY_COUNT 18000
  36
  37 /* RX queue tail drop threshold
  38  * currently considering 32 KB packets
  39  */
  40 #define CONG_THRESHOLD_RX_Q  (64 * 1024)
  41 #define CONG_RX_OAL     128
  42
  43 /* Size of the input SMMU mapped memory required by MC */
  44 #define DIST_PARAM_IOVA_SIZE 256
  45
  46 /* Enable TX Congestion control support
  47  * default is disable
  48  */
  49 #define DPAA2_TX_CGR_OFF        0x01
  50
  51 /* Disable RX tail drop, default is enable */
  52 #define DPAA2_RX_TAILDROP_OFF   0x04
  53
  54 #define DPAA2_RSS_OFFLOAD_ALL ( \
  55         ETH_RSS_IP | \
  56         ETH_RSS_UDP | \
  57         ETH_RSS_TCP | \
  58         ETH_RSS_SCTP)
  59
  60 /* LX2 FRC Parsed values (Little Endian) */
  61 #define DPAA2_PKT_TYPE_ETHER            0x0060
  62 #define DPAA2_PKT_TYPE_IPV4             0x0000
  63 #define DPAA2_PKT_TYPE_IPV6             0x0020
  64 #define DPAA2_PKT_TYPE_IPV4_EXT \
  65                         (0x0001 | DPAA2_PKT_TYPE_IPV4)
  66 #define DPAA2_PKT_TYPE_IPV6_EXT \
  67                         (0x0001 | DPAA2_PKT_TYPE_IPV6)
  68 #define DPAA2_PKT_TYPE_IPV4_TCP \
  69                         (0x000e | DPAA2_PKT_TYPE_IPV4)
  70 #define DPAA2_PKT_TYPE_IPV6_TCP \
  71                         (0x000e | DPAA2_PKT_TYPE_IPV6)
  72 #define DPAA2_PKT_TYPE_IPV4_UDP \
  73                         (0x0010 | DPAA2_PKT_TYPE_IPV4)
  74 #define DPAA2_PKT_TYPE_IPV6_UDP \
  75                         (0x0010 | DPAA2_PKT_TYPE_IPV6)
  76 #define DPAA2_PKT_TYPE_IPV4_SCTP        \
  77                         (0x000f | DPAA2_PKT_TYPE_IPV4)
  78 #define DPAA2_PKT_TYPE_IPV6_SCTP        \
  79                         (0x000f | DPAA2_PKT_TYPE_IPV6)
  80 #define DPAA2_PKT_TYPE_IPV4_ICMP \
  81                         (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT)
  82 #define DPAA2_PKT_TYPE_IPV6_ICMP \
  83                         (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT)
  84 #define DPAA2_PKT_TYPE_VLAN_1           0x0160
  85 #define DPAA2_PKT_TYPE_VLAN_2           0x0260
  86
  87 /* enable timestamp in mbuf*/
  88 extern enum pmd_dpaa2_ts dpaa2_enable_ts;
  89
  90 struct dpaa2_dev_priv {
  91         void *hw;
  92         int32_t hw_id;
  93         int32_t qdid;
  94         uint16_t token;
  95         uint8_t nb_tx_queues;
  96         uint8_t nb_rx_queues;
  97         void *rx_vq[MAX_RX_QUEUES];
  98         void *tx_vq[MAX_TX_QUEUES];
  99
 100         struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
 101         uint32_t options;
 102         uint8_t max_mac_filters;
 103         uint8_t max_vlan_filters;
 104         uint8_t num_rx_tc;
 105         uint8_t flags; /*dpaa2 config flags */
 106 };
 107
 108 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
 109                           uint64_t req_dist_set);
 110
 111 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
 112                            uint8_t tc_index);
 113
 114 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
 115
 116 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
 117                 int eth_rx_queue_id,
 118                 uint16_t dpcon_id,
 119                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
 120
 121 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
 122                 int eth_rx_queue_id);
 123
 124 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
 125                                uint16_t nb_pkts);
 126 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 127                                       const struct qbman_fd *fd,
 128                                       const struct qbman_result *dq,
 129                                       struct dpaa2_queue *rxq,
 130                                       struct rte_event *ev);
 131 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp,
 132                                     const struct qbman_fd *fd,
 133                                     const struct qbman_result *dq,
 134                                     struct dpaa2_queue *rxq,
 135                                     struct rte_event *ev);
 136 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 137 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 138 #endif /* _DPAA2_ETHDEV_H */