drivers/net/dpaa2/dpaa2_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2020 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <rte_ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_dev.h>
  17
  18 #include <rte_fslmc.h>
  19 #include <fslmc_vfio.h>
  20 #include <dpaa2_hw_pvt.h>
  21 #include <dpaa2_hw_dpio.h>
  22 #include <dpaa2_hw_mempool.h>
  23
  24 #include "dpaa2_pmd_logs.h"
  25 #include "dpaa2_ethdev.h"
  26 #include "base/dpaa2_hw_dpni_annot.h"
  27
  28 static inline uint32_t __rte_hot
  29 dpaa2_dev_rx_parse_slow(struct rte_mbuf *mbuf,
  30                         struct dpaa2_annot_hdr *annotation);
  31
  32 static void enable_tx_tstamp(struct qbman_fd *fd) __rte_unused;
  33
  34 #define DPAA2_MBUF_TO_CONTIG_FD(_mbuf, _fd, _bpid)  do { \
  35         DPAA2_SET_FD_ADDR(_fd, DPAA2_MBUF_VADDR_TO_IOVA(_mbuf)); \
  36         DPAA2_SET_FD_LEN(_fd, _mbuf->data_len); \
  37         DPAA2_SET_ONLY_FD_BPID(_fd, _bpid); \
  38         DPAA2_SET_FD_OFFSET(_fd, _mbuf->data_off); \
  39         DPAA2_SET_FD_FRC(_fd, 0);               \
  40         DPAA2_RESET_FD_CTRL(_fd);               \
  41         DPAA2_RESET_FD_FLC(_fd);                \
  42 } while (0)
  43
  44 static inline void __rte_hot
  45 dpaa2_dev_rx_parse_new(struct rte_mbuf *m, const struct qbman_fd *fd)
  46 {
  47         struct dpaa2_annot_hdr *annotation;
  48         uint16_t frc = DPAA2_GET_FD_FRC_PARSE_SUM(fd);
  49
  50         m->packet_type = RTE_PTYPE_UNKNOWN;
  51         switch (frc) {
  52         case DPAA2_PKT_TYPE_ETHER:
  53                 m->packet_type = RTE_PTYPE_L2_ETHER;
  54                 break;
  55         case DPAA2_PKT_TYPE_IPV4:
  56                 m->packet_type = RTE_PTYPE_L2_ETHER |
  57                         RTE_PTYPE_L3_IPV4;
  58                 break;
  59         case DPAA2_PKT_TYPE_IPV6:
  60                 m->packet_type = RTE_PTYPE_L2_ETHER |
  61                         RTE_PTYPE_L3_IPV6;
  62                 break;
  63         case DPAA2_PKT_TYPE_IPV4_EXT:
  64                 m->packet_type = RTE_PTYPE_L2_ETHER |
  65                         RTE_PTYPE_L3_IPV4_EXT;
  66                 break;
  67         case DPAA2_PKT_TYPE_IPV6_EXT:
  68                 m->packet_type = RTE_PTYPE_L2_ETHER |
  69                         RTE_PTYPE_L3_IPV6_EXT;
  70                 break;
  71         case DPAA2_PKT_TYPE_IPV4_TCP:
  72                 m->packet_type = RTE_PTYPE_L2_ETHER |
  73                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP;
  74                 break;
  75         case DPAA2_PKT_TYPE_IPV6_TCP:
  76                 m->packet_type = RTE_PTYPE_L2_ETHER |
  77                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP;
  78                 break;
  79         case DPAA2_PKT_TYPE_IPV4_UDP:
  80                 m->packet_type = RTE_PTYPE_L2_ETHER |
  81                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP;
  82                 break;
  83         case DPAA2_PKT_TYPE_IPV6_UDP:
  84                 m->packet_type = RTE_PTYPE_L2_ETHER |
  85                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP;
  86                 break;
  87         case DPAA2_PKT_TYPE_IPV4_SCTP:
  88                 m->packet_type = RTE_PTYPE_L2_ETHER |
  89                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP;
  90                 break;
  91         case DPAA2_PKT_TYPE_IPV6_SCTP:
  92                 m->packet_type = RTE_PTYPE_L2_ETHER |
  93                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP;
  94                 break;
  95         case DPAA2_PKT_TYPE_IPV4_ICMP:
  96                 m->packet_type = RTE_PTYPE_L2_ETHER |
  97                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_ICMP;
  98                 break;
  99         case DPAA2_PKT_TYPE_IPV6_ICMP:
 100                 m->packet_type = RTE_PTYPE_L2_ETHER |
 101                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_ICMP;
 102                 break;
 103         default:
 104                 m->packet_type = dpaa2_dev_rx_parse_slow(m,
 105                   (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 106                          + DPAA2_FD_PTA_SIZE));
 107         }
 108         m->hash.rss = fd->simple.flc_hi;
 109         m->ol_flags |= PKT_RX_RSS_HASH;
 110
 111         if (dpaa2_enable_ts == PMD_DPAA2_ENABLE_TS) {
 112                 annotation = (struct dpaa2_annot_hdr *)
 113                         ((size_t)DPAA2_IOVA_TO_VADDR(
 114                         DPAA2_GET_FD_ADDR(fd)) + DPAA2_FD_PTA_SIZE);
 115                 m->timestamp = annotation->word2;
 116                 m->ol_flags |= PKT_RX_TIMESTAMP;
 117                 DPAA2_PMD_DP_DEBUG("pkt timestamp:0x%" PRIx64 "", m->timestamp);
 118         }
 119
 120         DPAA2_PMD_DP_DEBUG("HW frc = 0x%x\t packet type =0x%x "
 121                 "ol_flags =0x%" PRIx64 "",
 122                 frc, m->packet_type, m->ol_flags);
 123 }
 124
 125 static inline uint32_t __rte_hot
 126 dpaa2_dev_rx_parse_slow(struct rte_mbuf *mbuf,
 127                         struct dpaa2_annot_hdr *annotation)
 128 {
 129         uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
 130         uint16_t *vlan_tci;
 131
 132         DPAA2_PMD_DP_DEBUG("(slow parse)annotation(3)=0x%" PRIx64 "\t"
 133                         "(4)=0x%" PRIx64 "\t",
 134                         annotation->word3, annotation->word4);
 135
 136 #if defined(RTE_LIBRTE_IEEE1588)
 137         if (BIT_ISSET_AT_POS(annotation->word1, DPAA2_ETH_FAS_PTP))
 138                 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP;
 139 #endif
 140
 141         if (BIT_ISSET_AT_POS(annotation->word3, L2_VLAN_1_PRESENT)) {
 142                 vlan_tci = rte_pktmbuf_mtod_offset(mbuf, uint16_t *,
 143                         (VLAN_TCI_OFFSET_1(annotation->word5) >> 16));
 144                 mbuf->vlan_tci = rte_be_to_cpu_16(*vlan_tci);
 145                 mbuf->ol_flags |= PKT_RX_VLAN;
 146                 pkt_type |= RTE_PTYPE_L2_ETHER_VLAN;
 147         } else if (BIT_ISSET_AT_POS(annotation->word3, L2_VLAN_N_PRESENT)) {
 148                 vlan_tci = rte_pktmbuf_mtod_offset(mbuf, uint16_t *,
 149                         (VLAN_TCI_OFFSET_1(annotation->word5) >> 16));
 150                 mbuf->vlan_tci = rte_be_to_cpu_16(*vlan_tci);
 151                 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_QINQ;
 152                 pkt_type |= RTE_PTYPE_L2_ETHER_QINQ;
 153         }
 154
 155         if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
 156                 pkt_type |= RTE_PTYPE_L2_ETHER_ARP;
 157                 goto parse_done;
 158         } else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) {
 159                 pkt_type |= RTE_PTYPE_L2_ETHER;
 160         } else {
 161                 goto parse_done;
 162         }
 163
 164         if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT |
 165                              L3_IPV4_N_PRESENT)) {
 166                 pkt_type |= RTE_PTYPE_L3_IPV4;
 167                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 168                         L3_IP_N_OPT_PRESENT))
 169                         pkt_type |= RTE_PTYPE_L3_IPV4_EXT;
 170
 171         } else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT |
 172                   L3_IPV6_N_PRESENT)) {
 173                 pkt_type |= RTE_PTYPE_L3_IPV6;
 174                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 175                     L3_IP_N_OPT_PRESENT))
 176                         pkt_type |= RTE_PTYPE_L3_IPV6_EXT;
 177         } else {
 178                 goto parse_done;
 179         }
 180
 181         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
 182                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 183         else if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
 184                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 185
 186         if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |
 187             L3_IP_1_MORE_FRAGMENT |
 188             L3_IP_N_FIRST_FRAGMENT |
 189             L3_IP_N_MORE_FRAGMENT)) {
 190                 pkt_type |= RTE_PTYPE_L4_FRAG;
 191                 goto parse_done;
 192         } else {
 193                 pkt_type |= RTE_PTYPE_L4_NONFRAG;
 194         }
 195
 196         if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))
 197                 pkt_type |= RTE_PTYPE_L4_UDP;
 198
 199         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))
 200                 pkt_type |= RTE_PTYPE_L4_TCP;
 201
 202         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))
 203                 pkt_type |= RTE_PTYPE_L4_SCTP;
 204
 205         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))
 206                 pkt_type |= RTE_PTYPE_L4_ICMP;
 207
 208         else if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))
 209                 pkt_type |= RTE_PTYPE_UNKNOWN;
 210
 211 parse_done:
 212         return pkt_type;
 213 }
 214
 215 static inline uint32_t __rte_hot
 216 dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr)
 217 {
 218         struct dpaa2_annot_hdr *annotation =
 219                         (struct dpaa2_annot_hdr *)hw_annot_addr;
 220
 221         DPAA2_PMD_DP_DEBUG("(fast parse) Annotation = 0x%" PRIx64 "\t",
 222                            annotation->word4);
 223
 224         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
 225                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 226         else if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
 227                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 228
 229         mbuf->ol_flags |= PKT_RX_TIMESTAMP;
 230         mbuf->timestamp = annotation->word2;
 231         DPAA2_PMD_DP_DEBUG("pkt timestamp: 0x%" PRIx64 "", mbuf->timestamp);
 232
 233         /* Check detailed parsing requirement */
 234         if (annotation->word3 & 0x7FFFFC3FFFF)
 235                 return dpaa2_dev_rx_parse_slow(mbuf, annotation);
 236
 237         /* Return some common types from parse processing */
 238         switch (annotation->word4) {
 239         case DPAA2_L3_IPv4:
 240                 return RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
 241         case DPAA2_L3_IPv6:
 242                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
 243         case DPAA2_L3_IPv4_TCP:
 244                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 245                                 RTE_PTYPE_L4_TCP;
 246         case DPAA2_L3_IPv4_UDP:
 247                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 248                                 RTE_PTYPE_L4_UDP;
 249         case DPAA2_L3_IPv6_TCP:
 250                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 251                                 RTE_PTYPE_L4_TCP;
 252         case DPAA2_L3_IPv6_UDP:
 253                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 254                                 RTE_PTYPE_L4_UDP;
 255         default:
 256                 break;
 257         }
 258
 259         return dpaa2_dev_rx_parse_slow(mbuf, annotation);
 260 }
 261
 262 static inline struct rte_mbuf *__rte_hot
 263 eth_sg_fd_to_mbuf(const struct qbman_fd *fd,
 264                   int port_id)
 265 {
 266         struct qbman_sge *sgt, *sge;
 267         size_t sg_addr, fd_addr;
 268         int i = 0;
 269         struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp;
 270
 271         fd_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
 272
 273         /* Get Scatter gather table address */
 274         sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd));
 275
 276         sge = &sgt[i++];
 277         sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
 278
 279         /* First Scatter gather entry */
 280         first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 281                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 282         /* Prepare all the metadata for first segment */
 283         first_seg->buf_addr = (uint8_t *)sg_addr;
 284         first_seg->ol_flags = 0;
 285         first_seg->data_off = DPAA2_GET_FLE_OFFSET(sge);
 286         first_seg->data_len = sge->length  & 0x1FFFF;
 287         first_seg->pkt_len = DPAA2_GET_FD_LEN(fd);
 288         first_seg->nb_segs = 1;
 289         first_seg->next = NULL;
 290         first_seg->port = port_id;
 291         if (dpaa2_svr_family == SVR_LX2160A)
 292                 dpaa2_dev_rx_parse_new(first_seg, fd);
 293         else
 294                 first_seg->packet_type = dpaa2_dev_rx_parse(first_seg,
 295                         (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 296                          + DPAA2_FD_PTA_SIZE));
 297
 298         rte_mbuf_refcnt_set(first_seg, 1);
 299         cur_seg = first_seg;
 300         while (!DPAA2_SG_IS_FINAL(sge)) {
 301                 sge = &sgt[i++];
 302                 sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(
 303                                 DPAA2_GET_FLE_ADDR(sge));
 304                 next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 305                         rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size);
 306                 next_seg->buf_addr  = (uint8_t *)sg_addr;
 307                 next_seg->data_off  = DPAA2_GET_FLE_OFFSET(sge);
 308                 next_seg->data_len  = sge->length  & 0x1FFFF;
 309                 first_seg->nb_segs += 1;
 310                 rte_mbuf_refcnt_set(next_seg, 1);
 311                 cur_seg->next = next_seg;
 312                 next_seg->next = NULL;
 313                 cur_seg = next_seg;
 314         }
 315         temp = DPAA2_INLINE_MBUF_FROM_BUF(fd_addr,
 316                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 317         rte_mbuf_refcnt_set(temp, 1);
 318         rte_pktmbuf_free_seg(temp);
 319
 320         return (void *)first_seg;
 321 }
 322
 323 static inline struct rte_mbuf *__rte_hot
 324 eth_fd_to_mbuf(const struct qbman_fd *fd,
 325                int port_id)
 326 {
 327         void *iova_addr = DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
 328         struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(iova_addr,
 329                      rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 330
 331         /* need to repopulated some of the fields,
 332          * as they may have changed in last transmission
 333          */
 334         mbuf->nb_segs = 1;
 335         mbuf->ol_flags = 0;
 336         mbuf->data_off = DPAA2_GET_FD_OFFSET(fd);
 337         mbuf->data_len = DPAA2_GET_FD_LEN(fd);
 338         mbuf->pkt_len = mbuf->data_len;
 339         mbuf->port = port_id;
 340         mbuf->next = NULL;
 341         rte_mbuf_refcnt_set(mbuf, 1);
 342
 343         /* Parse the packet */
 344         /* parse results for LX2 are there in FRC field of FD.
 345          * For other DPAA2 platforms , parse results are after
 346          * the private - sw annotation area
 347          */
 348
 349         if (dpaa2_svr_family == SVR_LX2160A)
 350                 dpaa2_dev_rx_parse_new(mbuf, fd);
 351         else
 352                 mbuf->packet_type = dpaa2_dev_rx_parse(mbuf,
 353                         (void *)((size_t)iova_addr + DPAA2_FD_PTA_SIZE));
 354
 355         DPAA2_PMD_DP_DEBUG("to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 356                 "fd_off=%d fd =%" PRIx64 ", meta = %d  bpid =%d, len=%d\n",
 357                 mbuf, mbuf->buf_addr, mbuf->data_off,
 358                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 359                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 360                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 361
 362         return mbuf;
 363 }
 364
 365 static int __rte_noinline __rte_hot
 366 eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
 367                   struct qbman_fd *fd, uint16_t bpid)
 368 {
 369         struct rte_mbuf *cur_seg = mbuf, *prev_seg, *mi, *temp;
 370         struct qbman_sge *sgt, *sge = NULL;
 371         int i;
 372
 373         temp = rte_pktmbuf_alloc(mbuf->pool);
 374         if (temp == NULL) {
 375                 DPAA2_PMD_DP_DEBUG("No memory to allocate S/G table\n");
 376                 return -ENOMEM;
 377         }
 378
 379         DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(temp));
 380         DPAA2_SET_FD_LEN(fd, mbuf->pkt_len);
 381         DPAA2_SET_ONLY_FD_BPID(fd, bpid);
 382         DPAA2_SET_FD_OFFSET(fd, temp->data_off);
 383         DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg);
 384         DPAA2_RESET_FD_FRC(fd);
 385         DPAA2_RESET_FD_CTRL(fd);
 386         /*Set Scatter gather table and Scatter gather entries*/
 387         sgt = (struct qbman_sge *)(
 388                         (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 389                         + DPAA2_GET_FD_OFFSET(fd));
 390
 391         for (i = 0; i < mbuf->nb_segs; i++) {
 392                 sge = &sgt[i];
 393                 /*Resetting the buffer pool id and offset field*/
 394                 sge->fin_bpid_offset = 0;
 395                 DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(cur_seg));
 396                 DPAA2_SET_FLE_OFFSET(sge, cur_seg->data_off);
 397                 sge->length = cur_seg->data_len;
 398                 if (RTE_MBUF_DIRECT(cur_seg)) {
 399                         if (rte_mbuf_refcnt_read(cur_seg) > 1) {
 400                                 /* If refcnt > 1, invalid bpid is set to ensure
 401                                  * buffer is not freed by HW
 402                                  */
 403                                 DPAA2_SET_FLE_IVP(sge);
 404                                 rte_mbuf_refcnt_update(cur_seg, -1);
 405                         } else
 406                                 DPAA2_SET_FLE_BPID(sge,
 407                                                 mempool_to_bpid(cur_seg->pool));
 408                         cur_seg = cur_seg->next;
 409                 } else {
 410                         /* Get owner MBUF from indirect buffer */
 411                         mi = rte_mbuf_from_indirect(cur_seg);
 412                         if (rte_mbuf_refcnt_read(mi) > 1) {
 413                                 /* If refcnt > 1, invalid bpid is set to ensure
 414                                  * owner buffer is not freed by HW
 415                                  */
 416                                 DPAA2_SET_FLE_IVP(sge);
 417                         } else {
 418                                 DPAA2_SET_FLE_BPID(sge,
 419                                                    mempool_to_bpid(mi->pool));
 420                                 rte_mbuf_refcnt_update(mi, 1);
 421                         }
 422                         prev_seg = cur_seg;
 423                         cur_seg = cur_seg->next;
 424                         prev_seg->next = NULL;
 425                         rte_pktmbuf_free(prev_seg);
 426                 }
 427         }
 428         DPAA2_SG_SET_FINAL(sge, true);
 429         return 0;
 430 }
 431
 432 static void
 433 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 434                struct qbman_fd *fd, uint16_t bpid) __rte_unused;
 435
 436 static void __rte_noinline __rte_hot
 437 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 438                struct qbman_fd *fd, uint16_t bpid)
 439 {
 440         DPAA2_MBUF_TO_CONTIG_FD(mbuf, fd, bpid);
 441
 442         DPAA2_PMD_DP_DEBUG("mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 443                 "fd_off=%d fd =%" PRIx64 ", meta = %d  bpid =%d, len=%d\n",
 444                 mbuf, mbuf->buf_addr, mbuf->data_off,
 445                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 446                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 447                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 448         if (RTE_MBUF_DIRECT(mbuf)) {
 449                 if (rte_mbuf_refcnt_read(mbuf) > 1) {
 450                         DPAA2_SET_FD_IVP(fd);
 451                         rte_mbuf_refcnt_update(mbuf, -1);
 452                 }
 453         } else {
 454                 struct rte_mbuf *mi;
 455
 456                 mi = rte_mbuf_from_indirect(mbuf);
 457                 if (rte_mbuf_refcnt_read(mi) > 1)
 458                         DPAA2_SET_FD_IVP(fd);
 459                 else
 460                         rte_mbuf_refcnt_update(mi, 1);
 461                 rte_pktmbuf_free(mbuf);
 462         }
 463 }
 464
 465 static inline int __rte_hot
 466 eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf,
 467                     struct qbman_fd *fd, uint16_t bpid)
 468 {
 469         struct rte_mbuf *m;
 470         void *mb = NULL;
 471
 472         if (rte_dpaa2_mbuf_alloc_bulk(
 473                 rte_dpaa2_bpid_info[bpid].bp_list->mp, &mb, 1)) {
 474                 DPAA2_PMD_DP_DEBUG("Unable to allocated DPAA2 buffer\n");
 475                 return -1;
 476         }
 477         m = (struct rte_mbuf *)mb;
 478         memcpy((char *)m->buf_addr + mbuf->data_off,
 479                (void *)((char *)mbuf->buf_addr + mbuf->data_off),
 480                 mbuf->pkt_len);
 481
 482         /* Copy required fields */
 483         m->data_off = mbuf->data_off;
 484         m->ol_flags = mbuf->ol_flags;
 485         m->packet_type = mbuf->packet_type;
 486         m->tx_offload = mbuf->tx_offload;
 487
 488         DPAA2_MBUF_TO_CONTIG_FD(m, fd, bpid);
 489
 490         DPAA2_PMD_DP_DEBUG(
 491                 "mbuf: %p, BMAN buf addr: %p, fdaddr: %" PRIx64 ", bpid: %d,"
 492                 " meta: %d, off: %d, len: %d\n",
 493                 (void *)mbuf,
 494                 mbuf->buf_addr,
 495                 DPAA2_GET_FD_ADDR(fd),
 496                 DPAA2_GET_FD_BPID(fd),
 497                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 498                 DPAA2_GET_FD_OFFSET(fd),
 499                 DPAA2_GET_FD_LEN(fd));
 500
 501 return 0;
 502 }
 503
 504 /* This function assumes that caller will be keep the same value for nb_pkts
 505  * across calls per queue, if that is not the case, better use non-prefetch
 506  * version of rx call.
 507  * It will return the packets as requested in previous call without honoring
 508  * the current nb_pkts or bufs space.
 509  */
 510 uint16_t
 511 dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 512 {
 513         /* Function receive frames for a given device and VQ*/
 514         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 515         struct qbman_result *dq_storage, *dq_storage1 = NULL;
 516         uint32_t fqid = dpaa2_q->fqid;
 517         int ret, num_rx = 0, pull_size;
 518         uint8_t pending, status;
 519         struct qbman_swp *swp;
 520         const struct qbman_fd *fd;
 521         struct qbman_pull_desc pulldesc;
 522         struct queue_storage_info_t *q_storage = dpaa2_q->q_storage;
 523         struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
 524 #if defined(RTE_LIBRTE_IEEE1588)
 525         struct dpaa2_dev_priv *priv = eth_data->dev_private;
 526 #endif
 527
 528         if (unlikely(!DPAA2_PER_LCORE_ETHRX_DPIO)) {
 529                 ret = dpaa2_affine_qbman_ethrx_swp();
 530                 if (ret) {
 531                         DPAA2_PMD_ERR("Failure in affining portal");
 532                         return 0;
 533                 }
 534         }
 535
 536         if (unlikely(!rte_dpaa2_bpid_info &&
 537                      rte_eal_process_type() == RTE_PROC_SECONDARY))
 538                 rte_dpaa2_bpid_info = dpaa2_q->bp_array;
 539
 540         swp = DPAA2_PER_LCORE_ETHRX_PORTAL;
 541         pull_size = (nb_pkts > dpaa2_dqrr_size) ? dpaa2_dqrr_size : nb_pkts;
 542         if (unlikely(!q_storage->active_dqs)) {
 543                 q_storage->toggle = 0;
 544                 dq_storage = q_storage->dq_storage[q_storage->toggle];
 545                 q_storage->last_num_pkts = pull_size;
 546                 qbman_pull_desc_clear(&pulldesc);
 547                 qbman_pull_desc_set_numframes(&pulldesc,
 548                                               q_storage->last_num_pkts);
 549                 qbman_pull_desc_set_fq(&pulldesc, fqid);
 550                 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 551                         (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
 552                 if (check_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)) {
 553                         while (!qbman_check_command_complete(
 554                                get_swp_active_dqs(
 555                                DPAA2_PER_LCORE_ETHRX_DPIO->index)))
 556                                 ;
 557                         clear_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index);
 558                 }
 559                 while (1) {
 560                         if (qbman_swp_pull(swp, &pulldesc)) {
 561                                 DPAA2_PMD_DP_DEBUG("VDQ command is not issued."
 562                                                   " QBMAN is busy (1)\n");
 563                                 /* Portal was busy, try again */
 564                                 continue;
 565                         }
 566                         break;
 567                 }
 568                 q_storage->active_dqs = dq_storage;
 569                 q_storage->active_dpio_id = DPAA2_PER_LCORE_ETHRX_DPIO->index;
 570                 set_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index,
 571                                    dq_storage);
 572         }
 573
 574         dq_storage = q_storage->active_dqs;
 575         rte_prefetch0((void *)(size_t)(dq_storage));
 576         rte_prefetch0((void *)(size_t)(dq_storage + 1));
 577
 578         /* Prepare next pull descriptor. This will give space for the
 579          * prefething done on DQRR entries
 580          */
 581         q_storage->toggle ^= 1;
 582         dq_storage1 = q_storage->dq_storage[q_storage->toggle];
 583         qbman_pull_desc_clear(&pulldesc);
 584         qbman_pull_desc_set_numframes(&pulldesc, pull_size);
 585         qbman_pull_desc_set_fq(&pulldesc, fqid);
 586         qbman_pull_desc_set_storage(&pulldesc, dq_storage1,
 587                 (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1);
 588
 589         /* Check if the previous issued command is completed.
 590          * Also seems like the SWP is shared between the Ethernet Driver
 591          * and the SEC driver.
 592          */
 593         while (!qbman_check_command_complete(dq_storage))
 594                 ;
 595         if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id))
 596                 clear_swp_active_dqs(q_storage->active_dpio_id);
 597
 598         pending = 1;
 599
 600         do {
 601                 /* Loop until the dq_storage is updated with
 602                  * new token by QBMAN
 603                  */
 604                 while (!qbman_check_new_result(dq_storage))
 605                         ;
 606                 rte_prefetch0((void *)((size_t)(dq_storage + 2)));
 607                 /* Check whether Last Pull command is Expired and
 608                  * setting Condition for Loop termination
 609                  */
 610                 if (qbman_result_DQ_is_pull_complete(dq_storage)) {
 611                         pending = 0;
 612                         /* Check for valid frame. */
 613                         status = qbman_result_DQ_flags(dq_storage);
 614                         if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
 615                                 continue;
 616                 }
 617                 fd = qbman_result_DQ_fd(dq_storage);
 618
 619 #ifndef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
 620                 if (dpaa2_svr_family != SVR_LX2160A) {
 621                         const struct qbman_fd *next_fd =
 622                                 qbman_result_DQ_fd(dq_storage + 1);
 623                         /* Prefetch Annotation address for the parse results */
 624                         rte_prefetch0(DPAA2_IOVA_TO_VADDR((DPAA2_GET_FD_ADDR(
 625                                 next_fd) + DPAA2_FD_PTA_SIZE + 16)));
 626                 }
 627 #endif
 628
 629                 if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
 630                         bufs[num_rx] = eth_sg_fd_to_mbuf(fd, eth_data->port_id);
 631                 else
 632                         bufs[num_rx] = eth_fd_to_mbuf(fd, eth_data->port_id);
 633 #if defined(RTE_LIBRTE_IEEE1588)
 634                 priv->rx_timestamp = bufs[num_rx]->timestamp;
 635 #endif
 636
 637                 if (eth_data->dev_conf.rxmode.offloads &
 638                                 DEV_RX_OFFLOAD_VLAN_STRIP)
 639                         rte_vlan_strip(bufs[num_rx]);
 640
 641                 dq_storage++;
 642                 num_rx++;
 643         } while (pending);
 644
 645         if (check_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)) {
 646                 while (!qbman_check_command_complete(
 647                        get_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)))
 648                         ;
 649                 clear_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index);
 650         }
 651         /* issue a volatile dequeue command for next pull */
 652         while (1) {
 653                 if (qbman_swp_pull(swp, &pulldesc)) {
 654                         DPAA2_PMD_DP_DEBUG("VDQ command is not issued."
 655                                           "QBMAN is busy (2)\n");
 656                         continue;
 657                 }
 658                 break;
 659         }
 660         q_storage->active_dqs = dq_storage1;
 661         q_storage->active_dpio_id = DPAA2_PER_LCORE_ETHRX_DPIO->index;
 662         set_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index, dq_storage1);
 663
 664         dpaa2_q->rx_pkts += num_rx;
 665
 666         return num_rx;
 667 }
 668
 669 void __rte_hot
 670 dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 671                                  const struct qbman_fd *fd,
 672                                  const struct qbman_result *dq,
 673                                  struct dpaa2_queue *rxq,
 674                                  struct rte_event *ev)
 675 {
 676         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
 677                 DPAA2_FD_PTA_SIZE + 16));
 678
 679         ev->flow_id = rxq->ev.flow_id;
 680         ev->sub_event_type = rxq->ev.sub_event_type;
 681         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 682         ev->op = RTE_EVENT_OP_NEW;
 683         ev->sched_type = rxq->ev.sched_type;
 684         ev->queue_id = rxq->ev.queue_id;
 685         ev->priority = rxq->ev.priority;
 686
 687         ev->mbuf = eth_fd_to_mbuf(fd, rxq->eth_data->port_id);
 688
 689         qbman_swp_dqrr_consume(swp, dq);
 690 }
 691
 692 void __rte_hot
 693 dpaa2_dev_process_atomic_event(struct qbman_swp *swp __rte_unused,
 694                                const struct qbman_fd *fd,
 695                                const struct qbman_result *dq,
 696                                struct dpaa2_queue *rxq,
 697                                struct rte_event *ev)
 698 {
 699         uint8_t dqrr_index;
 700
 701         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
 702                 DPAA2_FD_PTA_SIZE + 16));
 703
 704         ev->flow_id = rxq->ev.flow_id;
 705         ev->sub_event_type = rxq->ev.sub_event_type;
 706         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 707         ev->op = RTE_EVENT_OP_NEW;
 708         ev->sched_type = rxq->ev.sched_type;
 709         ev->queue_id = rxq->ev.queue_id;
 710         ev->priority = rxq->ev.priority;
 711
 712         ev->mbuf = eth_fd_to_mbuf(fd, rxq->eth_data->port_id);
 713
 714         dqrr_index = qbman_get_dqrr_idx(dq);
 715         ev->mbuf->seqn = dqrr_index + 1;
 716         DPAA2_PER_LCORE_DQRR_SIZE++;
 717         DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
 718         DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
 719 }
 720
 721 void __rte_hot
 722 dpaa2_dev_process_ordered_event(struct qbman_swp *swp,
 723                                 const struct qbman_fd *fd,
 724                                 const struct qbman_result *dq,
 725                                 struct dpaa2_queue *rxq,
 726                                 struct rte_event *ev)
 727 {
 728         rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) +
 729                 DPAA2_FD_PTA_SIZE + 16));
 730
 731         ev->flow_id = rxq->ev.flow_id;
 732         ev->sub_event_type = rxq->ev.sub_event_type;
 733         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 734         ev->op = RTE_EVENT_OP_NEW;
 735         ev->sched_type = rxq->ev.sched_type;
 736         ev->queue_id = rxq->ev.queue_id;
 737         ev->priority = rxq->ev.priority;
 738
 739         ev->mbuf = eth_fd_to_mbuf(fd, rxq->eth_data->port_id);
 740
 741         ev->mbuf->seqn = DPAA2_ENQUEUE_FLAG_ORP;
 742         ev->mbuf->seqn |= qbman_result_DQ_odpid(dq) << DPAA2_EQCR_OPRID_SHIFT;
 743         ev->mbuf->seqn |= qbman_result_DQ_seqnum(dq) << DPAA2_EQCR_SEQNUM_SHIFT;
 744
 745         qbman_swp_dqrr_consume(swp, dq);
 746 }
 747
 748 uint16_t
 749 dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 750 {
 751         /* Function receive frames for a given device and VQ */
 752         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 753         struct qbman_result *dq_storage;
 754         uint32_t fqid = dpaa2_q->fqid;
 755         int ret, num_rx = 0, next_pull = nb_pkts, num_pulled;
 756         uint8_t pending, status;
 757         struct qbman_swp *swp;
 758         const struct qbman_fd *fd;
 759         struct qbman_pull_desc pulldesc;
 760         struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
 761
 762         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 763                 ret = dpaa2_affine_qbman_swp();
 764                 if (ret) {
 765                         DPAA2_PMD_ERR("Failure in affining portal\n");
 766                         return 0;
 767                 }
 768         }
 769         swp = DPAA2_PER_LCORE_PORTAL;
 770
 771         do {
 772                 dq_storage = dpaa2_q->q_storage->dq_storage[0];
 773                 qbman_pull_desc_clear(&pulldesc);
 774                 qbman_pull_desc_set_fq(&pulldesc, fqid);
 775                 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 776                                 (size_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
 777
 778                 if (next_pull > dpaa2_dqrr_size) {
 779                         qbman_pull_desc_set_numframes(&pulldesc,
 780                                 dpaa2_dqrr_size);
 781                         next_pull -= dpaa2_dqrr_size;
 782                 } else {
 783                         qbman_pull_desc_set_numframes(&pulldesc, next_pull);
 784                         next_pull = 0;
 785                 }
 786
 787                 while (1) {
 788                         if (qbman_swp_pull(swp, &pulldesc)) {
 789                                 DPAA2_PMD_DP_DEBUG(
 790                                         "VDQ command is not issued.QBMAN is busy\n");
 791                                 /* Portal was busy, try again */
 792                                 continue;
 793                         }
 794                         break;
 795                 }
 796
 797                 rte_prefetch0((void *)((size_t)(dq_storage + 1)));
 798                 /* Check if the previous issued command is completed. */
 799                 while (!qbman_check_command_complete(dq_storage))
 800                         ;
 801
 802                 num_pulled = 0;
 803                 pending = 1;
 804                 do {
 805                         /* Loop until the dq_storage is updated with
 806                          * new token by QBMAN
 807                          */
 808                         while (!qbman_check_new_result(dq_storage))
 809                                 ;
 810                         rte_prefetch0((void *)((size_t)(dq_storage + 2)));
 811                         /* Check whether Last Pull command is Expired and
 812                          * setting Condition for Loop termination
 813                          */
 814                         if (qbman_result_DQ_is_pull_complete(dq_storage)) {
 815                                 pending = 0;
 816                                 /* Check for valid frame. */
 817                                 status = qbman_result_DQ_flags(dq_storage);
 818                                 if (unlikely((status &
 819                                         QBMAN_DQ_STAT_VALIDFRAME) == 0))
 820                                         continue;
 821                         }
 822                         fd = qbman_result_DQ_fd(dq_storage);
 823
 824 #ifndef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
 825                         if (dpaa2_svr_family != SVR_LX2160A) {
 826                                 const struct qbman_fd *next_fd =
 827                                         qbman_result_DQ_fd(dq_storage + 1);
 828
 829                                 /* Prefetch Annotation address for the parse
 830                                  * results.
 831                                  */
 832                                 rte_prefetch0((DPAA2_IOVA_TO_VADDR(
 833                                         DPAA2_GET_FD_ADDR(next_fd) +
 834                                         DPAA2_FD_PTA_SIZE + 16)));
 835                         }
 836 #endif
 837
 838                         if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
 839                                 bufs[num_rx] = eth_sg_fd_to_mbuf(fd,
 840                                                         eth_data->port_id);
 841                         else
 842                                 bufs[num_rx] = eth_fd_to_mbuf(fd,
 843                                                         eth_data->port_id);
 844
 845                 if (eth_data->dev_conf.rxmode.offloads &
 846                                 DEV_RX_OFFLOAD_VLAN_STRIP) {
 847                         rte_vlan_strip(bufs[num_rx]);
 848                 }
 849
 850                         dq_storage++;
 851                         num_rx++;
 852                         num_pulled++;
 853                 } while (pending);
 854         /* Last VDQ provided all packets and more packets are requested */
 855         } while (next_pull && num_pulled == dpaa2_dqrr_size);
 856
 857         dpaa2_q->rx_pkts += num_rx;
 858
 859         return num_rx;
 860 }
 861
 862 uint16_t dpaa2_dev_tx_conf(void *queue)
 863 {
 864         /* Function receive frames for a given device and VQ */
 865         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 866         struct qbman_result *dq_storage;
 867         uint32_t fqid = dpaa2_q->fqid;
 868         int ret, num_tx_conf = 0, num_pulled;
 869         uint8_t pending, status;
 870         struct qbman_swp *swp;
 871         const struct qbman_fd *fd, *next_fd;
 872         struct qbman_pull_desc pulldesc;
 873         struct qbman_release_desc releasedesc;
 874         uint32_t bpid;
 875         uint64_t buf;
 876 #if defined(RTE_LIBRTE_IEEE1588)
 877         struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
 878         struct dpaa2_dev_priv *priv = eth_data->dev_private;
 879         struct dpaa2_annot_hdr *annotation;
 880 #endif
 881
 882         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 883                 ret = dpaa2_affine_qbman_swp();
 884                 if (ret) {
 885                         DPAA2_PMD_ERR("Failure in affining portal\n");
 886                         return 0;
 887                 }
 888         }
 889         swp = DPAA2_PER_LCORE_PORTAL;
 890
 891         do {
 892                 dq_storage = dpaa2_q->q_storage->dq_storage[0];
 893                 qbman_pull_desc_clear(&pulldesc);
 894                 qbman_pull_desc_set_fq(&pulldesc, fqid);
 895                 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 896                                 (size_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
 897
 898                 qbman_pull_desc_set_numframes(&pulldesc, dpaa2_dqrr_size);
 899
 900                 while (1) {
 901                         if (qbman_swp_pull(swp, &pulldesc)) {
 902                                 DPAA2_PMD_DP_DEBUG("VDQ command is not issued."
 903                                                    "QBMAN is busy\n");
 904                                 /* Portal was busy, try again */
 905                                 continue;
 906                         }
 907                         break;
 908                 }
 909
 910                 rte_prefetch0((void *)((size_t)(dq_storage + 1)));
 911                 /* Check if the previous issued command is completed. */
 912                 while (!qbman_check_command_complete(dq_storage))
 913                         ;
 914
 915                 num_pulled = 0;
 916                 pending = 1;
 917                 do {
 918                         /* Loop until the dq_storage is updated with
 919                          * new token by QBMAN
 920                          */
 921                         while (!qbman_check_new_result(dq_storage))
 922                                 ;
 923                         rte_prefetch0((void *)((size_t)(dq_storage + 2)));
 924                         /* Check whether Last Pull command is Expired and
 925                          * setting Condition for Loop termination
 926                          */
 927                         if (qbman_result_DQ_is_pull_complete(dq_storage)) {
 928                                 pending = 0;
 929                                 /* Check for valid frame. */
 930                                 status = qbman_result_DQ_flags(dq_storage);
 931                                 if (unlikely((status &
 932                                         QBMAN_DQ_STAT_VALIDFRAME) == 0))
 933                                         continue;
 934                         }
 935                         fd = qbman_result_DQ_fd(dq_storage);
 936
 937                         next_fd = qbman_result_DQ_fd(dq_storage + 1);
 938                         /* Prefetch Annotation address for the parse results */
 939                         rte_prefetch0((void *)(size_t)
 940                                 (DPAA2_GET_FD_ADDR(next_fd) +
 941                                  DPAA2_FD_PTA_SIZE + 16));
 942
 943                         bpid = DPAA2_GET_FD_BPID(fd);
 944
 945                         /* Create a release descriptor required for releasing
 946                          * buffers into QBMAN
 947                          */
 948                         qbman_release_desc_clear(&releasedesc);
 949                         qbman_release_desc_set_bpid(&releasedesc, bpid);
 950
 951                         buf = DPAA2_GET_FD_ADDR(fd);
 952                         /* feed them to bman */
 953                         do {
 954                                 ret = qbman_swp_release(swp, &releasedesc,
 955                                                         &buf, 1);
 956                         } while (ret == -EBUSY);
 957
 958                         dq_storage++;
 959                         num_tx_conf++;
 960                         num_pulled++;
 961 #if defined(RTE_LIBRTE_IEEE1588)
 962                         annotation = (struct dpaa2_annot_hdr *)((size_t)
 963                                 DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) +
 964                                 DPAA2_FD_PTA_SIZE);
 965                         priv->tx_timestamp = annotation->word2;
 966 #endif
 967                 } while (pending);
 968
 969         /* Last VDQ provided all packets and more packets are requested */
 970         } while (num_pulled == dpaa2_dqrr_size);
 971
 972         dpaa2_q->rx_pkts += num_tx_conf;
 973
 974         return num_tx_conf;
 975 }
 976
 977 /* Configure the egress frame annotation for timestamp update */
 978 static void enable_tx_tstamp(struct qbman_fd *fd)
 979 {
 980         struct dpaa2_faead *fd_faead;
 981
 982         /* Set frame annotation status field as valid */
 983         (fd)->simple.frc |= DPAA2_FD_FRC_FASV;
 984
 985         /* Set frame annotation egress action descriptor as valid */
 986         (fd)->simple.frc |= DPAA2_FD_FRC_FAEADV;
 987
 988         /* Set Annotation Length as 128B */
 989         (fd)->simple.ctrl |= DPAA2_FD_CTRL_ASAL;
 990
 991         /* enable update of confirmation frame annotation */
 992         fd_faead = (struct dpaa2_faead *)((size_t)
 993                         DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) +
 994                         DPAA2_FD_PTA_SIZE + DPAA2_FD_HW_ANNOT_FAEAD_OFFSET);
 995         fd_faead->ctrl = DPAA2_ANNOT_FAEAD_A2V | DPAA2_ANNOT_FAEAD_UPDV |
 996                                 DPAA2_ANNOT_FAEAD_UPD;
 997 }
 998
 999 /*
1000  * Callback to handle sending packets through WRIOP based interface
1001  */
1002 uint16_t
1003 dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
1004 {
1005         /* Function to transmit the frames to given device and VQ*/
1006         uint32_t loop, retry_count;
1007         int32_t ret;
1008         struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
1009         struct rte_mbuf *mi;
1010         uint32_t frames_to_send;
1011         struct rte_mempool *mp;
1012         struct qbman_eq_desc eqdesc;
1013         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
1014         struct qbman_swp *swp;
1015         uint16_t num_tx = 0;
1016         uint16_t bpid;
1017         struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
1018         struct dpaa2_dev_priv *priv = eth_data->dev_private;
1019         uint32_t flags[MAX_TX_RING_SLOTS] = {0};
1020
1021         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1022                 ret = dpaa2_affine_qbman_swp();
1023                 if (ret) {
1024                         DPAA2_PMD_ERR("Failure in affining portal");
1025                         return 0;
1026                 }
1027         }
1028         swp = DPAA2_PER_LCORE_PORTAL;
1029
1030         DPAA2_PMD_DP_DEBUG("===> eth_data =%p, fqid =%d\n",
1031                         eth_data, dpaa2_q->fqid);
1032
1033 #ifdef RTE_LIBRTE_IEEE1588
1034         /* IEEE1588 driver need pointer to tx confirmation queue
1035          * corresponding to last packet transmitted for reading
1036          * the timestamp
1037          */
1038         priv->next_tx_conf_queue = dpaa2_q->tx_conf_queue;
1039         dpaa2_dev_tx_conf(dpaa2_q->tx_conf_queue);
1040 #endif
1041
1042         /*Prepare enqueue descriptor*/
1043         qbman_eq_desc_clear(&eqdesc);
1044         qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
1045         qbman_eq_desc_set_fq(&eqdesc, dpaa2_q->fqid);
1046
1047         /*Clear the unused FD fields before sending*/
1048         while (nb_pkts) {
1049                 /*Check if the queue is congested*/
1050                 retry_count = 0;
1051                 while (qbman_result_SCN_state(dpaa2_q->cscn)) {
1052                         retry_count++;
1053                         /* Retry for some time before giving up */
1054                         if (retry_count > CONG_RETRY_COUNT)
1055                                 goto skip_tx;
1056                 }
1057
1058                 frames_to_send = (nb_pkts > dpaa2_eqcr_size) ?
1059                         dpaa2_eqcr_size : nb_pkts;
1060
1061                 for (loop = 0; loop < frames_to_send; loop++) {
1062                         if ((*bufs)->seqn) {
1063                                 uint8_t dqrr_index = (*bufs)->seqn - 1;
1064
1065                                 flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
1066                                                 dqrr_index;
1067                                 DPAA2_PER_LCORE_DQRR_SIZE--;
1068                                 DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
1069                                 (*bufs)->seqn = DPAA2_INVALID_MBUF_SEQN;
1070                         }
1071
1072                         if (likely(RTE_MBUF_DIRECT(*bufs))) {
1073                                 mp = (*bufs)->pool;
1074                                 /* Check the basic scenario and set
1075                                  * the FD appropriately here itself.
1076                                  */
1077                                 if (likely(mp && mp->ops_index ==
1078                                     priv->bp_list->dpaa2_ops_index &&
1079                                     (*bufs)->nb_segs == 1 &&
1080                                     rte_mbuf_refcnt_read((*bufs)) == 1)) {
1081                                         if (unlikely(((*bufs)->ol_flags
1082                                                 & PKT_TX_VLAN_PKT) ||
1083                                                 (eth_data->dev_conf.txmode.offloads
1084                                                 & DEV_TX_OFFLOAD_VLAN_INSERT))) {
1085                                                 ret = rte_vlan_insert(bufs);
1086                                                 if (ret)
1087                                                         goto send_n_return;
1088                                         }
1089                                         DPAA2_MBUF_TO_CONTIG_FD((*bufs),
1090                                         &fd_arr[loop], mempool_to_bpid(mp));
1091                                         bufs++;
1092 #ifdef RTE_LIBRTE_IEEE1588
1093                                         enable_tx_tstamp(&fd_arr[loop]);
1094 #endif
1095                                         continue;
1096                                 }
1097                         } else {
1098                                 mi = rte_mbuf_from_indirect(*bufs);
1099                                 mp = mi->pool;
1100                         }
1101                         /* Not a hw_pkt pool allocated frame */
1102                         if (unlikely(!mp || !priv->bp_list)) {
1103                                 DPAA2_PMD_ERR("Err: No buffer pool attached");
1104                                 goto send_n_return;
1105                         }
1106
1107                         if (unlikely(((*bufs)->ol_flags & PKT_TX_VLAN_PKT) ||
1108                                 (eth_data->dev_conf.txmode.offloads
1109                                 & DEV_TX_OFFLOAD_VLAN_INSERT))) {
1110                                 int ret = rte_vlan_insert(bufs);
1111                                 if (ret)
1112                                         goto send_n_return;
1113                         }
1114                         if (mp->ops_index != priv->bp_list->dpaa2_ops_index) {
1115                                 DPAA2_PMD_WARN("Non DPAA2 buffer pool");
1116                                 /* alloc should be from the default buffer pool
1117                                  * attached to this interface
1118                                  */
1119                                 bpid = priv->bp_list->buf_pool.bpid;
1120
1121                                 if (unlikely((*bufs)->nb_segs > 1)) {
1122                                         DPAA2_PMD_ERR("S/G support not added"
1123                                                 " for non hw offload buffer");
1124                                         goto send_n_return;
1125                                 }
1126                                 if (eth_copy_mbuf_to_fd(*bufs,
1127                                                         &fd_arr[loop], bpid)) {
1128                                         goto send_n_return;
1129                                 }
1130                                 /* free the original packet */
1131                                 rte_pktmbuf_free(*bufs);
1132                         } else {
1133                                 bpid = mempool_to_bpid(mp);
1134                                 if (unlikely((*bufs)->nb_segs > 1)) {
1135                                         if (eth_mbuf_to_sg_fd(*bufs,
1136                                                         &fd_arr[loop], bpid))
1137                                                 goto send_n_return;
1138                                 } else {
1139                                         eth_mbuf_to_fd(*bufs,
1140                                                        &fd_arr[loop], bpid);
1141                                 }
1142                         }
1143 #ifdef RTE_LIBRTE_IEEE1588
1144                         enable_tx_tstamp(&fd_arr[loop]);
1145 #endif
1146                         bufs++;
1147                 }
1148
1149                 loop = 0;
1150                 retry_count = 0;
1151                 while (loop < frames_to_send) {
1152                         ret = qbman_swp_enqueue_multiple(swp, &eqdesc,
1153                                         &fd_arr[loop], &flags[loop],
1154                                         frames_to_send - loop);
1155                         if (unlikely(ret < 0)) {
1156                                 retry_count++;
1157                                 if (retry_count > DPAA2_MAX_TX_RETRY_COUNT) {
1158                                         num_tx += loop;
1159                                         nb_pkts -= loop;
1160                                         goto send_n_return;
1161                                 }
1162                         } else {
1163                                 loop += ret;
1164                                 retry_count = 0;
1165                         }
1166                 }
1167
1168                 num_tx += loop;
1169                 nb_pkts -= loop;
1170         }
1171         dpaa2_q->tx_pkts += num_tx;
1172         return num_tx;
1173
1174 send_n_return:
1175         /* send any already prepared fd */
1176         if (loop) {
1177                 unsigned int i = 0;
1178
1179                 retry_count = 0;
1180                 while (i < loop) {
1181                         ret = qbman_swp_enqueue_multiple(swp, &eqdesc,
1182                                                          &fd_arr[i],
1183                                                          &flags[i],
1184                                                          loop - i);
1185                         if (unlikely(ret < 0)) {
1186                                 retry_count++;
1187                                 if (retry_count > DPAA2_MAX_TX_RETRY_COUNT)
1188                                         break;
1189                         } else {
1190                                 i += ret;
1191                                 retry_count = 0;
1192                         }
1193                 }
1194                 num_tx += i;
1195         }
1196 skip_tx:
1197         dpaa2_q->tx_pkts += num_tx;
1198         return num_tx;
1199 }
1200
1201 void
1202 dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci)
1203 {
1204         struct dpaa2_dpio_dev *dpio_dev = DPAA2_PER_LCORE_DPIO;
1205         struct qbman_fd *fd;
1206         struct rte_mbuf *m;
1207
1208         fd = qbman_result_eqresp_fd(&dpio_dev->eqresp[eqresp_ci]);
1209
1210         /* Setting port id does not matter as we are to free the mbuf */
1211         m = eth_fd_to_mbuf(fd, 0);
1212         rte_pktmbuf_free(m);
1213 }
1214
1215 static void
1216 dpaa2_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,
1217                              struct rte_mbuf *m,
1218                              struct qbman_eq_desc *eqdesc)
1219 {
1220         struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
1221         struct dpaa2_dev_priv *priv = eth_data->dev_private;
1222         struct dpaa2_dpio_dev *dpio_dev = DPAA2_PER_LCORE_DPIO;
1223         struct eqresp_metadata *eqresp_meta;
1224         uint16_t orpid, seqnum;
1225         uint8_t dq_idx;
1226
1227         qbman_eq_desc_set_fq(eqdesc, dpaa2_q->fqid);
1228
1229         if (m->seqn & DPAA2_ENQUEUE_FLAG_ORP) {
1230                 orpid = (m->seqn & DPAA2_EQCR_OPRID_MASK) >>
1231                         DPAA2_EQCR_OPRID_SHIFT;
1232                 seqnum = (m->seqn & DPAA2_EQCR_SEQNUM_MASK) >>
1233                         DPAA2_EQCR_SEQNUM_SHIFT;
1234
1235                 if (!priv->en_loose_ordered) {
1236                         qbman_eq_desc_set_orp(eqdesc, 1, orpid, seqnum, 0);
1237                         qbman_eq_desc_set_response(eqdesc, (uint64_t)
1238                                 DPAA2_VADDR_TO_IOVA(&dpio_dev->eqresp[
1239                                 dpio_dev->eqresp_pi]), 1);
1240                         qbman_eq_desc_set_token(eqdesc, 1);
1241
1242                         eqresp_meta = &dpio_dev->eqresp_meta[
1243                                 dpio_dev->eqresp_pi];
1244                         eqresp_meta->dpaa2_q = dpaa2_q;
1245                         eqresp_meta->mp = m->pool;
1246
1247                         dpio_dev->eqresp_pi + 1 < MAX_EQ_RESP_ENTRIES ?
1248                                 dpio_dev->eqresp_pi++ :
1249                                 (dpio_dev->eqresp_pi = 0);
1250                 } else {
1251                         qbman_eq_desc_set_orp(eqdesc, 0, orpid, seqnum, 0);
1252                 }
1253         } else {
1254                 dq_idx = m->seqn - 1;
1255                 qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
1256                 DPAA2_PER_LCORE_DQRR_SIZE--;
1257                 DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx);
1258         }
1259         m->seqn = DPAA2_INVALID_MBUF_SEQN;
1260 }
1261
1262 /* Callback to handle sending ordered packets through WRIOP based interface */
1263 uint16_t
1264 dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
1265 {
1266         /* Function to transmit the frames to given device and VQ*/
1267         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
1268         struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
1269         struct dpaa2_dev_priv *priv = eth_data->dev_private;
1270         struct dpaa2_queue *order_sendq = (struct dpaa2_queue *)priv->tx_vq[0];
1271         struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
1272         struct rte_mbuf *mi;
1273         struct rte_mempool *mp;
1274         struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
1275         struct qbman_swp *swp;
1276         uint32_t frames_to_send, num_free_eq_desc;
1277         uint32_t loop, retry_count;
1278         int32_t ret;
1279         uint16_t num_tx = 0;
1280         uint16_t bpid;
1281
1282         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1283                 ret = dpaa2_affine_qbman_swp();
1284                 if (ret) {
1285                         DPAA2_PMD_ERR("Failure in affining portal");
1286                         return 0;
1287                 }
1288         }
1289         swp = DPAA2_PER_LCORE_PORTAL;
1290
1291         DPAA2_PMD_DP_DEBUG("===> eth_data =%p, fqid =%d\n",
1292                            eth_data, dpaa2_q->fqid);
1293
1294         /* This would also handle normal and atomic queues as any type
1295          * of packet can be enqueued when ordered queues are being used.
1296          */
1297         while (nb_pkts) {
1298                 /*Check if the queue is congested*/
1299                 retry_count = 0;
1300                 while (qbman_result_SCN_state(dpaa2_q->cscn)) {
1301                         retry_count++;
1302                         /* Retry for some time before giving up */
1303                         if (retry_count > CONG_RETRY_COUNT)
1304                                 goto skip_tx;
1305                 }
1306
1307                 frames_to_send = (nb_pkts > dpaa2_eqcr_size) ?
1308                         dpaa2_eqcr_size : nb_pkts;
1309
1310                 if (!priv->en_loose_ordered) {
1311                         if ((*bufs)->seqn & DPAA2_ENQUEUE_FLAG_ORP) {
1312                                 num_free_eq_desc = dpaa2_free_eq_descriptors();
1313                                 if (num_free_eq_desc < frames_to_send)
1314                                         frames_to_send = num_free_eq_desc;
1315                         }
1316                 }
1317
1318                 for (loop = 0; loop < frames_to_send; loop++) {
1319                         /*Prepare enqueue descriptor*/
1320                         qbman_eq_desc_clear(&eqdesc[loop]);
1321
1322                         if ((*bufs)->seqn) {
1323                                 /* Use only queue 0 for Tx in case of atomic/
1324                                  * ordered packets as packets can get unordered
1325                                  * when being tranmitted out from the interface
1326                                  */
1327                                 dpaa2_set_enqueue_descriptor(order_sendq,
1328                                                              (*bufs),
1329                                                              &eqdesc[loop]);
1330                         } else {
1331                                 qbman_eq_desc_set_no_orp(&eqdesc[loop],
1332                                                          DPAA2_EQ_RESP_ERR_FQ);
1333                                 qbman_eq_desc_set_fq(&eqdesc[loop],
1334                                                      dpaa2_q->fqid);
1335                         }
1336
1337                         if (likely(RTE_MBUF_DIRECT(*bufs))) {
1338                                 mp = (*bufs)->pool;
1339                                 /* Check the basic scenario and set
1340                                  * the FD appropriately here itself.
1341                                  */
1342                                 if (likely(mp && mp->ops_index ==
1343                                     priv->bp_list->dpaa2_ops_index &&
1344                                     (*bufs)->nb_segs == 1 &&
1345                                     rte_mbuf_refcnt_read((*bufs)) == 1)) {
1346                                         if (unlikely((*bufs)->ol_flags
1347                                                 & PKT_TX_VLAN_PKT)) {
1348                                           ret = rte_vlan_insert(bufs);
1349                                           if (ret)
1350                                                 goto send_n_return;
1351                                         }
1352                                         DPAA2_MBUF_TO_CONTIG_FD((*bufs),
1353                                                 &fd_arr[loop],
1354                                                 mempool_to_bpid(mp));
1355                                         bufs++;
1356                                         continue;
1357                                 }
1358                         } else {
1359                                 mi = rte_mbuf_from_indirect(*bufs);
1360                                 mp = mi->pool;
1361                         }
1362                         /* Not a hw_pkt pool allocated frame */
1363                         if (unlikely(!mp || !priv->bp_list)) {
1364                                 DPAA2_PMD_ERR("Err: No buffer pool attached");
1365                                 goto send_n_return;
1366                         }
1367
1368                         if (mp->ops_index != priv->bp_list->dpaa2_ops_index) {
1369                                 DPAA2_PMD_WARN("Non DPAA2 buffer pool");
1370                                 /* alloc should be from the default buffer pool
1371                                  * attached to this interface
1372                                  */
1373                                 bpid = priv->bp_list->buf_pool.bpid;
1374
1375                                 if (unlikely((*bufs)->nb_segs > 1)) {
1376                                         DPAA2_PMD_ERR(
1377                                                 "S/G not supp for non hw offload buffer");
1378                                         goto send_n_return;
1379                                 }
1380                                 if (eth_copy_mbuf_to_fd(*bufs,
1381                                                         &fd_arr[loop], bpid)) {
1382                                         goto send_n_return;
1383                                 }
1384                                 /* free the original packet */
1385                                 rte_pktmbuf_free(*bufs);
1386                         } else {
1387                                 bpid = mempool_to_bpid(mp);
1388                                 if (unlikely((*bufs)->nb_segs > 1)) {
1389                                         if (eth_mbuf_to_sg_fd(*bufs,
1390                                                               &fd_arr[loop],
1391                                                               bpid))
1392                                                 goto send_n_return;
1393                                 } else {
1394                                         eth_mbuf_to_fd(*bufs,
1395                                                        &fd_arr[loop], bpid);
1396                                 }
1397                         }
1398                         bufs++;
1399                 }
1400
1401                 loop = 0;
1402                 retry_count = 0;
1403                 while (loop < frames_to_send) {
1404                         ret = qbman_swp_enqueue_multiple_desc(swp,
1405                                         &eqdesc[loop], &fd_arr[loop],
1406                                         frames_to_send - loop);
1407                         if (unlikely(ret < 0)) {
1408                                 retry_count++;
1409                                 if (retry_count > DPAA2_MAX_TX_RETRY_COUNT) {
1410                                         num_tx += loop;
1411                                         nb_pkts -= loop;
1412                                         goto send_n_return;
1413                                 }
1414                         } else {
1415                                 loop += ret;
1416                                 retry_count = 0;
1417                         }
1418                 }
1419
1420                 num_tx += loop;
1421                 nb_pkts -= loop;
1422         }
1423         dpaa2_q->tx_pkts += num_tx;
1424         return num_tx;
1425
1426 send_n_return:
1427         /* send any already prepared fd */
1428         if (loop) {
1429                 unsigned int i = 0;
1430
1431                 retry_count = 0;
1432                 while (i < loop) {
1433                         ret = qbman_swp_enqueue_multiple_desc(swp,
1434                                        &eqdesc[loop], &fd_arr[i], loop - i);
1435                         if (unlikely(ret < 0)) {
1436                                 retry_count++;
1437                                 if (retry_count > DPAA2_MAX_TX_RETRY_COUNT)
1438                                         break;
1439                         } else {
1440                                 i += ret;
1441                                 retry_count = 0;
1442                         }
1443                 }
1444                 num_tx += i;
1445         }
1446 skip_tx:
1447         dpaa2_q->tx_pkts += num_tx;
1448         return num_tx;
1449 }
1450
1451 /**
1452  * Dummy DPDK callback for TX.
1453  *
1454  * This function is used to temporarily replace the real callback during
1455  * unsafe control operations on the queue, or in case of error.
1456  *
1457  * @param dpdk_txq
1458  *   Generic pointer to TX queue structure.
1459  * @param[in] pkts
1460  *   Packets to transmit.
1461  * @param pkts_n
1462  *   Number of packets in array.
1463  *
1464  * @return
1465  *   Number of packets successfully transmitted (<= pkts_n).
1466  */
1467 uint16_t
1468 dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
1469 {
1470         (void)queue;
1471         (void)bufs;
1472         (void)nb_pkts;
1473         return 0;
1474 }
1475
1476 #if defined(RTE_TOOLCHAIN_GCC)
1477 #pragma GCC diagnostic push
1478 #pragma GCC diagnostic ignored "-Wcast-qual"
1479 #elif defined(RTE_TOOLCHAIN_CLANG)
1480 #pragma clang diagnostic push
1481 #pragma clang diagnostic ignored "-Wcast-qual"
1482 #endif
1483
1484 /* This function loopbacks all the received packets.*/
1485 uint16_t
1486 dpaa2_dev_loopback_rx(void *queue,
1487                       struct rte_mbuf **bufs __rte_unused,
1488                       uint16_t nb_pkts)
1489 {
1490         /* Function receive frames for a given device and VQ*/
1491         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
1492         struct qbman_result *dq_storage, *dq_storage1 = NULL;
1493         uint32_t fqid = dpaa2_q->fqid;
1494         int ret, num_rx = 0, num_tx = 0, pull_size;
1495         uint8_t pending, status;
1496         struct qbman_swp *swp;
1497         struct qbman_fd *fd[DPAA2_LX2_DQRR_RING_SIZE];
1498         struct qbman_pull_desc pulldesc;
1499         struct qbman_eq_desc eqdesc;
1500         struct queue_storage_info_t *q_storage = dpaa2_q->q_storage;
1501         struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
1502         struct dpaa2_dev_priv *priv = eth_data->dev_private;
1503         struct dpaa2_queue *tx_q = priv->tx_vq[0];
1504         /* todo - currently we are using 1st TX queue only for loopback*/
1505
1506         if (unlikely(!DPAA2_PER_LCORE_ETHRX_DPIO)) {
1507                 ret = dpaa2_affine_qbman_ethrx_swp();
1508                 if (ret) {
1509                         DPAA2_PMD_ERR("Failure in affining portal");
1510                         return 0;
1511                 }
1512         }
1513         swp = DPAA2_PER_LCORE_ETHRX_PORTAL;
1514         pull_size = (nb_pkts > dpaa2_dqrr_size) ? dpaa2_dqrr_size : nb_pkts;
1515         if (unlikely(!q_storage->active_dqs)) {
1516                 q_storage->toggle = 0;
1517                 dq_storage = q_storage->dq_storage[q_storage->toggle];
1518                 q_storage->last_num_pkts = pull_size;
1519                 qbman_pull_desc_clear(&pulldesc);
1520                 qbman_pull_desc_set_numframes(&pulldesc,
1521                                               q_storage->last_num_pkts);
1522                 qbman_pull_desc_set_fq(&pulldesc, fqid);
1523                 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
1524                         (size_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
1525                 if (check_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)) {
1526                         while (!qbman_check_command_complete(
1527                                get_swp_active_dqs(
1528                                DPAA2_PER_LCORE_ETHRX_DPIO->index)))
1529                                 ;
1530                         clear_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index);
1531                 }
1532                 while (1) {
1533                         if (qbman_swp_pull(swp, &pulldesc)) {
1534                                 DPAA2_PMD_DP_DEBUG(
1535                                         "VDQ command not issued.QBMAN busy\n");
1536                                 /* Portal was busy, try again */
1537                                 continue;
1538                         }
1539                         break;
1540                 }
1541                 q_storage->active_dqs = dq_storage;
1542                 q_storage->active_dpio_id = DPAA2_PER_LCORE_ETHRX_DPIO->index;
1543                 set_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index,
1544                                    dq_storage);
1545         }
1546
1547         dq_storage = q_storage->active_dqs;
1548         rte_prefetch0((void *)(size_t)(dq_storage));
1549         rte_prefetch0((void *)(size_t)(dq_storage + 1));
1550
1551         /* Prepare next pull descriptor. This will give space for the
1552          * prefething done on DQRR entries
1553          */
1554         q_storage->toggle ^= 1;
1555         dq_storage1 = q_storage->dq_storage[q_storage->toggle];
1556         qbman_pull_desc_clear(&pulldesc);
1557         qbman_pull_desc_set_numframes(&pulldesc, pull_size);
1558         qbman_pull_desc_set_fq(&pulldesc, fqid);
1559         qbman_pull_desc_set_storage(&pulldesc, dq_storage1,
1560                 (size_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1);
1561
1562         /*Prepare enqueue descriptor*/
1563         qbman_eq_desc_clear(&eqdesc);
1564         qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
1565         qbman_eq_desc_set_response(&eqdesc, 0, 0);
1566         qbman_eq_desc_set_fq(&eqdesc, tx_q->fqid);
1567
1568         /* Check if the previous issued command is completed.
1569          * Also seems like the SWP is shared between the Ethernet Driver
1570          * and the SEC driver.
1571          */
1572         while (!qbman_check_command_complete(dq_storage))
1573                 ;
1574         if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id))
1575                 clear_swp_active_dqs(q_storage->active_dpio_id);
1576
1577         pending = 1;
1578
1579         do {
1580                 /* Loop until the dq_storage is updated with
1581                  * new token by QBMAN
1582                  */
1583                 while (!qbman_check_new_result(dq_storage))
1584                         ;
1585                 rte_prefetch0((void *)((size_t)(dq_storage + 2)));
1586                 /* Check whether Last Pull command is Expired and
1587                  * setting Condition for Loop termination
1588                  */
1589                 if (qbman_result_DQ_is_pull_complete(dq_storage)) {
1590                         pending = 0;
1591                         /* Check for valid frame. */
1592                         status = qbman_result_DQ_flags(dq_storage);
1593                         if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
1594                                 continue;
1595                 }
1596                 fd[num_rx] = (struct qbman_fd *)qbman_result_DQ_fd(dq_storage);
1597
1598                 dq_storage++;
1599                 num_rx++;
1600         } while (pending);
1601
1602         while (num_tx < num_rx) {
1603                 num_tx += qbman_swp_enqueue_multiple_fd(swp, &eqdesc,
1604                                 &fd[num_tx], 0, num_rx - num_tx);
1605         }
1606
1607         if (check_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)) {
1608                 while (!qbman_check_command_complete(
1609                        get_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index)))
1610                         ;
1611                 clear_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index);
1612         }
1613         /* issue a volatile dequeue command for next pull */
1614         while (1) {
1615                 if (qbman_swp_pull(swp, &pulldesc)) {
1616                         DPAA2_PMD_DP_DEBUG("VDQ command is not issued."
1617                                           "QBMAN is busy (2)\n");
1618                         continue;
1619                 }
1620                 break;
1621         }
1622         q_storage->active_dqs = dq_storage1;
1623         q_storage->active_dpio_id = DPAA2_PER_LCORE_ETHRX_DPIO->index;
1624         set_swp_active_dqs(DPAA2_PER_LCORE_ETHRX_DPIO->index, dq_storage1);
1625
1626         dpaa2_q->rx_pkts += num_rx;
1627         dpaa2_q->tx_pkts += num_tx;
1628
1629         return 0;
1630 }
1631 #if defined(RTE_TOOLCHAIN_GCC)
1632 #pragma GCC diagnostic pop
1633 #elif defined(RTE_TOOLCHAIN_CLANG)
1634 #pragma clang diagnostic pop
1635 #endif