drivers/net/e1000/base/e1000_82540.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 /*
   6  * 82540EM Gigabit Ethernet Controller
   7  * 82540EP Gigabit Ethernet Controller
   8  * 82545EM Gigabit Ethernet Controller (Copper)
   9  * 82545EM Gigabit Ethernet Controller (Fiber)
  10  * 82545GM Gigabit Ethernet Controller
  11  * 82546EB Gigabit Ethernet Controller (Copper)
  12  * 82546EB Gigabit Ethernet Controller (Fiber)
  13  * 82546GB Gigabit Ethernet Controller
  14  */
  15
  16 #include "e1000_api.h"
  17
  18 STATIC s32  e1000_init_phy_params_82540(struct e1000_hw *hw);
  19 STATIC s32  e1000_init_nvm_params_82540(struct e1000_hw *hw);
  20 STATIC s32  e1000_init_mac_params_82540(struct e1000_hw *hw);
  21 STATIC s32  e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
  22 STATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
  23 STATIC s32  e1000_init_hw_82540(struct e1000_hw *hw);
  24 STATIC s32  e1000_reset_hw_82540(struct e1000_hw *hw);
  25 STATIC s32  e1000_set_phy_mode_82540(struct e1000_hw *hw);
  26 STATIC s32  e1000_set_vco_speed_82540(struct e1000_hw *hw);
  27 STATIC s32  e1000_setup_copper_link_82540(struct e1000_hw *hw);
  28 STATIC s32  e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
  29 STATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
  30 STATIC s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
  31
  32 /**
  33  * e1000_init_phy_params_82540 - Init PHY func ptrs.
  34  * @hw: pointer to the HW structure
  35  **/
  36 STATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
  37 {
  38         struct e1000_phy_info *phy = &hw->phy;
  39         s32 ret_val;
  40
  41         phy->addr               = 1;
  42         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  43         phy->reset_delay_us     = 10000;
  44         phy->type               = e1000_phy_m88;
  45
  46         /* Function Pointers */
  47         phy->ops.check_polarity = e1000_check_polarity_m88;
  48         phy->ops.commit         = e1000_phy_sw_reset_generic;
  49         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
  50         phy->ops.get_cable_length = e1000_get_cable_length_m88;
  51         phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
  52         phy->ops.read_reg       = e1000_read_phy_reg_m88;
  53         phy->ops.reset          = e1000_phy_hw_reset_generic;
  54         phy->ops.write_reg      = e1000_write_phy_reg_m88;
  55         phy->ops.get_info       = e1000_get_phy_info_m88;
  56         phy->ops.power_up       = e1000_power_up_phy_copper;
  57         phy->ops.power_down     = e1000_power_down_phy_copper_82540;
  58
  59         ret_val = e1000_get_phy_id(hw);
  60         if (ret_val)
  61                 goto out;
  62
  63         /* Verify phy id */
  64         switch (hw->mac.type) {
  65         case e1000_82540:
  66         case e1000_82545:
  67         case e1000_82545_rev_3:
  68         case e1000_82546:
  69         case e1000_82546_rev_3:
  70                 if (phy->id == M88E1011_I_PHY_ID)
  71                         break;
  72                 /* Fall Through */
  73         default:
  74                 ret_val = -E1000_ERR_PHY;
  75                 goto out;
  76                 break;
  77         }
  78
  79 out:
  80         return ret_val;
  81 }
  82
  83 /**
  84  * e1000_init_nvm_params_82540 - Init NVM func ptrs.
  85  * @hw: pointer to the HW structure
  86  **/
  87 STATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
  88 {
  89         struct e1000_nvm_info *nvm = &hw->nvm;
  90         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
  91
  92         DEBUGFUNC("e1000_init_nvm_params_82540");
  93
  94         nvm->type = e1000_nvm_eeprom_microwire;
  95         nvm->delay_usec = 50;
  96         nvm->opcode_bits = 3;
  97         switch (nvm->override) {
  98         case e1000_nvm_override_microwire_large:
  99                 nvm->address_bits = 8;
 100                 nvm->word_size = 256;
 101                 break;
 102         case e1000_nvm_override_microwire_small:
 103                 nvm->address_bits = 6;
 104                 nvm->word_size = 64;
 105                 break;
 106         default:
 107                 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
 108                 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
 109                 break;
 110         }
 111
 112         /* Function Pointers */
 113         nvm->ops.acquire        = e1000_acquire_nvm_generic;
 114         nvm->ops.read           = e1000_read_nvm_microwire;
 115         nvm->ops.release        = e1000_release_nvm_generic;
 116         nvm->ops.update         = e1000_update_nvm_checksum_generic;
 117         nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 118         nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 119         nvm->ops.write          = e1000_write_nvm_microwire;
 120
 121         return E1000_SUCCESS;
 122 }
 123
 124 /**
 125  * e1000_init_mac_params_82540 - Init MAC func ptrs.
 126  * @hw: pointer to the HW structure
 127  **/
 128 STATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
 129 {
 130         struct e1000_mac_info *mac = &hw->mac;
 131         s32 ret_val = E1000_SUCCESS;
 132
 133         DEBUGFUNC("e1000_init_mac_params_82540");
 134
 135         /* Set media type */
 136         switch (hw->device_id) {
 137         case E1000_DEV_ID_82545EM_FIBER:
 138         case E1000_DEV_ID_82545GM_FIBER:
 139         case E1000_DEV_ID_82546EB_FIBER:
 140         case E1000_DEV_ID_82546GB_FIBER:
 141                 hw->phy.media_type = e1000_media_type_fiber;
 142                 break;
 143         case E1000_DEV_ID_82545GM_SERDES:
 144         case E1000_DEV_ID_82546GB_SERDES:
 145                 hw->phy.media_type = e1000_media_type_internal_serdes;
 146                 break;
 147         default:
 148                 hw->phy.media_type = e1000_media_type_copper;
 149                 break;
 150         }
 151
 152         /* Set mta register count */
 153         mac->mta_reg_count = 128;
 154         /* Set rar entry count */
 155         mac->rar_entry_count = E1000_RAR_ENTRIES;
 156
 157         /* Function pointers */
 158
 159         /* bus type/speed/width */
 160         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
 161         /* function id */
 162         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
 163         /* reset */
 164         mac->ops.reset_hw = e1000_reset_hw_82540;
 165         /* hw initialization */
 166         mac->ops.init_hw = e1000_init_hw_82540;
 167         /* link setup */
 168         mac->ops.setup_link = e1000_setup_link_generic;
 169         /* physical interface setup */
 170         mac->ops.setup_physical_interface =
 171                 (hw->phy.media_type == e1000_media_type_copper)
 172                         ? e1000_setup_copper_link_82540
 173                         : e1000_setup_fiber_serdes_link_82540;
 174         /* check for link */
 175         switch (hw->phy.media_type) {
 176         case e1000_media_type_copper:
 177                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 178                 break;
 179         case e1000_media_type_fiber:
 180                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 181                 break;
 182         case e1000_media_type_internal_serdes:
 183                 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
 184                 break;
 185         default:
 186                 ret_val = -E1000_ERR_CONFIG;
 187                 goto out;
 188                 break;
 189         }
 190         /* link info */
 191         mac->ops.get_link_up_info =
 192                 (hw->phy.media_type == e1000_media_type_copper)
 193                         ? e1000_get_speed_and_duplex_copper_generic
 194                         : e1000_get_speed_and_duplex_fiber_serdes_generic;
 195         /* multicast address update */
 196         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 197         /* writing VFTA */
 198         mac->ops.write_vfta = e1000_write_vfta_generic;
 199         /* clearing VFTA */
 200         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 201         /* read mac address */
 202         mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
 203         /* ID LED init */
 204         mac->ops.id_led_init = e1000_id_led_init_generic;
 205         /* setup LED */
 206         mac->ops.setup_led = e1000_setup_led_generic;
 207         /* cleanup LED */
 208         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 209         /* turn on/off LED */
 210         mac->ops.led_on = e1000_led_on_generic;
 211         mac->ops.led_off = e1000_led_off_generic;
 212         /* clear hardware counters */
 213         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
 214
 215 out:
 216         return ret_val;
 217 }
 218
 219 /**
 220  * e1000_init_function_pointers_82540 - Init func ptrs.
 221  * @hw: pointer to the HW structure
 222  *
 223  * Called to initialize all function pointers and parameters.
 224  **/
 225 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
 226 {
 227         DEBUGFUNC("e1000_init_function_pointers_82540");
 228
 229         hw->mac.ops.init_params = e1000_init_mac_params_82540;
 230         hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
 231         hw->phy.ops.init_params = e1000_init_phy_params_82540;
 232 }
 233
 234 /**
 235  *  e1000_reset_hw_82540 - Reset hardware
 236  *  @hw: pointer to the HW structure
 237  *
 238  *  This resets the hardware into a known state.
 239  **/
 240 STATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw)
 241 {
 242         u32 ctrl, manc;
 243         s32 ret_val = E1000_SUCCESS;
 244
 245         DEBUGFUNC("e1000_reset_hw_82540");
 246
 247         DEBUGOUT("Masking off all interrupts\n");
 248         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 249
 250         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 251         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 252         E1000_WRITE_FLUSH(hw);
 253
 254         /*
 255          * Delay to allow any outstanding PCI transactions to complete
 256          * before resetting the device.
 257          */
 258         msec_delay(10);
 259
 260         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 261
 262         DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
 263         switch (hw->mac.type) {
 264         case e1000_82545_rev_3:
 265         case e1000_82546_rev_3:
 266                 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
 267                 break;
 268         default:
 269                 /*
 270                  * These controllers can't ack the 64-bit write when
 271                  * issuing the reset, so we use IO-mapping as a
 272                  * workaround to issue the reset.
 273                  */
 274                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 275                 break;
 276         }
 277
 278         /* Wait for EEPROM reload */
 279         msec_delay(5);
 280
 281         /* Disable HW ARPs on ASF enabled adapters */
 282         manc = E1000_READ_REG(hw, E1000_MANC);
 283         manc &= ~E1000_MANC_ARP_EN;
 284         E1000_WRITE_REG(hw, E1000_MANC, manc);
 285
 286         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 287         E1000_READ_REG(hw, E1000_ICR);
 288
 289         return ret_val;
 290 }
 291
 292 /**
 293  *  e1000_init_hw_82540 - Initialize hardware
 294  *  @hw: pointer to the HW structure
 295  *
 296  *  This inits the hardware readying it for operation.
 297  **/
 298 STATIC s32 e1000_init_hw_82540(struct e1000_hw *hw)
 299 {
 300         struct e1000_mac_info *mac = &hw->mac;
 301         u32 txdctl, ctrl_ext;
 302         s32 ret_val;
 303         u16 i;
 304
 305         DEBUGFUNC("e1000_init_hw_82540");
 306
 307         /* Initialize identification LED */
 308         ret_val = mac->ops.id_led_init(hw);
 309         if (ret_val) {
 310                 DEBUGOUT("Error initializing identification LED\n");
 311                 /* This is not fatal and we should not stop init due to this */
 312         }
 313
 314         /* Disabling VLAN filtering */
 315         DEBUGOUT("Initializing the IEEE VLAN\n");
 316         if (mac->type < e1000_82545_rev_3)
 317                 E1000_WRITE_REG(hw, E1000_VET, 0);
 318
 319         mac->ops.clear_vfta(hw);
 320
 321         /* Setup the receive address. */
 322         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 323
 324         /* Zero out the Multicast HASH table */
 325         DEBUGOUT("Zeroing the MTA\n");
 326         for (i = 0; i < mac->mta_reg_count; i++) {
 327                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 328                 /*
 329                  * Avoid back to back register writes by adding the register
 330                  * read (flush).  This is to protect against some strange
 331                  * bridge configurations that may issue Memory Write Block
 332                  * (MWB) to our register space.  The *_rev_3 hardware at
 333                  * least doesn't respond correctly to every other dword in an
 334                  * MWB to our register space.
 335                  */
 336                 E1000_WRITE_FLUSH(hw);
 337         }
 338
 339         if (mac->type < e1000_82545_rev_3)
 340                 e1000_pcix_mmrbc_workaround_generic(hw);
 341
 342         /* Setup link and flow control */
 343         ret_val = mac->ops.setup_link(hw);
 344
 345         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 346         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 347                   E1000_TXDCTL_FULL_TX_DESC_WB;
 348         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 349
 350         /*
 351          * Clear all of the statistics registers (clear on read).  It is
 352          * important that we do this after we have tried to establish link
 353          * because the symbol error count will increment wildly if there
 354          * is no link.
 355          */
 356         e1000_clear_hw_cntrs_82540(hw);
 357
 358         if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
 359             (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
 360                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 361                 /*
 362                  * Relaxed ordering must be disabled to avoid a parity
 363                  * error crash in a PCI slot.
 364                  */
 365                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
 366                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 367         }
 368
 369         return ret_val;
 370 }
 371
 372 /**
 373  *  e1000_setup_copper_link_82540 - Configure copper link settings
 374  *  @hw: pointer to the HW structure
 375  *
 376  *  Calls the appropriate function to configure the link for auto-neg or forced
 377  *  speed and duplex.  Then we check for link, once link is established calls
 378  *  to configure collision distance and flow control are called.  If link is
 379  *  not established, we return -E1000_ERR_PHY (-2).
 380  **/
 381 STATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
 382 {
 383         u32 ctrl;
 384         s32 ret_val;
 385         u16 data;
 386
 387         DEBUGFUNC("e1000_setup_copper_link_82540");
 388
 389         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 390         ctrl |= E1000_CTRL_SLU;
 391         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 392         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 393
 394         ret_val = e1000_set_phy_mode_82540(hw);
 395         if (ret_val)
 396                 goto out;
 397
 398         if (hw->mac.type == e1000_82545_rev_3 ||
 399             hw->mac.type == e1000_82546_rev_3) {
 400                 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
 401                                                &data);
 402                 if (ret_val)
 403                         goto out;
 404                 data |= 0x00000008;
 405                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
 406                                                 data);
 407                 if (ret_val)
 408                         goto out;
 409         }
 410
 411         ret_val = e1000_copper_link_setup_m88(hw);
 412         if (ret_val)
 413                 goto out;
 414
 415         ret_val = e1000_setup_copper_link_generic(hw);
 416
 417 out:
 418         return ret_val;
 419 }
 420
 421 /**
 422  *  e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
 423  *  @hw: pointer to the HW structure
 424  *
 425  *  Set the output amplitude to the value in the EEPROM and adjust the VCO
 426  *  speed to improve Bit Error Rate (BER) performance.  Configures collision
 427  *  distance and flow control for fiber and serdes links.  Upon successful
 428  *  setup, poll for link.
 429  **/
 430 STATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
 431 {
 432         struct e1000_mac_info *mac = &hw->mac;
 433         s32 ret_val = E1000_SUCCESS;
 434
 435         DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
 436
 437         switch (mac->type) {
 438         case e1000_82545_rev_3:
 439         case e1000_82546_rev_3:
 440                 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
 441                         /*
 442                          * If we're on serdes media, adjust the output
 443                          * amplitude to value set in the EEPROM.
 444                          */
 445                         ret_val = e1000_adjust_serdes_amplitude_82540(hw);
 446                         if (ret_val)
 447                                 goto out;
 448                 }
 449                 /* Adjust VCO speed to improve BER performance */
 450                 ret_val = e1000_set_vco_speed_82540(hw);
 451                 if (ret_val)
 452                         goto out;
 453         default:
 454                 break;
 455         }
 456
 457         ret_val = e1000_setup_fiber_serdes_link_generic(hw);
 458
 459 out:
 460         return ret_val;
 461 }
 462
 463 /**
 464  *  e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
 465  *  @hw: pointer to the HW structure
 466  *
 467  *  Adjust the SERDES output amplitude based on the EEPROM settings.
 468  **/
 469 STATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
 470 {
 471         s32 ret_val;
 472         u16 nvm_data;
 473
 474         DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
 475
 476         ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
 477         if (ret_val)
 478                 goto out;
 479
 480         if (nvm_data != NVM_RESERVED_WORD) {
 481                 /* Adjust serdes output amplitude only. */
 482                 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
 483                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
 484                                                 nvm_data);
 485                 if (ret_val)
 486                         goto out;
 487         }
 488
 489 out:
 490         return ret_val;
 491 }
 492
 493 /**
 494  *  e1000_set_vco_speed_82540 - Set VCO speed for better performance
 495  *  @hw: pointer to the HW structure
 496  *
 497  *  Set the VCO speed to improve Bit Error Rate (BER) performance.
 498  **/
 499 STATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
 500 {
 501         s32  ret_val;
 502         u16 default_page = 0;
 503         u16 phy_data;
 504
 505         DEBUGFUNC("e1000_set_vco_speed_82540");
 506
 507         /* Set PHY register 30, page 5, bit 8 to 0 */
 508
 509         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
 510                                        &default_page);
 511         if (ret_val)
 512                 goto out;
 513
 514         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
 515         if (ret_val)
 516                 goto out;
 517
 518         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
 519         if (ret_val)
 520                 goto out;
 521
 522         phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
 523         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
 524         if (ret_val)
 525                 goto out;
 526
 527         /* Set PHY register 30, page 4, bit 11 to 1 */
 528
 529         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
 530         if (ret_val)
 531                 goto out;
 532
 533         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
 534         if (ret_val)
 535                 goto out;
 536
 537         phy_data |= M88E1000_PHY_VCO_REG_BIT11;
 538         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
 539         if (ret_val)
 540                 goto out;
 541
 542         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
 543                                         default_page);
 544
 545 out:
 546         return ret_val;
 547 }
 548
 549 /**
 550  *  e1000_set_phy_mode_82540 - Set PHY to class A mode
 551  *  @hw: pointer to the HW structure
 552  *
 553  *  Sets the PHY to class A mode and assumes the following operations will
 554  *  follow to enable the new class mode:
 555  *    1.  Do a PHY soft reset.
 556  *    2.  Restart auto-negotiation or force link.
 557  **/
 558 STATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
 559 {
 560         s32 ret_val = E1000_SUCCESS;
 561         u16 nvm_data;
 562
 563         DEBUGFUNC("e1000_set_phy_mode_82540");
 564
 565         if (hw->mac.type != e1000_82545_rev_3)
 566                 goto out;
 567
 568         ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
 569         if (ret_val) {
 570                 ret_val = -E1000_ERR_PHY;
 571                 goto out;
 572         }
 573
 574         if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
 575                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
 576                                                 0x000B);
 577                 if (ret_val) {
 578                         ret_val = -E1000_ERR_PHY;
 579                         goto out;
 580                 }
 581                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
 582                                                 0x8104);
 583                 if (ret_val) {
 584                         ret_val = -E1000_ERR_PHY;
 585                         goto out;
 586                 }
 587
 588         }
 589
 590 out:
 591         return ret_val;
 592 }
 593
 594 /**
 595  * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
 596  * @hw: pointer to the HW structure
 597  *
 598  * In the case of a PHY power down to save power, or to turn off link during a
 599  * driver unload, or wake on lan is not enabled, remove the link.
 600  **/
 601 STATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
 602 {
 603         /* If the management interface is not enabled, then power down */
 604         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
 605                 e1000_power_down_phy_copper(hw);
 606
 607         return;
 608 }
 609
 610 /**
 611  *  e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
 612  *  @hw: pointer to the HW structure
 613  *
 614  *  Clears the hardware counters by reading the counter registers.
 615  **/
 616 STATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
 617 {
 618         DEBUGFUNC("e1000_clear_hw_cntrs_82540");
 619
 620         e1000_clear_hw_cntrs_base_generic(hw);
 621
 622         E1000_READ_REG(hw, E1000_PRC64);
 623         E1000_READ_REG(hw, E1000_PRC127);
 624         E1000_READ_REG(hw, E1000_PRC255);
 625         E1000_READ_REG(hw, E1000_PRC511);
 626         E1000_READ_REG(hw, E1000_PRC1023);
 627         E1000_READ_REG(hw, E1000_PRC1522);
 628         E1000_READ_REG(hw, E1000_PTC64);
 629         E1000_READ_REG(hw, E1000_PTC127);
 630         E1000_READ_REG(hw, E1000_PTC255);
 631         E1000_READ_REG(hw, E1000_PTC511);
 632         E1000_READ_REG(hw, E1000_PTC1023);
 633         E1000_READ_REG(hw, E1000_PTC1522);
 634
 635         E1000_READ_REG(hw, E1000_ALGNERRC);
 636         E1000_READ_REG(hw, E1000_RXERRC);
 637         E1000_READ_REG(hw, E1000_TNCRS);
 638         E1000_READ_REG(hw, E1000_CEXTERR);
 639         E1000_READ_REG(hw, E1000_TSCTC);
 640         E1000_READ_REG(hw, E1000_TSCTFC);
 641
 642         E1000_READ_REG(hw, E1000_MGTPRC);
 643         E1000_READ_REG(hw, E1000_MGTPDC);
 644         E1000_READ_REG(hw, E1000_MGTPTC);
 645 }
 646
 647 /**
 648  *  e1000_read_mac_addr_82540 - Read device MAC address
 649  *  @hw: pointer to the HW structure
 650  *
 651  *  Reads the device MAC address from the EEPROM and stores the value.
 652  *  Since devices with two ports use the same EEPROM, we increment the
 653  *  last bit in the MAC address for the second port.
 654  *
 655  *  This version is being used over generic because of customer issues
 656  *  with VmWare and Virtual Box when using generic. It seems in
 657  *  the emulated 82545, RAR[0] does NOT have a valid address after a
 658  *  reset, this older method works and using this breaks nothing for
 659  *  these legacy adapters.
 660  **/
 661 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
 662 {
 663         s32  ret_val = E1000_SUCCESS;
 664         u16 offset, nvm_data, i;
 665
 666         DEBUGFUNC("e1000_read_mac_addr");
 667
 668         for (i = 0; i < ETH_ADDR_LEN; i += 2) {
 669                 offset = i >> 1;
 670                 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
 671                 if (ret_val) {
 672                         DEBUGOUT("NVM Read Error\n");
 673                         goto out;
 674                 }
 675                 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
 676                 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
 677         }
 678
 679         /* Flip last bit of mac address if we're on second port */
 680         if (hw->bus.func == E1000_FUNC_1)
 681                 hw->mac.perm_addr[5] ^= 1;
 682
 683         for (i = 0; i < ETH_ADDR_LEN; i++)
 684                 hw->mac.addr[i] = hw->mac.perm_addr[i];
 685
 686 out:
 687         return ret_val;
 688 }