drivers/net/e1000/base/e1000_82541.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2020 Intel Corporation
   3  */
   4
   5 /*
   6  * 82541EI Gigabit Ethernet Controller
   7  * 82541ER Gigabit Ethernet Controller
   8  * 82541GI Gigabit Ethernet Controller
   9  * 82541PI Gigabit Ethernet Controller
  10  * 82547EI Gigabit Ethernet Controller
  11  * 82547GI Gigabit Ethernet Controller
  12  */
  13
  14 #include "e1000_api.h"
  15
  16 STATIC s32  e1000_init_phy_params_82541(struct e1000_hw *hw);
  17 STATIC s32  e1000_init_nvm_params_82541(struct e1000_hw *hw);
  18 STATIC s32  e1000_init_mac_params_82541(struct e1000_hw *hw);
  19 STATIC s32  e1000_reset_hw_82541(struct e1000_hw *hw);
  20 STATIC s32  e1000_init_hw_82541(struct e1000_hw *hw);
  21 STATIC s32  e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
  22                                          u16 *duplex);
  23 STATIC s32  e1000_phy_hw_reset_82541(struct e1000_hw *hw);
  24 STATIC s32  e1000_setup_copper_link_82541(struct e1000_hw *hw);
  25 STATIC s32  e1000_check_for_link_82541(struct e1000_hw *hw);
  26 STATIC s32  e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
  27 STATIC s32  e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
  28                                           bool active);
  29 STATIC s32  e1000_setup_led_82541(struct e1000_hw *hw);
  30 STATIC s32  e1000_cleanup_led_82541(struct e1000_hw *hw);
  31 STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
  32 STATIC s32  e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
  33                                                      bool link_up);
  34 STATIC s32  e1000_phy_init_script_82541(struct e1000_hw *hw);
  35 STATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
  36
  37 STATIC const u16 e1000_igp_cable_length_table[] = {
  38         5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10,
  39         10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30,
  40         40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60,
  41         60, 60, 60, 60, 60, 60, 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80,
  42         80, 90, 90, 90, 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100,
  43         100, 100, 100, 100, 100, 100, 100, 100, 110, 110, 110, 110, 110, 110,
  44         110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 120, 120,
  45         120, 120, 120, 120, 120, 120, 120, 120};
  46 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
  47                 (sizeof(e1000_igp_cable_length_table) / \
  48                  sizeof(e1000_igp_cable_length_table[0]))
  49
  50 /**
  51  *  e1000_init_phy_params_82541 - Init PHY func ptrs.
  52  *  @hw: pointer to the HW structure
  53  **/
  54 STATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
  55 {
  56         struct e1000_phy_info *phy = &hw->phy;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("e1000_init_phy_params_82541");
  60
  61         phy->addr               = 1;
  62         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  63         phy->reset_delay_us     = 10000;
  64         phy->type               = e1000_phy_igp;
  65
  66         /* Function Pointers */
  67         phy->ops.check_polarity = e1000_check_polarity_igp;
  68         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
  69         phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
  70         phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
  71         phy->ops.get_info       = e1000_get_phy_info_igp;
  72         phy->ops.read_reg       = e1000_read_phy_reg_igp;
  73         phy->ops.reset          = e1000_phy_hw_reset_82541;
  74         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
  75         phy->ops.write_reg      = e1000_write_phy_reg_igp;
  76         phy->ops.power_up       = e1000_power_up_phy_copper;
  77         phy->ops.power_down     = e1000_power_down_phy_copper_82541;
  78
  79         ret_val = e1000_get_phy_id(hw);
  80         if (ret_val)
  81                 goto out;
  82
  83         /* Verify phy id */
  84         if (phy->id != IGP01E1000_I_PHY_ID) {
  85                 ret_val = -E1000_ERR_PHY;
  86                 goto out;
  87         }
  88
  89 out:
  90         return ret_val;
  91 }
  92
  93 /**
  94  *  e1000_init_nvm_params_82541 - Init NVM func ptrs.
  95  *  @hw: pointer to the HW structure
  96  **/
  97 STATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
  98 {
  99         struct e1000_nvm_info *nvm = &hw->nvm;
 100         s32 ret_val = E1000_SUCCESS;
 101         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 102         u16 size;
 103
 104         DEBUGFUNC("e1000_init_nvm_params_82541");
 105
 106         switch (nvm->override) {
 107         case e1000_nvm_override_spi_large:
 108                 nvm->type = e1000_nvm_eeprom_spi;
 109                 eecd |= E1000_EECD_ADDR_BITS;
 110                 break;
 111         case e1000_nvm_override_spi_small:
 112                 nvm->type = e1000_nvm_eeprom_spi;
 113                 eecd &= ~E1000_EECD_ADDR_BITS;
 114                 break;
 115         case e1000_nvm_override_microwire_large:
 116                 nvm->type = e1000_nvm_eeprom_microwire;
 117                 eecd |= E1000_EECD_SIZE;
 118                 break;
 119         case e1000_nvm_override_microwire_small:
 120                 nvm->type = e1000_nvm_eeprom_microwire;
 121                 eecd &= ~E1000_EECD_SIZE;
 122                 break;
 123         default:
 124                 nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi
 125                             : e1000_nvm_eeprom_microwire;
 126                 break;
 127         }
 128
 129         if (nvm->type == e1000_nvm_eeprom_spi) {
 130                 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8;
 131                 nvm->delay_usec = 1;
 132                 nvm->opcode_bits = 8;
 133                 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8;
 134
 135                 /* Function Pointers */
 136                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 137                 nvm->ops.read           = e1000_read_nvm_spi;
 138                 nvm->ops.release        = e1000_release_nvm_generic;
 139                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 140                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 141                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 142                 nvm->ops.write          = e1000_write_nvm_spi;
 143
 144                 /*
 145                  * nvm->word_size must be discovered after the pointers
 146                  * are set so we can verify the size from the nvm image
 147                  * itself.  Temporarily set it to a dummy value so the
 148                  * read will work.
 149                  */
 150                 nvm->word_size = 64;
 151                 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
 152                 if (ret_val)
 153                         goto out;
 154                 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
 155                 /*
 156                  * if size != 0, it can be added to a constant and become
 157                  * the left-shift value to set the word_size.  Otherwise,
 158                  * word_size stays at 64.
 159                  */
 160                 if (size) {
 161                         size += NVM_WORD_SIZE_BASE_SHIFT_82541;
 162                         nvm->word_size = 1 << size;
 163                 }
 164         } else {
 165                 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6;
 166                 nvm->delay_usec = 50;
 167                 nvm->opcode_bits = 3;
 168                 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64;
 169
 170                 /* Function Pointers */
 171                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 172                 nvm->ops.read           = e1000_read_nvm_microwire;
 173                 nvm->ops.release        = e1000_release_nvm_generic;
 174                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 175                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 176                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 177                 nvm->ops.write          = e1000_write_nvm_microwire;
 178         }
 179
 180 out:
 181         return ret_val;
 182 }
 183
 184 /**
 185  *  e1000_init_mac_params_82541 - Init MAC func ptrs.
 186  *  @hw: pointer to the HW structure
 187  **/
 188 STATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
 189 {
 190         struct e1000_mac_info *mac = &hw->mac;
 191
 192         DEBUGFUNC("e1000_init_mac_params_82541");
 193
 194         /* Set media type */
 195         hw->phy.media_type = e1000_media_type_copper;
 196         /* Set mta register count */
 197         mac->mta_reg_count = 128;
 198         /* Set rar entry count */
 199         mac->rar_entry_count = E1000_RAR_ENTRIES;
 200         /* Set if part includes ASF firmware */
 201         mac->asf_firmware_present = true;
 202
 203         /* Function Pointers */
 204
 205         /* bus type/speed/width */
 206         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
 207         /* function id */
 208         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 209         /* reset */
 210         mac->ops.reset_hw = e1000_reset_hw_82541;
 211         /* hw initialization */
 212         mac->ops.init_hw = e1000_init_hw_82541;
 213         /* link setup */
 214         mac->ops.setup_link = e1000_setup_link_generic;
 215         /* physical interface link setup */
 216         mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
 217         /* check for link */
 218         mac->ops.check_for_link = e1000_check_for_link_82541;
 219         /* link info */
 220         mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
 221         /* multicast address update */
 222         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 223         /* writing VFTA */
 224         mac->ops.write_vfta = e1000_write_vfta_generic;
 225         /* clearing VFTA */
 226         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 227         /* ID LED init */
 228         mac->ops.id_led_init = e1000_id_led_init_generic;
 229         /* setup LED */
 230         mac->ops.setup_led = e1000_setup_led_82541;
 231         /* cleanup LED */
 232         mac->ops.cleanup_led = e1000_cleanup_led_82541;
 233         /* turn on/off LED */
 234         mac->ops.led_on = e1000_led_on_generic;
 235         mac->ops.led_off = e1000_led_off_generic;
 236         /* clear hardware counters */
 237         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
 238
 239         return E1000_SUCCESS;
 240 }
 241
 242 /**
 243  *  e1000_init_function_pointers_82541 - Init func ptrs.
 244  *  @hw: pointer to the HW structure
 245  *
 246  *  Called to initialize all function pointers and parameters.
 247  **/
 248 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
 249 {
 250         DEBUGFUNC("e1000_init_function_pointers_82541");
 251
 252         hw->mac.ops.init_params = e1000_init_mac_params_82541;
 253         hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
 254         hw->phy.ops.init_params = e1000_init_phy_params_82541;
 255 }
 256
 257 /**
 258  *  e1000_reset_hw_82541 - Reset hardware
 259  *  @hw: pointer to the HW structure
 260  *
 261  *  This resets the hardware into a known state.
 262  **/
 263 STATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 264 {
 265         u32 ledctl, ctrl, manc;
 266
 267         DEBUGFUNC("e1000_reset_hw_82541");
 268
 269         DEBUGOUT("Masking off all interrupts\n");
 270         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 271
 272         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 273         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 274         E1000_WRITE_FLUSH(hw);
 275
 276         /*
 277          * Delay to allow any outstanding PCI transactions to complete
 278          * before resetting the device.
 279          */
 280         msec_delay(10);
 281
 282         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 283
 284         /* Must reset the Phy before resetting the MAC */
 285         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 286                 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
 287                 E1000_WRITE_FLUSH(hw);
 288                 msec_delay(5);
 289         }
 290
 291         DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
 292         switch (hw->mac.type) {
 293         case e1000_82541:
 294         case e1000_82541_rev_2:
 295                 /*
 296                  * These controllers can't ack the 64-bit write when
 297                  * issuing the reset, so we use IO-mapping as a
 298                  * workaround to issue the reset.
 299                  */
 300                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 301                 break;
 302         default:
 303                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 304                 break;
 305         }
 306
 307         /* Wait for NVM reload */
 308         msec_delay(20);
 309
 310         /* Disable HW ARPs on ASF enabled adapters */
 311         manc = E1000_READ_REG(hw, E1000_MANC);
 312         manc &= ~E1000_MANC_ARP_EN;
 313         E1000_WRITE_REG(hw, E1000_MANC, manc);
 314
 315         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 316                 e1000_phy_init_script_82541(hw);
 317
 318                 /* Configure activity LED after Phy reset */
 319                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 320                 ledctl &= IGP_ACTIVITY_LED_MASK;
 321                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 322                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 323         }
 324
 325         /* Once again, mask the interrupts */
 326         DEBUGOUT("Masking off all interrupts\n");
 327         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 328
 329         /* Clear any pending interrupt events. */
 330         E1000_READ_REG(hw, E1000_ICR);
 331
 332         return E1000_SUCCESS;
 333 }
 334
 335 /**
 336  *  e1000_init_hw_82541 - Initialize hardware
 337  *  @hw: pointer to the HW structure
 338  *
 339  *  This inits the hardware readying it for operation.
 340  **/
 341 STATIC s32 e1000_init_hw_82541(struct e1000_hw *hw)
 342 {
 343         struct e1000_mac_info *mac = &hw->mac;
 344         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 345         u32 i, txdctl;
 346         s32 ret_val;
 347
 348         DEBUGFUNC("e1000_init_hw_82541");
 349
 350         /* Initialize identification LED */
 351         ret_val = mac->ops.id_led_init(hw);
 352         if (ret_val) {
 353                 DEBUGOUT("Error initializing identification LED\n");
 354                 /* This is not fatal and we should not stop init due to this */
 355         }
 356
 357         /* Storing the Speed Power Down  value for later use */
 358         ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
 359                                        &dev_spec->spd_default);
 360         if (ret_val)
 361                 goto out;
 362
 363         /* Disabling VLAN filtering */
 364         DEBUGOUT("Initializing the IEEE VLAN\n");
 365         mac->ops.clear_vfta(hw);
 366
 367         /* Setup the receive address. */
 368         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 369
 370         /* Zero out the Multicast HASH table */
 371         DEBUGOUT("Zeroing the MTA\n");
 372         for (i = 0; i < mac->mta_reg_count; i++) {
 373                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 374                 /*
 375                  * Avoid back to back register writes by adding the register
 376                  * read (flush).  This is to protect against some strange
 377                  * bridge configurations that may issue Memory Write Block
 378                  * (MWB) to our register space.
 379                  */
 380                 E1000_WRITE_FLUSH(hw);
 381         }
 382
 383         /* Setup link and flow control */
 384         ret_val = mac->ops.setup_link(hw);
 385
 386         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 387         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 388                   E1000_TXDCTL_FULL_TX_DESC_WB;
 389         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 390
 391         /*
 392          * Clear all of the statistics registers (clear on read).  It is
 393          * important that we do this after we have tried to establish link
 394          * because the symbol error count will increment wildly if there
 395          * is no link.
 396          */
 397         e1000_clear_hw_cntrs_82541(hw);
 398
 399 out:
 400         return ret_val;
 401 }
 402
 403 /**
 404  * e1000_get_link_up_info_82541 - Report speed and duplex
 405  * @hw: pointer to the HW structure
 406  * @speed: pointer to speed buffer
 407  * @duplex: pointer to duplex buffer
 408  *
 409  * Retrieve the current speed and duplex configuration.
 410  **/
 411 STATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
 412                                         u16 *duplex)
 413 {
 414         struct e1000_phy_info *phy = &hw->phy;
 415         s32 ret_val;
 416         u16 data;
 417
 418         DEBUGFUNC("e1000_get_link_up_info_82541");
 419
 420         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
 421         if (ret_val)
 422                 goto out;
 423
 424         if (!phy->speed_downgraded)
 425                 goto out;
 426
 427         /*
 428          * IGP01 PHY may advertise full duplex operation after speed
 429          * downgrade even if it is operating at half duplex.
 430          * Here we set the duplex settings to match the duplex in the
 431          * link partner's capabilities.
 432          */
 433         ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
 434         if (ret_val)
 435                 goto out;
 436
 437         if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
 438                 *duplex = HALF_DUPLEX;
 439         } else {
 440                 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
 441                 if (ret_val)
 442                         goto out;
 443
 444                 if (*speed == SPEED_100) {
 445                         if (!(data & NWAY_LPAR_100TX_FD_CAPS))
 446                                 *duplex = HALF_DUPLEX;
 447                 } else if (*speed == SPEED_10) {
 448                         if (!(data & NWAY_LPAR_10T_FD_CAPS))
 449                                 *duplex = HALF_DUPLEX;
 450                 }
 451         }
 452
 453 out:
 454         return ret_val;
 455 }
 456
 457 /**
 458  *  e1000_phy_hw_reset_82541 - PHY hardware reset
 459  *  @hw: pointer to the HW structure
 460  *
 461  *  Verify the reset block is not blocking us from resetting.  Acquire
 462  *  semaphore (if necessary) and read/set/write the device control reset
 463  *  bit in the PHY.  Wait the appropriate delay time for the device to
 464  *  reset and release the semaphore (if necessary).
 465  **/
 466 STATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
 467 {
 468         s32 ret_val;
 469         u32 ledctl;
 470
 471         DEBUGFUNC("e1000_phy_hw_reset_82541");
 472
 473         ret_val = e1000_phy_hw_reset_generic(hw);
 474         if (ret_val)
 475                 goto out;
 476
 477         e1000_phy_init_script_82541(hw);
 478
 479         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 480                 /* Configure activity LED after PHY reset */
 481                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 482                 ledctl &= IGP_ACTIVITY_LED_MASK;
 483                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 484                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 485         }
 486
 487 out:
 488         return ret_val;
 489 }
 490
 491 /**
 492  *  e1000_setup_copper_link_82541 - Configure copper link settings
 493  *  @hw: pointer to the HW structure
 494  *
 495  *  Calls the appropriate function to configure the link for auto-neg or forced
 496  *  speed and duplex.  Then we check for link, once link is established calls
 497  *  to configure collision distance and flow control are called.  If link is
 498  *  not established, we return -E1000_ERR_PHY (-2).
 499  **/
 500 STATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
 501 {
 502         struct e1000_phy_info *phy = &hw->phy;
 503         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 504         s32  ret_val;
 505         u32 ctrl, ledctl;
 506
 507         DEBUGFUNC("e1000_setup_copper_link_82541");
 508
 509         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 510         ctrl |= E1000_CTRL_SLU;
 511         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 512         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 513
 514
 515         /* Earlier revs of the IGP phy require us to force MDI. */
 516         if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
 517                 dev_spec->dsp_config = e1000_dsp_config_disabled;
 518                 phy->mdix = 1;
 519         } else {
 520                 dev_spec->dsp_config = e1000_dsp_config_enabled;
 521         }
 522
 523         ret_val = e1000_copper_link_setup_igp(hw);
 524         if (ret_val)
 525                 goto out;
 526
 527         if (hw->mac.autoneg) {
 528                 if (dev_spec->ffe_config == e1000_ffe_config_active)
 529                         dev_spec->ffe_config = e1000_ffe_config_enabled;
 530         }
 531
 532         /* Configure activity LED after Phy reset */
 533         ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 534         ledctl &= IGP_ACTIVITY_LED_MASK;
 535         ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 536         E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 537
 538         ret_val = e1000_setup_copper_link_generic(hw);
 539
 540 out:
 541         return ret_val;
 542 }
 543
 544 /**
 545  *  e1000_check_for_link_82541 - Check/Store link connection
 546  *  @hw: pointer to the HW structure
 547  *
 548  *  This checks the link condition of the adapter and stores the
 549  *  results in the hw->mac structure.
 550  **/
 551 STATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw)
 552 {
 553         struct e1000_mac_info *mac = &hw->mac;
 554         s32 ret_val;
 555         bool link;
 556
 557         DEBUGFUNC("e1000_check_for_link_82541");
 558
 559         /*
 560          * We only want to go out to the PHY registers to see if Auto-Neg
 561          * has completed and/or if our link status has changed.  The
 562          * get_link_status flag is set upon receiving a Link Status
 563          * Change or Rx Sequence Error interrupt.
 564          */
 565         if (!mac->get_link_status) {
 566                 ret_val = E1000_SUCCESS;
 567                 goto out;
 568         }
 569
 570         /*
 571          * First we want to see if the MII Status Register reports
 572          * link.  If so, then we want to get the current speed/duplex
 573          * of the PHY.
 574          */
 575         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
 576         if (ret_val)
 577                 goto out;
 578
 579         if (!link) {
 580                 ret_val = e1000_config_dsp_after_link_change_82541(hw, false);
 581                 goto out; /* No link detected */
 582         }
 583
 584         mac->get_link_status = false;
 585
 586         /*
 587          * Check if there was DownShift, must be checked
 588          * immediately after link-up
 589          */
 590         e1000_check_downshift_generic(hw);
 591
 592         /*
 593          * If we are forcing speed/duplex, then we simply return since
 594          * we have already determined whether we have link or not.
 595          */
 596         if (!mac->autoneg) {
 597                 ret_val = -E1000_ERR_CONFIG;
 598                 goto out;
 599         }
 600
 601         ret_val = e1000_config_dsp_after_link_change_82541(hw, true);
 602
 603         /*
 604          * Auto-Neg is enabled.  Auto Speed Detection takes care
 605          * of MAC speed/duplex configuration.  So we only need to
 606          * configure Collision Distance in the MAC.
 607          */
 608         mac->ops.config_collision_dist(hw);
 609
 610         /*
 611          * Configure Flow Control now that Auto-Neg has completed.
 612          * First, we need to restore the desired flow control
 613          * settings because we may have had to re-autoneg with a
 614          * different link partner.
 615          */
 616         ret_val = e1000_config_fc_after_link_up_generic(hw);
 617         if (ret_val)
 618                 DEBUGOUT("Error configuring flow control\n");
 619
 620 out:
 621         return ret_val;
 622 }
 623
 624 /**
 625  *  e1000_config_dsp_after_link_change_82541 - Config DSP after link
 626  *  @hw: pointer to the HW structure
 627  *  @link_up: boolean flag for link up status
 628  *
 629  *  Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
 630  *  at any other case.
 631  *
 632  *  82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
 633  *  gigabit link is achieved to improve link quality.
 634  **/
 635 STATIC s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
 636                                                     bool link_up)
 637 {
 638         struct e1000_phy_info *phy = &hw->phy;
 639         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 640         s32 ret_val;
 641         u32 idle_errs = 0;
 642         u16 phy_data, phy_saved_data, speed, duplex, i;
 643         u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
 644         u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
 645                                                 IGP01E1000_PHY_AGC_PARAM_A,
 646                                                 IGP01E1000_PHY_AGC_PARAM_B,
 647                                                 IGP01E1000_PHY_AGC_PARAM_C,
 648                                                 IGP01E1000_PHY_AGC_PARAM_D};
 649
 650         DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
 651
 652         if (link_up) {
 653                 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 654                 if (ret_val) {
 655                         DEBUGOUT("Error getting link speed and duplex\n");
 656                         goto out;
 657                 }
 658
 659                 if (speed != SPEED_1000) {
 660                         ret_val = E1000_SUCCESS;
 661                         goto out;
 662                 }
 663
 664                 ret_val = phy->ops.get_cable_length(hw);
 665                 if (ret_val)
 666                         goto out;
 667
 668                 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
 669                     phy->min_cable_length >= 50) {
 670
 671                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 672                                 ret_val = phy->ops.read_reg(hw,
 673                                                             dsp_reg_array[i],
 674                                                             &phy_data);
 675                                 if (ret_val)
 676                                         goto out;
 677
 678                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 679
 680                                 ret_val = phy->ops.write_reg(hw,
 681                                                              dsp_reg_array[i],
 682                                                              phy_data);
 683                                 if (ret_val)
 684                                         goto out;
 685                         }
 686                         dev_spec->dsp_config = e1000_dsp_config_activated;
 687                 }
 688
 689                 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
 690                     (phy->min_cable_length >= 50)) {
 691                         ret_val = E1000_SUCCESS;
 692                         goto out;
 693                 }
 694
 695                 /* clear previous idle error counts */
 696                 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
 697                 if (ret_val)
 698                         goto out;
 699
 700                 for (i = 0; i < ffe_idle_err_timeout; i++) {
 701                         usec_delay(1000);
 702                         ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,
 703                                                     &phy_data);
 704                         if (ret_val)
 705                                 goto out;
 706
 707                         idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
 708                         if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
 709                                 dev_spec->ffe_config = e1000_ffe_config_active;
 710
 711                                 ret_val = phy->ops.write_reg(hw,
 712                                                   IGP01E1000_PHY_DSP_FFE,
 713                                                   IGP01E1000_PHY_DSP_FFE_CM_CP);
 714                                 if (ret_val)
 715                                         goto out;
 716                                 break;
 717                         }
 718
 719                         if (idle_errs)
 720                                 ffe_idle_err_timeout =
 721                                                  FFE_IDLE_ERR_COUNT_TIMEOUT_100;
 722                 }
 723         } else {
 724                 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
 725                         /*
 726                          * Save off the current value of register 0x2F5B
 727                          * to be restored at the end of the routines.
 728                          */
 729                         ret_val = phy->ops.read_reg(hw, 0x2F5B,
 730                                                     &phy_saved_data);
 731                         if (ret_val)
 732                                 goto out;
 733
 734                         /* Disable the PHY transmitter */
 735                         ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 736                         if (ret_val)
 737                                 goto out;
 738
 739                         msec_delay_irq(20);
 740
 741                         ret_val = phy->ops.write_reg(hw, 0x0000,
 742                                                      IGP01E1000_IEEE_FORCE_GIG);
 743                         if (ret_val)
 744                                 goto out;
 745                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 746                                 ret_val = phy->ops.read_reg(hw,
 747                                                             dsp_reg_array[i],
 748                                                             &phy_data);
 749                                 if (ret_val)
 750                                         goto out;
 751
 752                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 753                                 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
 754
 755                                 ret_val = phy->ops.write_reg(hw,
 756                                                              dsp_reg_array[i],
 757                                                              phy_data);
 758                                 if (ret_val)
 759                                         goto out;
 760                         }
 761
 762                         ret_val = phy->ops.write_reg(hw, 0x0000,
 763                                                IGP01E1000_IEEE_RESTART_AUTONEG);
 764                         if (ret_val)
 765                                 goto out;
 766
 767                         msec_delay_irq(20);
 768
 769                         /* Now enable the transmitter */
 770                         ret_val = phy->ops.write_reg(hw, 0x2F5B,
 771                                                      phy_saved_data);
 772                         if (ret_val)
 773                                 goto out;
 774
 775                         dev_spec->dsp_config = e1000_dsp_config_enabled;
 776                 }
 777
 778                 if (dev_spec->ffe_config != e1000_ffe_config_active) {
 779                         ret_val = E1000_SUCCESS;
 780                         goto out;
 781                 }
 782
 783                 /*
 784                  * Save off the current value of register 0x2F5B
 785                  * to be restored at the end of the routines.
 786                  */
 787                 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
 788                 if (ret_val)
 789                         goto out;
 790
 791                 /* Disable the PHY transmitter */
 792                 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 793                 if (ret_val)
 794                         goto out;
 795
 796                 msec_delay_irq(20);
 797
 798                 ret_val = phy->ops.write_reg(hw, 0x0000,
 799                                              IGP01E1000_IEEE_FORCE_GIG);
 800                 if (ret_val)
 801                         goto out;
 802
 803                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,
 804                                              IGP01E1000_PHY_DSP_FFE_DEFAULT);
 805                 if (ret_val)
 806                         goto out;
 807
 808                 ret_val = phy->ops.write_reg(hw, 0x0000,
 809                                              IGP01E1000_IEEE_RESTART_AUTONEG);
 810                 if (ret_val)
 811                         goto out;
 812
 813                 msec_delay_irq(20);
 814
 815                 /* Now enable the transmitter */
 816                 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
 817
 818                 if (ret_val)
 819                         goto out;
 820
 821                 dev_spec->ffe_config = e1000_ffe_config_enabled;
 822         }
 823
 824 out:
 825         return ret_val;
 826 }
 827
 828 /**
 829  *  e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
 830  *  @hw: pointer to the HW structure
 831  *
 832  *  The automatic gain control (agc) normalizes the amplitude of the
 833  *  received signal, adjusting for the attenuation produced by the
 834  *  cable.  By reading the AGC registers, which represent the
 835  *  combination of coarse and fine gain value, the value can be put
 836  *  into a lookup table to obtain the approximate cable length
 837  *  for each channel.
 838  **/
 839 STATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
 840 {
 841         struct e1000_phy_info *phy = &hw->phy;
 842         s32 ret_val = E1000_SUCCESS;
 843         u16 i, data;
 844         u16 cur_agc_value, agc_value = 0;
 845         u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
 846         u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A,
 847                                                          IGP01E1000_PHY_AGC_B,
 848                                                          IGP01E1000_PHY_AGC_C,
 849                                                          IGP01E1000_PHY_AGC_D};
 850
 851         DEBUGFUNC("e1000_get_cable_length_igp_82541");
 852
 853         /* Read the AGC registers for all channels */
 854         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 855                 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
 856                 if (ret_val)
 857                         goto out;
 858
 859                 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
 860
 861                 /* Bounds checking */
 862                 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
 863                     (cur_agc_value == 0)) {
 864                         ret_val = -E1000_ERR_PHY;
 865                         goto out;
 866                 }
 867
 868                 agc_value += cur_agc_value;
 869
 870                 if (min_agc_value > cur_agc_value)
 871                         min_agc_value = cur_agc_value;
 872         }
 873
 874         /* Remove the minimal AGC result for length < 50m */
 875         if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
 876                 agc_value -= min_agc_value;
 877                 /* Average the three remaining channels for the length. */
 878                 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
 879         } else {
 880                 /* Average the channels for the length. */
 881                 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
 882         }
 883
 884         phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
 885                                  IGP01E1000_AGC_RANGE)
 886                                 ? (e1000_igp_cable_length_table[agc_value] -
 887                                    IGP01E1000_AGC_RANGE)
 888                                 : 0;
 889         phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
 890                                 IGP01E1000_AGC_RANGE;
 891
 892         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 893
 894 out:
 895         return ret_val;
 896 }
 897
 898 /**
 899  *  e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
 900  *  @hw: pointer to the HW structure
 901  *  @active: boolean used to enable/disable lplu
 902  *
 903  *  Success returns 0, Failure returns 1
 904  *
 905  *  The low power link up (lplu) state is set to the power management level D3
 906  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 907  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 908  *  is used during Dx states where the power conservation is most important.
 909  *  During driver activity, SmartSpeed should be enabled so performance is
 910  *  maintained.
 911  **/
 912 STATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
 913 {
 914         struct e1000_phy_info *phy = &hw->phy;
 915         s32 ret_val;
 916         u16 data;
 917
 918         DEBUGFUNC("e1000_set_d3_lplu_state_82541");
 919
 920         switch (hw->mac.type) {
 921         case e1000_82541_rev_2:
 922         case e1000_82547_rev_2:
 923                 break;
 924         default:
 925                 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
 926                 goto out;
 927                 break;
 928         }
 929
 930         ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
 931         if (ret_val)
 932                 goto out;
 933
 934         if (!active) {
 935                 data &= ~IGP01E1000_GMII_FLEX_SPD;
 936                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
 937                 if (ret_val)
 938                         goto out;
 939
 940                 /*
 941                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 942                  * during Dx states where the power conservation is most
 943                  * important.  During driver activity we should enable
 944                  * SmartSpeed, so performance is maintained.
 945                  */
 946                 if (phy->smart_speed == e1000_smart_speed_on) {
 947                         ret_val = phy->ops.read_reg(hw,
 948                                                     IGP01E1000_PHY_PORT_CONFIG,
 949                                                     &data);
 950                         if (ret_val)
 951                                 goto out;
 952
 953                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 954                         ret_val = phy->ops.write_reg(hw,
 955                                                      IGP01E1000_PHY_PORT_CONFIG,
 956                                                      data);
 957                         if (ret_val)
 958                                 goto out;
 959                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 960                         ret_val = phy->ops.read_reg(hw,
 961                                                     IGP01E1000_PHY_PORT_CONFIG,
 962                                                     &data);
 963                         if (ret_val)
 964                                 goto out;
 965
 966                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 967                         ret_val = phy->ops.write_reg(hw,
 968                                                      IGP01E1000_PHY_PORT_CONFIG,
 969                                                      data);
 970                         if (ret_val)
 971                                 goto out;
 972                 }
 973         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 974                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 975                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 976                 data |= IGP01E1000_GMII_FLEX_SPD;
 977                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
 978                 if (ret_val)
 979                         goto out;
 980
 981                 /* When LPLU is enabled, we should disable SmartSpeed */
 982                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 983                                             &data);
 984                 if (ret_val)
 985                         goto out;
 986
 987                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 988                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 989                                              data);
 990         }
 991
 992 out:
 993         return ret_val;
 994 }
 995
 996 /**
 997  *  e1000_setup_led_82541 - Configures SW controllable LED
 998  *  @hw: pointer to the HW structure
 999  *
1000  *  This prepares the SW controllable LED for use and saves the current state
1001  *  of the LED so it can be later restored.
1002  **/
1003 STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw)
1004 {
1005         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1006         s32 ret_val;
1007
1008         DEBUGFUNC("e1000_setup_led_82541");
1009
1010         ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
1011                                        &dev_spec->spd_default);
1012         if (ret_val)
1013                 goto out;
1014
1015         ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1016                                         (u16)(dev_spec->spd_default &
1017                                         ~IGP01E1000_GMII_SPD));
1018         if (ret_val)
1019                 goto out;
1020
1021         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1022
1023 out:
1024         return ret_val;
1025 }
1026
1027 /**
1028  *  e1000_cleanup_led_82541 - Set LED config to default operation
1029  *  @hw: pointer to the HW structure
1030  *
1031  *  Remove the current LED configuration and set the LED configuration
1032  *  to the default value, saved from the EEPROM.
1033  **/
1034 STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1035 {
1036         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1037         s32 ret_val;
1038
1039         DEBUGFUNC("e1000_cleanup_led_82541");
1040
1041         ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1042                                         dev_spec->spd_default);
1043         if (ret_val)
1044                 goto out;
1045
1046         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1047
1048 out:
1049         return ret_val;
1050 }
1051
1052 /**
1053  *  e1000_phy_init_script_82541 - Initialize GbE PHY
1054  *  @hw: pointer to the HW structure
1055  *
1056  *  Initializes the IGP PHY.
1057  **/
1058 STATIC s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1059 {
1060         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1061         u32 ret_val;
1062         u16 phy_saved_data;
1063
1064         DEBUGFUNC("e1000_phy_init_script_82541");
1065
1066         if (!dev_spec->phy_init_script) {
1067                 ret_val = E1000_SUCCESS;
1068                 goto out;
1069         }
1070
1071         /* Delay after phy reset to enable NVM configuration to load */
1072         msec_delay(20);
1073
1074         /*
1075          * Save off the current value of register 0x2F5B to be restored at
1076          * the end of this routine.
1077          */
1078         ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1079
1080         /* Disabled the PHY transmitter */
1081         hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1082
1083         msec_delay(20);
1084
1085         hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1086
1087         msec_delay(5);
1088
1089         switch (hw->mac.type) {
1090         case e1000_82541:
1091         case e1000_82547:
1092                 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1093
1094                 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1095
1096                 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1097
1098                 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1099
1100                 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1101
1102                 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1103
1104                 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1105
1106                 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1107
1108                 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1109                 break;
1110         case e1000_82541_rev_2:
1111         case e1000_82547_rev_2:
1112                 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1113                 break;
1114         default:
1115                 break;
1116         }
1117
1118         hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1119
1120         msec_delay(20);
1121
1122         /* Now enable the transmitter */
1123         hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1124
1125         if (hw->mac.type == e1000_82547) {
1126                 u16 fused, fine, coarse;
1127
1128                 /* Move to analog registers page */
1129                 hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1130                                      &fused);
1131
1132                 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1133                         hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS,
1134                                              &fused);
1135
1136                         fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1137                         coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1138
1139                         if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1140                                 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1141                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1142                         } else if (coarse ==
1143                                    IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1144                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1145
1146                         fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1147                                 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1148                                 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1149
1150                         hw->phy.ops.write_reg(hw,
1151                                               IGP01E1000_ANALOG_FUSE_CONTROL,
1152                                               fused);
1153                         hw->phy.ops.write_reg(hw,
1154                                       IGP01E1000_ANALOG_FUSE_BYPASS,
1155                                       IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1156                 }
1157         }
1158
1159 out:
1160         return ret_val;
1161 }
1162
1163 /**
1164  *  e1000_init_script_state_82541 - Enable/Disable PHY init script
1165  *  @hw: pointer to the HW structure
1166  *  @state: boolean value used to enable/disable PHY init script
1167  *
1168  *  Allows the driver to enable/disable the PHY init script, if the PHY is an
1169  *  IGP PHY.
1170  **/
1171 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1172 {
1173         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1174
1175         DEBUGFUNC("e1000_init_script_state_82541");
1176
1177         if (hw->phy.type != e1000_phy_igp) {
1178                 DEBUGOUT("Initialization script not necessary.\n");
1179                 goto out;
1180         }
1181
1182         dev_spec->phy_init_script = state;
1183
1184 out:
1185         return;
1186 }
1187
1188 /**
1189  * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1190  * @hw: pointer to the HW structure
1191  *
1192  * In the case of a PHY power down to save power, or to turn off link during a
1193  * driver unload, or wake on lan is not enabled, remove the link.
1194  **/
1195 STATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1196 {
1197         /* If the management interface is not enabled, then power down */
1198         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1199                 e1000_power_down_phy_copper(hw);
1200
1201         return;
1202 }
1203
1204 /**
1205  *  e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1206  *  @hw: pointer to the HW structure
1207  *
1208  *  Clears the hardware counters by reading the counter registers.
1209  **/
1210 STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1211 {
1212         DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1213
1214         e1000_clear_hw_cntrs_base_generic(hw);
1215
1216         E1000_READ_REG(hw, E1000_PRC64);
1217         E1000_READ_REG(hw, E1000_PRC127);
1218         E1000_READ_REG(hw, E1000_PRC255);
1219         E1000_READ_REG(hw, E1000_PRC511);
1220         E1000_READ_REG(hw, E1000_PRC1023);
1221         E1000_READ_REG(hw, E1000_PRC1522);
1222         E1000_READ_REG(hw, E1000_PTC64);
1223         E1000_READ_REG(hw, E1000_PTC127);
1224         E1000_READ_REG(hw, E1000_PTC255);
1225         E1000_READ_REG(hw, E1000_PTC511);
1226         E1000_READ_REG(hw, E1000_PTC1023);
1227         E1000_READ_REG(hw, E1000_PTC1522);
1228
1229         E1000_READ_REG(hw, E1000_ALGNERRC);
1230         E1000_READ_REG(hw, E1000_RXERRC);
1231         E1000_READ_REG(hw, E1000_TNCRS);
1232         E1000_READ_REG(hw, E1000_CEXTERR);
1233         E1000_READ_REG(hw, E1000_TSCTC);
1234         E1000_READ_REG(hw, E1000_TSCTFC);
1235
1236         E1000_READ_REG(hw, E1000_MGTPRC);
1237         E1000_READ_REG(hw, E1000_MGTPDC);
1238         E1000_READ_REG(hw, E1000_MGTPTC);
1239 }