1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
5 #ifndef _E1000_82541_H_
6 #define _E1000_82541_H_
8 #define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
10 #define IGP01E1000_PHY_CHANNEL_NUM 4
12 #define IGP01E1000_PHY_AGC_A 0x1172
13 #define IGP01E1000_PHY_AGC_B 0x1272
14 #define IGP01E1000_PHY_AGC_C 0x1472
15 #define IGP01E1000_PHY_AGC_D 0x1872
17 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
18 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
19 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
20 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
22 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
23 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
25 #define IGP01E1000_PHY_DSP_RESET 0x1F33
27 #define IGP01E1000_PHY_DSP_FFE 0x1F35
28 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
29 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
31 #define IGP01E1000_IEEE_FORCE_GIG 0x0140
32 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
34 #define IGP01E1000_AGC_LENGTH_SHIFT 7
35 #define IGP01E1000_AGC_RANGE 10
37 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
38 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
40 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
41 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
42 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
43 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
45 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
46 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
47 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
48 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
49 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
50 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
51 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
52 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
53 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
55 #define IGP01E1000_MSE_CHANNEL_D 0x000F
56 #define IGP01E1000_MSE_CHANNEL_C 0x00F0
57 #define IGP01E1000_MSE_CHANNEL_B 0x0F00
58 #define IGP01E1000_MSE_CHANNEL_A 0xF000
61 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state);