drivers/net/e1000/base/e1000_82571.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 /* 82571EB Gigabit Ethernet Controller
   6  * 82571EB Gigabit Ethernet Controller (Copper)
   7  * 82571EB Gigabit Ethernet Controller (Fiber)
   8  * 82571EB Dual Port Gigabit Mezzanine Adapter
   9  * 82571EB Quad Port Gigabit Mezzanine Adapter
  10  * 82571PT Gigabit PT Quad Port Server ExpressModule
  11  * 82572EI Gigabit Ethernet Controller (Copper)
  12  * 82572EI Gigabit Ethernet Controller (Fiber)
  13  * 82572EI Gigabit Ethernet Controller
  14  * 82573V Gigabit Ethernet Controller (Copper)
  15  * 82573E Gigabit Ethernet Controller (Copper)
  16  * 82573L Gigabit Ethernet Controller
  17  * 82574L Gigabit Network Connection
  18  * 82583V Gigabit Network Connection
  19  */
  20
  21 #include "e1000_api.h"
  22
  23 STATIC s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  24 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw);
  25 STATIC s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  26                                   u16 words, u16 *data);
  27 STATIC s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  28 STATIC s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  29 STATIC s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  30 STATIC s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  31                                           bool active);
  32 STATIC s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  33 STATIC s32  e1000_init_hw_82571(struct e1000_hw *hw);
  34 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw);
  35 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  36 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw);
  37 STATIC s32  e1000_setup_link_82571(struct e1000_hw *hw);
  38 STATIC s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  39 STATIC s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  40 STATIC s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  41 STATIC s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  42 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  43 STATIC s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  44 STATIC s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  45 STATIC s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  46 STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  47 STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  48 STATIC s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  49 STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  50 STATIC s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
  51                                           bool active);
  52 STATIC s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
  53                                           bool active);
  54 STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  55 STATIC s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  56                                        u16 words, u16 *data);
  57 STATIC s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  58 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  59
  60 /**
  61  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  62  *  @hw: pointer to the HW structure
  63  **/
  64 STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  65 {
  66         struct e1000_phy_info *phy = &hw->phy;
  67         s32 ret_val;
  68
  69         DEBUGFUNC("e1000_init_phy_params_82571");
  70
  71         if (hw->phy.media_type != e1000_media_type_copper) {
  72                 phy->type = e1000_phy_none;
  73                 return E1000_SUCCESS;
  74         }
  75
  76         phy->addr                       = 1;
  77         phy->autoneg_mask               = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  78         phy->reset_delay_us             = 100;
  79
  80         phy->ops.check_reset_block      = e1000_check_reset_block_generic;
  81         phy->ops.reset                  = e1000_phy_hw_reset_generic;
  82         phy->ops.set_d0_lplu_state      = e1000_set_d0_lplu_state_82571;
  83         phy->ops.set_d3_lplu_state      = e1000_set_d3_lplu_state_generic;
  84         phy->ops.power_up               = e1000_power_up_phy_copper;
  85         phy->ops.power_down             = e1000_power_down_phy_copper_82571;
  86
  87         switch (hw->mac.type) {
  88         case e1000_82571:
  89         case e1000_82572:
  90                 phy->type               = e1000_phy_igp_2;
  91                 phy->ops.get_cfg_done   = e1000_get_cfg_done_82571;
  92                 phy->ops.get_info       = e1000_get_phy_info_igp;
  93                 phy->ops.check_polarity = e1000_check_polarity_igp;
  94                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
  95                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
  96                 phy->ops.read_reg       = e1000_read_phy_reg_igp;
  97                 phy->ops.write_reg      = e1000_write_phy_reg_igp;
  98                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
  99                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 100                 break;
 101         case e1000_82573:
 102                 phy->type               = e1000_phy_m88;
 103                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 104                 phy->ops.get_info       = e1000_get_phy_info_m88;
 105                 phy->ops.check_polarity = e1000_check_polarity_m88;
 106                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 107                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 108                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 109                 phy->ops.read_reg       = e1000_read_phy_reg_m88;
 110                 phy->ops.write_reg      = e1000_write_phy_reg_m88;
 111                 phy->ops.acquire        = e1000_get_hw_semaphore_82571;
 112                 phy->ops.release        = e1000_put_hw_semaphore_82571;
 113                 break;
 114         case e1000_82574:
 115         case e1000_82583:
 116                 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
 117
 118                 phy->type               = e1000_phy_bm;
 119                 phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 120                 phy->ops.get_info       = e1000_get_phy_info_m88;
 121                 phy->ops.check_polarity = e1000_check_polarity_m88;
 122                 phy->ops.commit         = e1000_phy_sw_reset_generic;
 123                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 124                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 125                 phy->ops.read_reg       = e1000_read_phy_reg_bm2;
 126                 phy->ops.write_reg      = e1000_write_phy_reg_bm2;
 127                 phy->ops.acquire        = e1000_get_hw_semaphore_82574;
 128                 phy->ops.release        = e1000_put_hw_semaphore_82574;
 129                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
 130                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 131                 break;
 132         default:
 133                 return -E1000_ERR_PHY;
 134                 break;
 135         }
 136
 137         /* This can only be done after all function pointers are setup. */
 138         ret_val = e1000_get_phy_id_82571(hw);
 139         if (ret_val) {
 140                 DEBUGOUT("Error getting PHY ID\n");
 141                 return ret_val;
 142         }
 143
 144         /* Verify phy id */
 145         switch (hw->mac.type) {
 146         case e1000_82571:
 147         case e1000_82572:
 148                 if (phy->id != IGP01E1000_I_PHY_ID)
 149                         ret_val = -E1000_ERR_PHY;
 150                 break;
 151         case e1000_82573:
 152                 if (phy->id != M88E1111_I_PHY_ID)
 153                         ret_val = -E1000_ERR_PHY;
 154                 break;
 155         case e1000_82574:
 156         case e1000_82583:
 157                 if (phy->id != BME1000_E_PHY_ID_R2)
 158                         ret_val = -E1000_ERR_PHY;
 159                 break;
 160         default:
 161                 ret_val = -E1000_ERR_PHY;
 162                 break;
 163         }
 164
 165         if (ret_val)
 166                 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 167
 168         return ret_val;
 169 }
 170
 171 /**
 172  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 173  *  @hw: pointer to the HW structure
 174  **/
 175 STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 176 {
 177         struct e1000_nvm_info *nvm = &hw->nvm;
 178         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 179         u16 size;
 180
 181         DEBUGFUNC("e1000_init_nvm_params_82571");
 182
 183         nvm->opcode_bits = 8;
 184         nvm->delay_usec = 1;
 185         switch (nvm->override) {
 186         case e1000_nvm_override_spi_large:
 187                 nvm->page_size = 32;
 188                 nvm->address_bits = 16;
 189                 break;
 190         case e1000_nvm_override_spi_small:
 191                 nvm->page_size = 8;
 192                 nvm->address_bits = 8;
 193                 break;
 194         default:
 195                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 196                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 197                 break;
 198         }
 199
 200         switch (hw->mac.type) {
 201         case e1000_82573:
 202         case e1000_82574:
 203         case e1000_82583:
 204                 if (((eecd >> 15) & 0x3) == 0x3) {
 205                         nvm->type = e1000_nvm_flash_hw;
 206                         nvm->word_size = 2048;
 207                         /* Autonomous Flash update bit must be cleared due
 208                          * to Flash update issue.
 209                          */
 210                         eecd &= ~E1000_EECD_AUPDEN;
 211                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 212                         break;
 213                 }
 214                 /* Fall Through */
 215         default:
 216                 nvm->type = e1000_nvm_eeprom_spi;
 217                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 218                              E1000_EECD_SIZE_EX_SHIFT);
 219                 /* Added to a constant, "size" becomes the left-shift value
 220                  * for setting word_size.
 221                  */
 222                 size += NVM_WORD_SIZE_BASE_SHIFT;
 223
 224                 /* EEPROM access above 16k is unsupported */
 225                 if (size > 14)
 226                         size = 14;
 227                 nvm->word_size = 1 << size;
 228                 break;
 229         }
 230
 231         /* Function Pointers */
 232         switch (hw->mac.type) {
 233         case e1000_82574:
 234         case e1000_82583:
 235                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 236                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 237                 break;
 238         default:
 239                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 240                 nvm->ops.release = e1000_release_nvm_82571;
 241                 break;
 242         }
 243         nvm->ops.read = e1000_read_nvm_eerd;
 244         nvm->ops.update = e1000_update_nvm_checksum_82571;
 245         nvm->ops.validate = e1000_validate_nvm_checksum_82571;
 246         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 247         nvm->ops.write = e1000_write_nvm_82571;
 248
 249         return E1000_SUCCESS;
 250 }
 251
 252 /**
 253  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 254  *  @hw: pointer to the HW structure
 255  **/
 256 STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 257 {
 258         struct e1000_mac_info *mac = &hw->mac;
 259         u32 swsm = 0;
 260         u32 swsm2 = 0;
 261         bool force_clear_smbi = false;
 262
 263         DEBUGFUNC("e1000_init_mac_params_82571");
 264
 265         /* Set media type and media-dependent function pointers */
 266         switch (hw->device_id) {
 267         case E1000_DEV_ID_82571EB_FIBER:
 268         case E1000_DEV_ID_82572EI_FIBER:
 269         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 270                 hw->phy.media_type = e1000_media_type_fiber;
 271                 mac->ops.setup_physical_interface =
 272                         e1000_setup_fiber_serdes_link_82571;
 273                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 274                 mac->ops.get_link_up_info =
 275                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 276                 break;
 277         case E1000_DEV_ID_82571EB_SERDES:
 278         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 279         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 280         case E1000_DEV_ID_82572EI_SERDES:
 281                 hw->phy.media_type = e1000_media_type_internal_serdes;
 282                 mac->ops.setup_physical_interface =
 283                         e1000_setup_fiber_serdes_link_82571;
 284                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 285                 mac->ops.get_link_up_info =
 286                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 287                 break;
 288         default:
 289                 hw->phy.media_type = e1000_media_type_copper;
 290                 mac->ops.setup_physical_interface =
 291                         e1000_setup_copper_link_82571;
 292                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 293                 mac->ops.get_link_up_info =
 294                         e1000_get_speed_and_duplex_copper_generic;
 295                 break;
 296         }
 297
 298         /* Set mta register count */
 299         mac->mta_reg_count = 128;
 300         /* Set rar entry count */
 301         mac->rar_entry_count = E1000_RAR_ENTRIES;
 302         /* Set if part includes ASF firmware */
 303         mac->asf_firmware_present = true;
 304         /* Adaptive IFS supported */
 305         mac->adaptive_ifs = true;
 306
 307         /* Function pointers */
 308
 309         /* bus type/speed/width */
 310         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 311         /* reset */
 312         mac->ops.reset_hw = e1000_reset_hw_82571;
 313         /* hw initialization */
 314         mac->ops.init_hw = e1000_init_hw_82571;
 315         /* link setup */
 316         mac->ops.setup_link = e1000_setup_link_82571;
 317         /* multicast address update */
 318         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 319         /* writing VFTA */
 320         mac->ops.write_vfta = e1000_write_vfta_generic;
 321         /* clearing VFTA */
 322         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 323         /* read mac address */
 324         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 325         /* ID LED init */
 326         mac->ops.id_led_init = e1000_id_led_init_generic;
 327         /* setup LED */
 328         mac->ops.setup_led = e1000_setup_led_generic;
 329         /* cleanup LED */
 330         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 331         /* turn off LED */
 332         mac->ops.led_off = e1000_led_off_generic;
 333         /* clear hardware counters */
 334         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 335
 336         /* MAC-specific function pointers */
 337         switch (hw->mac.type) {
 338         case e1000_82573:
 339                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 340                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 341                 mac->ops.led_on = e1000_led_on_generic;
 342                 mac->ops.blink_led = e1000_blink_led_generic;
 343
 344                 /* FWSM register */
 345                 mac->has_fwsm = true;
 346                 /* ARC supported; valid only if manageability features are
 347                  * enabled.
 348                  */
 349                 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
 350                                               E1000_FWSM_MODE_MASK);
 351                 break;
 352         case e1000_82574:
 353         case e1000_82583:
 354                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 355                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 356                 mac->ops.led_on = e1000_led_on_82574;
 357                 break;
 358         default:
 359                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 360                 mac->ops.led_on = e1000_led_on_generic;
 361                 mac->ops.blink_led = e1000_blink_led_generic;
 362
 363                 /* FWSM register */
 364                 mac->has_fwsm = true;
 365                 break;
 366         }
 367
 368         /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 369          * first NVM or PHY access. This should be done for single-port
 370          * devices, and for one port only on dual-port devices so that
 371          * for those devices we can still use the SMBI lock to synchronize
 372          * inter-port accesses to the PHY & NVM.
 373          */
 374         switch (hw->mac.type) {
 375         case e1000_82571:
 376         case e1000_82572:
 377                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 378
 379                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 380                         /* Only do this for the first interface on this card */
 381                         E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
 382                                         E1000_SWSM2_LOCK);
 383                         force_clear_smbi = true;
 384                 } else {
 385                         force_clear_smbi = false;
 386                 }
 387                 break;
 388         default:
 389                 force_clear_smbi = true;
 390                 break;
 391         }
 392
 393         if (force_clear_smbi) {
 394                 /* Make sure SWSM.SMBI is clear */
 395                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 396                 if (swsm & E1000_SWSM_SMBI) {
 397                         /* This bit should not be set on a first interface, and
 398                          * indicates that the bootagent or EFI code has
 399                          * improperly left this bit enabled
 400                          */
 401                         DEBUGOUT("Please update your 82571 Bootagent\n");
 402                 }
 403                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 404         }
 405
 406         /* Initialze device specific counter of SMBI acquisition timeouts. */
 407          hw->dev_spec._82571.smb_counter = 0;
 408
 409         return E1000_SUCCESS;
 410 }
 411
 412 /**
 413  *  e1000_init_function_pointers_82571 - Init func ptrs.
 414  *  @hw: pointer to the HW structure
 415  *
 416  *  Called to initialize all function pointers and parameters.
 417  **/
 418 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 419 {
 420         DEBUGFUNC("e1000_init_function_pointers_82571");
 421
 422         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 423         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 424         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 425 }
 426
 427 /**
 428  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 429  *  @hw: pointer to the HW structure
 430  *
 431  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 432  *  revision in the hardware structure.
 433  **/
 434 STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 435 {
 436         struct e1000_phy_info *phy = &hw->phy;
 437         s32 ret_val;
 438         u16 phy_id = 0;
 439
 440         DEBUGFUNC("e1000_get_phy_id_82571");
 441
 442         switch (hw->mac.type) {
 443         case e1000_82571:
 444         case e1000_82572:
 445                 /* The 82571 firmware may still be configuring the PHY.
 446                  * In this case, we cannot access the PHY until the
 447                  * configuration is done.  So we explicitly set the
 448                  * PHY ID.
 449                  */
 450                 phy->id = IGP01E1000_I_PHY_ID;
 451                 break;
 452         case e1000_82573:
 453                 return e1000_get_phy_id(hw);
 454                 break;
 455         case e1000_82574:
 456         case e1000_82583:
 457                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 458                 if (ret_val)
 459                         return ret_val;
 460
 461                 phy->id = (u32)(phy_id << 16);
 462                 usec_delay(20);
 463                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 464                 if (ret_val)
 465                         return ret_val;
 466
 467                 phy->id |= (u32)(phy_id);
 468                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 469                 break;
 470         default:
 471                 return -E1000_ERR_PHY;
 472                 break;
 473         }
 474
 475         return E1000_SUCCESS;
 476 }
 477
 478 /**
 479  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 480  *  @hw: pointer to the HW structure
 481  *
 482  *  Acquire the HW semaphore to access the PHY or NVM
 483  **/
 484 STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 485 {
 486         u32 swsm;
 487         s32 sw_timeout = hw->nvm.word_size + 1;
 488         s32 fw_timeout = hw->nvm.word_size + 1;
 489         s32 i = 0;
 490
 491         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 492
 493         /* If we have timedout 3 times on trying to acquire
 494          * the inter-port SMBI semaphore, there is old code
 495          * operating on the other port, and it is not
 496          * releasing SMBI. Modify the number of times that
 497          * we try for the semaphore to interwork with this
 498          * older code.
 499          */
 500         if (hw->dev_spec._82571.smb_counter > 2)
 501                 sw_timeout = 1;
 502
 503         /* Get the SW semaphore */
 504         while (i < sw_timeout) {
 505                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 506                 if (!(swsm & E1000_SWSM_SMBI))
 507                         break;
 508
 509                 usec_delay(50);
 510                 i++;
 511         }
 512
 513         if (i == sw_timeout) {
 514                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 515                 hw->dev_spec._82571.smb_counter++;
 516         }
 517         /* Get the FW semaphore. */
 518         for (i = 0; i < fw_timeout; i++) {
 519                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 520                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 521
 522                 /* Semaphore acquired if bit latched */
 523                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 524                         break;
 525
 526                 usec_delay(50);
 527         }
 528
 529         if (i == fw_timeout) {
 530                 /* Release semaphores */
 531                 e1000_put_hw_semaphore_82571(hw);
 532                 DEBUGOUT("Driver can't access the NVM\n");
 533                 return -E1000_ERR_NVM;
 534         }
 535
 536         return E1000_SUCCESS;
 537 }
 538
 539 /**
 540  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 541  *  @hw: pointer to the HW structure
 542  *
 543  *  Release hardware semaphore used to access the PHY or NVM
 544  **/
 545 STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 546 {
 547         u32 swsm;
 548
 549         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 550
 551         swsm = E1000_READ_REG(hw, E1000_SWSM);
 552
 553         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 554
 555         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 556 }
 557
 558 /**
 559  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 560  *  @hw: pointer to the HW structure
 561  *
 562  *  Acquire the HW semaphore during reset.
 563  *
 564  **/
 565 STATIC s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 566 {
 567         u32 extcnf_ctrl;
 568         s32 i = 0;
 569
 570         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 571
 572         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 573         do {
 574                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 575                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 576                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 577
 578                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 579                         break;
 580
 581                 msec_delay(2);
 582                 i++;
 583         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 584
 585         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 586                 /* Release semaphores */
 587                 e1000_put_hw_semaphore_82573(hw);
 588                 DEBUGOUT("Driver can't access the PHY\n");
 589                 return -E1000_ERR_PHY;
 590         }
 591
 592         return E1000_SUCCESS;
 593 }
 594
 595 /**
 596  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 597  *  @hw: pointer to the HW structure
 598  *
 599  *  Release hardware semaphore used during reset.
 600  *
 601  **/
 602 STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 603 {
 604         u32 extcnf_ctrl;
 605
 606         DEBUGFUNC("e1000_put_hw_semaphore_82573");
 607
 608         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 609         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 610         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 611 }
 612
 613 /**
 614  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 615  *  @hw: pointer to the HW structure
 616  *
 617  *  Acquire the HW semaphore to access the PHY or NVM.
 618  *
 619  **/
 620 STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 621 {
 622         s32 ret_val;
 623
 624         DEBUGFUNC("e1000_get_hw_semaphore_82574");
 625
 626         E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
 627         ret_val = e1000_get_hw_semaphore_82573(hw);
 628         if (ret_val)
 629                 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 630         return ret_val;
 631 }
 632
 633 /**
 634  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 635  *  @hw: pointer to the HW structure
 636  *
 637  *  Release hardware semaphore used to access the PHY or NVM
 638  *
 639  **/
 640 STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 641 {
 642         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 643
 644         e1000_put_hw_semaphore_82573(hw);
 645         E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 646 }
 647
 648 /**
 649  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 650  *  @hw: pointer to the HW structure
 651  *  @active: true to enable LPLU, false to disable
 652  *
 653  *  Sets the LPLU D0 state according to the active flag.
 654  *  LPLU will not be activated unless the
 655  *  device autonegotiation advertisement meets standards of
 656  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 657  *  This is a function pointer entry point only called by
 658  *  PHY setup routines.
 659  **/
 660 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 661 {
 662         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 663
 664         DEBUGFUNC("e1000_set_d0_lplu_state_82574");
 665
 666         if (active)
 667                 data |= E1000_PHY_CTRL_D0A_LPLU;
 668         else
 669                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 670
 671         E1000_WRITE_REG(hw, E1000_POEMB, data);
 672         return E1000_SUCCESS;
 673 }
 674
 675 /**
 676  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 677  *  @hw: pointer to the HW structure
 678  *  @active: boolean used to enable/disable lplu
 679  *
 680  *  The low power link up (lplu) state is set to the power management level D3
 681  *  when active is true, else clear lplu for D3. LPLU
 682  *  is used during Dx states where the power conservation is most important.
 683  *  During driver activity, SmartSpeed should be enabled so performance is
 684  *  maintained.
 685  **/
 686 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 687 {
 688         u32 data = E1000_READ_REG(hw, E1000_POEMB);
 689
 690         DEBUGFUNC("e1000_set_d3_lplu_state_82574");
 691
 692         if (!active) {
 693                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 694         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 695                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 696                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 697                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 698         }
 699
 700         E1000_WRITE_REG(hw, E1000_POEMB, data);
 701         return E1000_SUCCESS;
 702 }
 703
 704 /**
 705  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 706  *  @hw: pointer to the HW structure
 707  *
 708  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 709  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 710  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 711  *  hardware semaphore.
 712  **/
 713 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 714 {
 715         s32 ret_val;
 716
 717         DEBUGFUNC("e1000_acquire_nvm_82571");
 718
 719         ret_val = e1000_get_hw_semaphore_82571(hw);
 720         if (ret_val)
 721                 return ret_val;
 722
 723         switch (hw->mac.type) {
 724         case e1000_82573:
 725                 break;
 726         default:
 727                 ret_val = e1000_acquire_nvm_generic(hw);
 728                 break;
 729         }
 730
 731         if (ret_val)
 732                 e1000_put_hw_semaphore_82571(hw);
 733
 734         return ret_val;
 735 }
 736
 737 /**
 738  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 739  *  @hw: pointer to the HW structure
 740  *
 741  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 742  **/
 743 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw)
 744 {
 745         DEBUGFUNC("e1000_release_nvm_82571");
 746
 747         e1000_release_nvm_generic(hw);
 748         e1000_put_hw_semaphore_82571(hw);
 749 }
 750
 751 /**
 752  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 753  *  @hw: pointer to the HW structure
 754  *  @offset: offset within the EEPROM to be written to
 755  *  @words: number of words to write
 756  *  @data: 16 bit word(s) to be written to the EEPROM
 757  *
 758  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 759  *
 760  *  If e1000_update_nvm_checksum is not called after this function, the
 761  *  EEPROM will most likely contain an invalid checksum.
 762  **/
 763 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 764                                  u16 *data)
 765 {
 766         s32 ret_val;
 767
 768         DEBUGFUNC("e1000_write_nvm_82571");
 769
 770         switch (hw->mac.type) {
 771         case e1000_82573:
 772         case e1000_82574:
 773         case e1000_82583:
 774                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 775                 break;
 776         case e1000_82571:
 777         case e1000_82572:
 778                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 779                 break;
 780         default:
 781                 ret_val = -E1000_ERR_NVM;
 782                 break;
 783         }
 784
 785         return ret_val;
 786 }
 787
 788 /**
 789  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 790  *  @hw: pointer to the HW structure
 791  *
 792  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 793  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 794  *  value to the EEPROM.
 795  **/
 796 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 797 {
 798         u32 eecd;
 799         s32 ret_val;
 800         u16 i;
 801
 802         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 803
 804         ret_val = e1000_update_nvm_checksum_generic(hw);
 805         if (ret_val)
 806                 return ret_val;
 807
 808         /* If our nvm is an EEPROM, then we're done
 809          * otherwise, commit the checksum to the flash NVM.
 810          */
 811         if (hw->nvm.type != e1000_nvm_flash_hw)
 812                 return E1000_SUCCESS;
 813
 814         /* Check for pending operations. */
 815         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 816                 msec_delay(1);
 817                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 818                         break;
 819         }
 820
 821         if (i == E1000_FLASH_UPDATES)
 822                 return -E1000_ERR_NVM;
 823
 824         /* Reset the firmware if using STM opcode. */
 825         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 826                 /* The enabling of and the actual reset must be done
 827                  * in two write cycles.
 828                  */
 829                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 830                 E1000_WRITE_FLUSH(hw);
 831                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 832         }
 833
 834         /* Commit the write to flash */
 835         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 836         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 837
 838         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 839                 msec_delay(1);
 840                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
 841                         break;
 842         }
 843
 844         if (i == E1000_FLASH_UPDATES)
 845                 return -E1000_ERR_NVM;
 846
 847         return E1000_SUCCESS;
 848 }
 849
 850 /**
 851  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 852  *  @hw: pointer to the HW structure
 853  *
 854  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 855  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 856  **/
 857 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 858 {
 859         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 860
 861         if (hw->nvm.type == e1000_nvm_flash_hw)
 862                 e1000_fix_nvm_checksum_82571(hw);
 863
 864         return e1000_validate_nvm_checksum_generic(hw);
 865 }
 866
 867 /**
 868  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 869  *  @hw: pointer to the HW structure
 870  *  @offset: offset within the EEPROM to be written to
 871  *  @words: number of words to write
 872  *  @data: 16 bit word(s) to be written to the EEPROM
 873  *
 874  *  After checking for invalid values, poll the EEPROM to ensure the previous
 875  *  command has completed before trying to write the next word.  After write
 876  *  poll for completion.
 877  *
 878  *  If e1000_update_nvm_checksum is not called after this function, the
 879  *  EEPROM will most likely contain an invalid checksum.
 880  **/
 881 STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 882                                       u16 words, u16 *data)
 883 {
 884         struct e1000_nvm_info *nvm = &hw->nvm;
 885         u32 i, eewr = 0;
 886         s32 ret_val = E1000_SUCCESS;
 887
 888         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 889
 890         /* A check for invalid values:  offset too large, too many words,
 891          * and not enough words.
 892          */
 893         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 894             (words == 0)) {
 895                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 896                 return -E1000_ERR_NVM;
 897         }
 898
 899         for (i = 0; i < words; i++) {
 900                 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
 901                         ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
 902                         E1000_NVM_RW_REG_START);
 903
 904                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 905                 if (ret_val)
 906                         break;
 907
 908                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 909
 910                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 911                 if (ret_val)
 912                         break;
 913         }
 914
 915         return ret_val;
 916 }
 917
 918 /**
 919  *  e1000_get_cfg_done_82571 - Poll for configuration done
 920  *  @hw: pointer to the HW structure
 921  *
 922  *  Reads the management control register for the config done bit to be set.
 923  **/
 924 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 925 {
 926         s32 timeout = PHY_CFG_TIMEOUT;
 927
 928         DEBUGFUNC("e1000_get_cfg_done_82571");
 929
 930         while (timeout) {
 931                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 932                     E1000_NVM_CFG_DONE_PORT_0)
 933                         break;
 934                 msec_delay(1);
 935                 timeout--;
 936         }
 937         if (!timeout) {
 938                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 939                 return -E1000_ERR_RESET;
 940         }
 941
 942         return E1000_SUCCESS;
 943 }
 944
 945 /**
 946  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 947  *  @hw: pointer to the HW structure
 948  *  @active: true to enable LPLU, false to disable
 949  *
 950  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 951  *  this function also disables smart speed and vice versa.  LPLU will not be
 952  *  activated unless the device autonegotiation advertisement meets standards
 953  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 954  *  pointer entry point only called by PHY setup routines.
 955  **/
 956 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 957 {
 958         struct e1000_phy_info *phy = &hw->phy;
 959         s32 ret_val;
 960         u16 data;
 961
 962         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 963
 964         if (!(phy->ops.read_reg))
 965                 return E1000_SUCCESS;
 966
 967         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 968         if (ret_val)
 969                 return ret_val;
 970
 971         if (active) {
 972                 data |= IGP02E1000_PM_D0_LPLU;
 973                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 974                                              data);
 975                 if (ret_val)
 976                         return ret_val;
 977
 978                 /* When LPLU is enabled, we should disable SmartSpeed */
 979                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 980                                             &data);
 981                 if (ret_val)
 982                         return ret_val;
 983                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 984                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 985                                              data);
 986                 if (ret_val)
 987                         return ret_val;
 988         } else {
 989                 data &= ~IGP02E1000_PM_D0_LPLU;
 990                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 991                                              data);
 992                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 993                  * during Dx states where the power conservation is most
 994                  * important.  During driver activity we should enable
 995                  * SmartSpeed, so performance is maintained.
 996                  */
 997                 if (phy->smart_speed == e1000_smart_speed_on) {
 998                         ret_val = phy->ops.read_reg(hw,
 999                                                     IGP01E1000_PHY_PORT_CONFIG,
1000                                                     &data);
1001                         if (ret_val)
1002                                 return ret_val;
1003
1004                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1005                         ret_val = phy->ops.write_reg(hw,
1006                                                      IGP01E1000_PHY_PORT_CONFIG,
1007                                                      data);
1008                         if (ret_val)
1009                                 return ret_val;
1010                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1011                         ret_val = phy->ops.read_reg(hw,
1012                                                     IGP01E1000_PHY_PORT_CONFIG,
1013                                                     &data);
1014                         if (ret_val)
1015                                 return ret_val;
1016
1017                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1018                         ret_val = phy->ops.write_reg(hw,
1019                                                      IGP01E1000_PHY_PORT_CONFIG,
1020                                                      data);
1021                         if (ret_val)
1022                                 return ret_val;
1023                 }
1024         }
1025
1026         return E1000_SUCCESS;
1027 }
1028
1029 /**
1030  *  e1000_reset_hw_82571 - Reset hardware
1031  *  @hw: pointer to the HW structure
1032  *
1033  *  This resets the hardware into a known state.
1034  **/
1035 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1036 {
1037         u32 ctrl, ctrl_ext, eecd, tctl;
1038         s32 ret_val;
1039
1040         DEBUGFUNC("e1000_reset_hw_82571");
1041
1042         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1043          * on the last TLP read/write transaction when MAC is reset.
1044          */
1045         ret_val = e1000_disable_pcie_master_generic(hw);
1046         if (ret_val)
1047                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1048
1049         DEBUGOUT("Masking off all interrupts\n");
1050         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1051
1052         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1053         tctl = E1000_READ_REG(hw, E1000_TCTL);
1054         tctl &= ~E1000_TCTL_EN;
1055         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1056         E1000_WRITE_FLUSH(hw);
1057
1058         msec_delay(10);
1059
1060         /* Must acquire the MDIO ownership before MAC reset.
1061          * Ownership defaults to firmware after a reset.
1062          */
1063         switch (hw->mac.type) {
1064         case e1000_82573:
1065                 ret_val = e1000_get_hw_semaphore_82573(hw);
1066                 break;
1067         case e1000_82574:
1068         case e1000_82583:
1069                 ret_val = e1000_get_hw_semaphore_82574(hw);
1070                 break;
1071         default:
1072                 break;
1073         }
1074
1075         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1076
1077         DEBUGOUT("Issuing a global reset to MAC\n");
1078         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1079
1080         /* Must release MDIO ownership and mutex after MAC reset. */
1081         switch (hw->mac.type) {
1082         case e1000_82573:
1083                 /* Release mutex only if the hw semaphore is acquired */
1084                 if (!ret_val)
1085                         e1000_put_hw_semaphore_82573(hw);
1086                 break;
1087         case e1000_82574:
1088         case e1000_82583:
1089                 /* Release mutex only if the hw semaphore is acquired */
1090                 if (!ret_val)
1091                         e1000_put_hw_semaphore_82574(hw);
1092                 break;
1093         default:
1094                 break;
1095         }
1096
1097         if (hw->nvm.type == e1000_nvm_flash_hw) {
1098                 usec_delay(10);
1099                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1100                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1101                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1102                 E1000_WRITE_FLUSH(hw);
1103         }
1104
1105         ret_val = e1000_get_auto_rd_done_generic(hw);
1106         if (ret_val)
1107                 /* We don't want to continue accessing MAC registers. */
1108                 return ret_val;
1109
1110         /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1111          * Need to wait for Phy configuration completion before accessing
1112          * NVM and Phy.
1113          */
1114
1115         switch (hw->mac.type) {
1116         case e1000_82571:
1117         case e1000_82572:
1118                 /* REQ and GNT bits need to be cleared when using AUTO_RD
1119                  * to access the EEPROM.
1120                  */
1121                 eecd = E1000_READ_REG(hw, E1000_EECD);
1122                 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1123                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1124                 break;
1125         case e1000_82573:
1126         case e1000_82574:
1127         case e1000_82583:
1128                 msec_delay(25);
1129                 break;
1130         default:
1131                 break;
1132         }
1133
1134         /* Clear any pending interrupt events. */
1135         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1136         E1000_READ_REG(hw, E1000_ICR);
1137
1138         if (hw->mac.type == e1000_82571) {
1139                 /* Install any alternate MAC address into RAR0 */
1140                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1141                 if (ret_val)
1142                         return ret_val;
1143
1144                 e1000_set_laa_state_82571(hw, true);
1145         }
1146
1147         /* Reinitialize the 82571 serdes link state machine */
1148         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1149                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1150
1151         return E1000_SUCCESS;
1152 }
1153
1154 /**
1155  *  e1000_init_hw_82571 - Initialize hardware
1156  *  @hw: pointer to the HW structure
1157  *
1158  *  This inits the hardware readying it for operation.
1159  **/
1160 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
1161 {
1162         struct e1000_mac_info *mac = &hw->mac;
1163         u32 reg_data;
1164         s32 ret_val;
1165         u16 i, rar_count = mac->rar_entry_count;
1166
1167         DEBUGFUNC("e1000_init_hw_82571");
1168
1169         e1000_initialize_hw_bits_82571(hw);
1170
1171         /* Initialize identification LED */
1172         ret_val = mac->ops.id_led_init(hw);
1173         /* An error is not fatal and we should not stop init due to this */
1174         if (ret_val)
1175                 DEBUGOUT("Error initializing identification LED\n");
1176
1177         /* Disabling VLAN filtering */
1178         DEBUGOUT("Initializing the IEEE VLAN\n");
1179         mac->ops.clear_vfta(hw);
1180
1181         /* Setup the receive address.
1182          * If, however, a locally administered address was assigned to the
1183          * 82571, we must reserve a RAR for it to work around an issue where
1184          * resetting one port will reload the MAC on the other port.
1185          */
1186         if (e1000_get_laa_state_82571(hw))
1187                 rar_count--;
1188         e1000_init_rx_addrs_generic(hw, rar_count);
1189
1190         /* Zero out the Multicast HASH table */
1191         DEBUGOUT("Zeroing the MTA\n");
1192         for (i = 0; i < mac->mta_reg_count; i++)
1193                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1194
1195         /* Setup link and flow control */
1196         ret_val = mac->ops.setup_link(hw);
1197
1198         /* Set the transmit descriptor write-back policy */
1199         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1200         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1201                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1202         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1203
1204         /* ...for both queues. */
1205         switch (mac->type) {
1206         case e1000_82573:
1207                 e1000_enable_tx_pkt_filtering_generic(hw);
1208                 /* fall through */
1209         case e1000_82574:
1210         case e1000_82583:
1211                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1212                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1213                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1214                 break;
1215         default:
1216                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1217                 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1218                             E1000_TXDCTL_FULL_TX_DESC_WB |
1219                             E1000_TXDCTL_COUNT_DESC);
1220                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1221                 break;
1222         }
1223
1224         /* Clear all of the statistics registers (clear on read).  It is
1225          * important that we do this after we have tried to establish link
1226          * because the symbol error count will increment wildly if there
1227          * is no link.
1228          */
1229         e1000_clear_hw_cntrs_82571(hw);
1230
1231         /* MSI-X configure for 82574 */
1232         if (mac->type == e1000_82574)
1233                 E1000_WRITE_REG(hw, E1000_IVAR,
1234                                 (E1000_IVAR_INT_ALLOC_VALID << 16));
1235
1236         return ret_val;
1237 }
1238
1239 /**
1240  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1241  *  @hw: pointer to the HW structure
1242  *
1243  *  Initializes required hardware-dependent bits needed for normal operation.
1244  **/
1245 STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1246 {
1247         u32 reg;
1248
1249         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1250
1251         /* Transmit Descriptor Control 0 */
1252         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1253         reg |= (1 << 22);
1254         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1255
1256         /* Transmit Descriptor Control 1 */
1257         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1258         reg |= (1 << 22);
1259         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1260
1261         /* Transmit Arbitration Control 0 */
1262         reg = E1000_READ_REG(hw, E1000_TARC(0));
1263         reg &= ~(0xF << 27); /* 30:27 */
1264         switch (hw->mac.type) {
1265         case e1000_82571:
1266         case e1000_82572:
1267                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1268                 break;
1269         case e1000_82574:
1270         case e1000_82583:
1271                 reg |= (1 << 26);
1272                 break;
1273         default:
1274                 break;
1275         }
1276         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1277
1278         /* Transmit Arbitration Control 1 */
1279         reg = E1000_READ_REG(hw, E1000_TARC(1));
1280         switch (hw->mac.type) {
1281         case e1000_82571:
1282         case e1000_82572:
1283                 reg &= ~((1 << 29) | (1 << 30));
1284                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1285                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1286                         reg &= ~(1 << 28);
1287                 else
1288                         reg |= (1 << 28);
1289                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1290                 break;
1291         default:
1292                 break;
1293         }
1294
1295         /* Device Control */
1296         switch (hw->mac.type) {
1297         case e1000_82573:
1298         case e1000_82574:
1299         case e1000_82583:
1300                 reg = E1000_READ_REG(hw, E1000_CTRL);
1301                 reg &= ~(1 << 29);
1302                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1303                 break;
1304         default:
1305                 break;
1306         }
1307
1308         /* Extended Device Control */
1309         switch (hw->mac.type) {
1310         case e1000_82573:
1311         case e1000_82574:
1312         case e1000_82583:
1313                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1314                 reg &= ~(1 << 23);
1315                 reg |= (1 << 22);
1316                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1317                 break;
1318         default:
1319                 break;
1320         }
1321
1322         if (hw->mac.type == e1000_82571) {
1323                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1324                 reg |= E1000_PBA_ECC_CORR_EN;
1325                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1326         }
1327
1328         /* Workaround for hardware errata.
1329          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1330          */
1331         if ((hw->mac.type == e1000_82571) ||
1332            (hw->mac.type == e1000_82572)) {
1333                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1334                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1335                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1336         }
1337
1338         /* Disable IPv6 extension header parsing because some malformed
1339          * IPv6 headers can hang the Rx.
1340          */
1341         if (hw->mac.type <= e1000_82573) {
1342                 reg = E1000_READ_REG(hw, E1000_RFCTL);
1343                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1344                 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1345         }
1346
1347         /* PCI-Ex Control Registers */
1348         switch (hw->mac.type) {
1349         case e1000_82574:
1350         case e1000_82583:
1351                 reg = E1000_READ_REG(hw, E1000_GCR);
1352                 reg |= (1 << 22);
1353                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1354
1355                 /* Workaround for hardware errata.
1356                  * apply workaround for hardware errata documented in errata
1357                  * docs Fixes issue where some error prone or unreliable PCIe
1358                  * completions are occurring, particularly with ASPM enabled.
1359                  * Without fix, issue can cause Tx timeouts.
1360                  */
1361                 reg = E1000_READ_REG(hw, E1000_GCR2);
1362                 reg |= 1;
1363                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1364                 break;
1365         default:
1366                 break;
1367         }
1368
1369         return;
1370 }
1371
1372 /**
1373  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1374  *  @hw: pointer to the HW structure
1375  *
1376  *  Clears the register array which contains the VLAN filter table by
1377  *  setting all the values to 0.
1378  **/
1379 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw)
1380 {
1381         u32 offset;
1382         u32 vfta_value = 0;
1383         u32 vfta_offset = 0;
1384         u32 vfta_bit_in_reg = 0;
1385
1386         DEBUGFUNC("e1000_clear_vfta_82571");
1387
1388         switch (hw->mac.type) {
1389         case e1000_82573:
1390         case e1000_82574:
1391         case e1000_82583:
1392                 if (hw->mng_cookie.vlan_id != 0) {
1393                         /* The VFTA is a 4096b bit-field, each identifying
1394                          * a single VLAN ID.  The following operations
1395                          * determine which 32b entry (i.e. offset) into the
1396                          * array we want to set the VLAN ID (i.e. bit) of
1397                          * the manageability unit.
1398                          */
1399                         vfta_offset = (hw->mng_cookie.vlan_id >>
1400                                        E1000_VFTA_ENTRY_SHIFT) &
1401                             E1000_VFTA_ENTRY_MASK;
1402                         vfta_bit_in_reg =
1403                             1 << (hw->mng_cookie.vlan_id &
1404                                   E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1405                 }
1406                 break;
1407         default:
1408                 break;
1409         }
1410         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1411                 /* If the offset we want to clear is the same offset of the
1412                  * manageability VLAN ID, then clear all bits except that of
1413                  * the manageability unit.
1414                  */
1415                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1416                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1417                 E1000_WRITE_FLUSH(hw);
1418         }
1419 }
1420
1421 /**
1422  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1423  *  @hw: pointer to the HW structure
1424  *
1425  *  Reads the NVM Initialization Control Word 2 and returns true
1426  *  (>0) if any manageability is enabled, else false (0).
1427  **/
1428 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1429 {
1430         u16 data;
1431         s32 ret_val;
1432
1433         DEBUGFUNC("e1000_check_mng_mode_82574");
1434
1435         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1436         if (ret_val)
1437                 return false;
1438
1439         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1440 }
1441
1442 /**
1443  *  e1000_led_on_82574 - Turn LED on
1444  *  @hw: pointer to the HW structure
1445  *
1446  *  Turn LED on.
1447  **/
1448 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw)
1449 {
1450         u32 ctrl;
1451         u32 i;
1452
1453         DEBUGFUNC("e1000_led_on_82574");
1454
1455         ctrl = hw->mac.ledctl_mode2;
1456         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1457                 /* If no link, then turn LED on by setting the invert bit
1458                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1459                  */
1460                 for (i = 0; i < 4; i++)
1461                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1462                             E1000_LEDCTL_MODE_LED_ON)
1463                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1464         }
1465         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1466
1467         return E1000_SUCCESS;
1468 }
1469
1470 /**
1471  *  e1000_check_phy_82574 - check 82574 phy hung state
1472  *  @hw: pointer to the HW structure
1473  *
1474  *  Returns whether phy is hung or not
1475  **/
1476 bool e1000_check_phy_82574(struct e1000_hw *hw)
1477 {
1478         u16 status_1kbt = 0;
1479         u16 receive_errors = 0;
1480         s32 ret_val;
1481
1482         DEBUGFUNC("e1000_check_phy_82574");
1483
1484         /* Read PHY Receive Error counter first, if its is max - all F's then
1485          * read the Base1000T status register If both are max then PHY is hung.
1486          */
1487         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1488                                        &receive_errors);
1489         if (ret_val)
1490                 return false;
1491         if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1492                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1493                                                &status_1kbt);
1494                 if (ret_val)
1495                         return false;
1496                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1497                     E1000_IDLE_ERROR_COUNT_MASK)
1498                         return true;
1499         }
1500
1501         return false;
1502 }
1503
1504
1505 /**
1506  *  e1000_setup_link_82571 - Setup flow control and link settings
1507  *  @hw: pointer to the HW structure
1508  *
1509  *  Determines which flow control settings to use, then configures flow
1510  *  control.  Calls the appropriate media-specific link configuration
1511  *  function.  Assuming the adapter has a valid link partner, a valid link
1512  *  should be established.  Assumes the hardware has previously been reset
1513  *  and the transmitter and receiver are not enabled.
1514  **/
1515 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw)
1516 {
1517         DEBUGFUNC("e1000_setup_link_82571");
1518
1519         /* 82573 does not have a word in the NVM to determine
1520          * the default flow control setting, so we explicitly
1521          * set it to full.
1522          */
1523         switch (hw->mac.type) {
1524         case e1000_82573:
1525         case e1000_82574:
1526         case e1000_82583:
1527                 if (hw->fc.requested_mode == e1000_fc_default)
1528                         hw->fc.requested_mode = e1000_fc_full;
1529                 break;
1530         default:
1531                 break;
1532         }
1533
1534         return e1000_setup_link_generic(hw);
1535 }
1536
1537 /**
1538  *  e1000_setup_copper_link_82571 - Configure copper link settings
1539  *  @hw: pointer to the HW structure
1540  *
1541  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1542  *  for link, once link is established calls to configure collision distance
1543  *  and flow control are called.
1544  **/
1545 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1546 {
1547         u32 ctrl;
1548         s32 ret_val;
1549
1550         DEBUGFUNC("e1000_setup_copper_link_82571");
1551
1552         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1553         ctrl |= E1000_CTRL_SLU;
1554         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1555         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1556
1557         switch (hw->phy.type) {
1558         case e1000_phy_m88:
1559         case e1000_phy_bm:
1560                 ret_val = e1000_copper_link_setup_m88(hw);
1561                 break;
1562         case e1000_phy_igp_2:
1563                 ret_val = e1000_copper_link_setup_igp(hw);
1564                 break;
1565         default:
1566                 return -E1000_ERR_PHY;
1567                 break;
1568         }
1569
1570         if (ret_val)
1571                 return ret_val;
1572
1573         return e1000_setup_copper_link_generic(hw);
1574 }
1575
1576 /**
1577  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1578  *  @hw: pointer to the HW structure
1579  *
1580  *  Configures collision distance and flow control for fiber and serdes links.
1581  *  Upon successful setup, poll for link.
1582  **/
1583 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1584 {
1585         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1586
1587         switch (hw->mac.type) {
1588         case e1000_82571:
1589         case e1000_82572:
1590                 /* If SerDes loopback mode is entered, there is no form
1591                  * of reset to take the adapter out of that mode.  So we
1592                  * have to explicitly take the adapter out of loopback
1593                  * mode.  This prevents drivers from twiddling their thumbs
1594                  * if another tool failed to take it out of loopback mode.
1595                  */
1596                 E1000_WRITE_REG(hw, E1000_SCTL,
1597                                 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1598                 break;
1599         default:
1600                 break;
1601         }
1602
1603         return e1000_setup_fiber_serdes_link_generic(hw);
1604 }
1605
1606 /**
1607  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1608  *  @hw: pointer to the HW structure
1609  *
1610  *  Reports the link state as up or down.
1611  *
1612  *  If autonegotiation is supported by the link partner, the link state is
1613  *  determined by the result of autonegotiation. This is the most likely case.
1614  *  If autonegotiation is not supported by the link partner, and the link
1615  *  has a valid signal, force the link up.
1616  *
1617  *  The link state is represented internally here by 4 states:
1618  *
1619  *  1) down
1620  *  2) autoneg_progress
1621  *  3) autoneg_complete (the link successfully autonegotiated)
1622  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1623  *
1624  **/
1625 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1626 {
1627         struct e1000_mac_info *mac = &hw->mac;
1628         u32 rxcw;
1629         u32 ctrl;
1630         u32 status;
1631         u32 txcw;
1632         u32 i;
1633         s32 ret_val = E1000_SUCCESS;
1634
1635         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1636
1637         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1638         status = E1000_READ_REG(hw, E1000_STATUS);
1639         E1000_READ_REG(hw, E1000_RXCW);
1640         /* SYNCH bit and IV bit are sticky */
1641         usec_delay(10);
1642         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1643
1644         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1645                 /* Receiver is synchronized with no invalid bits.  */
1646                 switch (mac->serdes_link_state) {
1647                 case e1000_serdes_link_autoneg_complete:
1648                         if (!(status & E1000_STATUS_LU)) {
1649                                 /* We have lost link, retry autoneg before
1650                                  * reporting link failure
1651                                  */
1652                                 mac->serdes_link_state =
1653                                     e1000_serdes_link_autoneg_progress;
1654                                 mac->serdes_has_link = false;
1655                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1656                         } else {
1657                                 mac->serdes_has_link = true;
1658                         }
1659                         break;
1660
1661                 case e1000_serdes_link_forced_up:
1662                         /* If we are receiving /C/ ordered sets, re-enable
1663                          * auto-negotiation in the TXCW register and disable
1664                          * forced link in the Device Control register in an
1665                          * attempt to auto-negotiate with our link partner.
1666                          */
1667                         if (rxcw & E1000_RXCW_C) {
1668                                 /* Enable autoneg, and unforce link up */
1669                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1670                                 E1000_WRITE_REG(hw, E1000_CTRL,
1671                                     (ctrl & ~E1000_CTRL_SLU));
1672                                 mac->serdes_link_state =
1673                                     e1000_serdes_link_autoneg_progress;
1674                                 mac->serdes_has_link = false;
1675                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1676                         } else {
1677                                 mac->serdes_has_link = true;
1678                         }
1679                         break;
1680
1681                 case e1000_serdes_link_autoneg_progress:
1682                         if (rxcw & E1000_RXCW_C) {
1683                                 /* We received /C/ ordered sets, meaning the
1684                                  * link partner has autonegotiated, and we can
1685                                  * trust the Link Up (LU) status bit.
1686                                  */
1687                                 if (status & E1000_STATUS_LU) {
1688                                         mac->serdes_link_state =
1689                                             e1000_serdes_link_autoneg_complete;
1690                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1691                                         mac->serdes_has_link = true;
1692                                 } else {
1693                                         /* Autoneg completed, but failed. */
1694                                         mac->serdes_link_state =
1695                                             e1000_serdes_link_down;
1696                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1697                                 }
1698                         } else {
1699                                 /* The link partner did not autoneg.
1700                                  * Force link up and full duplex, and change
1701                                  * state to forced.
1702                                  */
1703                                 E1000_WRITE_REG(hw, E1000_TXCW,
1704                                 (mac->txcw & ~E1000_TXCW_ANE));
1705                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1706                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1707
1708                                 /* Configure Flow Control after link up. */
1709                                 ret_val =
1710                                     e1000_config_fc_after_link_up_generic(hw);
1711                                 if (ret_val) {
1712                                         DEBUGOUT("Error config flow control\n");
1713                                         break;
1714                                 }
1715                                 mac->serdes_link_state =
1716                                                 e1000_serdes_link_forced_up;
1717                                 mac->serdes_has_link = true;
1718                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1719                         }
1720                         break;
1721
1722                 case e1000_serdes_link_down:
1723                 default:
1724                         /* The link was down but the receiver has now gained
1725                          * valid sync, so lets see if we can bring the link
1726                          * up.
1727                          */
1728                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1729                         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1730                                         ~E1000_CTRL_SLU));
1731                         mac->serdes_link_state =
1732                                         e1000_serdes_link_autoneg_progress;
1733                         mac->serdes_has_link = false;
1734                         DEBUGOUT("DOWN      -> AN_PROG\n");
1735                         break;
1736                 }
1737         } else {
1738                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1739                         mac->serdes_has_link = false;
1740                         mac->serdes_link_state = e1000_serdes_link_down;
1741                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1742                 } else {
1743                         /* Check several times, if SYNCH bit and CONFIG
1744                          * bit both are consistently 1 then simply ignore
1745                          * the IV bit and restart Autoneg
1746                          */
1747                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1748                                 usec_delay(10);
1749                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1750                                 if ((rxcw & E1000_RXCW_SYNCH) &&
1751                                     (rxcw & E1000_RXCW_C))
1752                                         continue;
1753
1754                                 if (rxcw & E1000_RXCW_IV) {
1755                                         mac->serdes_has_link = false;
1756                                         mac->serdes_link_state =
1757                                                         e1000_serdes_link_down;
1758                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1759                                         break;
1760                                 }
1761                         }
1762
1763                         if (i == AN_RETRY_COUNT) {
1764                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1765                                 txcw |= E1000_TXCW_ANE;
1766                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1767                                 mac->serdes_link_state =
1768                                         e1000_serdes_link_autoneg_progress;
1769                                 mac->serdes_has_link = false;
1770                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1771                         }
1772                 }
1773         }
1774
1775         return ret_val;
1776 }
1777
1778 /**
1779  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1780  *  @hw: pointer to the HW structure
1781  *  @data: pointer to the NVM (EEPROM)
1782  *
1783  *  Read the EEPROM for the current default LED configuration.  If the
1784  *  LED configuration is not valid, set to a valid LED configuration.
1785  **/
1786 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1787 {
1788         s32 ret_val;
1789
1790         DEBUGFUNC("e1000_valid_led_default_82571");
1791
1792         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1793         if (ret_val) {
1794                 DEBUGOUT("NVM Read Error\n");
1795                 return ret_val;
1796         }
1797
1798         switch (hw->mac.type) {
1799         case e1000_82573:
1800         case e1000_82574:
1801         case e1000_82583:
1802                 if (*data == ID_LED_RESERVED_F746)
1803                         *data = ID_LED_DEFAULT_82573;
1804                 break;
1805         default:
1806                 if (*data == ID_LED_RESERVED_0000 ||
1807                     *data == ID_LED_RESERVED_FFFF)
1808                         *data = ID_LED_DEFAULT;
1809                 break;
1810         }
1811
1812         return E1000_SUCCESS;
1813 }
1814
1815 /**
1816  *  e1000_get_laa_state_82571 - Get locally administered address state
1817  *  @hw: pointer to the HW structure
1818  *
1819  *  Retrieve and return the current locally administered address state.
1820  **/
1821 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1822 {
1823         DEBUGFUNC("e1000_get_laa_state_82571");
1824
1825         if (hw->mac.type != e1000_82571)
1826                 return false;
1827
1828         return hw->dev_spec._82571.laa_is_present;
1829 }
1830
1831 /**
1832  *  e1000_set_laa_state_82571 - Set locally administered address state
1833  *  @hw: pointer to the HW structure
1834  *  @state: enable/disable locally administered address
1835  *
1836  *  Enable/Disable the current locally administered address state.
1837  **/
1838 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1839 {
1840         DEBUGFUNC("e1000_set_laa_state_82571");
1841
1842         if (hw->mac.type != e1000_82571)
1843                 return;
1844
1845         hw->dev_spec._82571.laa_is_present = state;
1846
1847         /* If workaround is activated... */
1848         if (state)
1849                 /* Hold a copy of the LAA in RAR[14] This is done so that
1850                  * between the time RAR[0] gets clobbered and the time it
1851                  * gets fixed, the actual LAA is in one of the RARs and no
1852                  * incoming packets directed to this port are dropped.
1853                  * Eventually the LAA will be in RAR[0] and RAR[14].
1854                  */
1855                 hw->mac.ops.rar_set(hw, hw->mac.addr,
1856                                     hw->mac.rar_entry_count - 1);
1857         return;
1858 }
1859
1860 /**
1861  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1862  *  @hw: pointer to the HW structure
1863  *
1864  *  Verifies that the EEPROM has completed the update.  After updating the
1865  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1866  *  the checksum fix is not implemented, we need to set the bit and update
1867  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1868  *  we need to return bad checksum.
1869  **/
1870 STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1871 {
1872         struct e1000_nvm_info *nvm = &hw->nvm;
1873         s32 ret_val;
1874         u16 data;
1875
1876         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1877
1878         if (nvm->type != e1000_nvm_flash_hw)
1879                 return E1000_SUCCESS;
1880
1881         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1882          * 10h-12h.  Checksum may need to be fixed.
1883          */
1884         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1885         if (ret_val)
1886                 return ret_val;
1887
1888         if (!(data & 0x10)) {
1889                 /* Read 0x23 and check bit 15.  This bit is a 1
1890                  * when the checksum has already been fixed.  If
1891                  * the checksum is still wrong and this bit is a
1892                  * 1, we need to return bad checksum.  Otherwise,
1893                  * we need to set this bit to a 1 and update the
1894                  * checksum.
1895                  */
1896                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1897                 if (ret_val)
1898                         return ret_val;
1899
1900                 if (!(data & 0x8000)) {
1901                         data |= 0x8000;
1902                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1903                         if (ret_val)
1904                                 return ret_val;
1905                         ret_val = nvm->ops.update(hw);
1906                         if (ret_val)
1907                                 return ret_val;
1908                 }
1909         }
1910
1911         return E1000_SUCCESS;
1912 }
1913
1914
1915 /**
1916  *  e1000_read_mac_addr_82571 - Read device MAC address
1917  *  @hw: pointer to the HW structure
1918  **/
1919 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1920 {
1921         DEBUGFUNC("e1000_read_mac_addr_82571");
1922
1923         if (hw->mac.type == e1000_82571) {
1924                 s32 ret_val;
1925
1926                 /* If there's an alternate MAC address place it in RAR0
1927                  * so that it will override the Si installed default perm
1928                  * address.
1929                  */
1930                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1931                 if (ret_val)
1932                         return ret_val;
1933         }
1934
1935         return e1000_read_mac_addr_generic(hw);
1936 }
1937
1938 /**
1939  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1940  * @hw: pointer to the HW structure
1941  *
1942  * In the case of a PHY power down to save power, or to turn off link during a
1943  * driver unload, or wake on lan is not enabled, remove the link.
1944  **/
1945 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1946 {
1947         struct e1000_phy_info *phy = &hw->phy;
1948         struct e1000_mac_info *mac = &hw->mac;
1949
1950         if (!phy->ops.check_reset_block)
1951                 return;
1952
1953         /* If the management interface is not enabled, then power down */
1954         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1955                 e1000_power_down_phy_copper(hw);
1956
1957         return;
1958 }
1959
1960 /**
1961  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1962  *  @hw: pointer to the HW structure
1963  *
1964  *  Clears the hardware counters by reading the counter registers.
1965  **/
1966 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1967 {
1968         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1969
1970         e1000_clear_hw_cntrs_base_generic(hw);
1971
1972         E1000_READ_REG(hw, E1000_PRC64);
1973         E1000_READ_REG(hw, E1000_PRC127);
1974         E1000_READ_REG(hw, E1000_PRC255);
1975         E1000_READ_REG(hw, E1000_PRC511);
1976         E1000_READ_REG(hw, E1000_PRC1023);
1977         E1000_READ_REG(hw, E1000_PRC1522);
1978         E1000_READ_REG(hw, E1000_PTC64);
1979         E1000_READ_REG(hw, E1000_PTC127);
1980         E1000_READ_REG(hw, E1000_PTC255);
1981         E1000_READ_REG(hw, E1000_PTC511);
1982         E1000_READ_REG(hw, E1000_PTC1023);
1983         E1000_READ_REG(hw, E1000_PTC1522);
1984
1985         E1000_READ_REG(hw, E1000_ALGNERRC);
1986         E1000_READ_REG(hw, E1000_RXERRC);
1987         E1000_READ_REG(hw, E1000_TNCRS);
1988         E1000_READ_REG(hw, E1000_CEXTERR);
1989         E1000_READ_REG(hw, E1000_TSCTC);
1990         E1000_READ_REG(hw, E1000_TSCTFC);
1991
1992         E1000_READ_REG(hw, E1000_MGTPRC);
1993         E1000_READ_REG(hw, E1000_MGTPDC);
1994         E1000_READ_REG(hw, E1000_MGTPTC);
1995
1996         E1000_READ_REG(hw, E1000_IAC);
1997         E1000_READ_REG(hw, E1000_ICRXOC);
1998
1999         E1000_READ_REG(hw, E1000_ICRXPTC);
2000         E1000_READ_REG(hw, E1000_ICRXATC);
2001         E1000_READ_REG(hw, E1000_ICTXPTC);
2002         E1000_READ_REG(hw, E1000_ICTXATC);
2003         E1000_READ_REG(hw, E1000_ICTXQEC);
2004         E1000_READ_REG(hw, E1000_ICTXQMTC);
2005         E1000_READ_REG(hw, E1000_ICRXDMTC);
2006 }