1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 /* 82571EB Gigabit Ethernet Controller
35 * 82571EB Gigabit Ethernet Controller (Copper)
36 * 82571EB Gigabit Ethernet Controller (Fiber)
37 * 82571EB Dual Port Gigabit Mezzanine Adapter
38 * 82571EB Quad Port Gigabit Mezzanine Adapter
39 * 82571PT Gigabit PT Quad Port Server ExpressModule
40 * 82572EI Gigabit Ethernet Controller (Copper)
41 * 82572EI Gigabit Ethernet Controller (Fiber)
42 * 82572EI Gigabit Ethernet Controller
43 * 82573V Gigabit Ethernet Controller (Copper)
44 * 82573E Gigabit Ethernet Controller (Copper)
45 * 82573L Gigabit Ethernet Controller
46 * 82574L Gigabit Network Connection
47 * 82583V Gigabit Network Connection
50 #include "e1000_api.h"
52 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
53 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw);
54 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
57 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
58 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
59 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
61 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw);
62 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw);
63 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw);
64 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
65 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw);
66 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw);
67 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
68 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
69 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
70 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
71 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
72 STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
73 STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
74 STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
75 STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
76 STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
77 STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
78 STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
79 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
81 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
83 STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
84 STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
85 u16 words, u16 *data);
86 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
87 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
90 * e1000_init_phy_params_82571 - Init PHY func ptrs.
91 * @hw: pointer to the HW structure
93 STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
95 struct e1000_phy_info *phy = &hw->phy;
98 DEBUGFUNC("e1000_init_phy_params_82571");
100 if (hw->phy.media_type != e1000_media_type_copper) {
101 phy->type = e1000_phy_none;
102 return E1000_SUCCESS;
106 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
107 phy->reset_delay_us = 100;
109 phy->ops.check_reset_block = e1000_check_reset_block_generic;
110 phy->ops.reset = e1000_phy_hw_reset_generic;
111 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
112 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
113 phy->ops.power_up = e1000_power_up_phy_copper;
114 phy->ops.power_down = e1000_power_down_phy_copper_82571;
116 switch (hw->mac.type) {
119 phy->type = e1000_phy_igp_2;
120 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
121 phy->ops.get_info = e1000_get_phy_info_igp;
122 phy->ops.check_polarity = e1000_check_polarity_igp;
123 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
124 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
125 phy->ops.read_reg = e1000_read_phy_reg_igp;
126 phy->ops.write_reg = e1000_write_phy_reg_igp;
127 phy->ops.acquire = e1000_get_hw_semaphore_82571;
128 phy->ops.release = e1000_put_hw_semaphore_82571;
131 phy->type = e1000_phy_m88;
132 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
133 phy->ops.get_info = e1000_get_phy_info_m88;
134 phy->ops.check_polarity = e1000_check_polarity_m88;
135 phy->ops.commit = e1000_phy_sw_reset_generic;
136 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
137 phy->ops.get_cable_length = e1000_get_cable_length_m88;
138 phy->ops.read_reg = e1000_read_phy_reg_m88;
139 phy->ops.write_reg = e1000_write_phy_reg_m88;
140 phy->ops.acquire = e1000_get_hw_semaphore_82571;
141 phy->ops.release = e1000_put_hw_semaphore_82571;
145 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
147 phy->type = e1000_phy_bm;
148 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
149 phy->ops.get_info = e1000_get_phy_info_m88;
150 phy->ops.check_polarity = e1000_check_polarity_m88;
151 phy->ops.commit = e1000_phy_sw_reset_generic;
152 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
153 phy->ops.get_cable_length = e1000_get_cable_length_m88;
154 phy->ops.read_reg = e1000_read_phy_reg_bm2;
155 phy->ops.write_reg = e1000_write_phy_reg_bm2;
156 phy->ops.acquire = e1000_get_hw_semaphore_82574;
157 phy->ops.release = e1000_put_hw_semaphore_82574;
158 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
159 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
162 return -E1000_ERR_PHY;
166 /* This can only be done after all function pointers are setup. */
167 ret_val = e1000_get_phy_id_82571(hw);
169 DEBUGOUT("Error getting PHY ID\n");
174 switch (hw->mac.type) {
177 if (phy->id != IGP01E1000_I_PHY_ID)
178 ret_val = -E1000_ERR_PHY;
181 if (phy->id != M88E1111_I_PHY_ID)
182 ret_val = -E1000_ERR_PHY;
186 if (phy->id != BME1000_E_PHY_ID_R2)
187 ret_val = -E1000_ERR_PHY;
190 ret_val = -E1000_ERR_PHY;
195 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
201 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
202 * @hw: pointer to the HW structure
204 STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
206 struct e1000_nvm_info *nvm = &hw->nvm;
207 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
210 DEBUGFUNC("e1000_init_nvm_params_82571");
212 nvm->opcode_bits = 8;
214 switch (nvm->override) {
215 case e1000_nvm_override_spi_large:
217 nvm->address_bits = 16;
219 case e1000_nvm_override_spi_small:
221 nvm->address_bits = 8;
224 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
225 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
229 switch (hw->mac.type) {
233 if (((eecd >> 15) & 0x3) == 0x3) {
234 nvm->type = e1000_nvm_flash_hw;
235 nvm->word_size = 2048;
236 /* Autonomous Flash update bit must be cleared due
237 * to Flash update issue.
239 eecd &= ~E1000_EECD_AUPDEN;
240 E1000_WRITE_REG(hw, E1000_EECD, eecd);
245 nvm->type = e1000_nvm_eeprom_spi;
246 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
247 E1000_EECD_SIZE_EX_SHIFT);
248 /* Added to a constant, "size" becomes the left-shift value
249 * for setting word_size.
251 size += NVM_WORD_SIZE_BASE_SHIFT;
253 /* EEPROM access above 16k is unsupported */
256 nvm->word_size = 1 << size;
260 /* Function Pointers */
261 switch (hw->mac.type) {
264 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
265 nvm->ops.release = e1000_put_hw_semaphore_82574;
268 nvm->ops.acquire = e1000_acquire_nvm_82571;
269 nvm->ops.release = e1000_release_nvm_82571;
272 nvm->ops.read = e1000_read_nvm_eerd;
273 nvm->ops.update = e1000_update_nvm_checksum_82571;
274 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
275 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
276 nvm->ops.write = e1000_write_nvm_82571;
278 return E1000_SUCCESS;
282 * e1000_init_mac_params_82571 - Init MAC func ptrs.
283 * @hw: pointer to the HW structure
285 STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
287 struct e1000_mac_info *mac = &hw->mac;
290 bool force_clear_smbi = false;
292 DEBUGFUNC("e1000_init_mac_params_82571");
294 /* Set media type and media-dependent function pointers */
295 switch (hw->device_id) {
296 case E1000_DEV_ID_82571EB_FIBER:
297 case E1000_DEV_ID_82572EI_FIBER:
298 case E1000_DEV_ID_82571EB_QUAD_FIBER:
299 hw->phy.media_type = e1000_media_type_fiber;
300 mac->ops.setup_physical_interface =
301 e1000_setup_fiber_serdes_link_82571;
302 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
303 mac->ops.get_link_up_info =
304 e1000_get_speed_and_duplex_fiber_serdes_generic;
306 case E1000_DEV_ID_82571EB_SERDES:
307 case E1000_DEV_ID_82571EB_SERDES_DUAL:
308 case E1000_DEV_ID_82571EB_SERDES_QUAD:
309 case E1000_DEV_ID_82572EI_SERDES:
310 hw->phy.media_type = e1000_media_type_internal_serdes;
311 mac->ops.setup_physical_interface =
312 e1000_setup_fiber_serdes_link_82571;
313 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
314 mac->ops.get_link_up_info =
315 e1000_get_speed_and_duplex_fiber_serdes_generic;
318 hw->phy.media_type = e1000_media_type_copper;
319 mac->ops.setup_physical_interface =
320 e1000_setup_copper_link_82571;
321 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
322 mac->ops.get_link_up_info =
323 e1000_get_speed_and_duplex_copper_generic;
327 /* Set mta register count */
328 mac->mta_reg_count = 128;
329 /* Set rar entry count */
330 mac->rar_entry_count = E1000_RAR_ENTRIES;
331 /* Set if part includes ASF firmware */
332 mac->asf_firmware_present = true;
333 /* Adaptive IFS supported */
334 mac->adaptive_ifs = true;
336 /* Function pointers */
338 /* bus type/speed/width */
339 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
341 mac->ops.reset_hw = e1000_reset_hw_82571;
342 /* hw initialization */
343 mac->ops.init_hw = e1000_init_hw_82571;
345 mac->ops.setup_link = e1000_setup_link_82571;
346 /* multicast address update */
347 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
349 mac->ops.write_vfta = e1000_write_vfta_generic;
351 mac->ops.clear_vfta = e1000_clear_vfta_82571;
352 /* read mac address */
353 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
355 mac->ops.id_led_init = e1000_id_led_init_generic;
357 mac->ops.setup_led = e1000_setup_led_generic;
359 mac->ops.cleanup_led = e1000_cleanup_led_generic;
361 mac->ops.led_off = e1000_led_off_generic;
362 /* clear hardware counters */
363 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
365 /* MAC-specific function pointers */
366 switch (hw->mac.type) {
368 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
369 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
370 mac->ops.led_on = e1000_led_on_generic;
371 mac->ops.blink_led = e1000_blink_led_generic;
374 mac->has_fwsm = true;
375 /* ARC supported; valid only if manageability features are
378 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
379 E1000_FWSM_MODE_MASK);
383 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
384 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
385 mac->ops.led_on = e1000_led_on_82574;
388 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
389 mac->ops.led_on = e1000_led_on_generic;
390 mac->ops.blink_led = e1000_blink_led_generic;
393 mac->has_fwsm = true;
397 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
398 * first NVM or PHY access. This should be done for single-port
399 * devices, and for one port only on dual-port devices so that
400 * for those devices we can still use the SMBI lock to synchronize
401 * inter-port accesses to the PHY & NVM.
403 switch (hw->mac.type) {
406 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
408 if (!(swsm2 & E1000_SWSM2_LOCK)) {
409 /* Only do this for the first interface on this card */
410 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
412 force_clear_smbi = true;
414 force_clear_smbi = false;
418 force_clear_smbi = true;
422 if (force_clear_smbi) {
423 /* Make sure SWSM.SMBI is clear */
424 swsm = E1000_READ_REG(hw, E1000_SWSM);
425 if (swsm & E1000_SWSM_SMBI) {
426 /* This bit should not be set on a first interface, and
427 * indicates that the bootagent or EFI code has
428 * improperly left this bit enabled
430 DEBUGOUT("Please update your 82571 Bootagent\n");
432 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
435 /* Initialze device specific counter of SMBI acquisition timeouts. */
436 hw->dev_spec._82571.smb_counter = 0;
438 return E1000_SUCCESS;
442 * e1000_init_function_pointers_82571 - Init func ptrs.
443 * @hw: pointer to the HW structure
445 * Called to initialize all function pointers and parameters.
447 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
449 DEBUGFUNC("e1000_init_function_pointers_82571");
451 hw->mac.ops.init_params = e1000_init_mac_params_82571;
452 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
453 hw->phy.ops.init_params = e1000_init_phy_params_82571;
457 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
458 * @hw: pointer to the HW structure
460 * Reads the PHY registers and stores the PHY ID and possibly the PHY
461 * revision in the hardware structure.
463 STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
465 struct e1000_phy_info *phy = &hw->phy;
469 DEBUGFUNC("e1000_get_phy_id_82571");
471 switch (hw->mac.type) {
474 /* The 82571 firmware may still be configuring the PHY.
475 * In this case, we cannot access the PHY until the
476 * configuration is done. So we explicitly set the
479 phy->id = IGP01E1000_I_PHY_ID;
482 return e1000_get_phy_id(hw);
486 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
490 phy->id = (u32)(phy_id << 16);
492 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
496 phy->id |= (u32)(phy_id);
497 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
500 return -E1000_ERR_PHY;
504 return E1000_SUCCESS;
508 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
509 * @hw: pointer to the HW structure
511 * Acquire the HW semaphore to access the PHY or NVM
513 STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
516 s32 sw_timeout = hw->nvm.word_size + 1;
517 s32 fw_timeout = hw->nvm.word_size + 1;
520 DEBUGFUNC("e1000_get_hw_semaphore_82571");
522 /* If we have timedout 3 times on trying to acquire
523 * the inter-port SMBI semaphore, there is old code
524 * operating on the other port, and it is not
525 * releasing SMBI. Modify the number of times that
526 * we try for the semaphore to interwork with this
529 if (hw->dev_spec._82571.smb_counter > 2)
532 /* Get the SW semaphore */
533 while (i < sw_timeout) {
534 swsm = E1000_READ_REG(hw, E1000_SWSM);
535 if (!(swsm & E1000_SWSM_SMBI))
542 if (i == sw_timeout) {
543 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
544 hw->dev_spec._82571.smb_counter++;
546 /* Get the FW semaphore. */
547 for (i = 0; i < fw_timeout; i++) {
548 swsm = E1000_READ_REG(hw, E1000_SWSM);
549 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
551 /* Semaphore acquired if bit latched */
552 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
558 if (i == fw_timeout) {
559 /* Release semaphores */
560 e1000_put_hw_semaphore_82571(hw);
561 DEBUGOUT("Driver can't access the NVM\n");
562 return -E1000_ERR_NVM;
565 return E1000_SUCCESS;
569 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
570 * @hw: pointer to the HW structure
572 * Release hardware semaphore used to access the PHY or NVM
574 STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
578 DEBUGFUNC("e1000_put_hw_semaphore_generic");
580 swsm = E1000_READ_REG(hw, E1000_SWSM);
582 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
584 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
588 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
589 * @hw: pointer to the HW structure
591 * Acquire the HW semaphore during reset.
594 STATIC s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
599 DEBUGFUNC("e1000_get_hw_semaphore_82573");
601 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
603 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
604 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
605 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
607 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
612 } while (i < MDIO_OWNERSHIP_TIMEOUT);
614 if (i == MDIO_OWNERSHIP_TIMEOUT) {
615 /* Release semaphores */
616 e1000_put_hw_semaphore_82573(hw);
617 DEBUGOUT("Driver can't access the PHY\n");
618 return -E1000_ERR_PHY;
621 return E1000_SUCCESS;
625 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
626 * @hw: pointer to the HW structure
628 * Release hardware semaphore used during reset.
631 STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
635 DEBUGFUNC("e1000_put_hw_semaphore_82573");
637 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
638 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
639 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
643 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
644 * @hw: pointer to the HW structure
646 * Acquire the HW semaphore to access the PHY or NVM.
649 STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
653 DEBUGFUNC("e1000_get_hw_semaphore_82574");
655 E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
656 ret_val = e1000_get_hw_semaphore_82573(hw);
658 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
663 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
664 * @hw: pointer to the HW structure
666 * Release hardware semaphore used to access the PHY or NVM
669 STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
671 DEBUGFUNC("e1000_put_hw_semaphore_82574");
673 e1000_put_hw_semaphore_82573(hw);
674 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
678 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
679 * @hw: pointer to the HW structure
680 * @active: true to enable LPLU, false to disable
682 * Sets the LPLU D0 state according to the active flag.
683 * LPLU will not be activated unless the
684 * device autonegotiation advertisement meets standards of
685 * either 10 or 10/100 or 10/100/1000 at all duplexes.
686 * This is a function pointer entry point only called by
687 * PHY setup routines.
689 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
691 u32 data = E1000_READ_REG(hw, E1000_POEMB);
693 DEBUGFUNC("e1000_set_d0_lplu_state_82574");
696 data |= E1000_PHY_CTRL_D0A_LPLU;
698 data &= ~E1000_PHY_CTRL_D0A_LPLU;
700 E1000_WRITE_REG(hw, E1000_POEMB, data);
701 return E1000_SUCCESS;
705 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
706 * @hw: pointer to the HW structure
707 * @active: boolean used to enable/disable lplu
709 * The low power link up (lplu) state is set to the power management level D3
710 * when active is true, else clear lplu for D3. LPLU
711 * is used during Dx states where the power conservation is most important.
712 * During driver activity, SmartSpeed should be enabled so performance is
715 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
717 u32 data = E1000_READ_REG(hw, E1000_POEMB);
719 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
722 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
723 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
724 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
725 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
726 data |= E1000_PHY_CTRL_NOND0A_LPLU;
729 E1000_WRITE_REG(hw, E1000_POEMB, data);
730 return E1000_SUCCESS;
734 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
735 * @hw: pointer to the HW structure
737 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
738 * Then for non-82573 hardware, set the EEPROM access request bit and wait
739 * for EEPROM access grant bit. If the access grant bit is not set, release
740 * hardware semaphore.
742 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
746 DEBUGFUNC("e1000_acquire_nvm_82571");
748 ret_val = e1000_get_hw_semaphore_82571(hw);
752 switch (hw->mac.type) {
756 ret_val = e1000_acquire_nvm_generic(hw);
761 e1000_put_hw_semaphore_82571(hw);
767 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
768 * @hw: pointer to the HW structure
770 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
772 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw)
774 DEBUGFUNC("e1000_release_nvm_82571");
776 e1000_release_nvm_generic(hw);
777 e1000_put_hw_semaphore_82571(hw);
781 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
782 * @hw: pointer to the HW structure
783 * @offset: offset within the EEPROM to be written to
784 * @words: number of words to write
785 * @data: 16 bit word(s) to be written to the EEPROM
787 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
789 * If e1000_update_nvm_checksum is not called after this function, the
790 * EEPROM will most likely contain an invalid checksum.
792 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
797 DEBUGFUNC("e1000_write_nvm_82571");
799 switch (hw->mac.type) {
803 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
807 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
810 ret_val = -E1000_ERR_NVM;
818 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
819 * @hw: pointer to the HW structure
821 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
822 * up to the checksum. Then calculates the EEPROM checksum and writes the
823 * value to the EEPROM.
825 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
831 DEBUGFUNC("e1000_update_nvm_checksum_82571");
833 ret_val = e1000_update_nvm_checksum_generic(hw);
837 /* If our nvm is an EEPROM, then we're done
838 * otherwise, commit the checksum to the flash NVM.
840 if (hw->nvm.type != e1000_nvm_flash_hw)
841 return E1000_SUCCESS;
843 /* Check for pending operations. */
844 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
846 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
850 if (i == E1000_FLASH_UPDATES)
851 return -E1000_ERR_NVM;
853 /* Reset the firmware if using STM opcode. */
854 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
855 /* The enabling of and the actual reset must be done
856 * in two write cycles.
858 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
859 E1000_WRITE_FLUSH(hw);
860 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
863 /* Commit the write to flash */
864 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
865 E1000_WRITE_REG(hw, E1000_EECD, eecd);
867 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
869 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
873 if (i == E1000_FLASH_UPDATES)
874 return -E1000_ERR_NVM;
876 return E1000_SUCCESS;
880 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
881 * @hw: pointer to the HW structure
883 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
884 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
886 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
888 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
890 if (hw->nvm.type == e1000_nvm_flash_hw)
891 e1000_fix_nvm_checksum_82571(hw);
893 return e1000_validate_nvm_checksum_generic(hw);
897 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
898 * @hw: pointer to the HW structure
899 * @offset: offset within the EEPROM to be written to
900 * @words: number of words to write
901 * @data: 16 bit word(s) to be written to the EEPROM
903 * After checking for invalid values, poll the EEPROM to ensure the previous
904 * command has completed before trying to write the next word. After write
905 * poll for completion.
907 * If e1000_update_nvm_checksum is not called after this function, the
908 * EEPROM will most likely contain an invalid checksum.
910 STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
911 u16 words, u16 *data)
913 struct e1000_nvm_info *nvm = &hw->nvm;
915 s32 ret_val = E1000_SUCCESS;
917 DEBUGFUNC("e1000_write_nvm_eewr_82571");
919 /* A check for invalid values: offset too large, too many words,
920 * and not enough words.
922 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
924 DEBUGOUT("nvm parameter(s) out of bounds\n");
925 return -E1000_ERR_NVM;
928 for (i = 0; i < words; i++) {
929 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
930 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
931 E1000_NVM_RW_REG_START);
933 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
937 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
939 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
948 * e1000_get_cfg_done_82571 - Poll for configuration done
949 * @hw: pointer to the HW structure
951 * Reads the management control register for the config done bit to be set.
953 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
955 s32 timeout = PHY_CFG_TIMEOUT;
957 DEBUGFUNC("e1000_get_cfg_done_82571");
960 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
961 E1000_NVM_CFG_DONE_PORT_0)
967 DEBUGOUT("MNG configuration cycle has not completed.\n");
968 return -E1000_ERR_RESET;
971 return E1000_SUCCESS;
975 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
976 * @hw: pointer to the HW structure
977 * @active: true to enable LPLU, false to disable
979 * Sets the LPLU D0 state according to the active flag. When activating LPLU
980 * this function also disables smart speed and vice versa. LPLU will not be
981 * activated unless the device autonegotiation advertisement meets standards
982 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
983 * pointer entry point only called by PHY setup routines.
985 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
987 struct e1000_phy_info *phy = &hw->phy;
991 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
993 if (!(phy->ops.read_reg))
994 return E1000_SUCCESS;
996 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1001 data |= IGP02E1000_PM_D0_LPLU;
1002 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1007 /* When LPLU is enabled, we should disable SmartSpeed */
1008 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1012 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1013 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1018 data &= ~IGP02E1000_PM_D0_LPLU;
1019 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1021 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1022 * during Dx states where the power conservation is most
1023 * important. During driver activity we should enable
1024 * SmartSpeed, so performance is maintained.
1026 if (phy->smart_speed == e1000_smart_speed_on) {
1027 ret_val = phy->ops.read_reg(hw,
1028 IGP01E1000_PHY_PORT_CONFIG,
1033 data |= IGP01E1000_PSCFR_SMART_SPEED;
1034 ret_val = phy->ops.write_reg(hw,
1035 IGP01E1000_PHY_PORT_CONFIG,
1039 } else if (phy->smart_speed == e1000_smart_speed_off) {
1040 ret_val = phy->ops.read_reg(hw,
1041 IGP01E1000_PHY_PORT_CONFIG,
1046 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1047 ret_val = phy->ops.write_reg(hw,
1048 IGP01E1000_PHY_PORT_CONFIG,
1055 return E1000_SUCCESS;
1059 * e1000_reset_hw_82571 - Reset hardware
1060 * @hw: pointer to the HW structure
1062 * This resets the hardware into a known state.
1064 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1066 u32 ctrl, ctrl_ext, eecd, tctl;
1069 DEBUGFUNC("e1000_reset_hw_82571");
1071 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1072 * on the last TLP read/write transaction when MAC is reset.
1074 ret_val = e1000_disable_pcie_master_generic(hw);
1076 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1078 DEBUGOUT("Masking off all interrupts\n");
1079 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1081 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1082 tctl = E1000_READ_REG(hw, E1000_TCTL);
1083 tctl &= ~E1000_TCTL_EN;
1084 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1085 E1000_WRITE_FLUSH(hw);
1089 /* Must acquire the MDIO ownership before MAC reset.
1090 * Ownership defaults to firmware after a reset.
1092 switch (hw->mac.type) {
1094 ret_val = e1000_get_hw_semaphore_82573(hw);
1098 ret_val = e1000_get_hw_semaphore_82574(hw);
1104 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1106 DEBUGOUT("Issuing a global reset to MAC\n");
1107 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1109 /* Must release MDIO ownership and mutex after MAC reset. */
1110 switch (hw->mac.type) {
1112 /* Release mutex only if the hw semaphore is acquired */
1114 e1000_put_hw_semaphore_82573(hw);
1118 /* Release mutex only if the hw semaphore is acquired */
1120 e1000_put_hw_semaphore_82574(hw);
1126 if (hw->nvm.type == e1000_nvm_flash_hw) {
1128 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1129 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1130 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1131 E1000_WRITE_FLUSH(hw);
1134 ret_val = e1000_get_auto_rd_done_generic(hw);
1136 /* We don't want to continue accessing MAC registers. */
1139 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1140 * Need to wait for Phy configuration completion before accessing
1144 switch (hw->mac.type) {
1147 /* REQ and GNT bits need to be cleared when using AUTO_RD
1148 * to access the EEPROM.
1150 eecd = E1000_READ_REG(hw, E1000_EECD);
1151 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1152 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1163 /* Clear any pending interrupt events. */
1164 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1165 E1000_READ_REG(hw, E1000_ICR);
1167 if (hw->mac.type == e1000_82571) {
1168 /* Install any alternate MAC address into RAR0 */
1169 ret_val = e1000_check_alt_mac_addr_generic(hw);
1173 e1000_set_laa_state_82571(hw, true);
1176 /* Reinitialize the 82571 serdes link state machine */
1177 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1178 hw->mac.serdes_link_state = e1000_serdes_link_down;
1180 return E1000_SUCCESS;
1184 * e1000_init_hw_82571 - Initialize hardware
1185 * @hw: pointer to the HW structure
1187 * This inits the hardware readying it for operation.
1189 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
1191 struct e1000_mac_info *mac = &hw->mac;
1194 u16 i, rar_count = mac->rar_entry_count;
1196 DEBUGFUNC("e1000_init_hw_82571");
1198 e1000_initialize_hw_bits_82571(hw);
1200 /* Initialize identification LED */
1201 ret_val = mac->ops.id_led_init(hw);
1202 /* An error is not fatal and we should not stop init due to this */
1204 DEBUGOUT("Error initializing identification LED\n");
1206 /* Disabling VLAN filtering */
1207 DEBUGOUT("Initializing the IEEE VLAN\n");
1208 mac->ops.clear_vfta(hw);
1210 /* Setup the receive address.
1211 * If, however, a locally administered address was assigned to the
1212 * 82571, we must reserve a RAR for it to work around an issue where
1213 * resetting one port will reload the MAC on the other port.
1215 if (e1000_get_laa_state_82571(hw))
1217 e1000_init_rx_addrs_generic(hw, rar_count);
1219 /* Zero out the Multicast HASH table */
1220 DEBUGOUT("Zeroing the MTA\n");
1221 for (i = 0; i < mac->mta_reg_count; i++)
1222 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1224 /* Setup link and flow control */
1225 ret_val = mac->ops.setup_link(hw);
1227 /* Set the transmit descriptor write-back policy */
1228 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1229 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1230 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1231 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1233 /* ...for both queues. */
1234 switch (mac->type) {
1236 e1000_enable_tx_pkt_filtering_generic(hw);
1240 reg_data = E1000_READ_REG(hw, E1000_GCR);
1241 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1242 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1245 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1246 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1247 E1000_TXDCTL_FULL_TX_DESC_WB |
1248 E1000_TXDCTL_COUNT_DESC);
1249 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1253 /* Clear all of the statistics registers (clear on read). It is
1254 * important that we do this after we have tried to establish link
1255 * because the symbol error count will increment wildly if there
1258 e1000_clear_hw_cntrs_82571(hw);
1260 /* MSI-X configure for 82574 */
1261 if (mac->type == e1000_82574)
1262 E1000_WRITE_REG(hw, E1000_IVAR,
1263 (E1000_IVAR_INT_ALLOC_VALID << 16));
1269 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1270 * @hw: pointer to the HW structure
1272 * Initializes required hardware-dependent bits needed for normal operation.
1274 STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1278 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1280 /* Transmit Descriptor Control 0 */
1281 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1283 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1285 /* Transmit Descriptor Control 1 */
1286 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1288 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1290 /* Transmit Arbitration Control 0 */
1291 reg = E1000_READ_REG(hw, E1000_TARC(0));
1292 reg &= ~(0xF << 27); /* 30:27 */
1293 switch (hw->mac.type) {
1296 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1305 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1307 /* Transmit Arbitration Control 1 */
1308 reg = E1000_READ_REG(hw, E1000_TARC(1));
1309 switch (hw->mac.type) {
1312 reg &= ~((1 << 29) | (1 << 30));
1313 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1314 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1318 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1324 /* Device Control */
1325 switch (hw->mac.type) {
1329 reg = E1000_READ_REG(hw, E1000_CTRL);
1331 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1337 /* Extended Device Control */
1338 switch (hw->mac.type) {
1342 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1345 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1351 if (hw->mac.type == e1000_82571) {
1352 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1353 reg |= E1000_PBA_ECC_CORR_EN;
1354 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1357 /* Workaround for hardware errata.
1358 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1360 if ((hw->mac.type == e1000_82571) ||
1361 (hw->mac.type == e1000_82572)) {
1362 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1363 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1364 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1367 /* Disable IPv6 extension header parsing because some malformed
1368 * IPv6 headers can hang the Rx.
1370 if (hw->mac.type <= e1000_82573) {
1371 reg = E1000_READ_REG(hw, E1000_RFCTL);
1372 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1373 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1376 /* PCI-Ex Control Registers */
1377 switch (hw->mac.type) {
1380 reg = E1000_READ_REG(hw, E1000_GCR);
1382 E1000_WRITE_REG(hw, E1000_GCR, reg);
1384 /* Workaround for hardware errata.
1385 * apply workaround for hardware errata documented in errata
1386 * docs Fixes issue where some error prone or unreliable PCIe
1387 * completions are occurring, particularly with ASPM enabled.
1388 * Without fix, issue can cause Tx timeouts.
1390 reg = E1000_READ_REG(hw, E1000_GCR2);
1392 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1402 * e1000_clear_vfta_82571 - Clear VLAN filter table
1403 * @hw: pointer to the HW structure
1405 * Clears the register array which contains the VLAN filter table by
1406 * setting all the values to 0.
1408 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw)
1412 u32 vfta_offset = 0;
1413 u32 vfta_bit_in_reg = 0;
1415 DEBUGFUNC("e1000_clear_vfta_82571");
1417 switch (hw->mac.type) {
1421 if (hw->mng_cookie.vlan_id != 0) {
1422 /* The VFTA is a 4096b bit-field, each identifying
1423 * a single VLAN ID. The following operations
1424 * determine which 32b entry (i.e. offset) into the
1425 * array we want to set the VLAN ID (i.e. bit) of
1426 * the manageability unit.
1428 vfta_offset = (hw->mng_cookie.vlan_id >>
1429 E1000_VFTA_ENTRY_SHIFT) &
1430 E1000_VFTA_ENTRY_MASK;
1432 1 << (hw->mng_cookie.vlan_id &
1433 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1439 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1440 /* If the offset we want to clear is the same offset of the
1441 * manageability VLAN ID, then clear all bits except that of
1442 * the manageability unit.
1444 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1445 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1446 E1000_WRITE_FLUSH(hw);
1451 * e1000_check_mng_mode_82574 - Check manageability is enabled
1452 * @hw: pointer to the HW structure
1454 * Reads the NVM Initialization Control Word 2 and returns true
1455 * (>0) if any manageability is enabled, else false (0).
1457 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1462 DEBUGFUNC("e1000_check_mng_mode_82574");
1464 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1468 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1472 * e1000_led_on_82574 - Turn LED on
1473 * @hw: pointer to the HW structure
1477 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw)
1482 DEBUGFUNC("e1000_led_on_82574");
1484 ctrl = hw->mac.ledctl_mode2;
1485 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1486 /* If no link, then turn LED on by setting the invert bit
1487 * for each LED that's "on" (0x0E) in ledctl_mode2.
1489 for (i = 0; i < 4; i++)
1490 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1491 E1000_LEDCTL_MODE_LED_ON)
1492 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1494 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1496 return E1000_SUCCESS;
1500 * e1000_check_phy_82574 - check 82574 phy hung state
1501 * @hw: pointer to the HW structure
1503 * Returns whether phy is hung or not
1505 bool e1000_check_phy_82574(struct e1000_hw *hw)
1507 u16 status_1kbt = 0;
1508 u16 receive_errors = 0;
1511 DEBUGFUNC("e1000_check_phy_82574");
1513 /* Read PHY Receive Error counter first, if its is max - all F's then
1514 * read the Base1000T status register If both are max then PHY is hung.
1516 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1520 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1521 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1525 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1526 E1000_IDLE_ERROR_COUNT_MASK)
1535 * e1000_setup_link_82571 - Setup flow control and link settings
1536 * @hw: pointer to the HW structure
1538 * Determines which flow control settings to use, then configures flow
1539 * control. Calls the appropriate media-specific link configuration
1540 * function. Assuming the adapter has a valid link partner, a valid link
1541 * should be established. Assumes the hardware has previously been reset
1542 * and the transmitter and receiver are not enabled.
1544 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw)
1546 DEBUGFUNC("e1000_setup_link_82571");
1548 /* 82573 does not have a word in the NVM to determine
1549 * the default flow control setting, so we explicitly
1552 switch (hw->mac.type) {
1556 if (hw->fc.requested_mode == e1000_fc_default)
1557 hw->fc.requested_mode = e1000_fc_full;
1563 return e1000_setup_link_generic(hw);
1567 * e1000_setup_copper_link_82571 - Configure copper link settings
1568 * @hw: pointer to the HW structure
1570 * Configures the link for auto-neg or forced speed and duplex. Then we check
1571 * for link, once link is established calls to configure collision distance
1572 * and flow control are called.
1574 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1579 DEBUGFUNC("e1000_setup_copper_link_82571");
1581 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1582 ctrl |= E1000_CTRL_SLU;
1583 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1584 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1586 switch (hw->phy.type) {
1589 ret_val = e1000_copper_link_setup_m88(hw);
1591 case e1000_phy_igp_2:
1592 ret_val = e1000_copper_link_setup_igp(hw);
1595 return -E1000_ERR_PHY;
1602 return e1000_setup_copper_link_generic(hw);
1606 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1607 * @hw: pointer to the HW structure
1609 * Configures collision distance and flow control for fiber and serdes links.
1610 * Upon successful setup, poll for link.
1612 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1614 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1616 switch (hw->mac.type) {
1619 /* If SerDes loopback mode is entered, there is no form
1620 * of reset to take the adapter out of that mode. So we
1621 * have to explicitly take the adapter out of loopback
1622 * mode. This prevents drivers from twiddling their thumbs
1623 * if another tool failed to take it out of loopback mode.
1625 E1000_WRITE_REG(hw, E1000_SCTL,
1626 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1632 return e1000_setup_fiber_serdes_link_generic(hw);
1636 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1637 * @hw: pointer to the HW structure
1639 * Reports the link state as up or down.
1641 * If autonegotiation is supported by the link partner, the link state is
1642 * determined by the result of autonegotiation. This is the most likely case.
1643 * If autonegotiation is not supported by the link partner, and the link
1644 * has a valid signal, force the link up.
1646 * The link state is represented internally here by 4 states:
1649 * 2) autoneg_progress
1650 * 3) autoneg_complete (the link successfully autonegotiated)
1651 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1654 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1656 struct e1000_mac_info *mac = &hw->mac;
1662 s32 ret_val = E1000_SUCCESS;
1664 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1666 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1667 status = E1000_READ_REG(hw, E1000_STATUS);
1668 E1000_READ_REG(hw, E1000_RXCW);
1669 /* SYNCH bit and IV bit are sticky */
1671 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1673 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1674 /* Receiver is synchronized with no invalid bits. */
1675 switch (mac->serdes_link_state) {
1676 case e1000_serdes_link_autoneg_complete:
1677 if (!(status & E1000_STATUS_LU)) {
1678 /* We have lost link, retry autoneg before
1679 * reporting link failure
1681 mac->serdes_link_state =
1682 e1000_serdes_link_autoneg_progress;
1683 mac->serdes_has_link = false;
1684 DEBUGOUT("AN_UP -> AN_PROG\n");
1686 mac->serdes_has_link = true;
1690 case e1000_serdes_link_forced_up:
1691 /* If we are receiving /C/ ordered sets, re-enable
1692 * auto-negotiation in the TXCW register and disable
1693 * forced link in the Device Control register in an
1694 * attempt to auto-negotiate with our link partner.
1696 if (rxcw & E1000_RXCW_C) {
1697 /* Enable autoneg, and unforce link up */
1698 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1699 E1000_WRITE_REG(hw, E1000_CTRL,
1700 (ctrl & ~E1000_CTRL_SLU));
1701 mac->serdes_link_state =
1702 e1000_serdes_link_autoneg_progress;
1703 mac->serdes_has_link = false;
1704 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1706 mac->serdes_has_link = true;
1710 case e1000_serdes_link_autoneg_progress:
1711 if (rxcw & E1000_RXCW_C) {
1712 /* We received /C/ ordered sets, meaning the
1713 * link partner has autonegotiated, and we can
1714 * trust the Link Up (LU) status bit.
1716 if (status & E1000_STATUS_LU) {
1717 mac->serdes_link_state =
1718 e1000_serdes_link_autoneg_complete;
1719 DEBUGOUT("AN_PROG -> AN_UP\n");
1720 mac->serdes_has_link = true;
1722 /* Autoneg completed, but failed. */
1723 mac->serdes_link_state =
1724 e1000_serdes_link_down;
1725 DEBUGOUT("AN_PROG -> DOWN\n");
1728 /* The link partner did not autoneg.
1729 * Force link up and full duplex, and change
1732 E1000_WRITE_REG(hw, E1000_TXCW,
1733 (mac->txcw & ~E1000_TXCW_ANE));
1734 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1735 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1737 /* Configure Flow Control after link up. */
1739 e1000_config_fc_after_link_up_generic(hw);
1741 DEBUGOUT("Error config flow control\n");
1744 mac->serdes_link_state =
1745 e1000_serdes_link_forced_up;
1746 mac->serdes_has_link = true;
1747 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1751 case e1000_serdes_link_down:
1753 /* The link was down but the receiver has now gained
1754 * valid sync, so lets see if we can bring the link
1757 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1758 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1760 mac->serdes_link_state =
1761 e1000_serdes_link_autoneg_progress;
1762 mac->serdes_has_link = false;
1763 DEBUGOUT("DOWN -> AN_PROG\n");
1767 if (!(rxcw & E1000_RXCW_SYNCH)) {
1768 mac->serdes_has_link = false;
1769 mac->serdes_link_state = e1000_serdes_link_down;
1770 DEBUGOUT("ANYSTATE -> DOWN\n");
1772 /* Check several times, if SYNCH bit and CONFIG
1773 * bit both are consistently 1 then simply ignore
1774 * the IV bit and restart Autoneg
1776 for (i = 0; i < AN_RETRY_COUNT; i++) {
1778 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1779 if ((rxcw & E1000_RXCW_SYNCH) &&
1780 (rxcw & E1000_RXCW_C))
1783 if (rxcw & E1000_RXCW_IV) {
1784 mac->serdes_has_link = false;
1785 mac->serdes_link_state =
1786 e1000_serdes_link_down;
1787 DEBUGOUT("ANYSTATE -> DOWN\n");
1792 if (i == AN_RETRY_COUNT) {
1793 txcw = E1000_READ_REG(hw, E1000_TXCW);
1794 txcw |= E1000_TXCW_ANE;
1795 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1796 mac->serdes_link_state =
1797 e1000_serdes_link_autoneg_progress;
1798 mac->serdes_has_link = false;
1799 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1808 * e1000_valid_led_default_82571 - Verify a valid default LED config
1809 * @hw: pointer to the HW structure
1810 * @data: pointer to the NVM (EEPROM)
1812 * Read the EEPROM for the current default LED configuration. If the
1813 * LED configuration is not valid, set to a valid LED configuration.
1815 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1819 DEBUGFUNC("e1000_valid_led_default_82571");
1821 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1823 DEBUGOUT("NVM Read Error\n");
1827 switch (hw->mac.type) {
1831 if (*data == ID_LED_RESERVED_F746)
1832 *data = ID_LED_DEFAULT_82573;
1835 if (*data == ID_LED_RESERVED_0000 ||
1836 *data == ID_LED_RESERVED_FFFF)
1837 *data = ID_LED_DEFAULT;
1841 return E1000_SUCCESS;
1845 * e1000_get_laa_state_82571 - Get locally administered address state
1846 * @hw: pointer to the HW structure
1848 * Retrieve and return the current locally administered address state.
1850 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1852 DEBUGFUNC("e1000_get_laa_state_82571");
1854 if (hw->mac.type != e1000_82571)
1857 return hw->dev_spec._82571.laa_is_present;
1861 * e1000_set_laa_state_82571 - Set locally administered address state
1862 * @hw: pointer to the HW structure
1863 * @state: enable/disable locally administered address
1865 * Enable/Disable the current locally administered address state.
1867 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1869 DEBUGFUNC("e1000_set_laa_state_82571");
1871 if (hw->mac.type != e1000_82571)
1874 hw->dev_spec._82571.laa_is_present = state;
1876 /* If workaround is activated... */
1878 /* Hold a copy of the LAA in RAR[14] This is done so that
1879 * between the time RAR[0] gets clobbered and the time it
1880 * gets fixed, the actual LAA is in one of the RARs and no
1881 * incoming packets directed to this port are dropped.
1882 * Eventually the LAA will be in RAR[0] and RAR[14].
1884 hw->mac.ops.rar_set(hw, hw->mac.addr,
1885 hw->mac.rar_entry_count - 1);
1890 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1891 * @hw: pointer to the HW structure
1893 * Verifies that the EEPROM has completed the update. After updating the
1894 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1895 * the checksum fix is not implemented, we need to set the bit and update
1896 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1897 * we need to return bad checksum.
1899 STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1901 struct e1000_nvm_info *nvm = &hw->nvm;
1905 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1907 if (nvm->type != e1000_nvm_flash_hw)
1908 return E1000_SUCCESS;
1910 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1911 * 10h-12h. Checksum may need to be fixed.
1913 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1917 if (!(data & 0x10)) {
1918 /* Read 0x23 and check bit 15. This bit is a 1
1919 * when the checksum has already been fixed. If
1920 * the checksum is still wrong and this bit is a
1921 * 1, we need to return bad checksum. Otherwise,
1922 * we need to set this bit to a 1 and update the
1925 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1929 if (!(data & 0x8000)) {
1931 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1934 ret_val = nvm->ops.update(hw);
1940 return E1000_SUCCESS;
1945 * e1000_read_mac_addr_82571 - Read device MAC address
1946 * @hw: pointer to the HW structure
1948 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1950 DEBUGFUNC("e1000_read_mac_addr_82571");
1952 if (hw->mac.type == e1000_82571) {
1955 /* If there's an alternate MAC address place it in RAR0
1956 * so that it will override the Si installed default perm
1959 ret_val = e1000_check_alt_mac_addr_generic(hw);
1964 return e1000_read_mac_addr_generic(hw);
1968 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1969 * @hw: pointer to the HW structure
1971 * In the case of a PHY power down to save power, or to turn off link during a
1972 * driver unload, or wake on lan is not enabled, remove the link.
1974 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1976 struct e1000_phy_info *phy = &hw->phy;
1977 struct e1000_mac_info *mac = &hw->mac;
1979 if (!phy->ops.check_reset_block)
1982 /* If the management interface is not enabled, then power down */
1983 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1984 e1000_power_down_phy_copper(hw);
1990 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1991 * @hw: pointer to the HW structure
1993 * Clears the hardware counters by reading the counter registers.
1995 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1997 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1999 e1000_clear_hw_cntrs_base_generic(hw);
2001 E1000_READ_REG(hw, E1000_PRC64);
2002 E1000_READ_REG(hw, E1000_PRC127);
2003 E1000_READ_REG(hw, E1000_PRC255);
2004 E1000_READ_REG(hw, E1000_PRC511);
2005 E1000_READ_REG(hw, E1000_PRC1023);
2006 E1000_READ_REG(hw, E1000_PRC1522);
2007 E1000_READ_REG(hw, E1000_PTC64);
2008 E1000_READ_REG(hw, E1000_PTC127);
2009 E1000_READ_REG(hw, E1000_PTC255);
2010 E1000_READ_REG(hw, E1000_PTC511);
2011 E1000_READ_REG(hw, E1000_PTC1023);
2012 E1000_READ_REG(hw, E1000_PTC1522);
2014 E1000_READ_REG(hw, E1000_ALGNERRC);
2015 E1000_READ_REG(hw, E1000_RXERRC);
2016 E1000_READ_REG(hw, E1000_TNCRS);
2017 E1000_READ_REG(hw, E1000_CEXTERR);
2018 E1000_READ_REG(hw, E1000_TSCTC);
2019 E1000_READ_REG(hw, E1000_TSCTFC);
2021 E1000_READ_REG(hw, E1000_MGTPRC);
2022 E1000_READ_REG(hw, E1000_MGTPDC);
2023 E1000_READ_REG(hw, E1000_MGTPTC);
2025 E1000_READ_REG(hw, E1000_IAC);
2026 E1000_READ_REG(hw, E1000_ICRXOC);
2028 E1000_READ_REG(hw, E1000_ICRXPTC);
2029 E1000_READ_REG(hw, E1000_ICRXATC);
2030 E1000_READ_REG(hw, E1000_ICTXPTC);
2031 E1000_READ_REG(hw, E1000_ICTXATC);
2032 E1000_READ_REG(hw, E1000_ICTXQEC);
2033 E1000_READ_REG(hw, E1000_ICTXQMTC);
2034 E1000_READ_REG(hw, E1000_ICRXDMTC);