1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
35 * 82575EB Gigabit Network Connection
36 * 82575EB Gigabit Backplane Connection
37 * 82575GB Gigabit Network Connection
38 * 82576 Gigabit Network Connection
39 * 82576 Quad Port Gigabit Mezzanine Adapter
40 * 82580 Gigabit Network Connection
41 * I350 Gigabit Network Connection
44 #include "e1000_api.h"
45 #include "e1000_i210.h"
47 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
48 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
49 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
51 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
53 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
54 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
55 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
58 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
61 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);
63 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 *data);
65 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 data);
67 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
69 STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
71 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
73 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
74 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw);
76 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
77 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
78 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
79 u32 offset, u16 data);
80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
81 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
82 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
83 u16 *speed, u16 *duplex);
84 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
87 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
88 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
118 STATIC const u16 e1000_82580_rxpbs_table[] = {
119 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
120 #define E1000_82580_RXPBS_TABLE_SIZE \
121 (sizeof(e1000_82580_rxpbs_table) / \
122 sizeof(e1000_82580_rxpbs_table[0]))
126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
127 * @hw: pointer to the HW structure
129 * Called to determine if the I2C pins are being used for I2C or as an
130 * external MDIO interface since the two options are mutually exclusive.
132 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
135 bool ext_mdio = false;
137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
139 switch (hw->mac.type) {
142 reg = E1000_READ_REG(hw, E1000_MDIC);
143 ext_mdio = !!(reg & E1000_MDIC_DEST);
150 reg = E1000_READ_REG(hw, E1000_MDICNFG);
151 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
160 * e1000_init_phy_params_82575 - Init PHY func ptrs.
161 * @hw: pointer to the HW structure
163 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
165 struct e1000_phy_info *phy = &hw->phy;
166 s32 ret_val = E1000_SUCCESS;
169 DEBUGFUNC("e1000_init_phy_params_82575");
171 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
172 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
174 if (hw->phy.media_type != e1000_media_type_copper) {
175 phy->type = e1000_phy_none;
179 phy->ops.power_up = e1000_power_up_phy_copper;
180 phy->ops.power_down = e1000_power_down_phy_copper_82575;
182 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
183 phy->reset_delay_us = 100;
185 phy->ops.acquire = e1000_acquire_phy_82575;
186 phy->ops.check_reset_block = e1000_check_reset_block_generic;
187 phy->ops.commit = e1000_phy_sw_reset_generic;
188 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
189 phy->ops.release = e1000_release_phy_82575;
191 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
193 if (e1000_sgmii_active_82575(hw)) {
194 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
195 ctrl_ext |= E1000_CTRL_I2C_ENA;
197 phy->ops.reset = e1000_phy_hw_reset_generic;
198 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
202 e1000_reset_mdicnfg_82580(hw);
204 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
205 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
206 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
208 switch (hw->mac.type) {
212 phy->ops.read_reg = e1000_read_phy_reg_82580;
213 phy->ops.write_reg = e1000_write_phy_reg_82580;
217 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
218 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
221 phy->ops.read_reg = e1000_read_phy_reg_igp;
222 phy->ops.write_reg = e1000_write_phy_reg_igp;
226 /* Set phy->phy_addr and phy->id. */
227 ret_val = e1000_get_phy_id_82575(hw);
229 /* Verify phy id and set remaining function pointers */
231 case M88E1543_E_PHY_ID:
232 case M88E1512_E_PHY_ID:
233 case I347AT4_E_PHY_ID:
234 case M88E1112_E_PHY_ID:
235 case M88E1340M_E_PHY_ID:
236 case M88E1111_I_PHY_ID:
237 phy->type = e1000_phy_m88;
238 phy->ops.check_polarity = e1000_check_polarity_m88;
239 phy->ops.get_info = e1000_get_phy_info_m88;
240 if (phy->id == I347AT4_E_PHY_ID ||
241 phy->id == M88E1112_E_PHY_ID ||
242 phy->id == M88E1340M_E_PHY_ID)
243 phy->ops.get_cable_length =
244 e1000_get_cable_length_m88_gen2;
245 else if (phy->id == M88E1543_E_PHY_ID ||
246 phy->id == M88E1512_E_PHY_ID)
247 phy->ops.get_cable_length =
248 e1000_get_cable_length_m88_gen2;
250 phy->ops.get_cable_length = e1000_get_cable_length_m88;
251 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
252 /* Check if this PHY is confgured for media swap. */
253 if (phy->id == M88E1112_E_PHY_ID) {
256 ret_val = phy->ops.write_reg(hw,
257 E1000_M88E1112_PAGE_ADDR,
262 ret_val = phy->ops.read_reg(hw,
263 E1000_M88E1112_MAC_CTRL_1,
268 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
269 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
270 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
271 data == E1000_M88E1112_AUTO_COPPER_BASEX)
272 hw->mac.ops.check_for_link =
273 e1000_check_for_link_media_swap;
275 if (phy->id == M88E1512_E_PHY_ID) {
276 ret_val = e1000_initialize_M88E1512_phy(hw);
281 case IGP03E1000_E_PHY_ID:
282 case IGP04E1000_E_PHY_ID:
283 phy->type = e1000_phy_igp_3;
284 phy->ops.check_polarity = e1000_check_polarity_igp;
285 phy->ops.get_info = e1000_get_phy_info_igp;
286 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
287 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
288 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
289 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
291 case I82580_I_PHY_ID:
293 phy->type = e1000_phy_82580;
294 phy->ops.check_polarity = e1000_check_polarity_82577;
295 phy->ops.force_speed_duplex =
296 e1000_phy_force_speed_duplex_82577;
297 phy->ops.get_cable_length = e1000_get_cable_length_82577;
298 phy->ops.get_info = e1000_get_phy_info_82577;
299 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
300 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
303 phy->type = e1000_phy_i210;
304 phy->ops.check_polarity = e1000_check_polarity_m88;
305 phy->ops.get_info = e1000_get_phy_info_m88;
306 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
307 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
308 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
309 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
312 ret_val = -E1000_ERR_PHY;
321 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
322 * @hw: pointer to the HW structure
324 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
326 struct e1000_nvm_info *nvm = &hw->nvm;
327 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
330 DEBUGFUNC("e1000_init_nvm_params_82575");
332 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
333 E1000_EECD_SIZE_EX_SHIFT);
335 * Added to a constant, "size" becomes the left-shift value
336 * for setting word_size.
338 size += NVM_WORD_SIZE_BASE_SHIFT;
340 /* Just in case size is out of range, cap it to the largest
341 * EEPROM size supported
346 nvm->word_size = 1 << size;
347 if (hw->mac.type < e1000_i210) {
348 nvm->opcode_bits = 8;
351 switch (nvm->override) {
352 case e1000_nvm_override_spi_large:
354 nvm->address_bits = 16;
356 case e1000_nvm_override_spi_small:
358 nvm->address_bits = 8;
361 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
362 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
366 if (nvm->word_size == (1 << 15))
367 nvm->page_size = 128;
369 nvm->type = e1000_nvm_eeprom_spi;
371 nvm->type = e1000_nvm_flash_hw;
374 /* Function Pointers */
375 nvm->ops.acquire = e1000_acquire_nvm_82575;
376 nvm->ops.release = e1000_release_nvm_82575;
377 if (nvm->word_size < (1 << 15))
378 nvm->ops.read = e1000_read_nvm_eerd;
380 nvm->ops.read = e1000_read_nvm_spi;
382 nvm->ops.write = e1000_write_nvm_spi;
383 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
384 nvm->ops.update = e1000_update_nvm_checksum_generic;
385 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
387 /* override generic family function pointers for specific descendants */
388 switch (hw->mac.type) {
390 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
391 nvm->ops.update = e1000_update_nvm_checksum_82580;
395 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
396 nvm->ops.update = e1000_update_nvm_checksum_i350;
402 return E1000_SUCCESS;
406 * e1000_init_mac_params_82575 - Init MAC func ptrs.
407 * @hw: pointer to the HW structure
409 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
411 struct e1000_mac_info *mac = &hw->mac;
412 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
414 DEBUGFUNC("e1000_init_mac_params_82575");
416 /* Derives media type */
417 e1000_get_media_type_82575(hw);
418 /* Set mta register count */
419 mac->mta_reg_count = 128;
420 /* Set uta register count */
421 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
422 /* Set rar entry count */
423 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
424 if (mac->type == e1000_82576)
425 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
426 if (mac->type == e1000_82580)
427 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
428 if (mac->type == e1000_i350 || mac->type == e1000_i354)
429 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
431 /* Enable EEE default settings for EEE supported devices */
432 if (mac->type >= e1000_i350)
433 dev_spec->eee_disable = false;
435 /* Allow a single clear of the SW semaphore on I210 and newer */
436 if (mac->type >= e1000_i210)
437 dev_spec->clear_semaphore_once = true;
439 /* Set if part includes ASF firmware */
440 mac->asf_firmware_present = true;
442 mac->has_fwsm = true;
443 /* ARC supported; valid only if manageability features are enabled. */
444 mac->arc_subsystem_valid =
445 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
447 /* Function pointers */
449 /* bus type/speed/width */
450 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
452 if (mac->type >= e1000_82580)
453 mac->ops.reset_hw = e1000_reset_hw_82580;
455 mac->ops.reset_hw = e1000_reset_hw_82575;
456 /* hw initialization */
457 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
458 mac->ops.init_hw = e1000_init_hw_i210;
460 mac->ops.init_hw = e1000_init_hw_82575;
462 mac->ops.setup_link = e1000_setup_link_generic;
463 /* physical interface link setup */
464 mac->ops.setup_physical_interface =
465 (hw->phy.media_type == e1000_media_type_copper)
466 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
467 /* physical interface shutdown */
468 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
469 /* physical interface power up */
470 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
472 mac->ops.check_for_link = e1000_check_for_link_82575;
473 /* read mac address */
474 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
475 /* configure collision distance */
476 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
477 /* multicast address update */
478 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
479 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
481 mac->ops.write_vfta = e1000_write_vfta_i350;
483 mac->ops.clear_vfta = e1000_clear_vfta_i350;
486 mac->ops.write_vfta = e1000_write_vfta_generic;
488 mac->ops.clear_vfta = e1000_clear_vfta_generic;
490 if (hw->mac.type >= e1000_82580)
491 mac->ops.validate_mdi_setting =
492 e1000_validate_mdi_setting_crossover_generic;
494 mac->ops.id_led_init = e1000_id_led_init_generic;
496 mac->ops.blink_led = e1000_blink_led_generic;
498 mac->ops.setup_led = e1000_setup_led_generic;
500 mac->ops.cleanup_led = e1000_cleanup_led_generic;
501 /* turn on/off LED */
502 mac->ops.led_on = e1000_led_on_generic;
503 mac->ops.led_off = e1000_led_off_generic;
504 /* clear hardware counters */
505 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
507 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
508 /* acquire SW_FW sync */
509 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
510 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
511 if (mac->type >= e1000_i210) {
512 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
513 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
516 /* set lan id for port to determine which phy lock to use */
517 hw->mac.ops.set_lan_id(hw);
519 return E1000_SUCCESS;
523 * e1000_init_function_pointers_82575 - Init func ptrs.
524 * @hw: pointer to the HW structure
526 * Called to initialize all function pointers and parameters.
528 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
530 DEBUGFUNC("e1000_init_function_pointers_82575");
532 hw->mac.ops.init_params = e1000_init_mac_params_82575;
533 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
534 hw->phy.ops.init_params = e1000_init_phy_params_82575;
535 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
539 * e1000_acquire_phy_82575 - Acquire rights to access PHY
540 * @hw: pointer to the HW structure
542 * Acquire access rights to the correct PHY.
544 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
546 u16 mask = E1000_SWFW_PHY0_SM;
548 DEBUGFUNC("e1000_acquire_phy_82575");
550 if (hw->bus.func == E1000_FUNC_1)
551 mask = E1000_SWFW_PHY1_SM;
552 else if (hw->bus.func == E1000_FUNC_2)
553 mask = E1000_SWFW_PHY2_SM;
554 else if (hw->bus.func == E1000_FUNC_3)
555 mask = E1000_SWFW_PHY3_SM;
557 return hw->mac.ops.acquire_swfw_sync(hw, mask);
561 * e1000_release_phy_82575 - Release rights to access PHY
562 * @hw: pointer to the HW structure
564 * A wrapper to release access rights to the correct PHY.
566 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
568 u16 mask = E1000_SWFW_PHY0_SM;
570 DEBUGFUNC("e1000_release_phy_82575");
572 if (hw->bus.func == E1000_FUNC_1)
573 mask = E1000_SWFW_PHY1_SM;
574 else if (hw->bus.func == E1000_FUNC_2)
575 mask = E1000_SWFW_PHY2_SM;
576 else if (hw->bus.func == E1000_FUNC_3)
577 mask = E1000_SWFW_PHY3_SM;
579 hw->mac.ops.release_swfw_sync(hw, mask);
583 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
584 * @hw: pointer to the HW structure
585 * @offset: register offset to be read
586 * @data: pointer to the read data
588 * Reads the PHY register at offset using the serial gigabit media independent
589 * interface and stores the retrieved information in data.
591 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
594 s32 ret_val = -E1000_ERR_PARAM;
596 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
598 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
599 DEBUGOUT1("PHY Address %u is out of range\n", offset);
603 ret_val = hw->phy.ops.acquire(hw);
607 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
609 hw->phy.ops.release(hw);
616 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
617 * @hw: pointer to the HW structure
618 * @offset: register offset to write to
619 * @data: data to write at register offset
621 * Writes the data to PHY register at the offset using the serial gigabit
622 * media independent interface.
624 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
627 s32 ret_val = -E1000_ERR_PARAM;
629 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
631 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
632 DEBUGOUT1("PHY Address %d is out of range\n", offset);
636 ret_val = hw->phy.ops.acquire(hw);
640 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
642 hw->phy.ops.release(hw);
649 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
650 * @hw: pointer to the HW structure
652 * Retrieves the PHY address and ID for both PHY's which do and do not use
655 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
657 struct e1000_phy_info *phy = &hw->phy;
658 s32 ret_val = E1000_SUCCESS;
663 DEBUGFUNC("e1000_get_phy_id_82575");
665 /* some i354 devices need an extra read for phy id */
666 if (hw->mac.type == e1000_i354)
667 e1000_get_phy_id(hw);
670 * For SGMII PHYs, we try the list of possible addresses until
671 * we find one that works. For non-SGMII PHYs
672 * (e.g. integrated copper PHYs), an address of 1 should
673 * work. The result of this function should mean phy->phy_addr
674 * and phy->id are set correctly.
676 if (!e1000_sgmii_active_82575(hw)) {
678 ret_val = e1000_get_phy_id(hw);
682 if (e1000_sgmii_uses_mdio_82575(hw)) {
683 switch (hw->mac.type) {
686 mdic = E1000_READ_REG(hw, E1000_MDIC);
687 mdic &= E1000_MDIC_PHY_MASK;
688 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
695 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
696 mdic &= E1000_MDICNFG_PHY_MASK;
697 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
700 ret_val = -E1000_ERR_PHY;
704 ret_val = e1000_get_phy_id(hw);
708 /* Power on sgmii phy if it is disabled */
709 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
710 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
711 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
712 E1000_WRITE_FLUSH(hw);
716 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
717 * Therefore, we need to test 1-7
719 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
720 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
721 if (ret_val == E1000_SUCCESS) {
722 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
725 * At the time of this writing, The M88 part is
726 * the only supported SGMII PHY product.
728 if (phy_id == M88_VENDOR)
731 DEBUGOUT1("PHY address %u was unreadable\n",
736 /* A valid PHY type couldn't be found. */
737 if (phy->addr == 8) {
739 ret_val = -E1000_ERR_PHY;
741 ret_val = e1000_get_phy_id(hw);
744 /* restore previous sfp cage power state */
745 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
752 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
753 * @hw: pointer to the HW structure
755 * Resets the PHY using the serial gigabit media independent interface.
757 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
759 s32 ret_val = E1000_SUCCESS;
760 struct e1000_phy_info *phy = &hw->phy;
762 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
765 * This isn't a true "hard" reset, but is the only reset
766 * available to us at this time.
769 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
771 if (!(hw->phy.ops.write_reg))
775 * SFP documentation requires the following to configure the SPF module
776 * to work on SGMII. No further documentation is given.
778 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
782 ret_val = hw->phy.ops.commit(hw);
786 if (phy->id == M88E1512_E_PHY_ID)
787 ret_val = e1000_initialize_M88E1512_phy(hw);
793 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
794 * @hw: pointer to the HW structure
795 * @active: true to enable LPLU, false to disable
797 * Sets the LPLU D0 state according to the active flag. When
798 * activating LPLU this function also disables smart speed
799 * and vice versa. LPLU will not be activated unless the
800 * device autonegotiation advertisement meets standards of
801 * either 10 or 10/100 or 10/100/1000 at all duplexes.
802 * This is a function pointer entry point only called by
803 * PHY setup routines.
805 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
807 struct e1000_phy_info *phy = &hw->phy;
808 s32 ret_val = E1000_SUCCESS;
811 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
813 if (!(hw->phy.ops.read_reg))
816 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
821 data |= IGP02E1000_PM_D0_LPLU;
822 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
827 /* When LPLU is enabled, we should disable SmartSpeed */
828 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
830 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
831 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
836 data &= ~IGP02E1000_PM_D0_LPLU;
837 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
840 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
841 * during Dx states where the power conservation is most
842 * important. During driver activity we should enable
843 * SmartSpeed, so performance is maintained.
845 if (phy->smart_speed == e1000_smart_speed_on) {
846 ret_val = phy->ops.read_reg(hw,
847 IGP01E1000_PHY_PORT_CONFIG,
852 data |= IGP01E1000_PSCFR_SMART_SPEED;
853 ret_val = phy->ops.write_reg(hw,
854 IGP01E1000_PHY_PORT_CONFIG,
858 } else if (phy->smart_speed == e1000_smart_speed_off) {
859 ret_val = phy->ops.read_reg(hw,
860 IGP01E1000_PHY_PORT_CONFIG,
865 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
866 ret_val = phy->ops.write_reg(hw,
867 IGP01E1000_PHY_PORT_CONFIG,
879 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
880 * @hw: pointer to the HW structure
881 * @active: true to enable LPLU, false to disable
883 * Sets the LPLU D0 state according to the active flag. When
884 * activating LPLU this function also disables smart speed
885 * and vice versa. LPLU will not be activated unless the
886 * device autonegotiation advertisement meets standards of
887 * either 10 or 10/100 or 10/100/1000 at all duplexes.
888 * This is a function pointer entry point only called by
889 * PHY setup routines.
891 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
893 struct e1000_phy_info *phy = &hw->phy;
896 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
898 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
901 data |= E1000_82580_PM_D0_LPLU;
903 /* When LPLU is enabled, we should disable SmartSpeed */
904 data &= ~E1000_82580_PM_SPD;
906 data &= ~E1000_82580_PM_D0_LPLU;
909 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
910 * during Dx states where the power conservation is most
911 * important. During driver activity we should enable
912 * SmartSpeed, so performance is maintained.
914 if (phy->smart_speed == e1000_smart_speed_on)
915 data |= E1000_82580_PM_SPD;
916 else if (phy->smart_speed == e1000_smart_speed_off)
917 data &= ~E1000_82580_PM_SPD;
920 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
921 return E1000_SUCCESS;
925 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
926 * @hw: pointer to the HW structure
927 * @active: boolean used to enable/disable lplu
929 * Success returns 0, Failure returns 1
931 * The low power link up (lplu) state is set to the power management level D3
932 * and SmartSpeed is disabled when active is true, else clear lplu for D3
933 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
934 * is used during Dx states where the power conservation is most important.
935 * During driver activity, SmartSpeed should be enabled so performance is
938 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
940 struct e1000_phy_info *phy = &hw->phy;
943 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
945 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
948 data &= ~E1000_82580_PM_D3_LPLU;
950 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
951 * during Dx states where the power conservation is most
952 * important. During driver activity we should enable
953 * SmartSpeed, so performance is maintained.
955 if (phy->smart_speed == e1000_smart_speed_on)
956 data |= E1000_82580_PM_SPD;
957 else if (phy->smart_speed == e1000_smart_speed_off)
958 data &= ~E1000_82580_PM_SPD;
959 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
960 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
961 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
962 data |= E1000_82580_PM_D3_LPLU;
963 /* When LPLU is enabled, we should disable SmartSpeed */
964 data &= ~E1000_82580_PM_SPD;
967 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
968 return E1000_SUCCESS;
972 * e1000_acquire_nvm_82575 - Request for access to EEPROM
973 * @hw: pointer to the HW structure
975 * Acquire the necessary semaphores for exclusive access to the EEPROM.
976 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
977 * Return successful if access grant bit set, else clear the request for
978 * EEPROM access and return -E1000_ERR_NVM (-1).
980 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
982 s32 ret_val = E1000_SUCCESS;
984 DEBUGFUNC("e1000_acquire_nvm_82575");
986 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
991 * Check if there is some access
992 * error this access may hook on
994 if (hw->mac.type == e1000_i350) {
995 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
996 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
997 E1000_EECD_TIMEOUT)) {
998 /* Clear all access error flags */
999 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1000 E1000_EECD_ERROR_CLR);
1001 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1005 if (hw->mac.type == e1000_82580) {
1006 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1007 if (eecd & E1000_EECD_BLOCKED) {
1008 /* Clear access error flag */
1009 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1010 E1000_EECD_BLOCKED);
1011 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1015 ret_val = e1000_acquire_nvm_generic(hw);
1017 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1024 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
1025 * @hw: pointer to the HW structure
1027 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1028 * then release the semaphores acquired.
1030 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1032 DEBUGFUNC("e1000_release_nvm_82575");
1034 e1000_release_nvm_generic(hw);
1036 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1040 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1041 * @hw: pointer to the HW structure
1042 * @mask: specifies which semaphore to acquire
1044 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1045 * will also specify which port we're acquiring the lock for.
1047 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1051 u32 fwmask = mask << 16;
1052 s32 ret_val = E1000_SUCCESS;
1053 s32 i = 0, timeout = 200;
1055 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1057 while (i < timeout) {
1058 if (e1000_get_hw_semaphore_generic(hw)) {
1059 ret_val = -E1000_ERR_SWFW_SYNC;
1063 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1064 if (!(swfw_sync & (fwmask | swmask)))
1068 * Firmware currently using resource (fwmask)
1069 * or other software thread using resource (swmask)
1071 e1000_put_hw_semaphore_generic(hw);
1077 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1078 ret_val = -E1000_ERR_SWFW_SYNC;
1082 swfw_sync |= swmask;
1083 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1085 e1000_put_hw_semaphore_generic(hw);
1092 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1093 * @hw: pointer to the HW structure
1094 * @mask: specifies which semaphore to acquire
1096 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1097 * will also specify which port we're releasing the lock for.
1099 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1103 DEBUGFUNC("e1000_release_swfw_sync_82575");
1105 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1108 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1110 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1112 e1000_put_hw_semaphore_generic(hw);
1116 * e1000_get_cfg_done_82575 - Read config done bit
1117 * @hw: pointer to the HW structure
1119 * Read the management control register for the config done bit for
1120 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1121 * to read the config done bit, so an error is *ONLY* logged and returns
1122 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1123 * would not be able to be reset or change link.
1125 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1127 s32 timeout = PHY_CFG_TIMEOUT;
1128 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1130 DEBUGFUNC("e1000_get_cfg_done_82575");
1132 if (hw->bus.func == E1000_FUNC_1)
1133 mask = E1000_NVM_CFG_DONE_PORT_1;
1134 else if (hw->bus.func == E1000_FUNC_2)
1135 mask = E1000_NVM_CFG_DONE_PORT_2;
1136 else if (hw->bus.func == E1000_FUNC_3)
1137 mask = E1000_NVM_CFG_DONE_PORT_3;
1139 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1145 DEBUGOUT("MNG configuration cycle has not completed.\n");
1147 /* If EEPROM is not marked present, init the PHY manually */
1148 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1149 (hw->phy.type == e1000_phy_igp_3))
1150 e1000_phy_init_script_igp3(hw);
1152 return E1000_SUCCESS;
1156 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1157 * @hw: pointer to the HW structure
1158 * @speed: stores the current speed
1159 * @duplex: stores the current duplex
1161 * This is a wrapper function, if using the serial gigabit media independent
1162 * interface, use PCS to retrieve the link speed and duplex information.
1163 * Otherwise, use the generic function to get the link speed and duplex info.
1165 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1170 DEBUGFUNC("e1000_get_link_up_info_82575");
1172 if (hw->phy.media_type != e1000_media_type_copper)
1173 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1176 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1183 * e1000_check_for_link_82575 - Check for link
1184 * @hw: pointer to the HW structure
1186 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1187 * use the generic interface for determining link.
1189 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1194 DEBUGFUNC("e1000_check_for_link_82575");
1196 if (hw->phy.media_type != e1000_media_type_copper) {
1197 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1200 * Use this flag to determine if link needs to be checked or
1201 * not. If we have link clear the flag so that we do not
1202 * continue to check for link.
1204 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1207 * Configure Flow Control now that Auto-Neg has completed.
1208 * First, we need to restore the desired flow control
1209 * settings because we may have had to re-autoneg with a
1210 * different link partner.
1212 ret_val = e1000_config_fc_after_link_up_generic(hw);
1214 DEBUGOUT("Error configuring flow control\n");
1216 ret_val = e1000_check_for_copper_link_generic(hw);
1223 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1224 * @hw: pointer to the HW structure
1226 * Poll the M88E1112 interfaces to see which interface achieved link.
1228 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1230 struct e1000_phy_info *phy = &hw->phy;
1235 DEBUGFUNC("e1000_check_for_link_media_swap");
1237 /* Check the copper medium. */
1238 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1242 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1246 if (data & E1000_M88E1112_STATUS_LINK)
1247 port = E1000_MEDIA_PORT_COPPER;
1249 /* Check the other medium. */
1250 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1254 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1258 /* reset page to 0 */
1259 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1263 if (data & E1000_M88E1112_STATUS_LINK)
1264 port = E1000_MEDIA_PORT_OTHER;
1266 /* Determine if a swap needs to happen. */
1267 if (port && (hw->dev_spec._82575.media_port != port)) {
1268 hw->dev_spec._82575.media_port = port;
1269 hw->dev_spec._82575.media_changed = true;
1271 ret_val = e1000_check_for_link_82575(hw);
1274 return E1000_SUCCESS;
1278 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1279 * @hw: pointer to the HW structure
1281 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1285 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1287 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1288 !e1000_sgmii_active_82575(hw))
1291 /* Enable PCS to turn on link */
1292 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1293 reg |= E1000_PCS_CFG_PCS_EN;
1294 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1296 /* Power up the laser */
1297 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1298 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1299 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1301 /* flush the write to verify completion */
1302 E1000_WRITE_FLUSH(hw);
1307 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1308 * @hw: pointer to the HW structure
1309 * @speed: stores the current speed
1310 * @duplex: stores the current duplex
1312 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1313 * duplex, then store the values in the pointers provided.
1315 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1316 u16 *speed, u16 *duplex)
1318 struct e1000_mac_info *mac = &hw->mac;
1322 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1325 * Read the PCS Status register for link state. For non-copper mode,
1326 * the status register is not accurate. The PCS status register is
1329 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1332 * The link up bit determines when link is up on autoneg.
1334 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1335 mac->serdes_has_link = true;
1337 /* Detect and store PCS speed */
1338 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1339 *speed = SPEED_1000;
1340 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1345 /* Detect and store PCS duplex */
1346 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1347 *duplex = FULL_DUPLEX;
1349 *duplex = HALF_DUPLEX;
1351 /* Check if it is an I354 2.5Gb backplane connection. */
1352 if (mac->type == e1000_i354) {
1353 status = E1000_READ_REG(hw, E1000_STATUS);
1354 if ((status & E1000_STATUS_2P5_SKU) &&
1355 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1356 *speed = SPEED_2500;
1357 *duplex = FULL_DUPLEX;
1358 DEBUGOUT("2500 Mbs, ");
1359 DEBUGOUT("Full Duplex\n");
1364 mac->serdes_has_link = false;
1369 return E1000_SUCCESS;
1373 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1374 * @hw: pointer to the HW structure
1376 * In the case of serdes shut down sfp and PCS on driver unload
1377 * when management pass thru is not enabled.
1379 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1383 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1385 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1386 !e1000_sgmii_active_82575(hw))
1389 if (!e1000_enable_mng_pass_thru(hw)) {
1390 /* Disable PCS to turn off link */
1391 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1392 reg &= ~E1000_PCS_CFG_PCS_EN;
1393 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1395 /* shutdown the laser */
1396 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1397 reg |= E1000_CTRL_EXT_SDP3_DATA;
1398 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1400 /* flush the write to verify completion */
1401 E1000_WRITE_FLUSH(hw);
1409 * e1000_reset_hw_82575 - Reset hardware
1410 * @hw: pointer to the HW structure
1412 * This resets the hardware into a known state.
1414 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1419 DEBUGFUNC("e1000_reset_hw_82575");
1422 * Prevent the PCI-E bus from sticking if there is no TLP connection
1423 * on the last TLP read/write transaction when MAC is reset.
1425 ret_val = e1000_disable_pcie_master_generic(hw);
1427 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1429 /* set the completion timeout for interface */
1430 ret_val = e1000_set_pcie_completion_timeout(hw);
1432 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1434 DEBUGOUT("Masking off all interrupts\n");
1435 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1437 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1438 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1439 E1000_WRITE_FLUSH(hw);
1443 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1445 DEBUGOUT("Issuing a global reset to MAC\n");
1446 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1448 ret_val = e1000_get_auto_rd_done_generic(hw);
1451 * When auto config read does not complete, do not
1452 * return with an error. This can happen in situations
1453 * where there is no eeprom and prevents getting link.
1455 DEBUGOUT("Auto Read Done did not complete\n");
1458 /* If EEPROM is not present, run manual init scripts */
1459 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1460 e1000_reset_init_script_82575(hw);
1462 /* Clear any pending interrupt events. */
1463 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1464 E1000_READ_REG(hw, E1000_ICR);
1466 /* Install any alternate MAC address into RAR0 */
1467 ret_val = e1000_check_alt_mac_addr_generic(hw);
1473 * e1000_init_hw_82575 - Initialize hardware
1474 * @hw: pointer to the HW structure
1476 * This inits the hardware readying it for operation.
1478 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1480 struct e1000_mac_info *mac = &hw->mac;
1482 u16 i, rar_count = mac->rar_entry_count;
1484 DEBUGFUNC("e1000_init_hw_82575");
1486 /* Initialize identification LED */
1487 ret_val = mac->ops.id_led_init(hw);
1489 DEBUGOUT("Error initializing identification LED\n");
1490 /* This is not fatal and we should not stop init due to this */
1493 /* Disabling VLAN filtering */
1494 DEBUGOUT("Initializing the IEEE VLAN\n");
1495 mac->ops.clear_vfta(hw);
1497 /* Setup the receive address */
1498 e1000_init_rx_addrs_generic(hw, rar_count);
1500 /* Zero out the Multicast HASH table */
1501 DEBUGOUT("Zeroing the MTA\n");
1502 for (i = 0; i < mac->mta_reg_count; i++)
1503 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1505 /* Zero out the Unicast HASH table */
1506 DEBUGOUT("Zeroing the UTA\n");
1507 for (i = 0; i < mac->uta_reg_count; i++)
1508 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1510 /* Setup link and flow control */
1511 ret_val = mac->ops.setup_link(hw);
1513 /* Set the default MTU size */
1514 hw->dev_spec._82575.mtu = 1500;
1517 * Clear all of the statistics registers (clear on read). It is
1518 * important that we do this after we have tried to establish link
1519 * because the symbol error count will increment wildly if there
1522 e1000_clear_hw_cntrs_82575(hw);
1528 * e1000_setup_copper_link_82575 - Configure copper link settings
1529 * @hw: pointer to the HW structure
1531 * Configures the link for auto-neg or forced speed and duplex. Then we check
1532 * for link, once link is established calls to configure collision distance
1533 * and flow control are called.
1535 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1541 DEBUGFUNC("e1000_setup_copper_link_82575");
1543 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1544 ctrl |= E1000_CTRL_SLU;
1545 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1546 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1548 /* Clear Go Link Disconnect bit on supported devices */
1549 switch (hw->mac.type) {
1554 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1555 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1556 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1562 ret_val = e1000_setup_serdes_link_82575(hw);
1566 if (e1000_sgmii_active_82575(hw)) {
1567 /* allow time for SFP cage time to power up phy */
1570 ret_val = hw->phy.ops.reset(hw);
1572 DEBUGOUT("Error resetting the PHY.\n");
1576 switch (hw->phy.type) {
1577 case e1000_phy_i210:
1579 switch (hw->phy.id) {
1580 case I347AT4_E_PHY_ID:
1581 case M88E1112_E_PHY_ID:
1582 case M88E1340M_E_PHY_ID:
1583 case M88E1543_E_PHY_ID:
1584 case M88E1512_E_PHY_ID:
1586 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1589 ret_val = e1000_copper_link_setup_m88(hw);
1593 case e1000_phy_igp_3:
1594 ret_val = e1000_copper_link_setup_igp(hw);
1596 case e1000_phy_82580:
1597 ret_val = e1000_copper_link_setup_82577(hw);
1600 ret_val = -E1000_ERR_PHY;
1607 ret_val = e1000_setup_copper_link_generic(hw);
1613 * e1000_setup_serdes_link_82575 - Setup link for serdes
1614 * @hw: pointer to the HW structure
1616 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1617 * used on copper connections where the serialized gigabit media independent
1618 * interface (sgmii), or serdes fiber is being used. Configures the link
1619 * for auto-negotiation or forces speed/duplex.
1621 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1623 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1625 s32 ret_val = E1000_SUCCESS;
1628 DEBUGFUNC("e1000_setup_serdes_link_82575");
1630 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1631 !e1000_sgmii_active_82575(hw))
1635 * On the 82575, SerDes loopback mode persists until it is
1636 * explicitly turned off or a power cycle is performed. A read to
1637 * the register does not indicate its status. Therefore, we ensure
1638 * loopback mode is disabled during initialization.
1640 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1642 /* power on the sfp cage if present */
1643 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1644 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1645 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1647 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1648 ctrl_reg |= E1000_CTRL_SLU;
1650 /* set both sw defined pins on 82575/82576*/
1651 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1652 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1654 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1656 /* default pcs_autoneg to the same setting as mac autoneg */
1657 pcs_autoneg = hw->mac.autoneg;
1659 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1660 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1661 /* sgmii mode lets the phy handle forcing speed/duplex */
1663 /* autoneg time out should be disabled for SGMII mode */
1664 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1666 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1667 /* disable PCS autoneg and support parallel detect only */
1668 pcs_autoneg = false;
1669 /* fall through to default case */
1671 if (hw->mac.type == e1000_82575 ||
1672 hw->mac.type == e1000_82576) {
1673 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1675 DEBUGOUT("NVM Read Error\n");
1679 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1680 pcs_autoneg = false;
1684 * non-SGMII modes only supports a speed of 1000/Full for the
1685 * link so it is best to just force the MAC and let the pcs
1686 * link either autoneg or be forced to 1000/Full
1688 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1689 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1691 /* set speed of 1000/Full if speed/duplex is forced */
1692 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1696 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1699 * New SerDes mode allows for forcing speed or autonegotiating speed
1700 * at 1gb. Autoneg should be default set by most drivers. This is the
1701 * mode that will be compatible with older link partners and switches.
1702 * However, both are supported by the hardware and some drivers/tools.
1704 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1705 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1708 /* Set PCS register for autoneg */
1709 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1710 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1712 /* Disable force flow control for autoneg */
1713 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1715 /* Configure flow control advertisement for autoneg */
1716 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1717 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1719 switch (hw->fc.requested_mode) {
1721 case e1000_fc_rx_pause:
1722 anadv_reg |= E1000_TXCW_ASM_DIR;
1723 anadv_reg |= E1000_TXCW_PAUSE;
1725 case e1000_fc_tx_pause:
1726 anadv_reg |= E1000_TXCW_ASM_DIR;
1732 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1734 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1736 /* Set PCS register for forced link */
1737 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1739 /* Force flow control for forced link */
1740 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1742 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1745 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1747 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1748 e1000_force_mac_fc_generic(hw);
1754 * e1000_get_media_type_82575 - derives current media type.
1755 * @hw: pointer to the HW structure
1757 * The media type is chosen reflecting few settings.
1758 * The following are taken into account:
1759 * - link mode set in the current port Init Control Word #3
1760 * - current link mode settings in CSR register
1761 * - MDIO vs. I2C PHY control interface chosen
1762 * - SFP module media type
1764 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1766 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1767 s32 ret_val = E1000_SUCCESS;
1771 /* Set internal phy as default */
1772 dev_spec->sgmii_active = false;
1773 dev_spec->module_plugged = false;
1775 /* Get CSR setting */
1776 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1778 /* extract link mode setting */
1779 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1781 switch (link_mode) {
1782 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1783 hw->phy.media_type = e1000_media_type_internal_serdes;
1785 case E1000_CTRL_EXT_LINK_MODE_GMII:
1786 hw->phy.media_type = e1000_media_type_copper;
1788 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1789 /* Get phy control interface type set (MDIO vs. I2C)*/
1790 if (e1000_sgmii_uses_mdio_82575(hw)) {
1791 hw->phy.media_type = e1000_media_type_copper;
1792 dev_spec->sgmii_active = true;
1795 /* fall through for I2C based SGMII */
1796 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1797 /* read media type from SFP EEPROM */
1798 ret_val = e1000_set_sfp_media_type_82575(hw);
1799 if ((ret_val != E1000_SUCCESS) ||
1800 (hw->phy.media_type == e1000_media_type_unknown)) {
1802 * If media type was not identified then return media
1803 * type defined by the CTRL_EXT settings.
1805 hw->phy.media_type = e1000_media_type_internal_serdes;
1807 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1808 hw->phy.media_type = e1000_media_type_copper;
1809 dev_spec->sgmii_active = true;
1815 /* do not change link mode for 100BaseFX */
1816 if (dev_spec->eth_flags.e100_base_fx)
1819 /* change current link mode setting */
1820 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1822 if (hw->phy.media_type == e1000_media_type_copper)
1823 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1825 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1827 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1836 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1837 * @hw: pointer to the HW structure
1839 * The media type is chosen based on SFP module.
1840 * compatibility flags retrieved from SFP ID EEPROM.
1842 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1844 s32 ret_val = E1000_ERR_CONFIG;
1846 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1847 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1848 u8 tranceiver_type = 0;
1851 /* Turn I2C interface ON and power on sfp cage */
1852 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1853 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1854 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1856 E1000_WRITE_FLUSH(hw);
1858 /* Read SFP module data */
1860 ret_val = e1000_read_sfp_data_byte(hw,
1861 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1863 if (ret_val == E1000_SUCCESS)
1868 if (ret_val != E1000_SUCCESS)
1871 ret_val = e1000_read_sfp_data_byte(hw,
1872 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1874 if (ret_val != E1000_SUCCESS)
1877 /* Check if there is some SFP module plugged and powered */
1878 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1879 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1880 dev_spec->module_plugged = true;
1881 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1882 hw->phy.media_type = e1000_media_type_internal_serdes;
1883 } else if (eth_flags->e100_base_fx) {
1884 dev_spec->sgmii_active = true;
1885 hw->phy.media_type = e1000_media_type_internal_serdes;
1886 } else if (eth_flags->e1000_base_t) {
1887 dev_spec->sgmii_active = true;
1888 hw->phy.media_type = e1000_media_type_copper;
1890 hw->phy.media_type = e1000_media_type_unknown;
1891 DEBUGOUT("PHY module has not been recognized\n");
1895 hw->phy.media_type = e1000_media_type_unknown;
1897 ret_val = E1000_SUCCESS;
1899 /* Restore I2C interface setting */
1900 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1905 * e1000_valid_led_default_82575 - Verify a valid default LED config
1906 * @hw: pointer to the HW structure
1907 * @data: pointer to the NVM (EEPROM)
1909 * Read the EEPROM for the current default LED configuration. If the
1910 * LED configuration is not valid, set to a valid LED configuration.
1912 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1916 DEBUGFUNC("e1000_valid_led_default_82575");
1918 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1920 DEBUGOUT("NVM Read Error\n");
1924 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1925 switch (hw->phy.media_type) {
1926 case e1000_media_type_internal_serdes:
1927 *data = ID_LED_DEFAULT_82575_SERDES;
1929 case e1000_media_type_copper:
1931 *data = ID_LED_DEFAULT;
1940 * e1000_sgmii_active_82575 - Return sgmii state
1941 * @hw: pointer to the HW structure
1943 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1944 * which can be enabled for use in the embedded applications. Simply
1945 * return the current state of the sgmii interface.
1947 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1949 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1950 return dev_spec->sgmii_active;
1954 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1955 * @hw: pointer to the HW structure
1957 * Inits recommended HW defaults after a reset when there is no EEPROM
1958 * detected. This is only for the 82575.
1960 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1962 DEBUGFUNC("e1000_reset_init_script_82575");
1964 if (hw->mac.type == e1000_82575) {
1965 DEBUGOUT("Running reset init script for 82575\n");
1966 /* SerDes configuration via SERDESCTRL */
1967 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1968 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1969 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1970 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1972 /* CCM configuration via CCMCTL register */
1973 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1974 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1976 /* PCIe lanes configuration */
1977 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1978 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1979 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1980 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1982 /* PCIe PLL Configuration */
1983 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1984 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1985 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1988 return E1000_SUCCESS;
1992 * e1000_read_mac_addr_82575 - Read device MAC address
1993 * @hw: pointer to the HW structure
1995 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1999 DEBUGFUNC("e1000_read_mac_addr_82575");
2002 * If there's an alternate MAC address place it in RAR0
2003 * so that it will override the Si installed default perm
2006 ret_val = e1000_check_alt_mac_addr_generic(hw);
2010 ret_val = e1000_read_mac_addr_generic(hw);
2017 * e1000_config_collision_dist_82575 - Configure collision distance
2018 * @hw: pointer to the HW structure
2020 * Configures the collision distance to the default value and is used
2021 * during link setup.
2023 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2027 DEBUGFUNC("e1000_config_collision_dist_82575");
2029 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2031 tctl_ext &= ~E1000_TCTL_EXT_COLD;
2032 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2034 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2035 E1000_WRITE_FLUSH(hw);
2039 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2040 * @hw: pointer to the HW structure
2042 * In the case of a PHY power down to save power, or to turn off link during a
2043 * driver unload, or wake on lan is not enabled, remove the link.
2045 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2047 struct e1000_phy_info *phy = &hw->phy;
2049 if (!(phy->ops.check_reset_block))
2052 /* If the management interface is not enabled, then power down */
2053 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2054 e1000_power_down_phy_copper(hw);
2060 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2061 * @hw: pointer to the HW structure
2063 * Clears the hardware counters by reading the counter registers.
2065 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2067 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2069 e1000_clear_hw_cntrs_base_generic(hw);
2071 E1000_READ_REG(hw, E1000_PRC64);
2072 E1000_READ_REG(hw, E1000_PRC127);
2073 E1000_READ_REG(hw, E1000_PRC255);
2074 E1000_READ_REG(hw, E1000_PRC511);
2075 E1000_READ_REG(hw, E1000_PRC1023);
2076 E1000_READ_REG(hw, E1000_PRC1522);
2077 E1000_READ_REG(hw, E1000_PTC64);
2078 E1000_READ_REG(hw, E1000_PTC127);
2079 E1000_READ_REG(hw, E1000_PTC255);
2080 E1000_READ_REG(hw, E1000_PTC511);
2081 E1000_READ_REG(hw, E1000_PTC1023);
2082 E1000_READ_REG(hw, E1000_PTC1522);
2084 E1000_READ_REG(hw, E1000_ALGNERRC);
2085 E1000_READ_REG(hw, E1000_RXERRC);
2086 E1000_READ_REG(hw, E1000_TNCRS);
2087 E1000_READ_REG(hw, E1000_CEXTERR);
2088 E1000_READ_REG(hw, E1000_TSCTC);
2089 E1000_READ_REG(hw, E1000_TSCTFC);
2091 E1000_READ_REG(hw, E1000_MGTPRC);
2092 E1000_READ_REG(hw, E1000_MGTPDC);
2093 E1000_READ_REG(hw, E1000_MGTPTC);
2095 E1000_READ_REG(hw, E1000_IAC);
2096 E1000_READ_REG(hw, E1000_ICRXOC);
2098 E1000_READ_REG(hw, E1000_ICRXPTC);
2099 E1000_READ_REG(hw, E1000_ICRXATC);
2100 E1000_READ_REG(hw, E1000_ICTXPTC);
2101 E1000_READ_REG(hw, E1000_ICTXATC);
2102 E1000_READ_REG(hw, E1000_ICTXQEC);
2103 E1000_READ_REG(hw, E1000_ICTXQMTC);
2104 E1000_READ_REG(hw, E1000_ICRXDMTC);
2106 E1000_READ_REG(hw, E1000_CBTMPC);
2107 E1000_READ_REG(hw, E1000_HTDPMC);
2108 E1000_READ_REG(hw, E1000_CBRMPC);
2109 E1000_READ_REG(hw, E1000_RPTHC);
2110 E1000_READ_REG(hw, E1000_HGPTC);
2111 E1000_READ_REG(hw, E1000_HTCBDPC);
2112 E1000_READ_REG(hw, E1000_HGORCL);
2113 E1000_READ_REG(hw, E1000_HGORCH);
2114 E1000_READ_REG(hw, E1000_HGOTCL);
2115 E1000_READ_REG(hw, E1000_HGOTCH);
2116 E1000_READ_REG(hw, E1000_LENERRS);
2118 /* This register should not be read in copper configurations */
2119 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2120 e1000_sgmii_active_82575(hw))
2121 E1000_READ_REG(hw, E1000_SCVPC);
2125 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2126 * @hw: pointer to the HW structure
2128 * After rx enable if managability is enabled then there is likely some
2129 * bad data at the start of the fifo and possibly in the DMA fifo. This
2130 * function clears the fifos and flushes any packets that came in as rx was
2133 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2135 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2138 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2139 if (hw->mac.type != e1000_82575 ||
2140 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2143 /* Disable all Rx queues */
2144 for (i = 0; i < 4; i++) {
2145 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2146 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2147 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2149 /* Poll all queues to verify they have shut down */
2150 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2153 for (i = 0; i < 4; i++)
2154 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2155 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2160 DEBUGOUT("Queue disable timed out after 10ms\n");
2162 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2163 * incoming packets are rejected. Set enable and wait 2ms so that
2164 * any packet that was coming in as RCTL.EN was set is flushed
2166 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2167 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2169 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2170 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2172 rctl = E1000_READ_REG(hw, E1000_RCTL);
2173 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2174 temp_rctl |= E1000_RCTL_LPE;
2176 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2177 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2178 E1000_WRITE_FLUSH(hw);
2181 /* Enable Rx queues that were previously enabled and restore our
2184 for (i = 0; i < 4; i++)
2185 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2186 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2187 E1000_WRITE_FLUSH(hw);
2189 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2190 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2192 /* Flush receive errors generated by workaround */
2193 E1000_READ_REG(hw, E1000_ROC);
2194 E1000_READ_REG(hw, E1000_RNBC);
2195 E1000_READ_REG(hw, E1000_MPC);
2199 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2200 * @hw: pointer to the HW structure
2202 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2203 * however the hardware default for these parts is 500us to 1ms which is less
2204 * than the 10ms recommended by the pci-e spec. To address this we need to
2205 * increase the value to either 10ms to 200ms for capability version 1 config,
2206 * or 16ms to 55ms for version 2.
2208 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2210 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2211 s32 ret_val = E1000_SUCCESS;
2214 /* only take action if timeout value is defaulted to 0 */
2215 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2219 * if capababilities version is type 1 we can write the
2220 * timeout of 10ms to 200ms through the GCR register
2222 if (!(gcr & E1000_GCR_CAP_VER2)) {
2223 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2228 * for version 2 capabilities we need to write the config space
2229 * directly in order to set the completion timeout value for
2232 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2237 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2239 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2242 /* disable completion timeout resend */
2243 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2245 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2250 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2251 * @hw: pointer to the hardware struct
2252 * @enable: state to enter, either enabled or disabled
2253 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2255 * enables/disables L2 switch anti-spoofing functionality.
2257 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2259 u32 reg_val, reg_offset;
2261 switch (hw->mac.type) {
2263 reg_offset = E1000_DTXSWC;
2267 reg_offset = E1000_TXSWC;
2273 reg_val = E1000_READ_REG(hw, reg_offset);
2275 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2276 E1000_DTXSWC_VLAN_SPOOF_MASK);
2277 /* The PF can spoof - it has to in order to
2278 * support emulation mode NICs
2280 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2282 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2283 E1000_DTXSWC_VLAN_SPOOF_MASK);
2285 E1000_WRITE_REG(hw, reg_offset, reg_val);
2289 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2290 * @hw: pointer to the hardware struct
2291 * @enable: state to enter, either enabled or disabled
2293 * enables/disables L2 switch loopback functionality.
2295 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2299 switch (hw->mac.type) {
2301 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2303 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2305 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2306 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2310 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2312 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2314 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2315 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2318 /* Currently no other hardware supports loopback */
2326 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2327 * @hw: pointer to the hardware struct
2328 * @enable: state to enter, either enabled or disabled
2330 * enables/disables replication of packets across multiple pools.
2332 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2334 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2337 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2339 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2341 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2345 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2346 * @hw: pointer to the HW structure
2347 * @offset: register offset to be read
2348 * @data: pointer to the read data
2350 * Reads the MDI control register in the PHY at offset and stores the
2351 * information read to data.
2353 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2357 DEBUGFUNC("e1000_read_phy_reg_82580");
2359 ret_val = hw->phy.ops.acquire(hw);
2363 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2365 hw->phy.ops.release(hw);
2372 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2373 * @hw: pointer to the HW structure
2374 * @offset: register offset to write to
2375 * @data: data to write to register at offset
2377 * Writes data to MDI control register in the PHY at offset.
2379 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2383 DEBUGFUNC("e1000_write_phy_reg_82580");
2385 ret_val = hw->phy.ops.acquire(hw);
2389 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2391 hw->phy.ops.release(hw);
2398 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2399 * @hw: pointer to the HW structure
2401 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2402 * the values found in the EEPROM. This addresses an issue in which these
2403 * bits are not restored from EEPROM after reset.
2405 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2407 s32 ret_val = E1000_SUCCESS;
2411 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2413 if (hw->mac.type != e1000_82580)
2415 if (!e1000_sgmii_active_82575(hw))
2418 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2419 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2422 DEBUGOUT("NVM Read Error\n");
2426 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2427 if (nvm_data & NVM_WORD24_EXT_MDIO)
2428 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2429 if (nvm_data & NVM_WORD24_COM_MDIO)
2430 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2431 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2437 * e1000_reset_hw_82580 - Reset hardware
2438 * @hw: pointer to the HW structure
2440 * This resets function or entire device (all ports, etc.)
2443 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2445 s32 ret_val = E1000_SUCCESS;
2446 /* BH SW mailbox bit in SW_FW_SYNC */
2447 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2449 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2451 DEBUGFUNC("e1000_reset_hw_82580");
2453 hw->dev_spec._82575.global_device_reset = false;
2455 /* 82580 does not reliably do global_device_reset due to hw errata */
2456 if (hw->mac.type == e1000_82580)
2457 global_device_reset = false;
2459 /* Get current control state. */
2460 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2463 * Prevent the PCI-E bus from sticking if there is no TLP connection
2464 * on the last TLP read/write transaction when MAC is reset.
2466 ret_val = e1000_disable_pcie_master_generic(hw);
2468 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2470 DEBUGOUT("Masking off all interrupts\n");
2471 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2472 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2473 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2474 E1000_WRITE_FLUSH(hw);
2478 /* Determine whether or not a global dev reset is requested */
2479 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2481 global_device_reset = false;
2483 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2484 E1000_STAT_DEV_RST_SET))
2485 ctrl |= E1000_CTRL_DEV_RST;
2487 ctrl |= E1000_CTRL_RST;
2489 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2491 switch (hw->device_id) {
2492 case E1000_DEV_ID_DH89XXCC_SGMII:
2495 E1000_WRITE_FLUSH(hw);
2499 /* Add delay to insure DEV_RST or RST has time to complete */
2502 ret_val = e1000_get_auto_rd_done_generic(hw);
2505 * When auto config read does not complete, do not
2506 * return with an error. This can happen in situations
2507 * where there is no eeprom and prevents getting link.
2509 DEBUGOUT("Auto Read Done did not complete\n");
2512 /* clear global device reset status bit */
2513 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2515 /* Clear any pending interrupt events. */
2516 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2517 E1000_READ_REG(hw, E1000_ICR);
2519 ret_val = e1000_reset_mdicnfg_82580(hw);
2521 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2523 /* Install any alternate MAC address into RAR0 */
2524 ret_val = e1000_check_alt_mac_addr_generic(hw);
2526 /* Release semaphore */
2527 if (global_device_reset)
2528 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2534 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2535 * @data: data received by reading RXPBS register
2537 * The 82580 uses a table based approach for packet buffer allocation sizes.
2538 * This function converts the retrieved value into the correct table value
2539 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2540 * 0x0 36 72 144 1 2 4 8 16
2541 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2543 u16 e1000_rxpbs_adjust_82580(u32 data)
2547 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2548 ret_val = e1000_82580_rxpbs_table[data];
2554 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2556 * @hw: pointer to the HW structure
2557 * @offset: offset in words of the checksum protected region
2559 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2560 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2562 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2564 s32 ret_val = E1000_SUCCESS;
2568 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2570 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2571 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2573 DEBUGOUT("NVM Read Error\n");
2576 checksum += nvm_data;
2579 if (checksum != (u16) NVM_SUM) {
2580 DEBUGOUT("NVM Checksum Invalid\n");
2581 ret_val = -E1000_ERR_NVM;
2590 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2592 * @hw: pointer to the HW structure
2593 * @offset: offset in words of the checksum protected region
2595 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2596 * up to the checksum. Then calculates the EEPROM checksum and writes the
2597 * value to the EEPROM.
2599 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2605 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2607 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2608 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2610 DEBUGOUT("NVM Read Error while updating checksum.\n");
2613 checksum += nvm_data;
2615 checksum = (u16) NVM_SUM - checksum;
2616 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2619 DEBUGOUT("NVM Write Error while updating checksum.\n");
2626 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2627 * @hw: pointer to the HW structure
2629 * Calculates the EEPROM section checksum by reading/adding each word of
2630 * the EEPROM and then verifies that the sum of the EEPROM is
2633 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2636 u16 eeprom_regions_count = 1;
2640 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2642 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2644 DEBUGOUT("NVM Read Error\n");
2648 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2649 /* if chekcsums compatibility bit is set validate checksums
2650 * for all 4 ports. */
2651 eeprom_regions_count = 4;
2654 for (j = 0; j < eeprom_regions_count; j++) {
2655 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2656 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2658 if (ret_val != E1000_SUCCESS)
2667 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2668 * @hw: pointer to the HW structure
2670 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2671 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2672 * checksum and writes the value to the EEPROM.
2674 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2680 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2682 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2684 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2688 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2689 /* set compatibility bit to validate checksums appropriately */
2690 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2691 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2694 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2699 for (j = 0; j < 4; j++) {
2700 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2701 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2711 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2712 * @hw: pointer to the HW structure
2714 * Calculates the EEPROM section checksum by reading/adding each word of
2715 * the EEPROM and then verifies that the sum of the EEPROM is
2718 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2720 s32 ret_val = E1000_SUCCESS;
2724 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2726 for (j = 0; j < 4; j++) {
2727 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2728 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2730 if (ret_val != E1000_SUCCESS)
2739 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2740 * @hw: pointer to the HW structure
2742 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2743 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2744 * checksum and writes the value to the EEPROM.
2746 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2748 s32 ret_val = E1000_SUCCESS;
2752 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2754 for (j = 0; j < 4; j++) {
2755 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2756 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2757 if (ret_val != E1000_SUCCESS)
2766 * __e1000_access_emi_reg - Read/write EMI register
2767 * @hw: pointer to the HW structure
2768 * @addr: EMI address to program
2769 * @data: pointer to value to read/write from/to the EMI address
2770 * @read: boolean flag to indicate read or write
2772 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2773 u16 *data, bool read)
2777 DEBUGFUNC("__e1000_access_emi_reg");
2779 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2784 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2786 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2792 * e1000_read_emi_reg - Read Extended Management Interface register
2793 * @hw: pointer to the HW structure
2794 * @addr: EMI address to program
2795 * @data: value to be read from the EMI address
2797 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2799 DEBUGFUNC("e1000_read_emi_reg");
2801 return __e1000_access_emi_reg(hw, addr, data, true);
2805 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2806 * @hw: pointer to the HW structure
2808 * Initialize Marverl 1512 to work correctly with Avoton.
2810 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2812 struct e1000_phy_info *phy = &hw->phy;
2813 s32 ret_val = E1000_SUCCESS;
2815 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2817 /* Check if this is correct PHY. */
2818 if (phy->id != M88E1512_E_PHY_ID)
2821 /* Switch to PHY page 0xFF. */
2822 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2826 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2830 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2834 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2838 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2842 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2846 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2850 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2854 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2858 /* Switch to PHY page 0xFB. */
2859 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2863 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2867 /* Switch to PHY page 0x12. */
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2872 /* Change mode to SGMII-to-Copper */
2873 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2877 /* Return the PHY to page 0. */
2878 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2882 ret_val = phy->ops.commit(hw);
2884 DEBUGOUT("Error committing the PHY changes\n");
2894 * e1000_set_eee_i350 - Enable/disable EEE support
2895 * @hw: pointer to the HW structure
2897 * Enable/disable EEE based on setting in dev_spec structure.
2900 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2902 s32 ret_val = E1000_SUCCESS;
2905 DEBUGFUNC("e1000_set_eee_i350");
2907 if ((hw->mac.type < e1000_i350) ||
2908 (hw->phy.media_type != e1000_media_type_copper))
2910 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2911 eeer = E1000_READ_REG(hw, E1000_EEER);
2913 /* enable or disable per user setting */
2914 if (!(hw->dev_spec._82575.eee_disable)) {
2915 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2917 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2918 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2921 /* This bit should not be set in normal operation. */
2922 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2923 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2925 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2926 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2929 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2930 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2931 E1000_READ_REG(hw, E1000_IPCNFG);
2932 E1000_READ_REG(hw, E1000_EEER);
2939 * e1000_set_eee_i354 - Enable/disable EEE support
2940 * @hw: pointer to the HW structure
2942 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2945 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2947 struct e1000_phy_info *phy = &hw->phy;
2948 s32 ret_val = E1000_SUCCESS;
2951 DEBUGFUNC("e1000_set_eee_i354");
2953 if ((hw->phy.media_type != e1000_media_type_copper) ||
2954 ((phy->id != M88E1543_E_PHY_ID) &&
2955 (phy->id != M88E1512_E_PHY_ID)))
2958 if (!hw->dev_spec._82575.eee_disable) {
2959 /* Switch to PHY page 18. */
2960 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2964 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2969 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2970 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2975 /* Return the PHY to page 0. */
2976 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2980 /* Turn on EEE advertisement. */
2981 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2982 E1000_EEE_ADV_DEV_I354,
2987 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2988 E1000_EEE_ADV_1000_SUPPORTED;
2989 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2990 E1000_EEE_ADV_DEV_I354,
2993 /* Turn off EEE advertisement. */
2994 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2995 E1000_EEE_ADV_DEV_I354,
3000 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3001 E1000_EEE_ADV_1000_SUPPORTED);
3002 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3003 E1000_EEE_ADV_DEV_I354,
3012 * e1000_get_eee_status_i354 - Get EEE status
3013 * @hw: pointer to the HW structure
3014 * @status: EEE status
3016 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
3019 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3021 struct e1000_phy_info *phy = &hw->phy;
3022 s32 ret_val = E1000_SUCCESS;
3025 DEBUGFUNC("e1000_get_eee_status_i354");
3027 /* Check if EEE is supported on this device. */
3028 if ((hw->phy.media_type != e1000_media_type_copper) ||
3029 ((phy->id != M88E1543_E_PHY_ID) &&
3030 (phy->id != M88E1512_E_PHY_ID)))
3033 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3034 E1000_PCS_STATUS_DEV_I354,
3039 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3040 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3046 /* Due to a hw errata, if the host tries to configure the VFTA register
3047 * while performing queries from the BMC or DMA, then the VFTA in some
3048 * cases won't be written.
3052 * e1000_clear_vfta_i350 - Clear VLAN filter table
3053 * @hw: pointer to the HW structure
3055 * Clears the register array which contains the VLAN filter table by
3056 * setting all the values to 0.
3058 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3063 DEBUGFUNC("e1000_clear_vfta_350");
3065 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3066 for (i = 0; i < 10; i++)
3067 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3069 E1000_WRITE_FLUSH(hw);
3074 * e1000_write_vfta_i350 - Write value to VLAN filter table
3075 * @hw: pointer to the HW structure
3076 * @offset: register offset in VLAN filter table
3077 * @value: register value written to VLAN filter table
3079 * Writes value at the given offset in the register array which stores
3080 * the VLAN filter table.
3082 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3086 DEBUGFUNC("e1000_write_vfta_350");
3088 for (i = 0; i < 10; i++)
3089 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3091 E1000_WRITE_FLUSH(hw);
3096 * e1000_set_i2c_bb - Enable I2C bit-bang
3097 * @hw: pointer to the HW structure
3099 * Enable I2C bit-bang interface
3102 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3104 s32 ret_val = E1000_SUCCESS;
3105 u32 ctrl_ext, i2cparams;
3107 DEBUGFUNC("e1000_set_i2c_bb");
3109 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3110 ctrl_ext |= E1000_CTRL_I2C_ENA;
3111 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3112 E1000_WRITE_FLUSH(hw);
3114 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3115 i2cparams |= E1000_I2CBB_EN;
3116 i2cparams |= E1000_I2C_DATA_OE_N;
3117 i2cparams |= E1000_I2C_CLK_OE_N;
3118 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3119 E1000_WRITE_FLUSH(hw);
3125 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3126 * @hw: pointer to hardware structure
3127 * @byte_offset: byte offset to read
3128 * @dev_addr: device address
3131 * Performs byte read operation over I2C interface at
3132 * a specified device address.
3134 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3135 u8 dev_addr, u8 *data)
3137 s32 status = E1000_SUCCESS;
3144 DEBUGFUNC("e1000_read_i2c_byte_generic");
3146 swfw_mask = E1000_SWFW_PHY0_SM;
3149 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3151 status = E1000_ERR_SWFW_SYNC;
3155 e1000_i2c_start(hw);
3157 /* Device Address and write indication */
3158 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3159 if (status != E1000_SUCCESS)
3162 status = e1000_get_i2c_ack(hw);
3163 if (status != E1000_SUCCESS)
3166 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3167 if (status != E1000_SUCCESS)
3170 status = e1000_get_i2c_ack(hw);
3171 if (status != E1000_SUCCESS)
3174 e1000_i2c_start(hw);
3176 /* Device Address and read indication */
3177 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3178 if (status != E1000_SUCCESS)
3181 status = e1000_get_i2c_ack(hw);
3182 if (status != E1000_SUCCESS)
3185 status = e1000_clock_in_i2c_byte(hw, data);
3186 if (status != E1000_SUCCESS)
3189 status = e1000_clock_out_i2c_bit(hw, nack);
3190 if (status != E1000_SUCCESS)
3197 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3199 e1000_i2c_bus_clear(hw);
3201 if (retry < max_retry)
3202 DEBUGOUT("I2C byte read error - Retrying.\n");
3204 DEBUGOUT("I2C byte read error.\n");
3206 } while (retry < max_retry);
3208 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3216 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3217 * @hw: pointer to hardware structure
3218 * @byte_offset: byte offset to write
3219 * @dev_addr: device address
3220 * @data: value to write
3222 * Performs byte write operation over I2C interface at
3223 * a specified device address.
3225 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3226 u8 dev_addr, u8 data)
3228 s32 status = E1000_SUCCESS;
3233 DEBUGFUNC("e1000_write_i2c_byte_generic");
3235 swfw_mask = E1000_SWFW_PHY0_SM;
3237 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3238 status = E1000_ERR_SWFW_SYNC;
3239 goto write_byte_out;
3243 e1000_i2c_start(hw);
3245 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3246 if (status != E1000_SUCCESS)
3249 status = e1000_get_i2c_ack(hw);
3250 if (status != E1000_SUCCESS)
3253 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3254 if (status != E1000_SUCCESS)
3257 status = e1000_get_i2c_ack(hw);
3258 if (status != E1000_SUCCESS)
3261 status = e1000_clock_out_i2c_byte(hw, data);
3262 if (status != E1000_SUCCESS)
3265 status = e1000_get_i2c_ack(hw);
3266 if (status != E1000_SUCCESS)
3273 e1000_i2c_bus_clear(hw);
3275 if (retry < max_retry)
3276 DEBUGOUT("I2C byte write error - Retrying.\n");
3278 DEBUGOUT("I2C byte write error.\n");
3279 } while (retry < max_retry);
3281 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3289 * e1000_i2c_start - Sets I2C start condition
3290 * @hw: pointer to hardware structure
3292 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3294 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3296 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3298 DEBUGFUNC("e1000_i2c_start");
3300 /* Start condition must begin with data and clock high */
3301 e1000_set_i2c_data(hw, &i2cctl, 1);
3302 e1000_raise_i2c_clk(hw, &i2cctl);
3304 /* Setup time for start condition (4.7us) */
3305 usec_delay(E1000_I2C_T_SU_STA);
3307 e1000_set_i2c_data(hw, &i2cctl, 0);
3309 /* Hold time for start condition (4us) */
3310 usec_delay(E1000_I2C_T_HD_STA);
3312 e1000_lower_i2c_clk(hw, &i2cctl);
3314 /* Minimum low period of clock is 4.7 us */
3315 usec_delay(E1000_I2C_T_LOW);
3320 * e1000_i2c_stop - Sets I2C stop condition
3321 * @hw: pointer to hardware structure
3323 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3325 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3327 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3329 DEBUGFUNC("e1000_i2c_stop");
3331 /* Stop condition must begin with data low and clock high */
3332 e1000_set_i2c_data(hw, &i2cctl, 0);
3333 e1000_raise_i2c_clk(hw, &i2cctl);
3335 /* Setup time for stop condition (4us) */
3336 usec_delay(E1000_I2C_T_SU_STO);
3338 e1000_set_i2c_data(hw, &i2cctl, 1);
3340 /* bus free time between stop and start (4.7us)*/
3341 usec_delay(E1000_I2C_T_BUF);
3345 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3346 * @hw: pointer to hardware structure
3347 * @data: data byte to clock in
3349 * Clocks in one byte data via I2C data/clock
3351 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3356 DEBUGFUNC("e1000_clock_in_i2c_byte");
3359 for (i = 7; i >= 0; i--) {
3360 e1000_clock_in_i2c_bit(hw, &bit);
3364 return E1000_SUCCESS;
3368 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3369 * @hw: pointer to hardware structure
3370 * @data: data byte clocked out
3372 * Clocks out one byte data via I2C data/clock
3374 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3376 s32 status = E1000_SUCCESS;
3381 DEBUGFUNC("e1000_clock_out_i2c_byte");
3383 for (i = 7; i >= 0; i--) {
3384 bit = (data >> i) & 0x1;
3385 status = e1000_clock_out_i2c_bit(hw, bit);
3387 if (status != E1000_SUCCESS)
3391 /* Release SDA line (set high) */
3392 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3394 i2cctl |= E1000_I2C_DATA_OE_N;
3395 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3396 E1000_WRITE_FLUSH(hw);
3402 * e1000_get_i2c_ack - Polls for I2C ACK
3403 * @hw: pointer to hardware structure
3405 * Clocks in/out one bit via I2C data/clock
3407 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3409 s32 status = E1000_SUCCESS;
3411 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3415 DEBUGFUNC("e1000_get_i2c_ack");
3417 e1000_raise_i2c_clk(hw, &i2cctl);
3419 /* Minimum high period of clock is 4us */
3420 usec_delay(E1000_I2C_T_HIGH);
3422 /* Wait until SCL returns high */
3423 for (i = 0; i < timeout; i++) {
3425 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3426 if (i2cctl & E1000_I2C_CLK_IN)
3429 if (!(i2cctl & E1000_I2C_CLK_IN))
3430 return E1000_ERR_I2C;
3432 ack = e1000_get_i2c_data(&i2cctl);
3434 DEBUGOUT("I2C ack was not received.\n");
3435 status = E1000_ERR_I2C;
3438 e1000_lower_i2c_clk(hw, &i2cctl);
3440 /* Minimum low period of clock is 4.7 us */
3441 usec_delay(E1000_I2C_T_LOW);
3447 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3448 * @hw: pointer to hardware structure
3449 * @data: read data value
3451 * Clocks in one bit via I2C data/clock
3453 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3455 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3457 DEBUGFUNC("e1000_clock_in_i2c_bit");
3459 e1000_raise_i2c_clk(hw, &i2cctl);
3461 /* Minimum high period of clock is 4us */
3462 usec_delay(E1000_I2C_T_HIGH);
3464 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3465 *data = e1000_get_i2c_data(&i2cctl);
3467 e1000_lower_i2c_clk(hw, &i2cctl);
3469 /* Minimum low period of clock is 4.7 us */
3470 usec_delay(E1000_I2C_T_LOW);
3472 return E1000_SUCCESS;
3476 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3477 * @hw: pointer to hardware structure
3478 * @data: data value to write
3480 * Clocks out one bit via I2C data/clock
3482 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3485 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3487 DEBUGFUNC("e1000_clock_out_i2c_bit");
3489 status = e1000_set_i2c_data(hw, &i2cctl, data);
3490 if (status == E1000_SUCCESS) {
3491 e1000_raise_i2c_clk(hw, &i2cctl);
3493 /* Minimum high period of clock is 4us */
3494 usec_delay(E1000_I2C_T_HIGH);
3496 e1000_lower_i2c_clk(hw, &i2cctl);
3498 /* Minimum low period of clock is 4.7 us.
3499 * This also takes care of the data hold time.
3501 usec_delay(E1000_I2C_T_LOW);
3503 status = E1000_ERR_I2C;
3504 DEBUGOUT1("I2C data was not set to %X\n", data);
3510 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3511 * @hw: pointer to hardware structure
3512 * @i2cctl: Current value of I2CCTL register
3514 * Raises the I2C clock line '0'->'1'
3516 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3518 DEBUGFUNC("e1000_raise_i2c_clk");
3520 *i2cctl |= E1000_I2C_CLK_OUT;
3521 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3522 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3523 E1000_WRITE_FLUSH(hw);
3525 /* SCL rise time (1000ns) */
3526 usec_delay(E1000_I2C_T_RISE);
3530 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3531 * @hw: pointer to hardware structure
3532 * @i2cctl: Current value of I2CCTL register
3534 * Lowers the I2C clock line '1'->'0'
3536 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3539 DEBUGFUNC("e1000_lower_i2c_clk");
3541 *i2cctl &= ~E1000_I2C_CLK_OUT;
3542 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3543 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3544 E1000_WRITE_FLUSH(hw);
3546 /* SCL fall time (300ns) */
3547 usec_delay(E1000_I2C_T_FALL);
3551 * e1000_set_i2c_data - Sets the I2C data bit
3552 * @hw: pointer to hardware structure
3553 * @i2cctl: Current value of I2CCTL register
3554 * @data: I2C data value (0 or 1) to set
3556 * Sets the I2C data bit
3558 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3560 s32 status = E1000_SUCCESS;
3562 DEBUGFUNC("e1000_set_i2c_data");
3565 *i2cctl |= E1000_I2C_DATA_OUT;
3567 *i2cctl &= ~E1000_I2C_DATA_OUT;
3569 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3570 *i2cctl |= E1000_I2C_CLK_OE_N;
3571 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3572 E1000_WRITE_FLUSH(hw);
3574 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3575 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3577 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3578 if (data != e1000_get_i2c_data(i2cctl)) {
3579 status = E1000_ERR_I2C;
3580 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3587 * e1000_get_i2c_data - Reads the I2C SDA data bit
3588 * @hw: pointer to hardware structure
3589 * @i2cctl: Current value of I2CCTL register
3591 * Returns the I2C data bit value
3593 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3597 DEBUGFUNC("e1000_get_i2c_data");
3599 if (*i2cctl & E1000_I2C_DATA_IN)
3608 * e1000_i2c_bus_clear - Clears the I2C bus
3609 * @hw: pointer to hardware structure
3611 * Clears the I2C bus by sending nine clock pulses.
3612 * Used when data line is stuck low.
3614 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3616 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3619 DEBUGFUNC("e1000_i2c_bus_clear");
3621 e1000_i2c_start(hw);
3623 e1000_set_i2c_data(hw, &i2cctl, 1);
3625 for (i = 0; i < 9; i++) {
3626 e1000_raise_i2c_clk(hw, &i2cctl);
3628 /* Min high period of clock is 4us */
3629 usec_delay(E1000_I2C_T_HIGH);
3631 e1000_lower_i2c_clk(hw, &i2cctl);
3633 /* Min low period of clock is 4.7us*/
3634 usec_delay(E1000_I2C_T_LOW);
3637 e1000_i2c_start(hw);
3639 /* Put the i2c bus back to default state */