drivers/net/e1000/base/e1000_82575.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 /*
   6  * 82575EB Gigabit Network Connection
   7  * 82575EB Gigabit Backplane Connection
   8  * 82575GB Gigabit Network Connection
   9  * 82576 Gigabit Network Connection
  10  * 82576 Quad Port Gigabit Mezzanine Adapter
  11  * 82580 Gigabit Network Connection
  12  * I350 Gigabit Network Connection
  13  */
  14
  15 #include "e1000_api.h"
  16 #include "e1000_i210.h"
  17
  18 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  19 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  20 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  21 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  22 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  23 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  24 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  25 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  26 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  27 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  28                                          u16 *duplex);
  29 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  30 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  31                                            u16 *data);
  32 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  33 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  34 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  35                                      u32 offset, u16 *data);
  36 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  37                                       u32 offset, u16 data);
  38 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  39                                           bool active);
  40 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  41                                           bool active);
  42 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  43                                           bool active);
  44 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  45 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  46 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  47 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  49 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  50                                             u32 offset, u16 data);
  51 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  52 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  53 STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  54                                                  u16 *speed, u16 *duplex);
  55 STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  56 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  57 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  58 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  60 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  61 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  62 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  63 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  64 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  65 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  66 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  67 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  68 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  69                                                  u16 offset);
  70 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
  71                                                    u16 offset);
  72 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
  73 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
  74 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
  75
  76 STATIC void e1000_i2c_start(struct e1000_hw *hw);
  77 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
  78 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
  79 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
  80 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
  81 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
  82 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
  83 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
  84 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
  85 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
  86 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
  87
  88 STATIC const u16 e1000_82580_rxpbs_table[] = {
  89         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
  90 #define E1000_82580_RXPBS_TABLE_SIZE \
  91         (sizeof(e1000_82580_rxpbs_table) / \
  92          sizeof(e1000_82580_rxpbs_table[0]))
  93
  94
  95 /**
  96  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
  97  *  @hw: pointer to the HW structure
  98  *
  99  *  Called to determine if the I2C pins are being used for I2C or as an
 100  *  external MDIO interface since the two options are mutually exclusive.
 101  **/
 102 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 103 {
 104         u32 reg = 0;
 105         bool ext_mdio = false;
 106
 107         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 108
 109         switch (hw->mac.type) {
 110         case e1000_82575:
 111         case e1000_82576:
 112                 reg = E1000_READ_REG(hw, E1000_MDIC);
 113                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 114                 break;
 115         case e1000_82580:
 116         case e1000_i350:
 117         case e1000_i354:
 118         case e1000_i210:
 119         case e1000_i211:
 120                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 121                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 122                 break;
 123         default:
 124                 break;
 125         }
 126         return ext_mdio;
 127 }
 128
 129 /**
 130  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 131  *  @hw: pointer to the HW structure
 132  **/
 133 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 134 {
 135         struct e1000_phy_info *phy = &hw->phy;
 136         s32 ret_val = E1000_SUCCESS;
 137         u32 ctrl_ext;
 138
 139         DEBUGFUNC("e1000_init_phy_params_82575");
 140
 141         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 142         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 143
 144         if (hw->phy.media_type != e1000_media_type_copper) {
 145                 phy->type = e1000_phy_none;
 146                 goto out;
 147         }
 148
 149         phy->ops.power_up   = e1000_power_up_phy_copper;
 150         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 151
 152         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 153         phy->reset_delay_us     = 100;
 154
 155         phy->ops.acquire        = e1000_acquire_phy_82575;
 156         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 157         phy->ops.commit         = e1000_phy_sw_reset_generic;
 158         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 159         phy->ops.release        = e1000_release_phy_82575;
 160
 161         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 162
 163         if (e1000_sgmii_active_82575(hw)) {
 164                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 165                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 166         } else {
 167                 phy->ops.reset = e1000_phy_hw_reset_generic;
 168                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 169         }
 170
 171         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 172         e1000_reset_mdicnfg_82580(hw);
 173
 174         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 175                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 176                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 177         } else {
 178                 switch (hw->mac.type) {
 179                 case e1000_82580:
 180                 case e1000_i350:
 181                 case e1000_i354:
 182                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 183                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 184                         break;
 185                 case e1000_i210:
 186                 case e1000_i211:
 187                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 188                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 189                         break;
 190                 default:
 191                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 192                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 193                 }
 194         }
 195
 196         /* Set phy->phy_addr and phy->id. */
 197         ret_val = e1000_get_phy_id_82575(hw);
 198
 199         /* Verify phy id and set remaining function pointers */
 200         switch (phy->id) {
 201         case M88E1543_E_PHY_ID:
 202         case M88E1512_E_PHY_ID:
 203         case I347AT4_E_PHY_ID:
 204         case M88E1112_E_PHY_ID:
 205         case M88E1340M_E_PHY_ID:
 206         case M88E1111_I_PHY_ID:
 207                 phy->type               = e1000_phy_m88;
 208                 phy->ops.check_polarity = e1000_check_polarity_m88;
 209                 phy->ops.get_info       = e1000_get_phy_info_m88;
 210                 if (phy->id == I347AT4_E_PHY_ID ||
 211                     phy->id == M88E1112_E_PHY_ID ||
 212                     phy->id == M88E1340M_E_PHY_ID)
 213                         phy->ops.get_cable_length =
 214                                          e1000_get_cable_length_m88_gen2;
 215                 else if (phy->id == M88E1543_E_PHY_ID ||
 216                          phy->id == M88E1512_E_PHY_ID)
 217                         phy->ops.get_cable_length =
 218                                          e1000_get_cable_length_m88_gen2;
 219                 else
 220                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 221                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 222                 /* Check if this PHY is confgured for media swap. */
 223                 if (phy->id == M88E1112_E_PHY_ID) {
 224                         u16 data;
 225
 226                         ret_val = phy->ops.write_reg(hw,
 227                                                      E1000_M88E1112_PAGE_ADDR,
 228                                                      2);
 229                         if (ret_val)
 230                                 goto out;
 231
 232                         ret_val = phy->ops.read_reg(hw,
 233                                                     E1000_M88E1112_MAC_CTRL_1,
 234                                                     &data);
 235                         if (ret_val)
 236                                 goto out;
 237
 238                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 239                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 240                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 241                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 242                                 hw->mac.ops.check_for_link =
 243                                                 e1000_check_for_link_media_swap;
 244                 }
 245                 if (phy->id == M88E1512_E_PHY_ID) {
 246                         ret_val = e1000_initialize_M88E1512_phy(hw);
 247                         if (ret_val)
 248                                 goto out;
 249                 }
 250                 if (phy->id == M88E1543_E_PHY_ID) {
 251                         ret_val = e1000_initialize_M88E1543_phy(hw);
 252                         if (ret_val)
 253                                 goto out;
 254                 }
 255                 break;
 256         case IGP03E1000_E_PHY_ID:
 257         case IGP04E1000_E_PHY_ID:
 258                 phy->type = e1000_phy_igp_3;
 259                 phy->ops.check_polarity = e1000_check_polarity_igp;
 260                 phy->ops.get_info = e1000_get_phy_info_igp;
 261                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 262                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 263                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 264                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 265                 break;
 266         case I82580_I_PHY_ID:
 267         case I350_I_PHY_ID:
 268                 phy->type = e1000_phy_82580;
 269                 phy->ops.check_polarity = e1000_check_polarity_82577;
 270                 phy->ops.force_speed_duplex =
 271                                          e1000_phy_force_speed_duplex_82577;
 272                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 273                 phy->ops.get_info = e1000_get_phy_info_82577;
 274                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 275                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 276                 break;
 277         case I210_I_PHY_ID:
 278                 phy->type               = e1000_phy_i210;
 279                 phy->ops.check_polarity = e1000_check_polarity_m88;
 280                 phy->ops.get_info       = e1000_get_phy_info_m88;
 281                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 282                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 283                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 284                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 285                 break;
 286         case BCM54616_E_PHY_ID:
 287                 phy->type               = e1000_phy_none;
 288                 break;
 289         default:
 290                 ret_val = -E1000_ERR_PHY;
 291                 goto out;
 292         }
 293
 294 out:
 295         return ret_val;
 296 }
 297
 298 /**
 299  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 300  *  @hw: pointer to the HW structure
 301  **/
 302 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 303 {
 304         struct e1000_nvm_info *nvm = &hw->nvm;
 305         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 306         u16 size;
 307
 308         DEBUGFUNC("e1000_init_nvm_params_82575");
 309
 310         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 311                      E1000_EECD_SIZE_EX_SHIFT);
 312         /*
 313          * Added to a constant, "size" becomes the left-shift value
 314          * for setting word_size.
 315          */
 316         size += NVM_WORD_SIZE_BASE_SHIFT;
 317
 318         /* Just in case size is out of range, cap it to the largest
 319          * EEPROM size supported
 320          */
 321         if (size > 15)
 322                 size = 15;
 323
 324         nvm->word_size = 1 << size;
 325         if (hw->mac.type < e1000_i210) {
 326                 nvm->opcode_bits = 8;
 327                 nvm->delay_usec = 1;
 328
 329                 switch (nvm->override) {
 330                 case e1000_nvm_override_spi_large:
 331                         nvm->page_size = 32;
 332                         nvm->address_bits = 16;
 333                         break;
 334                 case e1000_nvm_override_spi_small:
 335                         nvm->page_size = 8;
 336                         nvm->address_bits = 8;
 337                         break;
 338                 default:
 339                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 340                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 341                                             16 : 8;
 342                         break;
 343                 }
 344                 if (nvm->word_size == (1 << 15))
 345                         nvm->page_size = 128;
 346
 347                 nvm->type = e1000_nvm_eeprom_spi;
 348         } else {
 349                 nvm->type = e1000_nvm_flash_hw;
 350         }
 351
 352         /* Function Pointers */
 353         nvm->ops.acquire = e1000_acquire_nvm_82575;
 354         nvm->ops.release = e1000_release_nvm_82575;
 355         if (nvm->word_size < (1 << 15))
 356                 nvm->ops.read = e1000_read_nvm_eerd;
 357         else
 358                 nvm->ops.read = e1000_read_nvm_spi;
 359
 360         nvm->ops.write = e1000_write_nvm_spi;
 361         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 362         nvm->ops.update = e1000_update_nvm_checksum_generic;
 363         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 364
 365         /* override generic family function pointers for specific descendants */
 366         switch (hw->mac.type) {
 367         case e1000_82580:
 368                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 369                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 370                 break;
 371         case e1000_i350:
 372         case e1000_i354:
 373                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 374                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 375                 break;
 376         default:
 377                 break;
 378         }
 379
 380         return E1000_SUCCESS;
 381 }
 382
 383 /**
 384  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 385  *  @hw: pointer to the HW structure
 386  **/
 387 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 388 {
 389         struct e1000_mac_info *mac = &hw->mac;
 390         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 391
 392         DEBUGFUNC("e1000_init_mac_params_82575");
 393
 394         /* Derives media type */
 395         e1000_get_media_type_82575(hw);
 396         /* Set mta register count */
 397         mac->mta_reg_count = 128;
 398         /* Set uta register count */
 399         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 400         /* Set rar entry count */
 401         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 402         if (mac->type == e1000_82576)
 403                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 404         if (mac->type == e1000_82580)
 405                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 406         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 407                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 408
 409         /* Enable EEE default settings for EEE supported devices */
 410         if (mac->type >= e1000_i350)
 411                 dev_spec->eee_disable = false;
 412
 413         /* Allow a single clear of the SW semaphore on I210 and newer */
 414         if (mac->type >= e1000_i210)
 415                 dev_spec->clear_semaphore_once = true;
 416
 417         /* Set if part includes ASF firmware */
 418         mac->asf_firmware_present = true;
 419         /* FWSM register */
 420         mac->has_fwsm = true;
 421         /* ARC supported; valid only if manageability features are enabled. */
 422         mac->arc_subsystem_valid =
 423                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 424
 425         /* Function pointers */
 426
 427         /* bus type/speed/width */
 428         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 429         /* reset */
 430         if (mac->type >= e1000_82580)
 431                 mac->ops.reset_hw = e1000_reset_hw_82580;
 432         else
 433         mac->ops.reset_hw = e1000_reset_hw_82575;
 434         /* hw initialization */
 435         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 436                 mac->ops.init_hw = e1000_init_hw_i210;
 437         else
 438         mac->ops.init_hw = e1000_init_hw_82575;
 439         /* link setup */
 440         mac->ops.setup_link = e1000_setup_link_generic;
 441         /* physical interface link setup */
 442         mac->ops.setup_physical_interface =
 443                 (hw->phy.media_type == e1000_media_type_copper)
 444                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 445         /* physical interface shutdown */
 446         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 447         /* physical interface power up */
 448         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 449         /* check for link */
 450         mac->ops.check_for_link = e1000_check_for_link_82575;
 451         /* read mac address */
 452         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 453         /* configure collision distance */
 454         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 455         /* multicast address update */
 456         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 457         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 458                 /* writing VFTA */
 459                 mac->ops.write_vfta = e1000_write_vfta_i350;
 460                 /* clearing VFTA */
 461                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 462         } else {
 463                 /* writing VFTA */
 464                 mac->ops.write_vfta = e1000_write_vfta_generic;
 465                 /* clearing VFTA */
 466                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 467         }
 468         if (hw->mac.type >= e1000_82580)
 469                 mac->ops.validate_mdi_setting =
 470                                 e1000_validate_mdi_setting_crossover_generic;
 471         /* ID LED init */
 472         mac->ops.id_led_init = e1000_id_led_init_generic;
 473         /* blink LED */
 474         mac->ops.blink_led = e1000_blink_led_generic;
 475         /* setup LED */
 476         mac->ops.setup_led = e1000_setup_led_generic;
 477         /* cleanup LED */
 478         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 479         /* turn on/off LED */
 480         mac->ops.led_on = e1000_led_on_generic;
 481         mac->ops.led_off = e1000_led_off_generic;
 482         /* clear hardware counters */
 483         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 484         /* link info */
 485         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 486         /* acquire SW_FW sync */
 487         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 488         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 489         if (mac->type >= e1000_i210) {
 490                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 491                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 492         }
 493
 494         /* set lan id for port to determine which phy lock to use */
 495         hw->mac.ops.set_lan_id(hw);
 496
 497         return E1000_SUCCESS;
 498 }
 499
 500 /**
 501  *  e1000_init_function_pointers_82575 - Init func ptrs.
 502  *  @hw: pointer to the HW structure
 503  *
 504  *  Called to initialize all function pointers and parameters.
 505  **/
 506 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 507 {
 508         DEBUGFUNC("e1000_init_function_pointers_82575");
 509
 510         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 511         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 512         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 513         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 514 }
 515
 516 /**
 517  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 518  *  @hw: pointer to the HW structure
 519  *
 520  *  Acquire access rights to the correct PHY.
 521  **/
 522 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 523 {
 524         u16 mask = E1000_SWFW_PHY0_SM;
 525
 526         DEBUGFUNC("e1000_acquire_phy_82575");
 527
 528         if (hw->bus.func == E1000_FUNC_1)
 529                 mask = E1000_SWFW_PHY1_SM;
 530         else if (hw->bus.func == E1000_FUNC_2)
 531                 mask = E1000_SWFW_PHY2_SM;
 532         else if (hw->bus.func == E1000_FUNC_3)
 533                 mask = E1000_SWFW_PHY3_SM;
 534
 535         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 536 }
 537
 538 /**
 539  *  e1000_release_phy_82575 - Release rights to access PHY
 540  *  @hw: pointer to the HW structure
 541  *
 542  *  A wrapper to release access rights to the correct PHY.
 543  **/
 544 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 545 {
 546         u16 mask = E1000_SWFW_PHY0_SM;
 547
 548         DEBUGFUNC("e1000_release_phy_82575");
 549
 550         if (hw->bus.func == E1000_FUNC_1)
 551                 mask = E1000_SWFW_PHY1_SM;
 552         else if (hw->bus.func == E1000_FUNC_2)
 553                 mask = E1000_SWFW_PHY2_SM;
 554         else if (hw->bus.func == E1000_FUNC_3)
 555                 mask = E1000_SWFW_PHY3_SM;
 556
 557         hw->mac.ops.release_swfw_sync(hw, mask);
 558 }
 559
 560 /**
 561  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 562  *  @hw: pointer to the HW structure
 563  *  @offset: register offset to be read
 564  *  @data: pointer to the read data
 565  *
 566  *  Reads the PHY register at offset using the serial gigabit media independent
 567  *  interface and stores the retrieved information in data.
 568  **/
 569 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 570                                           u16 *data)
 571 {
 572         s32 ret_val = -E1000_ERR_PARAM;
 573
 574         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 575
 576         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 577                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 578                 goto out;
 579         }
 580
 581         ret_val = hw->phy.ops.acquire(hw);
 582         if (ret_val)
 583                 goto out;
 584
 585         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 586
 587         hw->phy.ops.release(hw);
 588
 589 out:
 590         return ret_val;
 591 }
 592
 593 /**
 594  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 595  *  @hw: pointer to the HW structure
 596  *  @offset: register offset to write to
 597  *  @data: data to write at register offset
 598  *
 599  *  Writes the data to PHY register at the offset using the serial gigabit
 600  *  media independent interface.
 601  **/
 602 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 603                                            u16 data)
 604 {
 605         s32 ret_val = -E1000_ERR_PARAM;
 606
 607         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 608
 609         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 610                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 611                 goto out;
 612         }
 613
 614         ret_val = hw->phy.ops.acquire(hw);
 615         if (ret_val)
 616                 goto out;
 617
 618         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 619
 620         hw->phy.ops.release(hw);
 621
 622 out:
 623         return ret_val;
 624 }
 625
 626 /**
 627  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 628  *  @hw: pointer to the HW structure
 629  *
 630  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 631  *  sgmi interface.
 632  **/
 633 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 634 {
 635         struct e1000_phy_info *phy = &hw->phy;
 636         s32  ret_val = E1000_SUCCESS;
 637         u16 phy_id;
 638         u32 ctrl_ext;
 639         u32 mdic;
 640
 641         DEBUGFUNC("e1000_get_phy_id_82575");
 642
 643         /* some i354 devices need an extra read for phy id */
 644         if (hw->mac.type == e1000_i354)
 645                 e1000_get_phy_id(hw);
 646
 647         /*
 648          * For SGMII PHYs, we try the list of possible addresses until
 649          * we find one that works.  For non-SGMII PHYs
 650          * (e.g. integrated copper PHYs), an address of 1 should
 651          * work.  The result of this function should mean phy->phy_addr
 652          * and phy->id are set correctly.
 653          */
 654         if (!e1000_sgmii_active_82575(hw)) {
 655                 phy->addr = 1;
 656                 ret_val = e1000_get_phy_id(hw);
 657                 goto out;
 658         }
 659
 660         if (e1000_sgmii_uses_mdio_82575(hw)) {
 661                 switch (hw->mac.type) {
 662                 case e1000_82575:
 663                 case e1000_82576:
 664                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 665                         mdic &= E1000_MDIC_PHY_MASK;
 666                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 667                         break;
 668                 case e1000_82580:
 669                 case e1000_i350:
 670                 case e1000_i354:
 671                 case e1000_i210:
 672                 case e1000_i211:
 673                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 674                         mdic &= E1000_MDICNFG_PHY_MASK;
 675                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 676                         break;
 677                 default:
 678                         ret_val = -E1000_ERR_PHY;
 679                         goto out;
 680                         break;
 681                 }
 682                 ret_val = e1000_get_phy_id(hw);
 683                 goto out;
 684         }
 685
 686         /* Power on sgmii phy if it is disabled */
 687         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 688         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 689                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 690         E1000_WRITE_FLUSH(hw);
 691         msec_delay(300);
 692
 693         /*
 694          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 695          * Therefore, we need to test 1-7
 696          */
 697         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 698                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 699                 if (ret_val == E1000_SUCCESS) {
 700                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 701                                   phy_id, phy->addr);
 702                         /*
 703                          * At the time of this writing, The M88 part is
 704                          * the only supported SGMII PHY product.
 705                          */
 706                         if (phy_id == M88_VENDOR)
 707                                 break;
 708                 } else {
 709                         DEBUGOUT1("PHY address %u was unreadable\n",
 710                                   phy->addr);
 711                 }
 712         }
 713
 714         /* A valid PHY type couldn't be found. */
 715         if (phy->addr == 8) {
 716                 phy->addr = 0;
 717                 ret_val = -E1000_ERR_PHY;
 718         } else {
 719                 ret_val = e1000_get_phy_id(hw);
 720         }
 721
 722         /* restore previous sfp cage power state */
 723         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 724
 725 out:
 726         return ret_val;
 727 }
 728
 729 /**
 730  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 731  *  @hw: pointer to the HW structure
 732  *
 733  *  Resets the PHY using the serial gigabit media independent interface.
 734  **/
 735 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 736 {
 737         s32 ret_val = E1000_SUCCESS;
 738         struct e1000_phy_info *phy = &hw->phy;
 739
 740         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 741
 742         /*
 743          * This isn't a true "hard" reset, but is the only reset
 744          * available to us at this time.
 745          */
 746
 747         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 748
 749         if (!(hw->phy.ops.write_reg))
 750                 goto out;
 751
 752         /*
 753          * SFP documentation requires the following to configure the SPF module
 754          * to work on SGMII.  No further documentation is given.
 755          */
 756         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 757         if (ret_val)
 758                 goto out;
 759
 760         ret_val = hw->phy.ops.commit(hw);
 761         if (ret_val)
 762                 goto out;
 763
 764         if (phy->id == M88E1512_E_PHY_ID)
 765                 ret_val = e1000_initialize_M88E1512_phy(hw);
 766 out:
 767         return ret_val;
 768 }
 769
 770 /**
 771  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 772  *  @hw: pointer to the HW structure
 773  *  @active: true to enable LPLU, false to disable
 774  *
 775  *  Sets the LPLU D0 state according to the active flag.  When
 776  *  activating LPLU this function also disables smart speed
 777  *  and vice versa.  LPLU will not be activated unless the
 778  *  device autonegotiation advertisement meets standards of
 779  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 780  *  This is a function pointer entry point only called by
 781  *  PHY setup routines.
 782  **/
 783 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 784 {
 785         struct e1000_phy_info *phy = &hw->phy;
 786         s32 ret_val = E1000_SUCCESS;
 787         u16 data;
 788
 789         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 790
 791         if (!(hw->phy.ops.read_reg))
 792                 goto out;
 793
 794         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 795         if (ret_val)
 796                 goto out;
 797
 798         if (active) {
 799                 data |= IGP02E1000_PM_D0_LPLU;
 800                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 801                                              data);
 802                 if (ret_val)
 803                         goto out;
 804
 805                 /* When LPLU is enabled, we should disable SmartSpeed */
 806                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 807                                             &data);
 808                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 809                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 810                                              data);
 811                 if (ret_val)
 812                         goto out;
 813         } else {
 814                 data &= ~IGP02E1000_PM_D0_LPLU;
 815                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 816                                              data);
 817                 /*
 818                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 819                  * during Dx states where the power conservation is most
 820                  * important.  During driver activity we should enable
 821                  * SmartSpeed, so performance is maintained.
 822                  */
 823                 if (phy->smart_speed == e1000_smart_speed_on) {
 824                         ret_val = phy->ops.read_reg(hw,
 825                                                     IGP01E1000_PHY_PORT_CONFIG,
 826                                                     &data);
 827                         if (ret_val)
 828                                 goto out;
 829
 830                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 831                         ret_val = phy->ops.write_reg(hw,
 832                                                      IGP01E1000_PHY_PORT_CONFIG,
 833                                                      data);
 834                         if (ret_val)
 835                                 goto out;
 836                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 837                         ret_val = phy->ops.read_reg(hw,
 838                                                     IGP01E1000_PHY_PORT_CONFIG,
 839                                                     &data);
 840                         if (ret_val)
 841                                 goto out;
 842
 843                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 844                         ret_val = phy->ops.write_reg(hw,
 845                                                      IGP01E1000_PHY_PORT_CONFIG,
 846                                                      data);
 847                         if (ret_val)
 848                                 goto out;
 849                 }
 850         }
 851
 852 out:
 853         return ret_val;
 854 }
 855
 856 /**
 857  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 858  *  @hw: pointer to the HW structure
 859  *  @active: true to enable LPLU, false to disable
 860  *
 861  *  Sets the LPLU D0 state according to the active flag.  When
 862  *  activating LPLU this function also disables smart speed
 863  *  and vice versa.  LPLU will not be activated unless the
 864  *  device autonegotiation advertisement meets standards of
 865  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 866  *  This is a function pointer entry point only called by
 867  *  PHY setup routines.
 868  **/
 869 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 870 {
 871         struct e1000_phy_info *phy = &hw->phy;
 872         u32 data;
 873
 874         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 875
 876         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 877
 878         if (active) {
 879                 data |= E1000_82580_PM_D0_LPLU;
 880
 881                 /* When LPLU is enabled, we should disable SmartSpeed */
 882                 data &= ~E1000_82580_PM_SPD;
 883         } else {
 884                 data &= ~E1000_82580_PM_D0_LPLU;
 885
 886                 /*
 887                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 888                  * during Dx states where the power conservation is most
 889                  * important.  During driver activity we should enable
 890                  * SmartSpeed, so performance is maintained.
 891                  */
 892                 if (phy->smart_speed == e1000_smart_speed_on)
 893                         data |= E1000_82580_PM_SPD;
 894                 else if (phy->smart_speed == e1000_smart_speed_off)
 895                         data &= ~E1000_82580_PM_SPD;
 896         }
 897
 898         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 899         return E1000_SUCCESS;
 900 }
 901
 902 /**
 903  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 904  *  @hw: pointer to the HW structure
 905  *  @active: boolean used to enable/disable lplu
 906  *
 907  *  Success returns 0, Failure returns 1
 908  *
 909  *  The low power link up (lplu) state is set to the power management level D3
 910  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 911  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 912  *  is used during Dx states where the power conservation is most important.
 913  *  During driver activity, SmartSpeed should be enabled so performance is
 914  *  maintained.
 915  **/
 916 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 917 {
 918         struct e1000_phy_info *phy = &hw->phy;
 919         u32 data;
 920
 921         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 922
 923         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 924
 925         if (!active) {
 926                 data &= ~E1000_82580_PM_D3_LPLU;
 927                 /*
 928                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 929                  * during Dx states where the power conservation is most
 930                  * important.  During driver activity we should enable
 931                  * SmartSpeed, so performance is maintained.
 932                  */
 933                 if (phy->smart_speed == e1000_smart_speed_on)
 934                         data |= E1000_82580_PM_SPD;
 935                 else if (phy->smart_speed == e1000_smart_speed_off)
 936                         data &= ~E1000_82580_PM_SPD;
 937         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 938                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 939                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 940                 data |= E1000_82580_PM_D3_LPLU;
 941                 /* When LPLU is enabled, we should disable SmartSpeed */
 942                 data &= ~E1000_82580_PM_SPD;
 943         }
 944
 945         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 946         return E1000_SUCCESS;
 947 }
 948
 949 /**
 950  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 951  *  @hw: pointer to the HW structure
 952  *
 953  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 954  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 955  *  Return successful if access grant bit set, else clear the request for
 956  *  EEPROM access and return -E1000_ERR_NVM (-1).
 957  **/
 958 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 959 {
 960         s32 ret_val = E1000_SUCCESS;
 961
 962         DEBUGFUNC("e1000_acquire_nvm_82575");
 963
 964         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 965         if (ret_val)
 966                 goto out;
 967
 968         /*
 969          * Check if there is some access
 970          * error this access may hook on
 971          */
 972         if (hw->mac.type == e1000_i350) {
 973                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 974                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 975                     E1000_EECD_TIMEOUT)) {
 976                         /* Clear all access error flags */
 977                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 978                                         E1000_EECD_ERROR_CLR);
 979                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 980                 }
 981         }
 982
 983         if (hw->mac.type == e1000_82580) {
 984                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 985                 if (eecd & E1000_EECD_BLOCKED) {
 986                         /* Clear access error flag */
 987                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 988                                         E1000_EECD_BLOCKED);
 989                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 990                 }
 991         }
 992
 993         ret_val = e1000_acquire_nvm_generic(hw);
 994         if (ret_val)
 995                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 996
 997 out:
 998         return ret_val;
 999 }
1000
1001 /**
1002  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1003  *  @hw: pointer to the HW structure
1004  *
1005  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1006  *  then release the semaphores acquired.
1007  **/
1008 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1009 {
1010         DEBUGFUNC("e1000_release_nvm_82575");
1011
1012         e1000_release_nvm_generic(hw);
1013
1014         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1015 }
1016
1017 /**
1018  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1019  *  @hw: pointer to the HW structure
1020  *  @mask: specifies which semaphore to acquire
1021  *
1022  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1023  *  will also specify which port we're acquiring the lock for.
1024  **/
1025 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1026 {
1027         u32 swfw_sync;
1028         u32 swmask = mask;
1029         u32 fwmask = mask << 16;
1030         s32 ret_val = E1000_SUCCESS;
1031         s32 i = 0, timeout = 200;
1032
1033         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1034
1035         while (i < timeout) {
1036                 if (e1000_get_hw_semaphore_generic(hw)) {
1037                         ret_val = -E1000_ERR_SWFW_SYNC;
1038                         goto out;
1039                 }
1040
1041                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1042                 if (!(swfw_sync & (fwmask | swmask)))
1043                         break;
1044
1045                 /*
1046                  * Firmware currently using resource (fwmask)
1047                  * or other software thread using resource (swmask)
1048                  */
1049                 e1000_put_hw_semaphore_generic(hw);
1050                 msec_delay_irq(5);
1051                 i++;
1052         }
1053
1054         if (i == timeout) {
1055                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1056                 ret_val = -E1000_ERR_SWFW_SYNC;
1057                 goto out;
1058         }
1059
1060         swfw_sync |= swmask;
1061         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1062
1063         e1000_put_hw_semaphore_generic(hw);
1064
1065 out:
1066         return ret_val;
1067 }
1068
1069 /**
1070  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1071  *  @hw: pointer to the HW structure
1072  *  @mask: specifies which semaphore to acquire
1073  *
1074  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1075  *  will also specify which port we're releasing the lock for.
1076  **/
1077 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1078 {
1079         u32 swfw_sync;
1080
1081         DEBUGFUNC("e1000_release_swfw_sync_82575");
1082
1083         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1084                 ; /* Empty */
1085
1086         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1087         swfw_sync &= ~mask;
1088         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1089
1090         e1000_put_hw_semaphore_generic(hw);
1091 }
1092
1093 /**
1094  *  e1000_get_cfg_done_82575 - Read config done bit
1095  *  @hw: pointer to the HW structure
1096  *
1097  *  Read the management control register for the config done bit for
1098  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1099  *  to read the config done bit, so an error is *ONLY* logged and returns
1100  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1101  *  would not be able to be reset or change link.
1102  **/
1103 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1104 {
1105         s32 timeout = PHY_CFG_TIMEOUT;
1106         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1107
1108         DEBUGFUNC("e1000_get_cfg_done_82575");
1109
1110         if (hw->bus.func == E1000_FUNC_1)
1111                 mask = E1000_NVM_CFG_DONE_PORT_1;
1112         else if (hw->bus.func == E1000_FUNC_2)
1113                 mask = E1000_NVM_CFG_DONE_PORT_2;
1114         else if (hw->bus.func == E1000_FUNC_3)
1115                 mask = E1000_NVM_CFG_DONE_PORT_3;
1116         while (timeout) {
1117                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1118                         break;
1119                 msec_delay(1);
1120                 timeout--;
1121         }
1122         if (!timeout)
1123                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1124
1125         /* If EEPROM is not marked present, init the PHY manually */
1126         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1127             (hw->phy.type == e1000_phy_igp_3))
1128                 e1000_phy_init_script_igp3(hw);
1129
1130         return E1000_SUCCESS;
1131 }
1132
1133 /**
1134  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1135  *  @hw: pointer to the HW structure
1136  *  @speed: stores the current speed
1137  *  @duplex: stores the current duplex
1138  *
1139  *  This is a wrapper function, if using the serial gigabit media independent
1140  *  interface, use PCS to retrieve the link speed and duplex information.
1141  *  Otherwise, use the generic function to get the link speed and duplex info.
1142  **/
1143 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1144                                         u16 *duplex)
1145 {
1146         s32 ret_val;
1147
1148         DEBUGFUNC("e1000_get_link_up_info_82575");
1149
1150         if (hw->phy.media_type != e1000_media_type_copper)
1151                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1152                                                                duplex);
1153         else
1154                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1155                                                                     duplex);
1156
1157         return ret_val;
1158 }
1159
1160 /**
1161  *  e1000_check_for_link_82575 - Check for link
1162  *  @hw: pointer to the HW structure
1163  *
1164  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1165  *  use the generic interface for determining link.
1166  **/
1167 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1168 {
1169         s32 ret_val;
1170         u16 speed, duplex;
1171
1172         DEBUGFUNC("e1000_check_for_link_82575");
1173
1174         if (hw->phy.media_type != e1000_media_type_copper) {
1175                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1176                                                                &duplex);
1177                 /*
1178                  * Use this flag to determine if link needs to be checked or
1179                  * not.  If we have link clear the flag so that we do not
1180                  * continue to check for link.
1181                  */
1182                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1183
1184                 /*
1185                  * Configure Flow Control now that Auto-Neg has completed.
1186                  * First, we need to restore the desired flow control
1187                  * settings because we may have had to re-autoneg with a
1188                  * different link partner.
1189                  */
1190                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1191                 if (ret_val)
1192                         DEBUGOUT("Error configuring flow control\n");
1193         } else {
1194                 ret_val = e1000_check_for_copper_link_generic(hw);
1195         }
1196
1197         return ret_val;
1198 }
1199
1200 /**
1201  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1202  *  @hw: pointer to the HW structure
1203  *
1204  *  Poll the M88E1112 interfaces to see which interface achieved link.
1205  */
1206 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1207 {
1208         struct e1000_phy_info *phy = &hw->phy;
1209         s32 ret_val;
1210         u16 data;
1211         u8 port = 0;
1212
1213         DEBUGFUNC("e1000_check_for_link_media_swap");
1214
1215         /* Check for copper. */
1216         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1217         if (ret_val)
1218                 return ret_val;
1219
1220         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1221         if (ret_val)
1222                 return ret_val;
1223
1224         if (data & E1000_M88E1112_STATUS_LINK)
1225                 port = E1000_MEDIA_PORT_COPPER;
1226
1227         /* Check for other. */
1228         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1229         if (ret_val)
1230                 return ret_val;
1231
1232         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1233         if (ret_val)
1234                 return ret_val;
1235
1236         if (data & E1000_M88E1112_STATUS_LINK)
1237                 port = E1000_MEDIA_PORT_OTHER;
1238
1239         /* Determine if a swap needs to happen. */
1240         if (port && (hw->dev_spec._82575.media_port != port)) {
1241                 hw->dev_spec._82575.media_port = port;
1242                 hw->dev_spec._82575.media_changed = true;
1243         }
1244
1245         if (port == E1000_MEDIA_PORT_COPPER) {
1246                 /* reset page to 0 */
1247                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1248                 if (ret_val)
1249                         return ret_val;
1250                 e1000_check_for_link_82575(hw);
1251         } else {
1252                 e1000_check_for_link_82575(hw);
1253                 /* reset page to 0 */
1254                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1255                 if (ret_val)
1256                         return ret_val;
1257         }
1258
1259         return E1000_SUCCESS;
1260 }
1261
1262 /**
1263  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1264  *  @hw: pointer to the HW structure
1265  **/
1266 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1267 {
1268         u32 reg;
1269
1270         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1271
1272         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1273             !e1000_sgmii_active_82575(hw))
1274                 return;
1275
1276         /* Enable PCS to turn on link */
1277         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1278         reg |= E1000_PCS_CFG_PCS_EN;
1279         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1280
1281         /* Power up the laser */
1282         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1283         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1284         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1285
1286         /* flush the write to verify completion */
1287         E1000_WRITE_FLUSH(hw);
1288         msec_delay(1);
1289 }
1290
1291 /**
1292  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1293  *  @hw: pointer to the HW structure
1294  *  @speed: stores the current speed
1295  *  @duplex: stores the current duplex
1296  *
1297  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1298  *  duplex, then store the values in the pointers provided.
1299  **/
1300 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1301                                                 u16 *speed, u16 *duplex)
1302 {
1303         struct e1000_mac_info *mac = &hw->mac;
1304         u32 pcs;
1305         u32 status;
1306
1307         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1308
1309         /*
1310          * Read the PCS Status register for link state. For non-copper mode,
1311          * the status register is not accurate. The PCS status register is
1312          * used instead.
1313          */
1314         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1315
1316         /*
1317          * The link up bit determines when link is up on autoneg.
1318          */
1319         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1320                 mac->serdes_has_link = true;
1321
1322                 /* Detect and store PCS speed */
1323                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1324                         *speed = SPEED_1000;
1325                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1326                         *speed = SPEED_100;
1327                 else
1328                         *speed = SPEED_10;
1329
1330                 /* Detect and store PCS duplex */
1331                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1332                         *duplex = FULL_DUPLEX;
1333                 else
1334                         *duplex = HALF_DUPLEX;
1335
1336                 /* Check if it is an I354 2.5Gb backplane connection. */
1337                 if (mac->type == e1000_i354) {
1338                         status = E1000_READ_REG(hw, E1000_STATUS);
1339                         if ((status & E1000_STATUS_2P5_SKU) &&
1340                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1341                                 *speed = SPEED_2500;
1342                                 *duplex = FULL_DUPLEX;
1343                                 DEBUGOUT("2500 Mbs, ");
1344                                 DEBUGOUT("Full Duplex\n");
1345                         }
1346                 }
1347
1348         } else {
1349                 mac->serdes_has_link = false;
1350                 *speed = 0;
1351                 *duplex = 0;
1352         }
1353
1354         return E1000_SUCCESS;
1355 }
1356
1357 /**
1358  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1359  *  @hw: pointer to the HW structure
1360  *
1361  *  In the case of serdes shut down sfp and PCS on driver unload
1362  *  when management pass thru is not enabled.
1363  **/
1364 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1365 {
1366         u32 reg;
1367
1368         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1369
1370         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1371             !e1000_sgmii_active_82575(hw))
1372                 return;
1373
1374         if (!e1000_enable_mng_pass_thru(hw)) {
1375                 /* Disable PCS to turn off link */
1376                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1377                 reg &= ~E1000_PCS_CFG_PCS_EN;
1378                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1379
1380                 /* shutdown the laser */
1381                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1382                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1383                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1384
1385                 /* flush the write to verify completion */
1386                 E1000_WRITE_FLUSH(hw);
1387                 msec_delay(1);
1388         }
1389
1390         return;
1391 }
1392
1393 /**
1394  *  e1000_reset_hw_82575 - Reset hardware
1395  *  @hw: pointer to the HW structure
1396  *
1397  *  This resets the hardware into a known state.
1398  **/
1399 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1400 {
1401         u32 ctrl;
1402         s32 ret_val;
1403
1404         DEBUGFUNC("e1000_reset_hw_82575");
1405
1406         /*
1407          * Prevent the PCI-E bus from sticking if there is no TLP connection
1408          * on the last TLP read/write transaction when MAC is reset.
1409          */
1410         ret_val = e1000_disable_pcie_master_generic(hw);
1411         if (ret_val)
1412                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1413
1414         /* set the completion timeout for interface */
1415         ret_val = e1000_set_pcie_completion_timeout(hw);
1416         if (ret_val)
1417                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1418
1419         DEBUGOUT("Masking off all interrupts\n");
1420         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1421
1422         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1423         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1424         E1000_WRITE_FLUSH(hw);
1425
1426         msec_delay(10);
1427
1428         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1429
1430         DEBUGOUT("Issuing a global reset to MAC\n");
1431         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1432
1433         ret_val = e1000_get_auto_rd_done_generic(hw);
1434         if (ret_val) {
1435                 /*
1436                  * When auto config read does not complete, do not
1437                  * return with an error. This can happen in situations
1438                  * where there is no eeprom and prevents getting link.
1439                  */
1440                 DEBUGOUT("Auto Read Done did not complete\n");
1441         }
1442
1443         /* If EEPROM is not present, run manual init scripts */
1444         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1445                 e1000_reset_init_script_82575(hw);
1446
1447         /* Clear any pending interrupt events. */
1448         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1449         E1000_READ_REG(hw, E1000_ICR);
1450
1451         /* Install any alternate MAC address into RAR0 */
1452         ret_val = e1000_check_alt_mac_addr_generic(hw);
1453
1454         return ret_val;
1455 }
1456
1457 /**
1458  *  e1000_init_hw_82575 - Initialize hardware
1459  *  @hw: pointer to the HW structure
1460  *
1461  *  This inits the hardware readying it for operation.
1462  **/
1463 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1464 {
1465         struct e1000_mac_info *mac = &hw->mac;
1466         s32 ret_val;
1467         u16 i, rar_count = mac->rar_entry_count;
1468
1469         DEBUGFUNC("e1000_init_hw_82575");
1470
1471         /* Initialize identification LED */
1472         ret_val = mac->ops.id_led_init(hw);
1473         if (ret_val) {
1474                 DEBUGOUT("Error initializing identification LED\n");
1475                 /* This is not fatal and we should not stop init due to this */
1476         }
1477
1478         /* Disabling VLAN filtering */
1479         DEBUGOUT("Initializing the IEEE VLAN\n");
1480         mac->ops.clear_vfta(hw);
1481
1482         /* Setup the receive address */
1483         e1000_init_rx_addrs_generic(hw, rar_count);
1484
1485         /* Zero out the Multicast HASH table */
1486         DEBUGOUT("Zeroing the MTA\n");
1487         for (i = 0; i < mac->mta_reg_count; i++)
1488                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1489
1490         /* Zero out the Unicast HASH table */
1491         DEBUGOUT("Zeroing the UTA\n");
1492         for (i = 0; i < mac->uta_reg_count; i++)
1493                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1494
1495         /* Setup link and flow control */
1496         ret_val = mac->ops.setup_link(hw);
1497
1498         /* Set the default MTU size */
1499         hw->dev_spec._82575.mtu = 1500;
1500
1501         /*
1502          * Clear all of the statistics registers (clear on read).  It is
1503          * important that we do this after we have tried to establish link
1504          * because the symbol error count will increment wildly if there
1505          * is no link.
1506          */
1507         e1000_clear_hw_cntrs_82575(hw);
1508
1509         return ret_val;
1510 }
1511
1512 /**
1513  *  e1000_setup_copper_link_82575 - Configure copper link settings
1514  *  @hw: pointer to the HW structure
1515  *
1516  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1517  *  for link, once link is established calls to configure collision distance
1518  *  and flow control are called.
1519  **/
1520 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1521 {
1522         u32 ctrl;
1523         s32 ret_val;
1524         u32 phpm_reg;
1525
1526         DEBUGFUNC("e1000_setup_copper_link_82575");
1527
1528         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1529         ctrl |= E1000_CTRL_SLU;
1530         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1531         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1532
1533         /* Clear Go Link Disconnect bit on supported devices */
1534         switch (hw->mac.type) {
1535         case e1000_82580:
1536         case e1000_i350:
1537         case e1000_i210:
1538         case e1000_i211:
1539                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1540                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1541                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1542                 break;
1543         default:
1544                 break;
1545         }
1546
1547         ret_val = e1000_setup_serdes_link_82575(hw);
1548         if (ret_val)
1549                 goto out;
1550
1551         if (e1000_sgmii_active_82575(hw)) {
1552                 /* allow time for SFP cage time to power up phy */
1553                 msec_delay(300);
1554
1555                 ret_val = hw->phy.ops.reset(hw);
1556                 if (ret_val) {
1557                         DEBUGOUT("Error resetting the PHY.\n");
1558                         goto out;
1559                 }
1560         }
1561         switch (hw->phy.type) {
1562         case e1000_phy_i210:
1563         case e1000_phy_m88:
1564                 switch (hw->phy.id) {
1565                 case I347AT4_E_PHY_ID:
1566                 case M88E1112_E_PHY_ID:
1567                 case M88E1340M_E_PHY_ID:
1568                 case M88E1543_E_PHY_ID:
1569                 case M88E1512_E_PHY_ID:
1570                 case I210_I_PHY_ID:
1571                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1572                         break;
1573                 default:
1574                         ret_val = e1000_copper_link_setup_m88(hw);
1575                         break;
1576                 }
1577                 break;
1578         case e1000_phy_igp_3:
1579                 ret_val = e1000_copper_link_setup_igp(hw);
1580                 break;
1581         case e1000_phy_82580:
1582                 ret_val = e1000_copper_link_setup_82577(hw);
1583                 break;
1584         case e1000_phy_none:
1585                 break;
1586         default:
1587                 ret_val = -E1000_ERR_PHY;
1588                 break;
1589         }
1590
1591         if (ret_val)
1592                 goto out;
1593
1594         ret_val = e1000_setup_copper_link_generic(hw);
1595 out:
1596         return ret_val;
1597 }
1598
1599 /**
1600  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1601  *  @hw: pointer to the HW structure
1602  *
1603  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1604  *  used on copper connections where the serialized gigabit media independent
1605  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1606  *  for auto-negotiation or forces speed/duplex.
1607  **/
1608 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1609 {
1610         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1611         bool pcs_autoneg;
1612         s32 ret_val = E1000_SUCCESS;
1613         u16 data;
1614
1615         DEBUGFUNC("e1000_setup_serdes_link_82575");
1616
1617         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1618             !e1000_sgmii_active_82575(hw))
1619                 return ret_val;
1620
1621         /*
1622          * On the 82575, SerDes loopback mode persists until it is
1623          * explicitly turned off or a power cycle is performed.  A read to
1624          * the register does not indicate its status.  Therefore, we ensure
1625          * loopback mode is disabled during initialization.
1626          */
1627         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1628
1629         /* power on the sfp cage if present */
1630         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1631         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1632         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1633
1634         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1635         ctrl_reg |= E1000_CTRL_SLU;
1636
1637         /* set both sw defined pins on 82575/82576*/
1638         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1639                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1640
1641         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1642
1643         /* default pcs_autoneg to the same setting as mac autoneg */
1644         pcs_autoneg = hw->mac.autoneg;
1645
1646         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1647         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1648                 /* sgmii mode lets the phy handle forcing speed/duplex */
1649                 pcs_autoneg = true;
1650                 /* autoneg time out should be disabled for SGMII mode */
1651                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1652                 break;
1653         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1654                 /* disable PCS autoneg and support parallel detect only */
1655                 pcs_autoneg = false;
1656                 /* fall through to default case */
1657         default:
1658                 if (hw->mac.type == e1000_82575 ||
1659                     hw->mac.type == e1000_82576) {
1660                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1661                         if (ret_val) {
1662                                 DEBUGOUT("NVM Read Error\n");
1663                                 return ret_val;
1664                         }
1665
1666                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1667                                 pcs_autoneg = false;
1668                 }
1669
1670                 /*
1671                  * non-SGMII modes only supports a speed of 1000/Full for the
1672                  * link so it is best to just force the MAC and let the pcs
1673                  * link either autoneg or be forced to 1000/Full
1674                  */
1675                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1676                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1677
1678                 /* set speed of 1000/Full if speed/duplex is forced */
1679                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1680                 break;
1681         }
1682
1683         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1684
1685         /*
1686          * New SerDes mode allows for forcing speed or autonegotiating speed
1687          * at 1gb. Autoneg should be default set by most drivers. This is the
1688          * mode that will be compatible with older link partners and switches.
1689          * However, both are supported by the hardware and some drivers/tools.
1690          */
1691         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1692                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1693
1694         if (pcs_autoneg) {
1695                 /* Set PCS register for autoneg */
1696                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1697                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1698
1699                 /* Disable force flow control for autoneg */
1700                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1701
1702                 /* Configure flow control advertisement for autoneg */
1703                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1704                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1705
1706                 switch (hw->fc.requested_mode) {
1707                 case e1000_fc_full:
1708                 case e1000_fc_rx_pause:
1709                         anadv_reg |= E1000_TXCW_ASM_DIR;
1710                         anadv_reg |= E1000_TXCW_PAUSE;
1711                         break;
1712                 case e1000_fc_tx_pause:
1713                         anadv_reg |= E1000_TXCW_ASM_DIR;
1714                         break;
1715                 default:
1716                         break;
1717                 }
1718
1719                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1720
1721                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1722         } else {
1723                 /* Set PCS register for forced link */
1724                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1725
1726                 /* Force flow control for forced link */
1727                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1728
1729                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1730         }
1731
1732         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1733
1734         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1735                 e1000_force_mac_fc_generic(hw);
1736
1737         return ret_val;
1738 }
1739
1740 /**
1741  *  e1000_get_media_type_82575 - derives current media type.
1742  *  @hw: pointer to the HW structure
1743  *
1744  *  The media type is chosen reflecting few settings.
1745  *  The following are taken into account:
1746  *  - link mode set in the current port Init Control Word #3
1747  *  - current link mode settings in CSR register
1748  *  - MDIO vs. I2C PHY control interface chosen
1749  *  - SFP module media type
1750  **/
1751 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1752 {
1753         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1754         s32 ret_val = E1000_SUCCESS;
1755         u32 ctrl_ext = 0;
1756         u32 link_mode = 0;
1757
1758         /* Set internal phy as default */
1759         dev_spec->sgmii_active = false;
1760         dev_spec->module_plugged = false;
1761
1762         /* Get CSR setting */
1763         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1764
1765         /* extract link mode setting */
1766         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1767
1768         switch (link_mode) {
1769         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1770                 hw->phy.media_type = e1000_media_type_internal_serdes;
1771                 break;
1772         case E1000_CTRL_EXT_LINK_MODE_GMII:
1773                 hw->phy.media_type = e1000_media_type_copper;
1774                 break;
1775         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1776                 /* Get phy control interface type set (MDIO vs. I2C)*/
1777                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1778                         hw->phy.media_type = e1000_media_type_copper;
1779                         dev_spec->sgmii_active = true;
1780                         break;
1781                 }
1782                 /* fall through for I2C based SGMII */
1783         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1784                 /* read media type from SFP EEPROM */
1785                 ret_val = e1000_set_sfp_media_type_82575(hw);
1786                 if ((ret_val != E1000_SUCCESS) ||
1787                     (hw->phy.media_type == e1000_media_type_unknown)) {
1788                         /*
1789                          * If media type was not identified then return media
1790                          * type defined by the CTRL_EXT settings.
1791                          */
1792                         hw->phy.media_type = e1000_media_type_internal_serdes;
1793
1794                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1795                                 hw->phy.media_type = e1000_media_type_copper;
1796                                 dev_spec->sgmii_active = true;
1797                         }
1798
1799                         break;
1800                 }
1801
1802                 /* do not change link mode for 100BaseFX */
1803                 if (dev_spec->eth_flags.e100_base_fx)
1804                         break;
1805
1806                 /* change current link mode setting */
1807                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1808
1809                 if (hw->phy.media_type == e1000_media_type_copper)
1810                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1811                 else
1812                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1813
1814                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1815
1816                 break;
1817         }
1818
1819         return ret_val;
1820 }
1821
1822 /**
1823  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1824  *  @hw: pointer to the HW structure
1825  *
1826  *  The media type is chosen based on SFP module.
1827  *  compatibility flags retrieved from SFP ID EEPROM.
1828  **/
1829 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1830 {
1831         s32 ret_val = E1000_ERR_CONFIG;
1832         u32 ctrl_ext = 0;
1833         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1834         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1835         u8 tranceiver_type = 0;
1836         s32 timeout = 3;
1837
1838         /* Turn I2C interface ON and power on sfp cage */
1839         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1840         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1841         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1842
1843         E1000_WRITE_FLUSH(hw);
1844
1845         /* Read SFP module data */
1846         while (timeout) {
1847                 ret_val = e1000_read_sfp_data_byte(hw,
1848                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1849                         &tranceiver_type);
1850                 if (ret_val == E1000_SUCCESS)
1851                         break;
1852                 msec_delay(100);
1853                 timeout--;
1854         }
1855         if (ret_val != E1000_SUCCESS)
1856                 goto out;
1857
1858         ret_val = e1000_read_sfp_data_byte(hw,
1859                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1860                         (u8 *)eth_flags);
1861         if (ret_val != E1000_SUCCESS)
1862                 goto out;
1863
1864         /* Check if there is some SFP module plugged and powered */
1865         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1866             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1867                 dev_spec->module_plugged = true;
1868                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1869                         hw->phy.media_type = e1000_media_type_internal_serdes;
1870                 } else if (eth_flags->e100_base_fx) {
1871                         dev_spec->sgmii_active = true;
1872                         hw->phy.media_type = e1000_media_type_internal_serdes;
1873                 } else if (eth_flags->e1000_base_t) {
1874                         dev_spec->sgmii_active = true;
1875                         hw->phy.media_type = e1000_media_type_copper;
1876                 } else {
1877                         hw->phy.media_type = e1000_media_type_unknown;
1878                         DEBUGOUT("PHY module has not been recognized\n");
1879                         goto out;
1880                 }
1881         } else {
1882                 hw->phy.media_type = e1000_media_type_unknown;
1883         }
1884         ret_val = E1000_SUCCESS;
1885 out:
1886         /* Restore I2C interface setting */
1887         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1888         return ret_val;
1889 }
1890
1891 /**
1892  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1893  *  @hw: pointer to the HW structure
1894  *  @data: pointer to the NVM (EEPROM)
1895  *
1896  *  Read the EEPROM for the current default LED configuration.  If the
1897  *  LED configuration is not valid, set to a valid LED configuration.
1898  **/
1899 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1900 {
1901         s32 ret_val;
1902
1903         DEBUGFUNC("e1000_valid_led_default_82575");
1904
1905         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1906         if (ret_val) {
1907                 DEBUGOUT("NVM Read Error\n");
1908                 goto out;
1909         }
1910
1911         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1912                 switch (hw->phy.media_type) {
1913                 case e1000_media_type_internal_serdes:
1914                         *data = ID_LED_DEFAULT_82575_SERDES;
1915                         break;
1916                 case e1000_media_type_copper:
1917                 default:
1918                         *data = ID_LED_DEFAULT;
1919                         break;
1920                 }
1921         }
1922 out:
1923         return ret_val;
1924 }
1925
1926 /**
1927  *  e1000_sgmii_active_82575 - Return sgmii state
1928  *  @hw: pointer to the HW structure
1929  *
1930  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1931  *  which can be enabled for use in the embedded applications.  Simply
1932  *  return the current state of the sgmii interface.
1933  **/
1934 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1935 {
1936         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1937         return dev_spec->sgmii_active;
1938 }
1939
1940 /**
1941  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1942  *  @hw: pointer to the HW structure
1943  *
1944  *  Inits recommended HW defaults after a reset when there is no EEPROM
1945  *  detected. This is only for the 82575.
1946  **/
1947 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1948 {
1949         DEBUGFUNC("e1000_reset_init_script_82575");
1950
1951         if (hw->mac.type == e1000_82575) {
1952                 DEBUGOUT("Running reset init script for 82575\n");
1953                 /* SerDes configuration via SERDESCTRL */
1954                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1955                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1956                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1957                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1958
1959                 /* CCM configuration via CCMCTL register */
1960                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1961                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1962
1963                 /* PCIe lanes configuration */
1964                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1965                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1966                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1967                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1968
1969                 /* PCIe PLL Configuration */
1970                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1971                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1972                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1973         }
1974
1975         return E1000_SUCCESS;
1976 }
1977
1978 /**
1979  *  e1000_read_mac_addr_82575 - Read device MAC address
1980  *  @hw: pointer to the HW structure
1981  **/
1982 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1983 {
1984         s32 ret_val;
1985
1986         DEBUGFUNC("e1000_read_mac_addr_82575");
1987
1988         /*
1989          * If there's an alternate MAC address place it in RAR0
1990          * so that it will override the Si installed default perm
1991          * address.
1992          */
1993         ret_val = e1000_check_alt_mac_addr_generic(hw);
1994         if (ret_val)
1995                 goto out;
1996
1997         ret_val = e1000_read_mac_addr_generic(hw);
1998
1999 out:
2000         return ret_val;
2001 }
2002
2003 /**
2004  *  e1000_config_collision_dist_82575 - Configure collision distance
2005  *  @hw: pointer to the HW structure
2006  *
2007  *  Configures the collision distance to the default value and is used
2008  *  during link setup.
2009  **/
2010 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2011 {
2012         u32 tctl_ext;
2013
2014         DEBUGFUNC("e1000_config_collision_dist_82575");
2015
2016         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2017
2018         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2019         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2020
2021         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2022         E1000_WRITE_FLUSH(hw);
2023 }
2024
2025 /**
2026  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2027  * @hw: pointer to the HW structure
2028  *
2029  * In the case of a PHY power down to save power, or to turn off link during a
2030  * driver unload, or wake on lan is not enabled, remove the link.
2031  **/
2032 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2033 {
2034         struct e1000_phy_info *phy = &hw->phy;
2035
2036         if (!(phy->ops.check_reset_block))
2037                 return;
2038
2039         /* If the management interface is not enabled, then power down */
2040         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2041                 e1000_power_down_phy_copper(hw);
2042
2043         return;
2044 }
2045
2046 /**
2047  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2048  *  @hw: pointer to the HW structure
2049  *
2050  *  Clears the hardware counters by reading the counter registers.
2051  **/
2052 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2053 {
2054         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2055
2056         e1000_clear_hw_cntrs_base_generic(hw);
2057
2058         E1000_READ_REG(hw, E1000_PRC64);
2059         E1000_READ_REG(hw, E1000_PRC127);
2060         E1000_READ_REG(hw, E1000_PRC255);
2061         E1000_READ_REG(hw, E1000_PRC511);
2062         E1000_READ_REG(hw, E1000_PRC1023);
2063         E1000_READ_REG(hw, E1000_PRC1522);
2064         E1000_READ_REG(hw, E1000_PTC64);
2065         E1000_READ_REG(hw, E1000_PTC127);
2066         E1000_READ_REG(hw, E1000_PTC255);
2067         E1000_READ_REG(hw, E1000_PTC511);
2068         E1000_READ_REG(hw, E1000_PTC1023);
2069         E1000_READ_REG(hw, E1000_PTC1522);
2070
2071         E1000_READ_REG(hw, E1000_ALGNERRC);
2072         E1000_READ_REG(hw, E1000_RXERRC);
2073         E1000_READ_REG(hw, E1000_TNCRS);
2074         E1000_READ_REG(hw, E1000_CEXTERR);
2075         E1000_READ_REG(hw, E1000_TSCTC);
2076         E1000_READ_REG(hw, E1000_TSCTFC);
2077
2078         E1000_READ_REG(hw, E1000_MGTPRC);
2079         E1000_READ_REG(hw, E1000_MGTPDC);
2080         E1000_READ_REG(hw, E1000_MGTPTC);
2081
2082         E1000_READ_REG(hw, E1000_IAC);
2083         E1000_READ_REG(hw, E1000_ICRXOC);
2084
2085         E1000_READ_REG(hw, E1000_ICRXPTC);
2086         E1000_READ_REG(hw, E1000_ICRXATC);
2087         E1000_READ_REG(hw, E1000_ICTXPTC);
2088         E1000_READ_REG(hw, E1000_ICTXATC);
2089         E1000_READ_REG(hw, E1000_ICTXQEC);
2090         E1000_READ_REG(hw, E1000_ICTXQMTC);
2091         E1000_READ_REG(hw, E1000_ICRXDMTC);
2092
2093         E1000_READ_REG(hw, E1000_CBTMPC);
2094         E1000_READ_REG(hw, E1000_HTDPMC);
2095         E1000_READ_REG(hw, E1000_CBRMPC);
2096         E1000_READ_REG(hw, E1000_RPTHC);
2097         E1000_READ_REG(hw, E1000_HGPTC);
2098         E1000_READ_REG(hw, E1000_HTCBDPC);
2099         E1000_READ_REG(hw, E1000_HGORCL);
2100         E1000_READ_REG(hw, E1000_HGORCH);
2101         E1000_READ_REG(hw, E1000_HGOTCL);
2102         E1000_READ_REG(hw, E1000_HGOTCH);
2103         E1000_READ_REG(hw, E1000_LENERRS);
2104
2105         /* This register should not be read in copper configurations */
2106         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2107             e1000_sgmii_active_82575(hw))
2108                 E1000_READ_REG(hw, E1000_SCVPC);
2109 }
2110
2111 /**
2112  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2113  *  @hw: pointer to the HW structure
2114  *
2115  *  After Rx enable, if manageability is enabled then there is likely some
2116  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2117  *  function clears the fifos and flushes any packets that came in as rx was
2118  *  being enabled.
2119  **/
2120 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2121 {
2122         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2123         int i, ms_wait;
2124
2125         DEBUGFUNC("e1000_rx_fifo_flush_82575");
2126
2127         /* disable IPv6 options as per hardware errata */
2128         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2129         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
2130         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2131
2132         if (hw->mac.type != e1000_82575 ||
2133             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2134                 return;
2135
2136         /* Disable all Rx queues */
2137         for (i = 0; i < 4; i++) {
2138                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2139                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2140                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2141         }
2142         /* Poll all queues to verify they have shut down */
2143         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2144                 msec_delay(1);
2145                 rx_enabled = 0;
2146                 for (i = 0; i < 4; i++)
2147                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2148                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2149                         break;
2150         }
2151
2152         if (ms_wait == 10)
2153                 DEBUGOUT("Queue disable timed out after 10ms\n");
2154
2155         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2156          * incoming packets are rejected.  Set enable and wait 2ms so that
2157          * any packet that was coming in as RCTL.EN was set is flushed
2158          */
2159         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2160
2161         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2162         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2163
2164         rctl = E1000_READ_REG(hw, E1000_RCTL);
2165         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2166         temp_rctl |= E1000_RCTL_LPE;
2167
2168         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2169         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2170         E1000_WRITE_FLUSH(hw);
2171         msec_delay(2);
2172
2173         /* Enable Rx queues that were previously enabled and restore our
2174          * previous state
2175          */
2176         for (i = 0; i < 4; i++)
2177                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2178         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2179         E1000_WRITE_FLUSH(hw);
2180
2181         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2182         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2183
2184         /* Flush receive errors generated by workaround */
2185         E1000_READ_REG(hw, E1000_ROC);
2186         E1000_READ_REG(hw, E1000_RNBC);
2187         E1000_READ_REG(hw, E1000_MPC);
2188 }
2189
2190 /**
2191  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2192  *  @hw: pointer to the HW structure
2193  *
2194  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2195  *  however the hardware default for these parts is 500us to 1ms which is less
2196  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2197  *  increase the value to either 10ms to 200ms for capability version 1 config,
2198  *  or 16ms to 55ms for version 2.
2199  **/
2200 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2201 {
2202         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2203         s32 ret_val = E1000_SUCCESS;
2204         u16 pcie_devctl2;
2205
2206         /* only take action if timeout value is defaulted to 0 */
2207         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2208                 goto out;
2209
2210         /*
2211          * if capababilities version is type 1 we can write the
2212          * timeout of 10ms to 200ms through the GCR register
2213          */
2214         if (!(gcr & E1000_GCR_CAP_VER2)) {
2215                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2216                 goto out;
2217         }
2218
2219         /*
2220          * for version 2 capabilities we need to write the config space
2221          * directly in order to set the completion timeout value for
2222          * 16ms to 55ms
2223          */
2224         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2225                                           &pcie_devctl2);
2226         if (ret_val)
2227                 goto out;
2228
2229         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2230
2231         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2232                                            &pcie_devctl2);
2233 out:
2234         /* disable completion timeout resend */
2235         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2236
2237         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2238         return ret_val;
2239 }
2240
2241 /**
2242  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2243  *  @hw: pointer to the hardware struct
2244  *  @enable: state to enter, either enabled or disabled
2245  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2246  *
2247  *  enables/disables L2 switch anti-spoofing functionality.
2248  **/
2249 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2250 {
2251         u32 reg_val, reg_offset;
2252
2253         switch (hw->mac.type) {
2254         case e1000_82576:
2255                 reg_offset = E1000_DTXSWC;
2256                 break;
2257         case e1000_i350:
2258         case e1000_i354:
2259                 reg_offset = E1000_TXSWC;
2260                 break;
2261         default:
2262                 return;
2263         }
2264
2265         reg_val = E1000_READ_REG(hw, reg_offset);
2266         if (enable) {
2267                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2268                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2269                 /* The PF can spoof - it has to in order to
2270                  * support emulation mode NICs
2271                  */
2272                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2273         } else {
2274                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2275                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2276         }
2277         E1000_WRITE_REG(hw, reg_offset, reg_val);
2278 }
2279
2280 /**
2281  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2282  *  @hw: pointer to the hardware struct
2283  *  @enable: state to enter, either enabled or disabled
2284  *
2285  *  enables/disables L2 switch loopback functionality.
2286  **/
2287 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2288 {
2289         u32 dtxswc;
2290
2291         switch (hw->mac.type) {
2292         case e1000_82576:
2293                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2294                 if (enable)
2295                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2296                 else
2297                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2298                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2299                 break;
2300         case e1000_i350:
2301         case e1000_i354:
2302                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2303                 if (enable)
2304                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2305                 else
2306                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2307                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2308                 break;
2309         default:
2310                 /* Currently no other hardware supports loopback */
2311                 break;
2312         }
2313
2314
2315 }
2316
2317 /**
2318  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2319  *  @hw: pointer to the hardware struct
2320  *  @enable: state to enter, either enabled or disabled
2321  *
2322  *  enables/disables replication of packets across multiple pools.
2323  **/
2324 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2325 {
2326         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2327
2328         if (enable)
2329                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2330         else
2331                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2332
2333         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2334 }
2335
2336 /**
2337  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2338  *  @hw: pointer to the HW structure
2339  *  @offset: register offset to be read
2340  *  @data: pointer to the read data
2341  *
2342  *  Reads the MDI control register in the PHY at offset and stores the
2343  *  information read to data.
2344  **/
2345 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2346 {
2347         s32 ret_val;
2348
2349         DEBUGFUNC("e1000_read_phy_reg_82580");
2350
2351         ret_val = hw->phy.ops.acquire(hw);
2352         if (ret_val)
2353                 goto out;
2354
2355         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2356
2357         hw->phy.ops.release(hw);
2358
2359 out:
2360         return ret_val;
2361 }
2362
2363 /**
2364  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2365  *  @hw: pointer to the HW structure
2366  *  @offset: register offset to write to
2367  *  @data: data to write to register at offset
2368  *
2369  *  Writes data to MDI control register in the PHY at offset.
2370  **/
2371 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2372 {
2373         s32 ret_val;
2374
2375         DEBUGFUNC("e1000_write_phy_reg_82580");
2376
2377         ret_val = hw->phy.ops.acquire(hw);
2378         if (ret_val)
2379                 goto out;
2380
2381         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2382
2383         hw->phy.ops.release(hw);
2384
2385 out:
2386         return ret_val;
2387 }
2388
2389 /**
2390  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2391  *  @hw: pointer to the HW structure
2392  *
2393  *  This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2394  *  the values found in the EEPROM.  This addresses an issue in which these
2395  *  bits are not restored from EEPROM after reset.
2396  **/
2397 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2398 {
2399         s32 ret_val = E1000_SUCCESS;
2400         u32 mdicnfg;
2401         u16 nvm_data = 0;
2402
2403         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2404
2405         if (hw->mac.type != e1000_82580)
2406                 goto out;
2407         if (!e1000_sgmii_active_82575(hw))
2408                 goto out;
2409
2410         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2411                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2412                                    &nvm_data);
2413         if (ret_val) {
2414                 DEBUGOUT("NVM Read Error\n");
2415                 goto out;
2416         }
2417
2418         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2419         if (nvm_data & NVM_WORD24_EXT_MDIO)
2420                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2421         if (nvm_data & NVM_WORD24_COM_MDIO)
2422                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2423         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2424 out:
2425         return ret_val;
2426 }
2427
2428 /**
2429  *  e1000_reset_hw_82580 - Reset hardware
2430  *  @hw: pointer to the HW structure
2431  *
2432  *  This resets function or entire device (all ports, etc.)
2433  *  to a known state.
2434  **/
2435 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2436 {
2437         s32 ret_val = E1000_SUCCESS;
2438         /* BH SW mailbox bit in SW_FW_SYNC */
2439         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2440         u32 ctrl;
2441         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2442
2443         DEBUGFUNC("e1000_reset_hw_82580");
2444
2445         hw->dev_spec._82575.global_device_reset = false;
2446
2447         /* 82580 does not reliably do global_device_reset due to hw errata */
2448         if (hw->mac.type == e1000_82580)
2449                 global_device_reset = false;
2450
2451         /* Get current control state. */
2452         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2453
2454         /*
2455          * Prevent the PCI-E bus from sticking if there is no TLP connection
2456          * on the last TLP read/write transaction when MAC is reset.
2457          */
2458         ret_val = e1000_disable_pcie_master_generic(hw);
2459         if (ret_val)
2460                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2461
2462         DEBUGOUT("Masking off all interrupts\n");
2463         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2464         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2465         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2466         E1000_WRITE_FLUSH(hw);
2467
2468         msec_delay(10);
2469
2470         /* Determine whether or not a global dev reset is requested */
2471         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2472             swmbsw_mask))
2473                         global_device_reset = false;
2474
2475         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2476             E1000_STAT_DEV_RST_SET))
2477                 ctrl |= E1000_CTRL_DEV_RST;
2478         else
2479                 ctrl |= E1000_CTRL_RST;
2480
2481         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2482
2483         switch (hw->device_id) {
2484         case E1000_DEV_ID_DH89XXCC_SGMII:
2485                 break;
2486         default:
2487                 E1000_WRITE_FLUSH(hw);
2488                 break;
2489         }
2490
2491         /* Add delay to insure DEV_RST or RST has time to complete */
2492         msec_delay(5);
2493
2494         ret_val = e1000_get_auto_rd_done_generic(hw);
2495         if (ret_val) {
2496                 /*
2497                  * When auto config read does not complete, do not
2498                  * return with an error. This can happen in situations
2499                  * where there is no eeprom and prevents getting link.
2500                  */
2501                 DEBUGOUT("Auto Read Done did not complete\n");
2502         }
2503
2504         /* clear global device reset status bit */
2505         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2506
2507         /* Clear any pending interrupt events. */
2508         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2509         E1000_READ_REG(hw, E1000_ICR);
2510
2511         ret_val = e1000_reset_mdicnfg_82580(hw);
2512         if (ret_val)
2513                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2514
2515         /* Install any alternate MAC address into RAR0 */
2516         ret_val = e1000_check_alt_mac_addr_generic(hw);
2517
2518         /* Release semaphore */
2519         if (global_device_reset)
2520                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2521
2522         return ret_val;
2523 }
2524
2525 /**
2526  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2527  *  @data: data received by reading RXPBS register
2528  *
2529  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2530  *  This function converts the retrieved value into the correct table value
2531  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2532  *  0x0 36  72 144   1   2   4   8  16
2533  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2534  */
2535 u16 e1000_rxpbs_adjust_82580(u32 data)
2536 {
2537         u16 ret_val = 0;
2538
2539         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2540                 ret_val = e1000_82580_rxpbs_table[data];
2541
2542         return ret_val;
2543 }
2544
2545 /**
2546  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2547  *  checksum
2548  *  @hw: pointer to the HW structure
2549  *  @offset: offset in words of the checksum protected region
2550  *
2551  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2552  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2553  **/
2554 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2555 {
2556         s32 ret_val = E1000_SUCCESS;
2557         u16 checksum = 0;
2558         u16 i, nvm_data;
2559
2560         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2561
2562         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2563                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2564                 if (ret_val) {
2565                         DEBUGOUT("NVM Read Error\n");
2566                         goto out;
2567                 }
2568                 checksum += nvm_data;
2569         }
2570
2571         if (checksum != (u16) NVM_SUM) {
2572                 DEBUGOUT("NVM Checksum Invalid\n");
2573                 ret_val = -E1000_ERR_NVM;
2574                 goto out;
2575         }
2576
2577 out:
2578         return ret_val;
2579 }
2580
2581 /**
2582  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2583  *  checksum
2584  *  @hw: pointer to the HW structure
2585  *  @offset: offset in words of the checksum protected region
2586  *
2587  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2588  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2589  *  value to the EEPROM.
2590  **/
2591 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2592 {
2593         s32 ret_val;
2594         u16 checksum = 0;
2595         u16 i, nvm_data;
2596
2597         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2598
2599         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2600                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2601                 if (ret_val) {
2602                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2603                         goto out;
2604                 }
2605                 checksum += nvm_data;
2606         }
2607         checksum = (u16) NVM_SUM - checksum;
2608         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2609                                     &checksum);
2610         if (ret_val)
2611                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2612
2613 out:
2614         return ret_val;
2615 }
2616
2617 /**
2618  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2619  *  @hw: pointer to the HW structure
2620  *
2621  *  Calculates the EEPROM section checksum by reading/adding each word of
2622  *  the EEPROM and then verifies that the sum of the EEPROM is
2623  *  equal to 0xBABA.
2624  **/
2625 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2626 {
2627         s32 ret_val;
2628         u16 eeprom_regions_count = 1;
2629         u16 j, nvm_data;
2630         u16 nvm_offset;
2631
2632         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2633
2634         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2635         if (ret_val) {
2636                 DEBUGOUT("NVM Read Error\n");
2637                 goto out;
2638         }
2639
2640         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2641                 /* if chekcsums compatibility bit is set validate checksums
2642                  * for all 4 ports. */
2643                 eeprom_regions_count = 4;
2644         }
2645
2646         for (j = 0; j < eeprom_regions_count; j++) {
2647                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2648                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2649                                                                   nvm_offset);
2650                 if (ret_val != E1000_SUCCESS)
2651                         goto out;
2652         }
2653
2654 out:
2655         return ret_val;
2656 }
2657
2658 /**
2659  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2660  *  @hw: pointer to the HW structure
2661  *
2662  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2663  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2664  *  checksum and writes the value to the EEPROM.
2665  **/
2666 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2667 {
2668         s32 ret_val;
2669         u16 j, nvm_data;
2670         u16 nvm_offset;
2671
2672         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2673
2674         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2675         if (ret_val) {
2676                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2677                 goto out;
2678         }
2679
2680         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2681                 /* set compatibility bit to validate checksums appropriately */
2682                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2683                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2684                                             &nvm_data);
2685                 if (ret_val) {
2686                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2687                         goto out;
2688                 }
2689         }
2690
2691         for (j = 0; j < 4; j++) {
2692                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2693                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2694                 if (ret_val)
2695                         goto out;
2696         }
2697
2698 out:
2699         return ret_val;
2700 }
2701
2702 /**
2703  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2704  *  @hw: pointer to the HW structure
2705  *
2706  *  Calculates the EEPROM section checksum by reading/adding each word of
2707  *  the EEPROM and then verifies that the sum of the EEPROM is
2708  *  equal to 0xBABA.
2709  **/
2710 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2711 {
2712         s32 ret_val = E1000_SUCCESS;
2713         u16 j;
2714         u16 nvm_offset;
2715
2716         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2717
2718         for (j = 0; j < 4; j++) {
2719                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2720                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2721                                                                   nvm_offset);
2722                 if (ret_val != E1000_SUCCESS)
2723                         goto out;
2724         }
2725
2726 out:
2727         return ret_val;
2728 }
2729
2730 /**
2731  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2732  *  @hw: pointer to the HW structure
2733  *
2734  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2735  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2736  *  checksum and writes the value to the EEPROM.
2737  **/
2738 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2739 {
2740         s32 ret_val = E1000_SUCCESS;
2741         u16 j;
2742         u16 nvm_offset;
2743
2744         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2745
2746         for (j = 0; j < 4; j++) {
2747                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2748                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2749                 if (ret_val != E1000_SUCCESS)
2750                         goto out;
2751         }
2752
2753 out:
2754         return ret_val;
2755 }
2756
2757 /**
2758  *  __e1000_access_emi_reg - Read/write EMI register
2759  *  @hw: pointer to the HW structure
2760  *  @addr: EMI address to program
2761  *  @data: pointer to value to read/write from/to the EMI address
2762  *  @read: boolean flag to indicate read or write
2763  **/
2764 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2765                                   u16 *data, bool read)
2766 {
2767         s32 ret_val;
2768
2769         DEBUGFUNC("__e1000_access_emi_reg");
2770
2771         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2772         if (ret_val)
2773                 return ret_val;
2774
2775         if (read)
2776                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2777         else
2778                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2779
2780         return ret_val;
2781 }
2782
2783 /**
2784  *  e1000_read_emi_reg - Read Extended Management Interface register
2785  *  @hw: pointer to the HW structure
2786  *  @addr: EMI address to program
2787  *  @data: value to be read from the EMI address
2788  **/
2789 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2790 {
2791         DEBUGFUNC("e1000_read_emi_reg");
2792
2793         return __e1000_access_emi_reg(hw, addr, data, true);
2794 }
2795
2796 /**
2797  *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2798  *  @hw: pointer to the HW structure
2799  *
2800  *  Initialize Marvell 1512 to work correctly with Avoton.
2801  **/
2802 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2803 {
2804         struct e1000_phy_info *phy = &hw->phy;
2805         s32 ret_val = E1000_SUCCESS;
2806
2807         DEBUGFUNC("e1000_initialize_M88E1512_phy");
2808
2809         /* Check if this is correct PHY. */
2810         if (phy->id != M88E1512_E_PHY_ID)
2811                 goto out;
2812
2813         /* Switch to PHY page 0xFF. */
2814         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2815         if (ret_val)
2816                 goto out;
2817
2818         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2819         if (ret_val)
2820                 goto out;
2821
2822         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2823         if (ret_val)
2824                 goto out;
2825
2826         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2827         if (ret_val)
2828                 goto out;
2829
2830         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2831         if (ret_val)
2832                 goto out;
2833
2834         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2835         if (ret_val)
2836                 goto out;
2837
2838         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2839         if (ret_val)
2840                 goto out;
2841
2842         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2843         if (ret_val)
2844                 goto out;
2845
2846         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2847         if (ret_val)
2848                 goto out;
2849
2850         /* Switch to PHY page 0xFB. */
2851         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2852         if (ret_val)
2853                 goto out;
2854
2855         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2856         if (ret_val)
2857                 goto out;
2858
2859         /* Switch to PHY page 0x12. */
2860         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2861         if (ret_val)
2862                 goto out;
2863
2864         /* Change mode to SGMII-to-Copper */
2865         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2866         if (ret_val)
2867                 goto out;
2868
2869         /* Return the PHY to page 0. */
2870         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2871         if (ret_val)
2872                 goto out;
2873
2874         ret_val = phy->ops.commit(hw);
2875         if (ret_val) {
2876                 DEBUGOUT("Error committing the PHY changes\n");
2877                 return ret_val;
2878         }
2879
2880         msec_delay(1000);
2881 out:
2882         return ret_val;
2883 }
2884
2885 /**
2886  *  e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2887  *  @hw: pointer to the HW structure
2888  *
2889  *  Initialize Marvell 1543 to work correctly with Avoton.
2890  **/
2891 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2892 {
2893         struct e1000_phy_info *phy = &hw->phy;
2894         s32 ret_val = E1000_SUCCESS;
2895
2896         DEBUGFUNC("e1000_initialize_M88E1543_phy");
2897
2898         /* Check if this is correct PHY. */
2899         if (phy->id != M88E1543_E_PHY_ID)
2900                 goto out;
2901
2902         /* Switch to PHY page 0xFF. */
2903         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2904         if (ret_val)
2905                 goto out;
2906
2907         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2908         if (ret_val)
2909                 goto out;
2910
2911         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2912         if (ret_val)
2913                 goto out;
2914
2915         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2916         if (ret_val)
2917                 goto out;
2918
2919         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2920         if (ret_val)
2921                 goto out;
2922
2923         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2924         if (ret_val)
2925                 goto out;
2926
2927         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2928         if (ret_val)
2929                 goto out;
2930
2931         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2932         if (ret_val)
2933                 goto out;
2934
2935         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2936         if (ret_val)
2937                 goto out;
2938
2939         /* Switch to PHY page 0xFB. */
2940         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2941         if (ret_val)
2942                 goto out;
2943
2944         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2945         if (ret_val)
2946                 goto out;
2947
2948         /* Switch to PHY page 0x12. */
2949         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2950         if (ret_val)
2951                 goto out;
2952
2953         /* Change mode to SGMII-to-Copper */
2954         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2955         if (ret_val)
2956                 goto out;
2957
2958         /* Switch to PHY page 1. */
2959         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2960         if (ret_val)
2961                 goto out;
2962
2963         /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2964         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2965         if (ret_val)
2966                 goto out;
2967
2968         /* Return the PHY to page 0. */
2969         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2970         if (ret_val)
2971                 goto out;
2972
2973         ret_val = phy->ops.commit(hw);
2974         if (ret_val) {
2975                 DEBUGOUT("Error committing the PHY changes\n");
2976                 return ret_val;
2977         }
2978
2979         msec_delay(1000);
2980 out:
2981         return ret_val;
2982 }
2983
2984 /**
2985  *  e1000_set_eee_i350 - Enable/disable EEE support
2986  *  @hw: pointer to the HW structure
2987  *  @adv1g: boolean flag enabling 1G EEE advertisement
2988  *  @adv100m: boolean flag enabling 100M EEE advertisement
2989  *
2990  *  Enable/disable EEE based on setting in dev_spec structure.
2991  *
2992  **/
2993 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2994 {
2995         u32 ipcnfg, eeer;
2996
2997         DEBUGFUNC("e1000_set_eee_i350");
2998
2999         if ((hw->mac.type < e1000_i350) ||
3000             (hw->phy.media_type != e1000_media_type_copper))
3001                 goto out;
3002         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
3003         eeer = E1000_READ_REG(hw, E1000_EEER);
3004
3005         /* enable or disable per user setting */
3006         if (!(hw->dev_spec._82575.eee_disable)) {
3007                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
3008
3009                 if (adv100M)
3010                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
3011                 else
3012                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
3013
3014                 if (adv1G)
3015                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
3016                 else
3017                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
3018
3019                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3020                          E1000_EEER_LPI_FC);
3021
3022                 /* This bit should not be set in normal operation. */
3023                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
3024                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
3025         } else {
3026                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
3027                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3028                           E1000_EEER_LPI_FC);
3029         }
3030         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
3031         E1000_WRITE_REG(hw, E1000_EEER, eeer);
3032         E1000_READ_REG(hw, E1000_IPCNFG);
3033         E1000_READ_REG(hw, E1000_EEER);
3034 out:
3035
3036         return E1000_SUCCESS;
3037 }
3038
3039 /**
3040  *  e1000_set_eee_i354 - Enable/disable EEE support
3041  *  @hw: pointer to the HW structure
3042  *  @adv1g: boolean flag enabling 1G EEE advertisement
3043  *  @adv100m: boolean flag enabling 100M EEE advertisement
3044  *
3045  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
3046  *
3047  **/
3048 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
3049 {
3050         struct e1000_phy_info *phy = &hw->phy;
3051         s32 ret_val = E1000_SUCCESS;
3052         u16 phy_data;
3053
3054         DEBUGFUNC("e1000_set_eee_i354");
3055
3056         if ((hw->phy.media_type != e1000_media_type_copper) ||
3057             ((phy->id != M88E1543_E_PHY_ID) &&
3058             (phy->id != M88E1512_E_PHY_ID)))
3059                 goto out;
3060
3061         if (!hw->dev_spec._82575.eee_disable) {
3062                 /* Switch to PHY page 18. */
3063                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3064                 if (ret_val)
3065                         goto out;
3066
3067                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3068                                             &phy_data);
3069                 if (ret_val)
3070                         goto out;
3071
3072                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
3073                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3074                                              phy_data);
3075                 if (ret_val)
3076                         goto out;
3077
3078                 /* Return the PHY to page 0. */
3079                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3080                 if (ret_val)
3081                         goto out;
3082
3083                 /* Turn on EEE advertisement. */
3084                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3085                                                E1000_EEE_ADV_DEV_I354,
3086                                                &phy_data);
3087                 if (ret_val)
3088                         goto out;
3089
3090                 if (adv100M)
3091                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
3092                 else
3093                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
3094
3095                 if (adv1G)
3096                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
3097                 else
3098                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
3099
3100                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3101                                                 E1000_EEE_ADV_DEV_I354,
3102                                                 phy_data);
3103         } else {
3104                 /* Turn off EEE advertisement. */
3105                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3106                                                E1000_EEE_ADV_DEV_I354,
3107                                                &phy_data);
3108                 if (ret_val)
3109                         goto out;
3110
3111                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3112                               E1000_EEE_ADV_1000_SUPPORTED);
3113                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3114                                                 E1000_EEE_ADV_DEV_I354,
3115                                                 phy_data);
3116         }
3117
3118 out:
3119         return ret_val;
3120 }
3121
3122 /**
3123  *  e1000_get_eee_status_i354 - Get EEE status
3124  *  @hw: pointer to the HW structure
3125  *  @status: EEE status
3126  *
3127  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3128  *  been received.
3129  **/
3130 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3131 {
3132         struct e1000_phy_info *phy = &hw->phy;
3133         s32 ret_val = E1000_SUCCESS;
3134         u16 phy_data;
3135
3136         DEBUGFUNC("e1000_get_eee_status_i354");
3137
3138         /* Check if EEE is supported on this device. */
3139         if ((hw->phy.media_type != e1000_media_type_copper) ||
3140             ((phy->id != M88E1543_E_PHY_ID) &&
3141             (phy->id != M88E1512_E_PHY_ID)))
3142                 goto out;
3143
3144         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3145                                        E1000_PCS_STATUS_DEV_I354,
3146                                        &phy_data);
3147         if (ret_val)
3148                 goto out;
3149
3150         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3151                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3152
3153 out:
3154         return ret_val;
3155 }
3156
3157 /* Due to a hw errata, if the host tries to  configure the VFTA register
3158  * while performing queries from the BMC or DMA, then the VFTA in some
3159  * cases won't be written.
3160  */
3161
3162 /**
3163  *  e1000_clear_vfta_i350 - Clear VLAN filter table
3164  *  @hw: pointer to the HW structure
3165  *
3166  *  Clears the register array which contains the VLAN filter table by
3167  *  setting all the values to 0.
3168  **/
3169 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3170 {
3171         u32 offset;
3172         int i;
3173
3174         DEBUGFUNC("e1000_clear_vfta_350");
3175
3176         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3177                 for (i = 0; i < 10; i++)
3178                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3179
3180                 E1000_WRITE_FLUSH(hw);
3181         }
3182 }
3183
3184 /**
3185  *  e1000_write_vfta_i350 - Write value to VLAN filter table
3186  *  @hw: pointer to the HW structure
3187  *  @offset: register offset in VLAN filter table
3188  *  @value: register value written to VLAN filter table
3189  *
3190  *  Writes value at the given offset in the register array which stores
3191  *  the VLAN filter table.
3192  **/
3193 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3194 {
3195         int i;
3196
3197         DEBUGFUNC("e1000_write_vfta_350");
3198
3199         for (i = 0; i < 10; i++)
3200                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3201
3202         E1000_WRITE_FLUSH(hw);
3203 }
3204
3205
3206 /**
3207  *  e1000_set_i2c_bb - Enable I2C bit-bang
3208  *  @hw: pointer to the HW structure
3209  *
3210  *  Enable I2C bit-bang interface
3211  *
3212  **/
3213 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3214 {
3215         s32 ret_val = E1000_SUCCESS;
3216         u32 ctrl_ext, i2cparams;
3217
3218         DEBUGFUNC("e1000_set_i2c_bb");
3219
3220         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3221         ctrl_ext |= E1000_CTRL_I2C_ENA;
3222         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3223         E1000_WRITE_FLUSH(hw);
3224
3225         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3226         i2cparams |= E1000_I2CBB_EN;
3227         i2cparams |= E1000_I2C_DATA_OE_N;
3228         i2cparams |= E1000_I2C_CLK_OE_N;
3229         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3230         E1000_WRITE_FLUSH(hw);
3231
3232         return ret_val;
3233 }
3234
3235 /**
3236  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3237  *  @hw: pointer to hardware structure
3238  *  @byte_offset: byte offset to read
3239  *  @dev_addr: device address
3240  *  @data: value read
3241  *
3242  *  Performs byte read operation over I2C interface at
3243  *  a specified device address.
3244  **/
3245 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3246                                 u8 dev_addr, u8 *data)
3247 {
3248         s32 status = E1000_SUCCESS;
3249         u32 max_retry = 10;
3250         u32 retry = 1;
3251         u16 swfw_mask = 0;
3252
3253         bool nack = true;
3254
3255         DEBUGFUNC("e1000_read_i2c_byte_generic");
3256
3257         swfw_mask = E1000_SWFW_PHY0_SM;
3258
3259         do {
3260                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3261                     != E1000_SUCCESS) {
3262                         status = E1000_ERR_SWFW_SYNC;
3263                         goto read_byte_out;
3264                 }
3265
3266                 e1000_i2c_start(hw);
3267
3268                 /* Device Address and write indication */
3269                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3270                 if (status != E1000_SUCCESS)
3271                         goto fail;
3272
3273                 status = e1000_get_i2c_ack(hw);
3274                 if (status != E1000_SUCCESS)
3275                         goto fail;
3276
3277                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3278                 if (status != E1000_SUCCESS)
3279                         goto fail;
3280
3281                 status = e1000_get_i2c_ack(hw);
3282                 if (status != E1000_SUCCESS)
3283                         goto fail;
3284
3285                 e1000_i2c_start(hw);
3286
3287                 /* Device Address and read indication */
3288                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3289                 if (status != E1000_SUCCESS)
3290                         goto fail;
3291
3292                 status = e1000_get_i2c_ack(hw);
3293                 if (status != E1000_SUCCESS)
3294                         goto fail;
3295
3296                 status = e1000_clock_in_i2c_byte(hw, data);
3297                 if (status != E1000_SUCCESS)
3298                         goto fail;
3299
3300                 status = e1000_clock_out_i2c_bit(hw, nack);
3301                 if (status != E1000_SUCCESS)
3302                         goto fail;
3303
3304                 e1000_i2c_stop(hw);
3305                 break;
3306
3307 fail:
3308                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3309                 msec_delay(100);
3310                 e1000_i2c_bus_clear(hw);
3311                 retry++;
3312                 if (retry < max_retry)
3313                         DEBUGOUT("I2C byte read error - Retrying.\n");
3314                 else
3315                         DEBUGOUT("I2C byte read error.\n");
3316
3317         } while (retry < max_retry);
3318
3319         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3320
3321 read_byte_out:
3322
3323         return status;
3324 }
3325
3326 /**
3327  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3328  *  @hw: pointer to hardware structure
3329  *  @byte_offset: byte offset to write
3330  *  @dev_addr: device address
3331  *  @data: value to write
3332  *
3333  *  Performs byte write operation over I2C interface at
3334  *  a specified device address.
3335  **/
3336 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3337                                  u8 dev_addr, u8 data)
3338 {
3339         s32 status = E1000_SUCCESS;
3340         u32 max_retry = 1;
3341         u32 retry = 0;
3342         u16 swfw_mask = 0;
3343
3344         DEBUGFUNC("e1000_write_i2c_byte_generic");
3345
3346         swfw_mask = E1000_SWFW_PHY0_SM;
3347
3348         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3349                 status = E1000_ERR_SWFW_SYNC;
3350                 goto write_byte_out;
3351         }
3352
3353         do {
3354                 e1000_i2c_start(hw);
3355
3356                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3357                 if (status != E1000_SUCCESS)
3358                         goto fail;
3359
3360                 status = e1000_get_i2c_ack(hw);
3361                 if (status != E1000_SUCCESS)
3362                         goto fail;
3363
3364                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3365                 if (status != E1000_SUCCESS)
3366                         goto fail;
3367
3368                 status = e1000_get_i2c_ack(hw);
3369                 if (status != E1000_SUCCESS)
3370                         goto fail;
3371
3372                 status = e1000_clock_out_i2c_byte(hw, data);
3373                 if (status != E1000_SUCCESS)
3374                         goto fail;
3375
3376                 status = e1000_get_i2c_ack(hw);
3377                 if (status != E1000_SUCCESS)
3378                         goto fail;
3379
3380                 e1000_i2c_stop(hw);
3381                 break;
3382
3383 fail:
3384                 e1000_i2c_bus_clear(hw);
3385                 retry++;
3386                 if (retry < max_retry)
3387                         DEBUGOUT("I2C byte write error - Retrying.\n");
3388                 else
3389                         DEBUGOUT("I2C byte write error.\n");
3390         } while (retry < max_retry);
3391
3392         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3393
3394 write_byte_out:
3395
3396         return status;
3397 }
3398
3399 /**
3400  *  e1000_i2c_start - Sets I2C start condition
3401  *  @hw: pointer to hardware structure
3402  *
3403  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3404  **/
3405 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3406 {
3407         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3408
3409         DEBUGFUNC("e1000_i2c_start");
3410
3411         /* Start condition must begin with data and clock high */
3412         e1000_set_i2c_data(hw, &i2cctl, 1);
3413         e1000_raise_i2c_clk(hw, &i2cctl);
3414
3415         /* Setup time for start condition (4.7us) */
3416         usec_delay(E1000_I2C_T_SU_STA);
3417
3418         e1000_set_i2c_data(hw, &i2cctl, 0);
3419
3420         /* Hold time for start condition (4us) */
3421         usec_delay(E1000_I2C_T_HD_STA);
3422
3423         e1000_lower_i2c_clk(hw, &i2cctl);
3424
3425         /* Minimum low period of clock is 4.7 us */
3426         usec_delay(E1000_I2C_T_LOW);
3427
3428 }
3429
3430 /**
3431  *  e1000_i2c_stop - Sets I2C stop condition
3432  *  @hw: pointer to hardware structure
3433  *
3434  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3435  **/
3436 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3437 {
3438         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3439
3440         DEBUGFUNC("e1000_i2c_stop");
3441
3442         /* Stop condition must begin with data low and clock high */
3443         e1000_set_i2c_data(hw, &i2cctl, 0);
3444         e1000_raise_i2c_clk(hw, &i2cctl);
3445
3446         /* Setup time for stop condition (4us) */
3447         usec_delay(E1000_I2C_T_SU_STO);
3448
3449         e1000_set_i2c_data(hw, &i2cctl, 1);
3450
3451         /* bus free time between stop and start (4.7us)*/
3452         usec_delay(E1000_I2C_T_BUF);
3453 }
3454
3455 /**
3456  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3457  *  @hw: pointer to hardware structure
3458  *  @data: data byte to clock in
3459  *
3460  *  Clocks in one byte data via I2C data/clock
3461  **/
3462 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3463 {
3464         s32 i;
3465         bool bit = 0;
3466
3467         DEBUGFUNC("e1000_clock_in_i2c_byte");
3468
3469         *data = 0;
3470         for (i = 7; i >= 0; i--) {
3471                 e1000_clock_in_i2c_bit(hw, &bit);
3472                 *data |= bit << i;
3473         }
3474
3475         return E1000_SUCCESS;
3476 }
3477
3478 /**
3479  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3480  *  @hw: pointer to hardware structure
3481  *  @data: data byte clocked out
3482  *
3483  *  Clocks out one byte data via I2C data/clock
3484  **/
3485 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3486 {
3487         s32 status = E1000_SUCCESS;
3488         s32 i;
3489         u32 i2cctl;
3490         bool bit = 0;
3491
3492         DEBUGFUNC("e1000_clock_out_i2c_byte");
3493
3494         for (i = 7; i >= 0; i--) {
3495                 bit = (data >> i) & 0x1;
3496                 status = e1000_clock_out_i2c_bit(hw, bit);
3497
3498                 if (status != E1000_SUCCESS)
3499                         break;
3500         }
3501
3502         /* Release SDA line (set high) */
3503         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3504
3505         i2cctl |= E1000_I2C_DATA_OE_N;
3506         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3507         E1000_WRITE_FLUSH(hw);
3508
3509         return status;
3510 }
3511
3512 /**
3513  *  e1000_get_i2c_ack - Polls for I2C ACK
3514  *  @hw: pointer to hardware structure
3515  *
3516  *  Clocks in/out one bit via I2C data/clock
3517  **/
3518 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3519 {
3520         s32 status = E1000_SUCCESS;
3521         u32 i = 0;
3522         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3523         u32 timeout = 10;
3524         bool ack = true;
3525
3526         DEBUGFUNC("e1000_get_i2c_ack");
3527
3528         e1000_raise_i2c_clk(hw, &i2cctl);
3529
3530         /* Minimum high period of clock is 4us */
3531         usec_delay(E1000_I2C_T_HIGH);
3532
3533         /* Wait until SCL returns high */
3534         for (i = 0; i < timeout; i++) {
3535                 usec_delay(1);
3536                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3537                 if (i2cctl & E1000_I2C_CLK_IN)
3538                         break;
3539         }
3540         if (!(i2cctl & E1000_I2C_CLK_IN))
3541                 return E1000_ERR_I2C;
3542
3543         ack = e1000_get_i2c_data(&i2cctl);
3544         if (ack) {
3545                 DEBUGOUT("I2C ack was not received.\n");
3546                 status = E1000_ERR_I2C;
3547         }
3548
3549         e1000_lower_i2c_clk(hw, &i2cctl);
3550
3551         /* Minimum low period of clock is 4.7 us */
3552         usec_delay(E1000_I2C_T_LOW);
3553
3554         return status;
3555 }
3556
3557 /**
3558  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3559  *  @hw: pointer to hardware structure
3560  *  @data: read data value
3561  *
3562  *  Clocks in one bit via I2C data/clock
3563  **/
3564 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3565 {
3566         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3567
3568         DEBUGFUNC("e1000_clock_in_i2c_bit");
3569
3570         e1000_raise_i2c_clk(hw, &i2cctl);
3571
3572         /* Minimum high period of clock is 4us */
3573         usec_delay(E1000_I2C_T_HIGH);
3574
3575         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3576         *data = e1000_get_i2c_data(&i2cctl);
3577
3578         e1000_lower_i2c_clk(hw, &i2cctl);
3579
3580         /* Minimum low period of clock is 4.7 us */
3581         usec_delay(E1000_I2C_T_LOW);
3582
3583         return E1000_SUCCESS;
3584 }
3585
3586 /**
3587  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3588  *  @hw: pointer to hardware structure
3589  *  @data: data value to write
3590  *
3591  *  Clocks out one bit via I2C data/clock
3592  **/
3593 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3594 {
3595         s32 status;
3596         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3597
3598         DEBUGFUNC("e1000_clock_out_i2c_bit");
3599
3600         status = e1000_set_i2c_data(hw, &i2cctl, data);
3601         if (status == E1000_SUCCESS) {
3602                 e1000_raise_i2c_clk(hw, &i2cctl);
3603
3604                 /* Minimum high period of clock is 4us */
3605                 usec_delay(E1000_I2C_T_HIGH);
3606
3607                 e1000_lower_i2c_clk(hw, &i2cctl);
3608
3609                 /* Minimum low period of clock is 4.7 us.
3610                  * This also takes care of the data hold time.
3611                  */
3612                 usec_delay(E1000_I2C_T_LOW);
3613         } else {
3614                 status = E1000_ERR_I2C;
3615                 DEBUGOUT1("I2C data was not set to %X\n", data);
3616         }
3617
3618         return status;
3619 }
3620 /**
3621  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3622  *  @hw: pointer to hardware structure
3623  *  @i2cctl: Current value of I2CCTL register
3624  *
3625  *  Raises the I2C clock line '0'->'1'
3626  **/
3627 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3628 {
3629         DEBUGFUNC("e1000_raise_i2c_clk");
3630
3631         *i2cctl |= E1000_I2C_CLK_OUT;
3632         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3633         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3634         E1000_WRITE_FLUSH(hw);
3635
3636         /* SCL rise time (1000ns) */
3637         usec_delay(E1000_I2C_T_RISE);
3638 }
3639
3640 /**
3641  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3642  *  @hw: pointer to hardware structure
3643  *  @i2cctl: Current value of I2CCTL register
3644  *
3645  *  Lowers the I2C clock line '1'->'0'
3646  **/
3647 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3648 {
3649
3650         DEBUGFUNC("e1000_lower_i2c_clk");
3651
3652         *i2cctl &= ~E1000_I2C_CLK_OUT;
3653         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3654         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3655         E1000_WRITE_FLUSH(hw);
3656
3657         /* SCL fall time (300ns) */
3658         usec_delay(E1000_I2C_T_FALL);
3659 }
3660
3661 /**
3662  *  e1000_set_i2c_data - Sets the I2C data bit
3663  *  @hw: pointer to hardware structure
3664  *  @i2cctl: Current value of I2CCTL register
3665  *  @data: I2C data value (0 or 1) to set
3666  *
3667  *  Sets the I2C data bit
3668  **/
3669 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3670 {
3671         s32 status = E1000_SUCCESS;
3672
3673         DEBUGFUNC("e1000_set_i2c_data");
3674
3675         if (data)
3676                 *i2cctl |= E1000_I2C_DATA_OUT;
3677         else
3678                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3679
3680         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3681         *i2cctl |= E1000_I2C_CLK_OE_N;
3682         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3683         E1000_WRITE_FLUSH(hw);
3684
3685         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3686         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3687
3688         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3689         if (data != e1000_get_i2c_data(i2cctl)) {
3690                 status = E1000_ERR_I2C;
3691                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3692         }
3693
3694         return status;
3695 }
3696
3697 /**
3698  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3699  *  @hw: pointer to hardware structure
3700  *  @i2cctl: Current value of I2CCTL register
3701  *
3702  *  Returns the I2C data bit value
3703  **/
3704 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3705 {
3706         bool data;
3707
3708         DEBUGFUNC("e1000_get_i2c_data");
3709
3710         if (*i2cctl & E1000_I2C_DATA_IN)
3711                 data = 1;
3712         else
3713                 data = 0;
3714
3715         return data;
3716 }
3717
3718 /**
3719  *  e1000_i2c_bus_clear - Clears the I2C bus
3720  *  @hw: pointer to hardware structure
3721  *
3722  *  Clears the I2C bus by sending nine clock pulses.
3723  *  Used when data line is stuck low.
3724  **/
3725 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3726 {
3727         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3728         u32 i;
3729
3730         DEBUGFUNC("e1000_i2c_bus_clear");
3731
3732         e1000_i2c_start(hw);
3733
3734         e1000_set_i2c_data(hw, &i2cctl, 1);
3735
3736         for (i = 0; i < 9; i++) {
3737                 e1000_raise_i2c_clk(hw, &i2cctl);
3738
3739                 /* Min high period of clock is 4us */
3740                 usec_delay(E1000_I2C_T_HIGH);
3741
3742                 e1000_lower_i2c_clk(hw, &i2cctl);
3743
3744                 /* Min low period of clock is 4.7us*/
3745                 usec_delay(E1000_I2C_T_LOW);
3746         }
3747
3748         e1000_i2c_start(hw);
3749
3750         /* Put the i2c bus back to default state */
3751         e1000_i2c_stop(hw);
3752 }
3753