1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
35 * 82575EB Gigabit Network Connection
36 * 82575EB Gigabit Backplane Connection
37 * 82575GB Gigabit Network Connection
38 * 82576 Gigabit Network Connection
39 * 82576 Quad Port Gigabit Mezzanine Adapter
40 * 82580 Gigabit Network Connection
41 * I350 Gigabit Network Connection
44 #include "e1000_api.h"
45 #include "e1000_i210.h"
47 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
48 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
49 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
51 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
53 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
54 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
55 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
58 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
61 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);
63 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 *data);
65 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 data);
67 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
69 STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
71 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
73 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
74 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw);
76 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
77 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
78 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
79 u32 offset, u16 data);
80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
81 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
82 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
83 u16 *speed, u16 *duplex);
84 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
87 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
88 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
118 STATIC const u16 e1000_82580_rxpbs_table[] = {
119 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
120 #define E1000_82580_RXPBS_TABLE_SIZE \
121 (sizeof(e1000_82580_rxpbs_table) / \
122 sizeof(e1000_82580_rxpbs_table[0]))
126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
127 * @hw: pointer to the HW structure
129 * Called to determine if the I2C pins are being used for I2C or as an
130 * external MDIO interface since the two options are mutually exclusive.
132 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
135 bool ext_mdio = false;
137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
139 switch (hw->mac.type) {
142 reg = E1000_READ_REG(hw, E1000_MDIC);
143 ext_mdio = !!(reg & E1000_MDIC_DEST);
150 reg = E1000_READ_REG(hw, E1000_MDICNFG);
151 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
160 * e1000_init_phy_params_82575 - Init PHY func ptrs.
161 * @hw: pointer to the HW structure
163 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
165 struct e1000_phy_info *phy = &hw->phy;
166 s32 ret_val = E1000_SUCCESS;
169 DEBUGFUNC("e1000_init_phy_params_82575");
171 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
172 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
174 if (hw->phy.media_type != e1000_media_type_copper) {
175 phy->type = e1000_phy_none;
179 phy->ops.power_up = e1000_power_up_phy_copper;
180 phy->ops.power_down = e1000_power_down_phy_copper_82575;
182 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
183 phy->reset_delay_us = 100;
185 phy->ops.acquire = e1000_acquire_phy_82575;
186 phy->ops.check_reset_block = e1000_check_reset_block_generic;
187 phy->ops.commit = e1000_phy_sw_reset_generic;
188 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
189 phy->ops.release = e1000_release_phy_82575;
191 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
193 if (e1000_sgmii_active_82575(hw)) {
194 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
195 ctrl_ext |= E1000_CTRL_I2C_ENA;
197 phy->ops.reset = e1000_phy_hw_reset_generic;
198 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
202 e1000_reset_mdicnfg_82580(hw);
204 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
205 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
206 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
208 switch (hw->mac.type) {
212 phy->ops.read_reg = e1000_read_phy_reg_82580;
213 phy->ops.write_reg = e1000_write_phy_reg_82580;
217 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
218 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
221 phy->ops.read_reg = e1000_read_phy_reg_igp;
222 phy->ops.write_reg = e1000_write_phy_reg_igp;
226 /* Set phy->phy_addr and phy->id. */
227 ret_val = e1000_get_phy_id_82575(hw);
229 /* Verify phy id and set remaining function pointers */
231 case M88E1543_E_PHY_ID:
232 case M88E1512_E_PHY_ID:
233 case I347AT4_E_PHY_ID:
234 case M88E1112_E_PHY_ID:
235 case M88E1340M_E_PHY_ID:
236 case M88E1111_I_PHY_ID:
237 phy->type = e1000_phy_m88;
238 phy->ops.check_polarity = e1000_check_polarity_m88;
239 phy->ops.get_info = e1000_get_phy_info_m88;
240 if (phy->id == I347AT4_E_PHY_ID ||
241 phy->id == M88E1112_E_PHY_ID ||
242 phy->id == M88E1340M_E_PHY_ID)
243 phy->ops.get_cable_length =
244 e1000_get_cable_length_m88_gen2;
245 else if (phy->id == M88E1543_E_PHY_ID ||
246 phy->id == M88E1512_E_PHY_ID)
247 phy->ops.get_cable_length =
248 e1000_get_cable_length_m88_gen2;
250 phy->ops.get_cable_length = e1000_get_cable_length_m88;
251 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
252 /* Check if this PHY is confgured for media swap. */
253 if (phy->id == M88E1112_E_PHY_ID) {
256 ret_val = phy->ops.write_reg(hw,
257 E1000_M88E1112_PAGE_ADDR,
262 ret_val = phy->ops.read_reg(hw,
263 E1000_M88E1112_MAC_CTRL_1,
268 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
269 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
270 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
271 data == E1000_M88E1112_AUTO_COPPER_BASEX)
272 hw->mac.ops.check_for_link =
273 e1000_check_for_link_media_swap;
275 if (phy->id == M88E1512_E_PHY_ID) {
276 ret_val = e1000_initialize_M88E1512_phy(hw);
281 case IGP03E1000_E_PHY_ID:
282 case IGP04E1000_E_PHY_ID:
283 phy->type = e1000_phy_igp_3;
284 phy->ops.check_polarity = e1000_check_polarity_igp;
285 phy->ops.get_info = e1000_get_phy_info_igp;
286 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
287 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
288 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
289 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
291 case I82580_I_PHY_ID:
293 phy->type = e1000_phy_82580;
294 phy->ops.check_polarity = e1000_check_polarity_82577;
295 phy->ops.force_speed_duplex =
296 e1000_phy_force_speed_duplex_82577;
297 phy->ops.get_cable_length = e1000_get_cable_length_82577;
298 phy->ops.get_info = e1000_get_phy_info_82577;
299 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
300 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
303 phy->type = e1000_phy_i210;
304 phy->ops.check_polarity = e1000_check_polarity_m88;
305 phy->ops.get_info = e1000_get_phy_info_m88;
306 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
307 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
308 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
309 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
312 ret_val = -E1000_ERR_PHY;
321 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
322 * @hw: pointer to the HW structure
324 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
326 struct e1000_nvm_info *nvm = &hw->nvm;
327 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
330 DEBUGFUNC("e1000_init_nvm_params_82575");
332 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
333 E1000_EECD_SIZE_EX_SHIFT);
335 * Added to a constant, "size" becomes the left-shift value
336 * for setting word_size.
338 size += NVM_WORD_SIZE_BASE_SHIFT;
340 /* Just in case size is out of range, cap it to the largest
341 * EEPROM size supported
346 nvm->word_size = 1 << size;
347 if (hw->mac.type < e1000_i210) {
348 nvm->opcode_bits = 8;
351 switch (nvm->override) {
352 case e1000_nvm_override_spi_large:
354 nvm->address_bits = 16;
356 case e1000_nvm_override_spi_small:
358 nvm->address_bits = 8;
361 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
362 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
366 if (nvm->word_size == (1 << 15))
367 nvm->page_size = 128;
369 nvm->type = e1000_nvm_eeprom_spi;
371 nvm->type = e1000_nvm_flash_hw;
374 /* Function Pointers */
375 nvm->ops.acquire = e1000_acquire_nvm_82575;
376 nvm->ops.release = e1000_release_nvm_82575;
377 if (nvm->word_size < (1 << 15))
378 nvm->ops.read = e1000_read_nvm_eerd;
380 nvm->ops.read = e1000_read_nvm_spi;
382 nvm->ops.write = e1000_write_nvm_spi;
383 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
384 nvm->ops.update = e1000_update_nvm_checksum_generic;
385 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
387 /* override generic family function pointers for specific descendants */
388 switch (hw->mac.type) {
390 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
391 nvm->ops.update = e1000_update_nvm_checksum_82580;
395 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
396 nvm->ops.update = e1000_update_nvm_checksum_i350;
402 return E1000_SUCCESS;
406 * e1000_init_mac_params_82575 - Init MAC func ptrs.
407 * @hw: pointer to the HW structure
409 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
411 struct e1000_mac_info *mac = &hw->mac;
412 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
414 DEBUGFUNC("e1000_init_mac_params_82575");
416 /* Derives media type */
417 e1000_get_media_type_82575(hw);
418 /* Set mta register count */
419 mac->mta_reg_count = 128;
420 /* Set uta register count */
421 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
422 /* Set rar entry count */
423 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
424 if (mac->type == e1000_82576)
425 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
426 if (mac->type == e1000_82580)
427 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
428 if (mac->type == e1000_i350 || mac->type == e1000_i354)
429 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
431 /* Enable EEE default settings for EEE supported devices */
432 if (mac->type >= e1000_i350)
433 dev_spec->eee_disable = false;
435 /* Allow a single clear of the SW semaphore on I210 and newer */
436 if (mac->type >= e1000_i210)
437 dev_spec->clear_semaphore_once = true;
439 /* Set if part includes ASF firmware */
440 mac->asf_firmware_present = true;
442 mac->has_fwsm = true;
443 /* ARC supported; valid only if manageability features are enabled. */
444 mac->arc_subsystem_valid =
445 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
447 /* Function pointers */
449 /* bus type/speed/width */
450 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
452 if (mac->type >= e1000_82580)
453 mac->ops.reset_hw = e1000_reset_hw_82580;
455 mac->ops.reset_hw = e1000_reset_hw_82575;
456 /* hw initialization */
457 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
458 mac->ops.init_hw = e1000_init_hw_i210;
460 mac->ops.init_hw = e1000_init_hw_82575;
462 mac->ops.setup_link = e1000_setup_link_generic;
463 /* physical interface link setup */
464 mac->ops.setup_physical_interface =
465 (hw->phy.media_type == e1000_media_type_copper)
466 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
467 /* physical interface shutdown */
468 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
469 /* physical interface power up */
470 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
472 mac->ops.check_for_link = e1000_check_for_link_82575;
473 /* read mac address */
474 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
475 /* configure collision distance */
476 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
477 /* multicast address update */
478 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
479 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
481 mac->ops.write_vfta = e1000_write_vfta_i350;
483 mac->ops.clear_vfta = e1000_clear_vfta_i350;
486 mac->ops.write_vfta = e1000_write_vfta_generic;
488 mac->ops.clear_vfta = e1000_clear_vfta_generic;
490 if (hw->mac.type >= e1000_82580)
491 mac->ops.validate_mdi_setting =
492 e1000_validate_mdi_setting_crossover_generic;
494 mac->ops.id_led_init = e1000_id_led_init_generic;
496 mac->ops.blink_led = e1000_blink_led_generic;
498 mac->ops.setup_led = e1000_setup_led_generic;
500 mac->ops.cleanup_led = e1000_cleanup_led_generic;
501 /* turn on/off LED */
502 mac->ops.led_on = e1000_led_on_generic;
503 mac->ops.led_off = e1000_led_off_generic;
504 /* clear hardware counters */
505 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
507 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
508 /* acquire SW_FW sync */
509 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
510 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
511 if (mac->type >= e1000_i210) {
512 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
513 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
516 /* set lan id for port to determine which phy lock to use */
517 hw->mac.ops.set_lan_id(hw);
519 return E1000_SUCCESS;
523 * e1000_init_function_pointers_82575 - Init func ptrs.
524 * @hw: pointer to the HW structure
526 * Called to initialize all function pointers and parameters.
528 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
530 DEBUGFUNC("e1000_init_function_pointers_82575");
532 hw->mac.ops.init_params = e1000_init_mac_params_82575;
533 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
534 hw->phy.ops.init_params = e1000_init_phy_params_82575;
535 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
539 * e1000_acquire_phy_82575 - Acquire rights to access PHY
540 * @hw: pointer to the HW structure
542 * Acquire access rights to the correct PHY.
544 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
546 u16 mask = E1000_SWFW_PHY0_SM;
548 DEBUGFUNC("e1000_acquire_phy_82575");
550 if (hw->bus.func == E1000_FUNC_1)
551 mask = E1000_SWFW_PHY1_SM;
552 else if (hw->bus.func == E1000_FUNC_2)
553 mask = E1000_SWFW_PHY2_SM;
554 else if (hw->bus.func == E1000_FUNC_3)
555 mask = E1000_SWFW_PHY3_SM;
557 return hw->mac.ops.acquire_swfw_sync(hw, mask);
561 * e1000_release_phy_82575 - Release rights to access PHY
562 * @hw: pointer to the HW structure
564 * A wrapper to release access rights to the correct PHY.
566 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
568 u16 mask = E1000_SWFW_PHY0_SM;
570 DEBUGFUNC("e1000_release_phy_82575");
572 if (hw->bus.func == E1000_FUNC_1)
573 mask = E1000_SWFW_PHY1_SM;
574 else if (hw->bus.func == E1000_FUNC_2)
575 mask = E1000_SWFW_PHY2_SM;
576 else if (hw->bus.func == E1000_FUNC_3)
577 mask = E1000_SWFW_PHY3_SM;
579 hw->mac.ops.release_swfw_sync(hw, mask);
583 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
584 * @hw: pointer to the HW structure
585 * @offset: register offset to be read
586 * @data: pointer to the read data
588 * Reads the PHY register at offset using the serial gigabit media independent
589 * interface and stores the retrieved information in data.
591 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
594 s32 ret_val = -E1000_ERR_PARAM;
596 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
598 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
599 DEBUGOUT1("PHY Address %u is out of range\n", offset);
603 ret_val = hw->phy.ops.acquire(hw);
607 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
609 hw->phy.ops.release(hw);
616 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
617 * @hw: pointer to the HW structure
618 * @offset: register offset to write to
619 * @data: data to write at register offset
621 * Writes the data to PHY register at the offset using the serial gigabit
622 * media independent interface.
624 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
627 s32 ret_val = -E1000_ERR_PARAM;
629 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
631 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
632 DEBUGOUT1("PHY Address %d is out of range\n", offset);
636 ret_val = hw->phy.ops.acquire(hw);
640 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
642 hw->phy.ops.release(hw);
649 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
650 * @hw: pointer to the HW structure
652 * Retrieves the PHY address and ID for both PHY's which do and do not use
655 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
657 struct e1000_phy_info *phy = &hw->phy;
658 s32 ret_val = E1000_SUCCESS;
663 DEBUGFUNC("e1000_get_phy_id_82575");
665 /* some i354 devices need an extra read for phy id */
666 if (hw->mac.type == e1000_i354)
667 e1000_get_phy_id(hw);
670 * For SGMII PHYs, we try the list of possible addresses until
671 * we find one that works. For non-SGMII PHYs
672 * (e.g. integrated copper PHYs), an address of 1 should
673 * work. The result of this function should mean phy->phy_addr
674 * and phy->id are set correctly.
676 if (!e1000_sgmii_active_82575(hw)) {
678 ret_val = e1000_get_phy_id(hw);
682 if (e1000_sgmii_uses_mdio_82575(hw)) {
683 switch (hw->mac.type) {
686 mdic = E1000_READ_REG(hw, E1000_MDIC);
687 mdic &= E1000_MDIC_PHY_MASK;
688 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
695 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
696 mdic &= E1000_MDICNFG_PHY_MASK;
697 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
700 ret_val = -E1000_ERR_PHY;
704 ret_val = e1000_get_phy_id(hw);
708 /* Power on sgmii phy if it is disabled */
709 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
710 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
711 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
712 E1000_WRITE_FLUSH(hw);
716 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
717 * Therefore, we need to test 1-7
719 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
720 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
721 if (ret_val == E1000_SUCCESS) {
722 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
725 * At the time of this writing, The M88 part is
726 * the only supported SGMII PHY product.
728 if (phy_id == M88_VENDOR)
731 DEBUGOUT1("PHY address %u was unreadable\n",
736 /* A valid PHY type couldn't be found. */
737 if (phy->addr == 8) {
739 ret_val = -E1000_ERR_PHY;
741 ret_val = e1000_get_phy_id(hw);
744 /* restore previous sfp cage power state */
745 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
752 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
753 * @hw: pointer to the HW structure
755 * Resets the PHY using the serial gigabit media independent interface.
757 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
759 s32 ret_val = E1000_SUCCESS;
760 struct e1000_phy_info *phy = &hw->phy;
762 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
765 * This isn't a true "hard" reset, but is the only reset
766 * available to us at this time.
769 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
771 if (!(hw->phy.ops.write_reg))
775 * SFP documentation requires the following to configure the SPF module
776 * to work on SGMII. No further documentation is given.
778 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
782 ret_val = hw->phy.ops.commit(hw);
786 if (phy->id == M88E1512_E_PHY_ID)
787 ret_val = e1000_initialize_M88E1512_phy(hw);
793 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
794 * @hw: pointer to the HW structure
795 * @active: true to enable LPLU, false to disable
797 * Sets the LPLU D0 state according to the active flag. When
798 * activating LPLU this function also disables smart speed
799 * and vice versa. LPLU will not be activated unless the
800 * device autonegotiation advertisement meets standards of
801 * either 10 or 10/100 or 10/100/1000 at all duplexes.
802 * This is a function pointer entry point only called by
803 * PHY setup routines.
805 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
807 struct e1000_phy_info *phy = &hw->phy;
808 s32 ret_val = E1000_SUCCESS;
811 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
813 if (!(hw->phy.ops.read_reg))
816 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
821 data |= IGP02E1000_PM_D0_LPLU;
822 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
827 /* When LPLU is enabled, we should disable SmartSpeed */
828 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
830 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
831 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
836 data &= ~IGP02E1000_PM_D0_LPLU;
837 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
840 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
841 * during Dx states where the power conservation is most
842 * important. During driver activity we should enable
843 * SmartSpeed, so performance is maintained.
845 if (phy->smart_speed == e1000_smart_speed_on) {
846 ret_val = phy->ops.read_reg(hw,
847 IGP01E1000_PHY_PORT_CONFIG,
852 data |= IGP01E1000_PSCFR_SMART_SPEED;
853 ret_val = phy->ops.write_reg(hw,
854 IGP01E1000_PHY_PORT_CONFIG,
858 } else if (phy->smart_speed == e1000_smart_speed_off) {
859 ret_val = phy->ops.read_reg(hw,
860 IGP01E1000_PHY_PORT_CONFIG,
865 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
866 ret_val = phy->ops.write_reg(hw,
867 IGP01E1000_PHY_PORT_CONFIG,
879 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
880 * @hw: pointer to the HW structure
881 * @active: true to enable LPLU, false to disable
883 * Sets the LPLU D0 state according to the active flag. When
884 * activating LPLU this function also disables smart speed
885 * and vice versa. LPLU will not be activated unless the
886 * device autonegotiation advertisement meets standards of
887 * either 10 or 10/100 or 10/100/1000 at all duplexes.
888 * This is a function pointer entry point only called by
889 * PHY setup routines.
891 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
893 struct e1000_phy_info *phy = &hw->phy;
896 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
898 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
901 data |= E1000_82580_PM_D0_LPLU;
903 /* When LPLU is enabled, we should disable SmartSpeed */
904 data &= ~E1000_82580_PM_SPD;
906 data &= ~E1000_82580_PM_D0_LPLU;
909 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
910 * during Dx states where the power conservation is most
911 * important. During driver activity we should enable
912 * SmartSpeed, so performance is maintained.
914 if (phy->smart_speed == e1000_smart_speed_on)
915 data |= E1000_82580_PM_SPD;
916 else if (phy->smart_speed == e1000_smart_speed_off)
917 data &= ~E1000_82580_PM_SPD;
920 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
921 return E1000_SUCCESS;
925 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
926 * @hw: pointer to the HW structure
927 * @active: boolean used to enable/disable lplu
929 * Success returns 0, Failure returns 1
931 * The low power link up (lplu) state is set to the power management level D3
932 * and SmartSpeed is disabled when active is true, else clear lplu for D3
933 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
934 * is used during Dx states where the power conservation is most important.
935 * During driver activity, SmartSpeed should be enabled so performance is
938 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
940 struct e1000_phy_info *phy = &hw->phy;
943 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
945 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
948 data &= ~E1000_82580_PM_D3_LPLU;
950 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
951 * during Dx states where the power conservation is most
952 * important. During driver activity we should enable
953 * SmartSpeed, so performance is maintained.
955 if (phy->smart_speed == e1000_smart_speed_on)
956 data |= E1000_82580_PM_SPD;
957 else if (phy->smart_speed == e1000_smart_speed_off)
958 data &= ~E1000_82580_PM_SPD;
959 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
960 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
961 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
962 data |= E1000_82580_PM_D3_LPLU;
963 /* When LPLU is enabled, we should disable SmartSpeed */
964 data &= ~E1000_82580_PM_SPD;
967 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
968 return E1000_SUCCESS;
972 * e1000_acquire_nvm_82575 - Request for access to EEPROM
973 * @hw: pointer to the HW structure
975 * Acquire the necessary semaphores for exclusive access to the EEPROM.
976 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
977 * Return successful if access grant bit set, else clear the request for
978 * EEPROM access and return -E1000_ERR_NVM (-1).
980 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
982 s32 ret_val = E1000_SUCCESS;
984 DEBUGFUNC("e1000_acquire_nvm_82575");
986 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
991 * Check if there is some access
992 * error this access may hook on
994 if (hw->mac.type == e1000_i350) {
995 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
996 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
997 E1000_EECD_TIMEOUT)) {
998 /* Clear all access error flags */
999 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1000 E1000_EECD_ERROR_CLR);
1001 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1005 if (hw->mac.type == e1000_82580) {
1006 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1007 if (eecd & E1000_EECD_BLOCKED) {
1008 /* Clear access error flag */
1009 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1010 E1000_EECD_BLOCKED);
1011 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1015 ret_val = e1000_acquire_nvm_generic(hw);
1017 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1024 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
1025 * @hw: pointer to the HW structure
1027 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1028 * then release the semaphores acquired.
1030 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1032 DEBUGFUNC("e1000_release_nvm_82575");
1034 e1000_release_nvm_generic(hw);
1036 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1040 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1041 * @hw: pointer to the HW structure
1042 * @mask: specifies which semaphore to acquire
1044 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1045 * will also specify which port we're acquiring the lock for.
1047 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1051 u32 fwmask = mask << 16;
1052 s32 ret_val = E1000_SUCCESS;
1053 s32 i = 0, timeout = 200;
1055 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1057 while (i < timeout) {
1058 if (e1000_get_hw_semaphore_generic(hw)) {
1059 ret_val = -E1000_ERR_SWFW_SYNC;
1063 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1064 if (!(swfw_sync & (fwmask | swmask)))
1068 * Firmware currently using resource (fwmask)
1069 * or other software thread using resource (swmask)
1071 e1000_put_hw_semaphore_generic(hw);
1077 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1078 ret_val = -E1000_ERR_SWFW_SYNC;
1082 swfw_sync |= swmask;
1083 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1085 e1000_put_hw_semaphore_generic(hw);
1092 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1093 * @hw: pointer to the HW structure
1094 * @mask: specifies which semaphore to acquire
1096 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1097 * will also specify which port we're releasing the lock for.
1099 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1103 DEBUGFUNC("e1000_release_swfw_sync_82575");
1105 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1108 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1110 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1112 e1000_put_hw_semaphore_generic(hw);
1116 * e1000_get_cfg_done_82575 - Read config done bit
1117 * @hw: pointer to the HW structure
1119 * Read the management control register for the config done bit for
1120 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1121 * to read the config done bit, so an error is *ONLY* logged and returns
1122 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1123 * would not be able to be reset or change link.
1125 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1127 s32 timeout = PHY_CFG_TIMEOUT;
1128 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1130 DEBUGFUNC("e1000_get_cfg_done_82575");
1132 if (hw->bus.func == E1000_FUNC_1)
1133 mask = E1000_NVM_CFG_DONE_PORT_1;
1134 else if (hw->bus.func == E1000_FUNC_2)
1135 mask = E1000_NVM_CFG_DONE_PORT_2;
1136 else if (hw->bus.func == E1000_FUNC_3)
1137 mask = E1000_NVM_CFG_DONE_PORT_3;
1139 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1145 DEBUGOUT("MNG configuration cycle has not completed.\n");
1147 /* If EEPROM is not marked present, init the PHY manually */
1148 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1149 (hw->phy.type == e1000_phy_igp_3))
1150 e1000_phy_init_script_igp3(hw);
1152 return E1000_SUCCESS;
1156 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1157 * @hw: pointer to the HW structure
1158 * @speed: stores the current speed
1159 * @duplex: stores the current duplex
1161 * This is a wrapper function, if using the serial gigabit media independent
1162 * interface, use PCS to retrieve the link speed and duplex information.
1163 * Otherwise, use the generic function to get the link speed and duplex info.
1165 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1170 DEBUGFUNC("e1000_get_link_up_info_82575");
1172 if (hw->phy.media_type != e1000_media_type_copper)
1173 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1176 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1183 * e1000_check_for_link_82575 - Check for link
1184 * @hw: pointer to the HW structure
1186 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1187 * use the generic interface for determining link.
1189 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1194 DEBUGFUNC("e1000_check_for_link_82575");
1196 if (hw->phy.media_type != e1000_media_type_copper) {
1197 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1200 * Use this flag to determine if link needs to be checked or
1201 * not. If we have link clear the flag so that we do not
1202 * continue to check for link.
1204 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1207 * Configure Flow Control now that Auto-Neg has completed.
1208 * First, we need to restore the desired flow control
1209 * settings because we may have had to re-autoneg with a
1210 * different link partner.
1212 ret_val = e1000_config_fc_after_link_up_generic(hw);
1214 DEBUGOUT("Error configuring flow control\n");
1216 ret_val = e1000_check_for_copper_link_generic(hw);
1223 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1224 * @hw: pointer to the HW structure
1226 * Poll the M88E1112 interfaces to see which interface achieved link.
1228 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1230 struct e1000_phy_info *phy = &hw->phy;
1235 DEBUGFUNC("e1000_check_for_link_media_swap");
1237 /* Check for copper. */
1238 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1242 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1246 if (data & E1000_M88E1112_STATUS_LINK)
1247 port = E1000_MEDIA_PORT_COPPER;
1249 /* Check for other. */
1250 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1254 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1258 if (data & E1000_M88E1112_STATUS_LINK)
1259 port = E1000_MEDIA_PORT_OTHER;
1261 /* Determine if a swap needs to happen. */
1262 if (port && (hw->dev_spec._82575.media_port != port)) {
1263 hw->dev_spec._82575.media_port = port;
1264 hw->dev_spec._82575.media_changed = true;
1267 if (port == E1000_MEDIA_PORT_COPPER) {
1268 /* reset page to 0 */
1269 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1272 e1000_check_for_link_82575(hw);
1274 e1000_check_for_link_82575(hw);
1275 /* reset page to 0 */
1276 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1281 return E1000_SUCCESS;
1285 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1286 * @hw: pointer to the HW structure
1288 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1292 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1294 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1295 !e1000_sgmii_active_82575(hw))
1298 /* Enable PCS to turn on link */
1299 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1300 reg |= E1000_PCS_CFG_PCS_EN;
1301 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1303 /* Power up the laser */
1304 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1305 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1306 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1308 /* flush the write to verify completion */
1309 E1000_WRITE_FLUSH(hw);
1314 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1315 * @hw: pointer to the HW structure
1316 * @speed: stores the current speed
1317 * @duplex: stores the current duplex
1319 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1320 * duplex, then store the values in the pointers provided.
1322 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1323 u16 *speed, u16 *duplex)
1325 struct e1000_mac_info *mac = &hw->mac;
1329 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1332 * Read the PCS Status register for link state. For non-copper mode,
1333 * the status register is not accurate. The PCS status register is
1336 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1339 * The link up bit determines when link is up on autoneg.
1341 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1342 mac->serdes_has_link = true;
1344 /* Detect and store PCS speed */
1345 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1346 *speed = SPEED_1000;
1347 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1352 /* Detect and store PCS duplex */
1353 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1354 *duplex = FULL_DUPLEX;
1356 *duplex = HALF_DUPLEX;
1358 /* Check if it is an I354 2.5Gb backplane connection. */
1359 if (mac->type == e1000_i354) {
1360 status = E1000_READ_REG(hw, E1000_STATUS);
1361 if ((status & E1000_STATUS_2P5_SKU) &&
1362 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1363 *speed = SPEED_2500;
1364 *duplex = FULL_DUPLEX;
1365 DEBUGOUT("2500 Mbs, ");
1366 DEBUGOUT("Full Duplex\n");
1371 mac->serdes_has_link = false;
1376 return E1000_SUCCESS;
1380 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1381 * @hw: pointer to the HW structure
1383 * In the case of serdes shut down sfp and PCS on driver unload
1384 * when management pass thru is not enabled.
1386 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1390 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1392 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1393 !e1000_sgmii_active_82575(hw))
1396 if (!e1000_enable_mng_pass_thru(hw)) {
1397 /* Disable PCS to turn off link */
1398 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1399 reg &= ~E1000_PCS_CFG_PCS_EN;
1400 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1402 /* shutdown the laser */
1403 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1404 reg |= E1000_CTRL_EXT_SDP3_DATA;
1405 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1407 /* flush the write to verify completion */
1408 E1000_WRITE_FLUSH(hw);
1416 * e1000_reset_hw_82575 - Reset hardware
1417 * @hw: pointer to the HW structure
1419 * This resets the hardware into a known state.
1421 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1426 DEBUGFUNC("e1000_reset_hw_82575");
1429 * Prevent the PCI-E bus from sticking if there is no TLP connection
1430 * on the last TLP read/write transaction when MAC is reset.
1432 ret_val = e1000_disable_pcie_master_generic(hw);
1434 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1436 /* set the completion timeout for interface */
1437 ret_val = e1000_set_pcie_completion_timeout(hw);
1439 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1441 DEBUGOUT("Masking off all interrupts\n");
1442 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1444 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1445 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1446 E1000_WRITE_FLUSH(hw);
1450 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1452 DEBUGOUT("Issuing a global reset to MAC\n");
1453 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1455 ret_val = e1000_get_auto_rd_done_generic(hw);
1458 * When auto config read does not complete, do not
1459 * return with an error. This can happen in situations
1460 * where there is no eeprom and prevents getting link.
1462 DEBUGOUT("Auto Read Done did not complete\n");
1465 /* If EEPROM is not present, run manual init scripts */
1466 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1467 e1000_reset_init_script_82575(hw);
1469 /* Clear any pending interrupt events. */
1470 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1471 E1000_READ_REG(hw, E1000_ICR);
1473 /* Install any alternate MAC address into RAR0 */
1474 ret_val = e1000_check_alt_mac_addr_generic(hw);
1480 * e1000_init_hw_82575 - Initialize hardware
1481 * @hw: pointer to the HW structure
1483 * This inits the hardware readying it for operation.
1485 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1487 struct e1000_mac_info *mac = &hw->mac;
1489 u16 i, rar_count = mac->rar_entry_count;
1491 DEBUGFUNC("e1000_init_hw_82575");
1493 /* Initialize identification LED */
1494 ret_val = mac->ops.id_led_init(hw);
1496 DEBUGOUT("Error initializing identification LED\n");
1497 /* This is not fatal and we should not stop init due to this */
1500 /* Disabling VLAN filtering */
1501 DEBUGOUT("Initializing the IEEE VLAN\n");
1502 mac->ops.clear_vfta(hw);
1504 /* Setup the receive address */
1505 e1000_init_rx_addrs_generic(hw, rar_count);
1507 /* Zero out the Multicast HASH table */
1508 DEBUGOUT("Zeroing the MTA\n");
1509 for (i = 0; i < mac->mta_reg_count; i++)
1510 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1512 /* Zero out the Unicast HASH table */
1513 DEBUGOUT("Zeroing the UTA\n");
1514 for (i = 0; i < mac->uta_reg_count; i++)
1515 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1517 /* Setup link and flow control */
1518 ret_val = mac->ops.setup_link(hw);
1520 /* Set the default MTU size */
1521 hw->dev_spec._82575.mtu = 1500;
1524 * Clear all of the statistics registers (clear on read). It is
1525 * important that we do this after we have tried to establish link
1526 * because the symbol error count will increment wildly if there
1529 e1000_clear_hw_cntrs_82575(hw);
1535 * e1000_setup_copper_link_82575 - Configure copper link settings
1536 * @hw: pointer to the HW structure
1538 * Configures the link for auto-neg or forced speed and duplex. Then we check
1539 * for link, once link is established calls to configure collision distance
1540 * and flow control are called.
1542 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1548 DEBUGFUNC("e1000_setup_copper_link_82575");
1550 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1551 ctrl |= E1000_CTRL_SLU;
1552 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1553 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1555 /* Clear Go Link Disconnect bit on supported devices */
1556 switch (hw->mac.type) {
1561 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1562 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1563 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1569 ret_val = e1000_setup_serdes_link_82575(hw);
1573 if (e1000_sgmii_active_82575(hw)) {
1574 /* allow time for SFP cage time to power up phy */
1577 ret_val = hw->phy.ops.reset(hw);
1579 DEBUGOUT("Error resetting the PHY.\n");
1583 switch (hw->phy.type) {
1584 case e1000_phy_i210:
1586 switch (hw->phy.id) {
1587 case I347AT4_E_PHY_ID:
1588 case M88E1112_E_PHY_ID:
1589 case M88E1340M_E_PHY_ID:
1590 case M88E1543_E_PHY_ID:
1591 case M88E1512_E_PHY_ID:
1593 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1596 ret_val = e1000_copper_link_setup_m88(hw);
1600 case e1000_phy_igp_3:
1601 ret_val = e1000_copper_link_setup_igp(hw);
1603 case e1000_phy_82580:
1604 ret_val = e1000_copper_link_setup_82577(hw);
1607 ret_val = -E1000_ERR_PHY;
1614 ret_val = e1000_setup_copper_link_generic(hw);
1620 * e1000_setup_serdes_link_82575 - Setup link for serdes
1621 * @hw: pointer to the HW structure
1623 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1624 * used on copper connections where the serialized gigabit media independent
1625 * interface (sgmii), or serdes fiber is being used. Configures the link
1626 * for auto-negotiation or forces speed/duplex.
1628 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1630 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1632 s32 ret_val = E1000_SUCCESS;
1635 DEBUGFUNC("e1000_setup_serdes_link_82575");
1637 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1638 !e1000_sgmii_active_82575(hw))
1642 * On the 82575, SerDes loopback mode persists until it is
1643 * explicitly turned off or a power cycle is performed. A read to
1644 * the register does not indicate its status. Therefore, we ensure
1645 * loopback mode is disabled during initialization.
1647 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1649 /* power on the sfp cage if present */
1650 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1651 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1652 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1654 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1655 ctrl_reg |= E1000_CTRL_SLU;
1657 /* set both sw defined pins on 82575/82576*/
1658 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1659 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1661 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1663 /* default pcs_autoneg to the same setting as mac autoneg */
1664 pcs_autoneg = hw->mac.autoneg;
1666 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1667 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1668 /* sgmii mode lets the phy handle forcing speed/duplex */
1670 /* autoneg time out should be disabled for SGMII mode */
1671 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1673 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1674 /* disable PCS autoneg and support parallel detect only */
1675 pcs_autoneg = false;
1676 /* fall through to default case */
1678 if (hw->mac.type == e1000_82575 ||
1679 hw->mac.type == e1000_82576) {
1680 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1682 DEBUGOUT("NVM Read Error\n");
1686 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1687 pcs_autoneg = false;
1691 * non-SGMII modes only supports a speed of 1000/Full for the
1692 * link so it is best to just force the MAC and let the pcs
1693 * link either autoneg or be forced to 1000/Full
1695 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1696 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1698 /* set speed of 1000/Full if speed/duplex is forced */
1699 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1703 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1706 * New SerDes mode allows for forcing speed or autonegotiating speed
1707 * at 1gb. Autoneg should be default set by most drivers. This is the
1708 * mode that will be compatible with older link partners and switches.
1709 * However, both are supported by the hardware and some drivers/tools.
1711 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1712 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1715 /* Set PCS register for autoneg */
1716 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1717 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1719 /* Disable force flow control for autoneg */
1720 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1722 /* Configure flow control advertisement for autoneg */
1723 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1724 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1726 switch (hw->fc.requested_mode) {
1728 case e1000_fc_rx_pause:
1729 anadv_reg |= E1000_TXCW_ASM_DIR;
1730 anadv_reg |= E1000_TXCW_PAUSE;
1732 case e1000_fc_tx_pause:
1733 anadv_reg |= E1000_TXCW_ASM_DIR;
1739 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1741 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1743 /* Set PCS register for forced link */
1744 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1746 /* Force flow control for forced link */
1747 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1749 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1752 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1754 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1755 e1000_force_mac_fc_generic(hw);
1761 * e1000_get_media_type_82575 - derives current media type.
1762 * @hw: pointer to the HW structure
1764 * The media type is chosen reflecting few settings.
1765 * The following are taken into account:
1766 * - link mode set in the current port Init Control Word #3
1767 * - current link mode settings in CSR register
1768 * - MDIO vs. I2C PHY control interface chosen
1769 * - SFP module media type
1771 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1773 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1774 s32 ret_val = E1000_SUCCESS;
1778 /* Set internal phy as default */
1779 dev_spec->sgmii_active = false;
1780 dev_spec->module_plugged = false;
1782 /* Get CSR setting */
1783 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1785 /* extract link mode setting */
1786 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1788 switch (link_mode) {
1789 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1790 hw->phy.media_type = e1000_media_type_internal_serdes;
1792 case E1000_CTRL_EXT_LINK_MODE_GMII:
1793 hw->phy.media_type = e1000_media_type_copper;
1795 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1796 /* Get phy control interface type set (MDIO vs. I2C)*/
1797 if (e1000_sgmii_uses_mdio_82575(hw)) {
1798 hw->phy.media_type = e1000_media_type_copper;
1799 dev_spec->sgmii_active = true;
1802 /* fall through for I2C based SGMII */
1803 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1804 /* read media type from SFP EEPROM */
1805 ret_val = e1000_set_sfp_media_type_82575(hw);
1806 if ((ret_val != E1000_SUCCESS) ||
1807 (hw->phy.media_type == e1000_media_type_unknown)) {
1809 * If media type was not identified then return media
1810 * type defined by the CTRL_EXT settings.
1812 hw->phy.media_type = e1000_media_type_internal_serdes;
1814 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1815 hw->phy.media_type = e1000_media_type_copper;
1816 dev_spec->sgmii_active = true;
1822 /* do not change link mode for 100BaseFX */
1823 if (dev_spec->eth_flags.e100_base_fx)
1826 /* change current link mode setting */
1827 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1829 if (hw->phy.media_type == e1000_media_type_copper)
1830 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1832 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1834 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1843 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1844 * @hw: pointer to the HW structure
1846 * The media type is chosen based on SFP module.
1847 * compatibility flags retrieved from SFP ID EEPROM.
1849 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1851 s32 ret_val = E1000_ERR_CONFIG;
1853 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1854 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1855 u8 tranceiver_type = 0;
1858 /* Turn I2C interface ON and power on sfp cage */
1859 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1860 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1861 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1863 E1000_WRITE_FLUSH(hw);
1865 /* Read SFP module data */
1867 ret_val = e1000_read_sfp_data_byte(hw,
1868 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1870 if (ret_val == E1000_SUCCESS)
1875 if (ret_val != E1000_SUCCESS)
1878 ret_val = e1000_read_sfp_data_byte(hw,
1879 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1881 if (ret_val != E1000_SUCCESS)
1884 /* Check if there is some SFP module plugged and powered */
1885 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1886 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1887 dev_spec->module_plugged = true;
1888 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1889 hw->phy.media_type = e1000_media_type_internal_serdes;
1890 } else if (eth_flags->e100_base_fx) {
1891 dev_spec->sgmii_active = true;
1892 hw->phy.media_type = e1000_media_type_internal_serdes;
1893 } else if (eth_flags->e1000_base_t) {
1894 dev_spec->sgmii_active = true;
1895 hw->phy.media_type = e1000_media_type_copper;
1897 hw->phy.media_type = e1000_media_type_unknown;
1898 DEBUGOUT("PHY module has not been recognized\n");
1902 hw->phy.media_type = e1000_media_type_unknown;
1904 ret_val = E1000_SUCCESS;
1906 /* Restore I2C interface setting */
1907 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1912 * e1000_valid_led_default_82575 - Verify a valid default LED config
1913 * @hw: pointer to the HW structure
1914 * @data: pointer to the NVM (EEPROM)
1916 * Read the EEPROM for the current default LED configuration. If the
1917 * LED configuration is not valid, set to a valid LED configuration.
1919 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1923 DEBUGFUNC("e1000_valid_led_default_82575");
1925 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1927 DEBUGOUT("NVM Read Error\n");
1931 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1932 switch (hw->phy.media_type) {
1933 case e1000_media_type_internal_serdes:
1934 *data = ID_LED_DEFAULT_82575_SERDES;
1936 case e1000_media_type_copper:
1938 *data = ID_LED_DEFAULT;
1947 * e1000_sgmii_active_82575 - Return sgmii state
1948 * @hw: pointer to the HW structure
1950 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1951 * which can be enabled for use in the embedded applications. Simply
1952 * return the current state of the sgmii interface.
1954 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1956 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1957 return dev_spec->sgmii_active;
1961 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1962 * @hw: pointer to the HW structure
1964 * Inits recommended HW defaults after a reset when there is no EEPROM
1965 * detected. This is only for the 82575.
1967 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1969 DEBUGFUNC("e1000_reset_init_script_82575");
1971 if (hw->mac.type == e1000_82575) {
1972 DEBUGOUT("Running reset init script for 82575\n");
1973 /* SerDes configuration via SERDESCTRL */
1974 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1975 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1976 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1977 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1979 /* CCM configuration via CCMCTL register */
1980 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1981 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1983 /* PCIe lanes configuration */
1984 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1985 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1986 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1987 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1989 /* PCIe PLL Configuration */
1990 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1991 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1992 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1995 return E1000_SUCCESS;
1999 * e1000_read_mac_addr_82575 - Read device MAC address
2000 * @hw: pointer to the HW structure
2002 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
2006 DEBUGFUNC("e1000_read_mac_addr_82575");
2009 * If there's an alternate MAC address place it in RAR0
2010 * so that it will override the Si installed default perm
2013 ret_val = e1000_check_alt_mac_addr_generic(hw);
2017 ret_val = e1000_read_mac_addr_generic(hw);
2024 * e1000_config_collision_dist_82575 - Configure collision distance
2025 * @hw: pointer to the HW structure
2027 * Configures the collision distance to the default value and is used
2028 * during link setup.
2030 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2034 DEBUGFUNC("e1000_config_collision_dist_82575");
2036 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2038 tctl_ext &= ~E1000_TCTL_EXT_COLD;
2039 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2041 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2042 E1000_WRITE_FLUSH(hw);
2046 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2047 * @hw: pointer to the HW structure
2049 * In the case of a PHY power down to save power, or to turn off link during a
2050 * driver unload, or wake on lan is not enabled, remove the link.
2052 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2054 struct e1000_phy_info *phy = &hw->phy;
2056 if (!(phy->ops.check_reset_block))
2059 /* If the management interface is not enabled, then power down */
2060 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2061 e1000_power_down_phy_copper(hw);
2067 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2068 * @hw: pointer to the HW structure
2070 * Clears the hardware counters by reading the counter registers.
2072 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2074 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2076 e1000_clear_hw_cntrs_base_generic(hw);
2078 E1000_READ_REG(hw, E1000_PRC64);
2079 E1000_READ_REG(hw, E1000_PRC127);
2080 E1000_READ_REG(hw, E1000_PRC255);
2081 E1000_READ_REG(hw, E1000_PRC511);
2082 E1000_READ_REG(hw, E1000_PRC1023);
2083 E1000_READ_REG(hw, E1000_PRC1522);
2084 E1000_READ_REG(hw, E1000_PTC64);
2085 E1000_READ_REG(hw, E1000_PTC127);
2086 E1000_READ_REG(hw, E1000_PTC255);
2087 E1000_READ_REG(hw, E1000_PTC511);
2088 E1000_READ_REG(hw, E1000_PTC1023);
2089 E1000_READ_REG(hw, E1000_PTC1522);
2091 E1000_READ_REG(hw, E1000_ALGNERRC);
2092 E1000_READ_REG(hw, E1000_RXERRC);
2093 E1000_READ_REG(hw, E1000_TNCRS);
2094 E1000_READ_REG(hw, E1000_CEXTERR);
2095 E1000_READ_REG(hw, E1000_TSCTC);
2096 E1000_READ_REG(hw, E1000_TSCTFC);
2098 E1000_READ_REG(hw, E1000_MGTPRC);
2099 E1000_READ_REG(hw, E1000_MGTPDC);
2100 E1000_READ_REG(hw, E1000_MGTPTC);
2102 E1000_READ_REG(hw, E1000_IAC);
2103 E1000_READ_REG(hw, E1000_ICRXOC);
2105 E1000_READ_REG(hw, E1000_ICRXPTC);
2106 E1000_READ_REG(hw, E1000_ICRXATC);
2107 E1000_READ_REG(hw, E1000_ICTXPTC);
2108 E1000_READ_REG(hw, E1000_ICTXATC);
2109 E1000_READ_REG(hw, E1000_ICTXQEC);
2110 E1000_READ_REG(hw, E1000_ICTXQMTC);
2111 E1000_READ_REG(hw, E1000_ICRXDMTC);
2113 E1000_READ_REG(hw, E1000_CBTMPC);
2114 E1000_READ_REG(hw, E1000_HTDPMC);
2115 E1000_READ_REG(hw, E1000_CBRMPC);
2116 E1000_READ_REG(hw, E1000_RPTHC);
2117 E1000_READ_REG(hw, E1000_HGPTC);
2118 E1000_READ_REG(hw, E1000_HTCBDPC);
2119 E1000_READ_REG(hw, E1000_HGORCL);
2120 E1000_READ_REG(hw, E1000_HGORCH);
2121 E1000_READ_REG(hw, E1000_HGOTCL);
2122 E1000_READ_REG(hw, E1000_HGOTCH);
2123 E1000_READ_REG(hw, E1000_LENERRS);
2125 /* This register should not be read in copper configurations */
2126 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2127 e1000_sgmii_active_82575(hw))
2128 E1000_READ_REG(hw, E1000_SCVPC);
2132 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2133 * @hw: pointer to the HW structure
2135 * After rx enable if managability is enabled then there is likely some
2136 * bad data at the start of the fifo and possibly in the DMA fifo. This
2137 * function clears the fifos and flushes any packets that came in as rx was
2140 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2142 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2145 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2146 if (hw->mac.type != e1000_82575 ||
2147 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2150 /* Disable all Rx queues */
2151 for (i = 0; i < 4; i++) {
2152 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2153 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2154 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2156 /* Poll all queues to verify they have shut down */
2157 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2160 for (i = 0; i < 4; i++)
2161 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2162 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2167 DEBUGOUT("Queue disable timed out after 10ms\n");
2169 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2170 * incoming packets are rejected. Set enable and wait 2ms so that
2171 * any packet that was coming in as RCTL.EN was set is flushed
2173 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2174 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2176 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2177 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2179 rctl = E1000_READ_REG(hw, E1000_RCTL);
2180 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2181 temp_rctl |= E1000_RCTL_LPE;
2183 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2184 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2185 E1000_WRITE_FLUSH(hw);
2188 /* Enable Rx queues that were previously enabled and restore our
2191 for (i = 0; i < 4; i++)
2192 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2193 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2194 E1000_WRITE_FLUSH(hw);
2196 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2197 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2199 /* Flush receive errors generated by workaround */
2200 E1000_READ_REG(hw, E1000_ROC);
2201 E1000_READ_REG(hw, E1000_RNBC);
2202 E1000_READ_REG(hw, E1000_MPC);
2206 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2207 * @hw: pointer to the HW structure
2209 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2210 * however the hardware default for these parts is 500us to 1ms which is less
2211 * than the 10ms recommended by the pci-e spec. To address this we need to
2212 * increase the value to either 10ms to 200ms for capability version 1 config,
2213 * or 16ms to 55ms for version 2.
2215 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2217 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2218 s32 ret_val = E1000_SUCCESS;
2221 /* only take action if timeout value is defaulted to 0 */
2222 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2226 * if capababilities version is type 1 we can write the
2227 * timeout of 10ms to 200ms through the GCR register
2229 if (!(gcr & E1000_GCR_CAP_VER2)) {
2230 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2235 * for version 2 capabilities we need to write the config space
2236 * directly in order to set the completion timeout value for
2239 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2244 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2246 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2249 /* disable completion timeout resend */
2250 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2252 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2257 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2258 * @hw: pointer to the hardware struct
2259 * @enable: state to enter, either enabled or disabled
2260 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2262 * enables/disables L2 switch anti-spoofing functionality.
2264 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2266 u32 reg_val, reg_offset;
2268 switch (hw->mac.type) {
2270 reg_offset = E1000_DTXSWC;
2274 reg_offset = E1000_TXSWC;
2280 reg_val = E1000_READ_REG(hw, reg_offset);
2282 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2283 E1000_DTXSWC_VLAN_SPOOF_MASK);
2284 /* The PF can spoof - it has to in order to
2285 * support emulation mode NICs
2287 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2289 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2290 E1000_DTXSWC_VLAN_SPOOF_MASK);
2292 E1000_WRITE_REG(hw, reg_offset, reg_val);
2296 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2297 * @hw: pointer to the hardware struct
2298 * @enable: state to enter, either enabled or disabled
2300 * enables/disables L2 switch loopback functionality.
2302 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2306 switch (hw->mac.type) {
2308 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2310 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2312 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2313 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2317 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2319 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2321 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2322 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2325 /* Currently no other hardware supports loopback */
2333 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2334 * @hw: pointer to the hardware struct
2335 * @enable: state to enter, either enabled or disabled
2337 * enables/disables replication of packets across multiple pools.
2339 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2341 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2344 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2346 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2348 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2352 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2353 * @hw: pointer to the HW structure
2354 * @offset: register offset to be read
2355 * @data: pointer to the read data
2357 * Reads the MDI control register in the PHY at offset and stores the
2358 * information read to data.
2360 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2364 DEBUGFUNC("e1000_read_phy_reg_82580");
2366 ret_val = hw->phy.ops.acquire(hw);
2370 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2372 hw->phy.ops.release(hw);
2379 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2380 * @hw: pointer to the HW structure
2381 * @offset: register offset to write to
2382 * @data: data to write to register at offset
2384 * Writes data to MDI control register in the PHY at offset.
2386 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2390 DEBUGFUNC("e1000_write_phy_reg_82580");
2392 ret_val = hw->phy.ops.acquire(hw);
2396 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2398 hw->phy.ops.release(hw);
2405 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2406 * @hw: pointer to the HW structure
2408 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2409 * the values found in the EEPROM. This addresses an issue in which these
2410 * bits are not restored from EEPROM after reset.
2412 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2414 s32 ret_val = E1000_SUCCESS;
2418 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2420 if (hw->mac.type != e1000_82580)
2422 if (!e1000_sgmii_active_82575(hw))
2425 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2426 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2429 DEBUGOUT("NVM Read Error\n");
2433 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2434 if (nvm_data & NVM_WORD24_EXT_MDIO)
2435 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2436 if (nvm_data & NVM_WORD24_COM_MDIO)
2437 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2438 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2444 * e1000_reset_hw_82580 - Reset hardware
2445 * @hw: pointer to the HW structure
2447 * This resets function or entire device (all ports, etc.)
2450 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2452 s32 ret_val = E1000_SUCCESS;
2453 /* BH SW mailbox bit in SW_FW_SYNC */
2454 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2456 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2458 DEBUGFUNC("e1000_reset_hw_82580");
2460 hw->dev_spec._82575.global_device_reset = false;
2462 /* 82580 does not reliably do global_device_reset due to hw errata */
2463 if (hw->mac.type == e1000_82580)
2464 global_device_reset = false;
2466 /* Get current control state. */
2467 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2470 * Prevent the PCI-E bus from sticking if there is no TLP connection
2471 * on the last TLP read/write transaction when MAC is reset.
2473 ret_val = e1000_disable_pcie_master_generic(hw);
2475 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2477 DEBUGOUT("Masking off all interrupts\n");
2478 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2479 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2480 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2481 E1000_WRITE_FLUSH(hw);
2485 /* Determine whether or not a global dev reset is requested */
2486 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2488 global_device_reset = false;
2490 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2491 E1000_STAT_DEV_RST_SET))
2492 ctrl |= E1000_CTRL_DEV_RST;
2494 ctrl |= E1000_CTRL_RST;
2496 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2498 switch (hw->device_id) {
2499 case E1000_DEV_ID_DH89XXCC_SGMII:
2502 E1000_WRITE_FLUSH(hw);
2506 /* Add delay to insure DEV_RST or RST has time to complete */
2509 ret_val = e1000_get_auto_rd_done_generic(hw);
2512 * When auto config read does not complete, do not
2513 * return with an error. This can happen in situations
2514 * where there is no eeprom and prevents getting link.
2516 DEBUGOUT("Auto Read Done did not complete\n");
2519 /* clear global device reset status bit */
2520 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2522 /* Clear any pending interrupt events. */
2523 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2524 E1000_READ_REG(hw, E1000_ICR);
2526 ret_val = e1000_reset_mdicnfg_82580(hw);
2528 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2530 /* Install any alternate MAC address into RAR0 */
2531 ret_val = e1000_check_alt_mac_addr_generic(hw);
2533 /* Release semaphore */
2534 if (global_device_reset)
2535 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2541 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2542 * @data: data received by reading RXPBS register
2544 * The 82580 uses a table based approach for packet buffer allocation sizes.
2545 * This function converts the retrieved value into the correct table value
2546 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2547 * 0x0 36 72 144 1 2 4 8 16
2548 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2550 u16 e1000_rxpbs_adjust_82580(u32 data)
2554 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2555 ret_val = e1000_82580_rxpbs_table[data];
2561 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2563 * @hw: pointer to the HW structure
2564 * @offset: offset in words of the checksum protected region
2566 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2567 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2569 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2571 s32 ret_val = E1000_SUCCESS;
2575 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2577 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2578 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2580 DEBUGOUT("NVM Read Error\n");
2583 checksum += nvm_data;
2586 if (checksum != (u16) NVM_SUM) {
2587 DEBUGOUT("NVM Checksum Invalid\n");
2588 ret_val = -E1000_ERR_NVM;
2597 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2599 * @hw: pointer to the HW structure
2600 * @offset: offset in words of the checksum protected region
2602 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2603 * up to the checksum. Then calculates the EEPROM checksum and writes the
2604 * value to the EEPROM.
2606 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2612 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2614 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2615 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2617 DEBUGOUT("NVM Read Error while updating checksum.\n");
2620 checksum += nvm_data;
2622 checksum = (u16) NVM_SUM - checksum;
2623 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2626 DEBUGOUT("NVM Write Error while updating checksum.\n");
2633 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2634 * @hw: pointer to the HW structure
2636 * Calculates the EEPROM section checksum by reading/adding each word of
2637 * the EEPROM and then verifies that the sum of the EEPROM is
2640 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2643 u16 eeprom_regions_count = 1;
2647 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2649 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2651 DEBUGOUT("NVM Read Error\n");
2655 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2656 /* if chekcsums compatibility bit is set validate checksums
2657 * for all 4 ports. */
2658 eeprom_regions_count = 4;
2661 for (j = 0; j < eeprom_regions_count; j++) {
2662 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2663 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2665 if (ret_val != E1000_SUCCESS)
2674 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2675 * @hw: pointer to the HW structure
2677 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2678 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2679 * checksum and writes the value to the EEPROM.
2681 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2687 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2689 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2691 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2695 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2696 /* set compatibility bit to validate checksums appropriately */
2697 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2698 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2701 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2706 for (j = 0; j < 4; j++) {
2707 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2708 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2718 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2719 * @hw: pointer to the HW structure
2721 * Calculates the EEPROM section checksum by reading/adding each word of
2722 * the EEPROM and then verifies that the sum of the EEPROM is
2725 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2727 s32 ret_val = E1000_SUCCESS;
2731 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2733 for (j = 0; j < 4; j++) {
2734 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2735 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2737 if (ret_val != E1000_SUCCESS)
2746 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2747 * @hw: pointer to the HW structure
2749 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2750 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2751 * checksum and writes the value to the EEPROM.
2753 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2755 s32 ret_val = E1000_SUCCESS;
2759 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2761 for (j = 0; j < 4; j++) {
2762 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2763 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2764 if (ret_val != E1000_SUCCESS)
2773 * __e1000_access_emi_reg - Read/write EMI register
2774 * @hw: pointer to the HW structure
2775 * @addr: EMI address to program
2776 * @data: pointer to value to read/write from/to the EMI address
2777 * @read: boolean flag to indicate read or write
2779 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2780 u16 *data, bool read)
2784 DEBUGFUNC("__e1000_access_emi_reg");
2786 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2791 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2793 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2799 * e1000_read_emi_reg - Read Extended Management Interface register
2800 * @hw: pointer to the HW structure
2801 * @addr: EMI address to program
2802 * @data: value to be read from the EMI address
2804 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2806 DEBUGFUNC("e1000_read_emi_reg");
2808 return __e1000_access_emi_reg(hw, addr, data, true);
2812 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2813 * @hw: pointer to the HW structure
2815 * Initialize Marverl 1512 to work correctly with Avoton.
2817 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2819 struct e1000_phy_info *phy = &hw->phy;
2820 s32 ret_val = E1000_SUCCESS;
2822 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2824 /* Check if this is correct PHY. */
2825 if (phy->id != M88E1512_E_PHY_ID)
2828 /* Switch to PHY page 0xFF. */
2829 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2833 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2837 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2841 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2845 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2849 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2853 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2857 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2861 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2865 /* Switch to PHY page 0xFB. */
2866 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2870 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2874 /* Switch to PHY page 0x12. */
2875 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2879 /* Change mode to SGMII-to-Copper */
2880 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2884 /* Return the PHY to page 0. */
2885 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2889 ret_val = phy->ops.commit(hw);
2891 DEBUGOUT("Error committing the PHY changes\n");
2901 * e1000_set_eee_i350 - Enable/disable EEE support
2902 * @hw: pointer to the HW structure
2904 * Enable/disable EEE based on setting in dev_spec structure.
2907 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2909 s32 ret_val = E1000_SUCCESS;
2912 DEBUGFUNC("e1000_set_eee_i350");
2914 if ((hw->mac.type < e1000_i350) ||
2915 (hw->phy.media_type != e1000_media_type_copper))
2917 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2918 eeer = E1000_READ_REG(hw, E1000_EEER);
2920 /* enable or disable per user setting */
2921 if (!(hw->dev_spec._82575.eee_disable)) {
2922 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2924 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2925 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2928 /* This bit should not be set in normal operation. */
2929 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2930 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2932 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2933 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2936 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2937 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2938 E1000_READ_REG(hw, E1000_IPCNFG);
2939 E1000_READ_REG(hw, E1000_EEER);
2946 * e1000_set_eee_i354 - Enable/disable EEE support
2947 * @hw: pointer to the HW structure
2949 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2952 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2954 struct e1000_phy_info *phy = &hw->phy;
2955 s32 ret_val = E1000_SUCCESS;
2958 DEBUGFUNC("e1000_set_eee_i354");
2960 if ((hw->phy.media_type != e1000_media_type_copper) ||
2961 ((phy->id != M88E1543_E_PHY_ID) &&
2962 (phy->id != M88E1512_E_PHY_ID)))
2965 if (!hw->dev_spec._82575.eee_disable) {
2966 /* Switch to PHY page 18. */
2967 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2971 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2976 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2977 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2982 /* Return the PHY to page 0. */
2983 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2987 /* Turn on EEE advertisement. */
2988 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2989 E1000_EEE_ADV_DEV_I354,
2994 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2995 E1000_EEE_ADV_1000_SUPPORTED;
2996 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2997 E1000_EEE_ADV_DEV_I354,
3000 /* Turn off EEE advertisement. */
3001 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3002 E1000_EEE_ADV_DEV_I354,
3007 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3008 E1000_EEE_ADV_1000_SUPPORTED);
3009 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3010 E1000_EEE_ADV_DEV_I354,
3019 * e1000_get_eee_status_i354 - Get EEE status
3020 * @hw: pointer to the HW structure
3021 * @status: EEE status
3023 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
3026 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3028 struct e1000_phy_info *phy = &hw->phy;
3029 s32 ret_val = E1000_SUCCESS;
3032 DEBUGFUNC("e1000_get_eee_status_i354");
3034 /* Check if EEE is supported on this device. */
3035 if ((hw->phy.media_type != e1000_media_type_copper) ||
3036 ((phy->id != M88E1543_E_PHY_ID) &&
3037 (phy->id != M88E1512_E_PHY_ID)))
3040 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3041 E1000_PCS_STATUS_DEV_I354,
3046 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3047 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3053 /* Due to a hw errata, if the host tries to configure the VFTA register
3054 * while performing queries from the BMC or DMA, then the VFTA in some
3055 * cases won't be written.
3059 * e1000_clear_vfta_i350 - Clear VLAN filter table
3060 * @hw: pointer to the HW structure
3062 * Clears the register array which contains the VLAN filter table by
3063 * setting all the values to 0.
3065 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3070 DEBUGFUNC("e1000_clear_vfta_350");
3072 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3073 for (i = 0; i < 10; i++)
3074 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3076 E1000_WRITE_FLUSH(hw);
3081 * e1000_write_vfta_i350 - Write value to VLAN filter table
3082 * @hw: pointer to the HW structure
3083 * @offset: register offset in VLAN filter table
3084 * @value: register value written to VLAN filter table
3086 * Writes value at the given offset in the register array which stores
3087 * the VLAN filter table.
3089 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3093 DEBUGFUNC("e1000_write_vfta_350");
3095 for (i = 0; i < 10; i++)
3096 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3098 E1000_WRITE_FLUSH(hw);
3103 * e1000_set_i2c_bb - Enable I2C bit-bang
3104 * @hw: pointer to the HW structure
3106 * Enable I2C bit-bang interface
3109 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3111 s32 ret_val = E1000_SUCCESS;
3112 u32 ctrl_ext, i2cparams;
3114 DEBUGFUNC("e1000_set_i2c_bb");
3116 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3117 ctrl_ext |= E1000_CTRL_I2C_ENA;
3118 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3119 E1000_WRITE_FLUSH(hw);
3121 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3122 i2cparams |= E1000_I2CBB_EN;
3123 i2cparams |= E1000_I2C_DATA_OE_N;
3124 i2cparams |= E1000_I2C_CLK_OE_N;
3125 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3126 E1000_WRITE_FLUSH(hw);
3132 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3133 * @hw: pointer to hardware structure
3134 * @byte_offset: byte offset to read
3135 * @dev_addr: device address
3138 * Performs byte read operation over I2C interface at
3139 * a specified device address.
3141 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3142 u8 dev_addr, u8 *data)
3144 s32 status = E1000_SUCCESS;
3151 DEBUGFUNC("e1000_read_i2c_byte_generic");
3153 swfw_mask = E1000_SWFW_PHY0_SM;
3156 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3158 status = E1000_ERR_SWFW_SYNC;
3162 e1000_i2c_start(hw);
3164 /* Device Address and write indication */
3165 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3166 if (status != E1000_SUCCESS)
3169 status = e1000_get_i2c_ack(hw);
3170 if (status != E1000_SUCCESS)
3173 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3174 if (status != E1000_SUCCESS)
3177 status = e1000_get_i2c_ack(hw);
3178 if (status != E1000_SUCCESS)
3181 e1000_i2c_start(hw);
3183 /* Device Address and read indication */
3184 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3185 if (status != E1000_SUCCESS)
3188 status = e1000_get_i2c_ack(hw);
3189 if (status != E1000_SUCCESS)
3192 status = e1000_clock_in_i2c_byte(hw, data);
3193 if (status != E1000_SUCCESS)
3196 status = e1000_clock_out_i2c_bit(hw, nack);
3197 if (status != E1000_SUCCESS)
3204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3206 e1000_i2c_bus_clear(hw);
3208 if (retry < max_retry)
3209 DEBUGOUT("I2C byte read error - Retrying.\n");
3211 DEBUGOUT("I2C byte read error.\n");
3213 } while (retry < max_retry);
3215 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3223 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3224 * @hw: pointer to hardware structure
3225 * @byte_offset: byte offset to write
3226 * @dev_addr: device address
3227 * @data: value to write
3229 * Performs byte write operation over I2C interface at
3230 * a specified device address.
3232 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3233 u8 dev_addr, u8 data)
3235 s32 status = E1000_SUCCESS;
3240 DEBUGFUNC("e1000_write_i2c_byte_generic");
3242 swfw_mask = E1000_SWFW_PHY0_SM;
3244 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3245 status = E1000_ERR_SWFW_SYNC;
3246 goto write_byte_out;
3250 e1000_i2c_start(hw);
3252 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3253 if (status != E1000_SUCCESS)
3256 status = e1000_get_i2c_ack(hw);
3257 if (status != E1000_SUCCESS)
3260 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3261 if (status != E1000_SUCCESS)
3264 status = e1000_get_i2c_ack(hw);
3265 if (status != E1000_SUCCESS)
3268 status = e1000_clock_out_i2c_byte(hw, data);
3269 if (status != E1000_SUCCESS)
3272 status = e1000_get_i2c_ack(hw);
3273 if (status != E1000_SUCCESS)
3280 e1000_i2c_bus_clear(hw);
3282 if (retry < max_retry)
3283 DEBUGOUT("I2C byte write error - Retrying.\n");
3285 DEBUGOUT("I2C byte write error.\n");
3286 } while (retry < max_retry);
3288 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3296 * e1000_i2c_start - Sets I2C start condition
3297 * @hw: pointer to hardware structure
3299 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3301 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3303 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3305 DEBUGFUNC("e1000_i2c_start");
3307 /* Start condition must begin with data and clock high */
3308 e1000_set_i2c_data(hw, &i2cctl, 1);
3309 e1000_raise_i2c_clk(hw, &i2cctl);
3311 /* Setup time for start condition (4.7us) */
3312 usec_delay(E1000_I2C_T_SU_STA);
3314 e1000_set_i2c_data(hw, &i2cctl, 0);
3316 /* Hold time for start condition (4us) */
3317 usec_delay(E1000_I2C_T_HD_STA);
3319 e1000_lower_i2c_clk(hw, &i2cctl);
3321 /* Minimum low period of clock is 4.7 us */
3322 usec_delay(E1000_I2C_T_LOW);
3327 * e1000_i2c_stop - Sets I2C stop condition
3328 * @hw: pointer to hardware structure
3330 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3332 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3334 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3336 DEBUGFUNC("e1000_i2c_stop");
3338 /* Stop condition must begin with data low and clock high */
3339 e1000_set_i2c_data(hw, &i2cctl, 0);
3340 e1000_raise_i2c_clk(hw, &i2cctl);
3342 /* Setup time for stop condition (4us) */
3343 usec_delay(E1000_I2C_T_SU_STO);
3345 e1000_set_i2c_data(hw, &i2cctl, 1);
3347 /* bus free time between stop and start (4.7us)*/
3348 usec_delay(E1000_I2C_T_BUF);
3352 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3353 * @hw: pointer to hardware structure
3354 * @data: data byte to clock in
3356 * Clocks in one byte data via I2C data/clock
3358 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3363 DEBUGFUNC("e1000_clock_in_i2c_byte");
3366 for (i = 7; i >= 0; i--) {
3367 e1000_clock_in_i2c_bit(hw, &bit);
3371 return E1000_SUCCESS;
3375 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3376 * @hw: pointer to hardware structure
3377 * @data: data byte clocked out
3379 * Clocks out one byte data via I2C data/clock
3381 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3383 s32 status = E1000_SUCCESS;
3388 DEBUGFUNC("e1000_clock_out_i2c_byte");
3390 for (i = 7; i >= 0; i--) {
3391 bit = (data >> i) & 0x1;
3392 status = e1000_clock_out_i2c_bit(hw, bit);
3394 if (status != E1000_SUCCESS)
3398 /* Release SDA line (set high) */
3399 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3401 i2cctl |= E1000_I2C_DATA_OE_N;
3402 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3403 E1000_WRITE_FLUSH(hw);
3409 * e1000_get_i2c_ack - Polls for I2C ACK
3410 * @hw: pointer to hardware structure
3412 * Clocks in/out one bit via I2C data/clock
3414 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3416 s32 status = E1000_SUCCESS;
3418 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3422 DEBUGFUNC("e1000_get_i2c_ack");
3424 e1000_raise_i2c_clk(hw, &i2cctl);
3426 /* Minimum high period of clock is 4us */
3427 usec_delay(E1000_I2C_T_HIGH);
3429 /* Wait until SCL returns high */
3430 for (i = 0; i < timeout; i++) {
3432 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3433 if (i2cctl & E1000_I2C_CLK_IN)
3436 if (!(i2cctl & E1000_I2C_CLK_IN))
3437 return E1000_ERR_I2C;
3439 ack = e1000_get_i2c_data(&i2cctl);
3441 DEBUGOUT("I2C ack was not received.\n");
3442 status = E1000_ERR_I2C;
3445 e1000_lower_i2c_clk(hw, &i2cctl);
3447 /* Minimum low period of clock is 4.7 us */
3448 usec_delay(E1000_I2C_T_LOW);
3454 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3455 * @hw: pointer to hardware structure
3456 * @data: read data value
3458 * Clocks in one bit via I2C data/clock
3460 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3462 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3464 DEBUGFUNC("e1000_clock_in_i2c_bit");
3466 e1000_raise_i2c_clk(hw, &i2cctl);
3468 /* Minimum high period of clock is 4us */
3469 usec_delay(E1000_I2C_T_HIGH);
3471 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3472 *data = e1000_get_i2c_data(&i2cctl);
3474 e1000_lower_i2c_clk(hw, &i2cctl);
3476 /* Minimum low period of clock is 4.7 us */
3477 usec_delay(E1000_I2C_T_LOW);
3479 return E1000_SUCCESS;
3483 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3484 * @hw: pointer to hardware structure
3485 * @data: data value to write
3487 * Clocks out one bit via I2C data/clock
3489 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3492 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3494 DEBUGFUNC("e1000_clock_out_i2c_bit");
3496 status = e1000_set_i2c_data(hw, &i2cctl, data);
3497 if (status == E1000_SUCCESS) {
3498 e1000_raise_i2c_clk(hw, &i2cctl);
3500 /* Minimum high period of clock is 4us */
3501 usec_delay(E1000_I2C_T_HIGH);
3503 e1000_lower_i2c_clk(hw, &i2cctl);
3505 /* Minimum low period of clock is 4.7 us.
3506 * This also takes care of the data hold time.
3508 usec_delay(E1000_I2C_T_LOW);
3510 status = E1000_ERR_I2C;
3511 DEBUGOUT1("I2C data was not set to %X\n", data);
3517 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3518 * @hw: pointer to hardware structure
3519 * @i2cctl: Current value of I2CCTL register
3521 * Raises the I2C clock line '0'->'1'
3523 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3525 DEBUGFUNC("e1000_raise_i2c_clk");
3527 *i2cctl |= E1000_I2C_CLK_OUT;
3528 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3529 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3530 E1000_WRITE_FLUSH(hw);
3532 /* SCL rise time (1000ns) */
3533 usec_delay(E1000_I2C_T_RISE);
3537 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3538 * @hw: pointer to hardware structure
3539 * @i2cctl: Current value of I2CCTL register
3541 * Lowers the I2C clock line '1'->'0'
3543 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3546 DEBUGFUNC("e1000_lower_i2c_clk");
3548 *i2cctl &= ~E1000_I2C_CLK_OUT;
3549 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3550 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3551 E1000_WRITE_FLUSH(hw);
3553 /* SCL fall time (300ns) */
3554 usec_delay(E1000_I2C_T_FALL);
3558 * e1000_set_i2c_data - Sets the I2C data bit
3559 * @hw: pointer to hardware structure
3560 * @i2cctl: Current value of I2CCTL register
3561 * @data: I2C data value (0 or 1) to set
3563 * Sets the I2C data bit
3565 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3567 s32 status = E1000_SUCCESS;
3569 DEBUGFUNC("e1000_set_i2c_data");
3572 *i2cctl |= E1000_I2C_DATA_OUT;
3574 *i2cctl &= ~E1000_I2C_DATA_OUT;
3576 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3577 *i2cctl |= E1000_I2C_CLK_OE_N;
3578 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3579 E1000_WRITE_FLUSH(hw);
3581 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3582 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3584 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3585 if (data != e1000_get_i2c_data(i2cctl)) {
3586 status = E1000_ERR_I2C;
3587 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3594 * e1000_get_i2c_data - Reads the I2C SDA data bit
3595 * @hw: pointer to hardware structure
3596 * @i2cctl: Current value of I2CCTL register
3598 * Returns the I2C data bit value
3600 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3604 DEBUGFUNC("e1000_get_i2c_data");
3606 if (*i2cctl & E1000_I2C_DATA_IN)
3615 * e1000_i2c_bus_clear - Clears the I2C bus
3616 * @hw: pointer to hardware structure
3618 * Clears the I2C bus by sending nine clock pulses.
3619 * Used when data line is stuck low.
3621 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3623 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3626 DEBUGFUNC("e1000_i2c_bus_clear");
3628 e1000_i2c_start(hw);
3630 e1000_set_i2c_data(hw, &i2cctl, 1);
3632 for (i = 0; i < 9; i++) {
3633 e1000_raise_i2c_clk(hw, &i2cctl);
3635 /* Min high period of clock is 4us */
3636 usec_delay(E1000_I2C_T_HIGH);
3638 e1000_lower_i2c_clk(hw, &i2cctl);
3640 /* Min low period of clock is 4.7us*/
3641 usec_delay(E1000_I2C_T_LOW);
3644 e1000_i2c_start(hw);
3646 /* Put the i2c bus back to default state */