1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
6 * 82575EB Gigabit Network Connection
7 * 82575EB Gigabit Backplane Connection
8 * 82575GB Gigabit Network Connection
9 * 82576 Gigabit Network Connection
10 * 82576 Quad Port Gigabit Mezzanine Adapter
11 * 82580 Gigabit Network Connection
12 * I350 Gigabit Network Connection
15 #include "e1000_api.h"
16 #include "e1000_i210.h"
18 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
19 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
20 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
21 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
22 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
23 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
24 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
25 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
27 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
28 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
30 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
31 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw);
32 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);
33 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
34 u32 offset, u16 *data);
35 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
36 u32 offset, u16 data);
37 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
39 STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
41 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
43 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
44 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
45 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw);
46 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
47 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
48 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
49 u32 offset, u16 data);
50 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
51 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
52 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
53 u16 *speed, u16 *duplex);
54 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
55 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
56 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
57 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
58 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
59 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
60 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
61 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
62 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
63 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
64 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
65 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
67 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
69 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
70 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
71 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
73 STATIC void e1000_i2c_start(struct e1000_hw *hw);
74 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
75 STATIC void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
76 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
77 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
78 STATIC void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
79 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
80 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
81 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
82 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
83 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
85 STATIC const u16 e1000_82580_rxpbs_table[] = {
86 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
87 #define E1000_82580_RXPBS_TABLE_SIZE \
88 (sizeof(e1000_82580_rxpbs_table) / \
89 sizeof(e1000_82580_rxpbs_table[0]))
93 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
94 * @hw: pointer to the HW structure
96 * Called to determine if the I2C pins are being used for I2C or as an
97 * external MDIO interface since the two options are mutually exclusive.
99 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
102 bool ext_mdio = false;
104 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
106 switch (hw->mac.type) {
109 reg = E1000_READ_REG(hw, E1000_MDIC);
110 ext_mdio = !!(reg & E1000_MDIC_DEST);
117 reg = E1000_READ_REG(hw, E1000_MDICNFG);
118 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
127 * e1000_init_phy_params_82575 - Initialize PHY function ptrs
128 * @hw: pointer to the HW structure
130 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
132 struct e1000_phy_info *phy = &hw->phy;
133 s32 ret_val = E1000_SUCCESS;
136 DEBUGFUNC("e1000_init_phy_params_82575");
138 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
139 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
141 if (hw->phy.media_type != e1000_media_type_copper) {
142 phy->type = e1000_phy_none;
146 phy->ops.power_up = e1000_power_up_phy_copper;
147 phy->ops.power_down = e1000_power_down_phy_copper_base;
149 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
150 phy->reset_delay_us = 100;
152 phy->ops.acquire = e1000_acquire_phy_base;
153 phy->ops.check_reset_block = e1000_check_reset_block_generic;
154 phy->ops.commit = e1000_phy_sw_reset_generic;
155 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
156 phy->ops.release = e1000_release_phy_base;
158 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
160 if (e1000_sgmii_active_82575(hw)) {
161 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
162 ctrl_ext |= E1000_CTRL_I2C_ENA;
164 phy->ops.reset = e1000_phy_hw_reset_generic;
165 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
168 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
169 e1000_reset_mdicnfg_82580(hw);
171 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
172 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
173 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
175 switch (hw->mac.type) {
179 phy->ops.read_reg = e1000_read_phy_reg_82580;
180 phy->ops.write_reg = e1000_write_phy_reg_82580;
184 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
185 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
188 phy->ops.read_reg = e1000_read_phy_reg_igp;
189 phy->ops.write_reg = e1000_write_phy_reg_igp;
193 /* Set phy->phy_addr and phy->id. */
194 ret_val = e1000_get_phy_id_82575(hw);
196 /* Verify phy id and set remaining function pointers */
198 case M88E1543_E_PHY_ID:
199 case M88E1512_E_PHY_ID:
200 case I347AT4_E_PHY_ID:
201 case M88E1112_E_PHY_ID:
202 case M88E1340M_E_PHY_ID:
203 phy->type = e1000_phy_m88;
204 phy->ops.check_polarity = e1000_check_polarity_m88;
205 phy->ops.get_info = e1000_get_phy_info_m88;
206 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
207 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
209 case M88E1111_I_PHY_ID:
210 phy->type = e1000_phy_m88;
211 phy->ops.check_polarity = e1000_check_polarity_m88;
212 phy->ops.get_info = e1000_get_phy_info_m88;
213 phy->ops.get_cable_length = e1000_get_cable_length_m88;
214 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
216 case IGP03E1000_E_PHY_ID:
217 case IGP04E1000_E_PHY_ID:
218 phy->type = e1000_phy_igp_3;
219 phy->ops.check_polarity = e1000_check_polarity_igp;
220 phy->ops.get_info = e1000_get_phy_info_igp;
221 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
222 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
223 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
224 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
226 case I82580_I_PHY_ID:
228 phy->type = e1000_phy_82580;
229 phy->ops.check_polarity = e1000_check_polarity_82577;
230 phy->ops.get_info = e1000_get_phy_info_82577;
231 phy->ops.get_cable_length = e1000_get_cable_length_82577;
232 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
233 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
234 phy->ops.force_speed_duplex =
235 e1000_phy_force_speed_duplex_82577;
238 phy->type = e1000_phy_i210;
239 phy->ops.check_polarity = e1000_check_polarity_m88;
240 phy->ops.get_info = e1000_get_phy_info_m88;
241 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
242 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
243 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
244 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
246 case BCM54616_E_PHY_ID:
247 phy->type = e1000_phy_none;
250 ret_val = -E1000_ERR_PHY;
254 /* Check if this PHY is configured for media swap. */
256 case M88E1112_E_PHY_ID:
260 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
263 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
268 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
269 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
270 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
271 data == E1000_M88E1112_AUTO_COPPER_BASEX)
272 hw->mac.ops.check_for_link =
273 e1000_check_for_link_media_swap;
276 case M88E1512_E_PHY_ID:
278 ret_val = e1000_initialize_M88E1512_phy(hw);
281 case M88E1543_E_PHY_ID:
283 ret_val = e1000_initialize_M88E1543_phy(hw);
295 * e1000_init_mac_params_82575 - Initialize MAC function ptrs
296 * @hw: pointer to the HW structure
298 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
300 struct e1000_mac_info *mac = &hw->mac;
301 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
303 DEBUGFUNC("e1000_init_mac_params_82575");
305 /* Initialize function pointer */
306 e1000_init_mac_ops_generic(hw);
308 /* Derives media type */
309 e1000_get_media_type_82575(hw);
310 /* Set MTA register count */
311 mac->mta_reg_count = 128;
312 /* Set UTA register count */
313 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
314 /* Set RAR entry count */
315 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
316 if (mac->type == e1000_82576)
317 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
318 if (mac->type == e1000_82580)
319 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
320 if (mac->type == e1000_i350 || mac->type == e1000_i354)
321 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
323 /* Enable EEE default settings for EEE supported devices */
324 if (mac->type >= e1000_i350)
325 dev_spec->eee_disable = false;
327 /* Allow a single clear of the SW semaphore on I210 and newer */
328 if (mac->type >= e1000_i210)
329 dev_spec->clear_semaphore_once = true;
331 /* Set if part includes ASF firmware */
332 mac->asf_firmware_present = true;
334 mac->has_fwsm = true;
335 /* ARC supported; valid only if manageability features are enabled. */
336 mac->arc_subsystem_valid =
337 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
339 /* Function pointers */
341 /* bus type/speed/width */
342 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
344 if (mac->type >= e1000_82580)
345 mac->ops.reset_hw = e1000_reset_hw_82580;
347 mac->ops.reset_hw = e1000_reset_hw_82575;
348 /* HW initialization */
349 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
350 mac->ops.init_hw = e1000_init_hw_i210;
352 mac->ops.init_hw = e1000_init_hw_82575;
354 mac->ops.setup_link = e1000_setup_link_generic;
355 /* physical interface link setup */
356 mac->ops.setup_physical_interface =
357 (hw->phy.media_type == e1000_media_type_copper)
358 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
359 /* physical interface shutdown */
360 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
361 /* physical interface power up */
362 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
364 mac->ops.check_for_link = e1000_check_for_link_82575;
365 /* read mac address */
366 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
367 /* configure collision distance */
368 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
369 /* multicast address update */
370 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
371 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
373 mac->ops.write_vfta = e1000_write_vfta_i350;
375 mac->ops.clear_vfta = e1000_clear_vfta_i350;
378 mac->ops.write_vfta = e1000_write_vfta_generic;
380 mac->ops.clear_vfta = e1000_clear_vfta_generic;
382 if (hw->mac.type >= e1000_82580)
383 mac->ops.validate_mdi_setting =
384 e1000_validate_mdi_setting_crossover_generic;
386 mac->ops.id_led_init = e1000_id_led_init_generic;
388 mac->ops.blink_led = e1000_blink_led_generic;
390 mac->ops.setup_led = e1000_setup_led_generic;
392 mac->ops.cleanup_led = e1000_cleanup_led_generic;
393 /* turn on/off LED */
394 mac->ops.led_on = e1000_led_on_generic;
395 mac->ops.led_off = e1000_led_off_generic;
396 /* clear hardware counters */
397 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
399 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
400 /* acquire SW_FW sync */
401 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
402 /* release SW_FW sync */
403 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
404 if (mac->type == e1000_i210 || mac->type == e1000_i211) {
405 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
406 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
409 /* set lan id for port to determine which phy lock to use */
410 hw->mac.ops.set_lan_id(hw);
412 return E1000_SUCCESS;
416 * e1000_init_nvm_params_82575 - Initialize NVM function ptrs
417 * @hw: pointer to the HW structure
419 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
421 struct e1000_nvm_info *nvm = &hw->nvm;
422 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
425 DEBUGFUNC("e1000_init_nvm_params_82575");
427 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
428 E1000_EECD_SIZE_EX_SHIFT);
429 /* Added to a constant, "size" becomes the left-shift value
430 * for setting word_size.
432 size += NVM_WORD_SIZE_BASE_SHIFT;
434 /* Just in case size is out of range, cap it to the largest
435 * EEPROM size supported
440 nvm->word_size = 1 << size;
441 if (hw->mac.type < e1000_i210) {
442 nvm->opcode_bits = 8;
445 switch (nvm->override) {
446 case e1000_nvm_override_spi_large:
448 nvm->address_bits = 16;
450 case e1000_nvm_override_spi_small:
452 nvm->address_bits = 8;
455 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
456 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
460 if (nvm->word_size == (1 << 15))
461 nvm->page_size = 128;
463 nvm->type = e1000_nvm_eeprom_spi;
465 nvm->type = e1000_nvm_flash_hw;
468 /* Function Pointers */
469 nvm->ops.acquire = e1000_acquire_nvm_82575;
470 nvm->ops.release = e1000_release_nvm_82575;
471 if (nvm->word_size < (1 << 15))
472 nvm->ops.read = e1000_read_nvm_eerd;
474 nvm->ops.read = e1000_read_nvm_spi;
476 nvm->ops.write = e1000_write_nvm_spi;
477 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
478 nvm->ops.update = e1000_update_nvm_checksum_generic;
479 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
481 /* override generic family function pointers for specific descendants */
482 switch (hw->mac.type) {
484 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
485 nvm->ops.update = e1000_update_nvm_checksum_82580;
488 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
489 nvm->ops.update = e1000_update_nvm_checksum_i350;
495 return E1000_SUCCESS;
499 * e1000_init_function_pointers_82575 - Init func ptrs.
500 * @hw: pointer to the HW structure
502 * Called to initialize all function pointers and parameters.
504 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
506 DEBUGFUNC("e1000_init_function_pointers_82575");
508 hw->mac.ops.init_params = e1000_init_mac_params_82575;
509 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
510 hw->phy.ops.init_params = e1000_init_phy_params_82575;
511 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
515 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
516 * @hw: pointer to the HW structure
517 * @offset: register offset to be read
518 * @data: pointer to the read data
520 * Reads the PHY register at offset using the serial gigabit media independent
521 * interface and stores the retrieved information in data.
523 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
526 s32 ret_val = -E1000_ERR_PARAM;
528 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
530 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
531 DEBUGOUT1("PHY Address %u is out of range\n", offset);
535 ret_val = hw->phy.ops.acquire(hw);
539 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
541 hw->phy.ops.release(hw);
548 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
549 * @hw: pointer to the HW structure
550 * @offset: register offset to write to
551 * @data: data to write at register offset
553 * Writes the data to PHY register at the offset using the serial gigabit
554 * media independent interface.
556 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
559 s32 ret_val = -E1000_ERR_PARAM;
561 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
563 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
564 DEBUGOUT1("PHY Address %d is out of range\n", offset);
568 ret_val = hw->phy.ops.acquire(hw);
572 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
574 hw->phy.ops.release(hw);
581 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
582 * @hw: pointer to the HW structure
584 * Retrieves the PHY address and ID for both PHY's which do and do not use
587 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
589 struct e1000_phy_info *phy = &hw->phy;
590 s32 ret_val = E1000_SUCCESS;
595 DEBUGFUNC("e1000_get_phy_id_82575");
597 /* some i354 devices need an extra read for phy id */
598 if (hw->mac.type == e1000_i354)
599 e1000_get_phy_id(hw);
602 * For SGMII PHYs, we try the list of possible addresses until
603 * we find one that works. For non-SGMII PHYs
604 * (e.g. integrated copper PHYs), an address of 1 should
605 * work. The result of this function should mean phy->phy_addr
606 * and phy->id are set correctly.
608 if (!e1000_sgmii_active_82575(hw)) {
610 ret_val = e1000_get_phy_id(hw);
614 if (e1000_sgmii_uses_mdio_82575(hw)) {
615 switch (hw->mac.type) {
618 mdic = E1000_READ_REG(hw, E1000_MDIC);
619 mdic &= E1000_MDIC_PHY_MASK;
620 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
627 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
628 mdic &= E1000_MDICNFG_PHY_MASK;
629 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
632 ret_val = -E1000_ERR_PHY;
636 ret_val = e1000_get_phy_id(hw);
640 /* Power on sgmii phy if it is disabled */
641 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
642 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
643 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
644 E1000_WRITE_FLUSH(hw);
648 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
649 * Therefore, we need to test 1-7
651 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
652 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
653 if (ret_val == E1000_SUCCESS) {
654 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
657 * At the time of this writing, The M88 part is
658 * the only supported SGMII PHY product.
660 if (phy_id == M88_VENDOR)
663 DEBUGOUT1("PHY address %u was unreadable\n",
668 /* A valid PHY type couldn't be found. */
669 if (phy->addr == 8) {
671 ret_val = -E1000_ERR_PHY;
673 ret_val = e1000_get_phy_id(hw);
676 /* restore previous sfp cage power state */
677 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
684 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
685 * @hw: pointer to the HW structure
687 * Resets the PHY using the serial gigabit media independent interface.
689 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
691 s32 ret_val = E1000_SUCCESS;
692 struct e1000_phy_info *phy = &hw->phy;
694 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
697 * This isn't a true "hard" reset, but is the only reset
698 * available to us at this time.
701 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
703 if (!(hw->phy.ops.write_reg))
707 * SFP documentation requires the following to configure the SPF module
708 * to work on SGMII. No further documentation is given.
710 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
714 ret_val = hw->phy.ops.commit(hw);
718 if (phy->id == M88E1512_E_PHY_ID)
719 ret_val = e1000_initialize_M88E1512_phy(hw);
725 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
726 * @hw: pointer to the HW structure
727 * @active: true to enable LPLU, false to disable
729 * Sets the LPLU D0 state according to the active flag. When
730 * activating LPLU this function also disables smart speed
731 * and vice versa. LPLU will not be activated unless the
732 * device autonegotiation advertisement meets standards of
733 * either 10 or 10/100 or 10/100/1000 at all duplexes.
734 * This is a function pointer entry point only called by
735 * PHY setup routines.
737 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
739 struct e1000_phy_info *phy = &hw->phy;
740 s32 ret_val = E1000_SUCCESS;
743 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
745 if (!(hw->phy.ops.read_reg))
748 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
753 data |= IGP02E1000_PM_D0_LPLU;
754 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
759 /* When LPLU is enabled, we should disable SmartSpeed */
760 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
762 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
763 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
768 data &= ~IGP02E1000_PM_D0_LPLU;
769 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
772 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
773 * during Dx states where the power conservation is most
774 * important. During driver activity we should enable
775 * SmartSpeed, so performance is maintained.
777 if (phy->smart_speed == e1000_smart_speed_on) {
778 ret_val = phy->ops.read_reg(hw,
779 IGP01E1000_PHY_PORT_CONFIG,
784 data |= IGP01E1000_PSCFR_SMART_SPEED;
785 ret_val = phy->ops.write_reg(hw,
786 IGP01E1000_PHY_PORT_CONFIG,
790 } else if (phy->smart_speed == e1000_smart_speed_off) {
791 ret_val = phy->ops.read_reg(hw,
792 IGP01E1000_PHY_PORT_CONFIG,
797 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
798 ret_val = phy->ops.write_reg(hw,
799 IGP01E1000_PHY_PORT_CONFIG,
811 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
812 * @hw: pointer to the HW structure
813 * @active: true to enable LPLU, false to disable
815 * Sets the LPLU D0 state according to the active flag. When
816 * activating LPLU this function also disables smart speed
817 * and vice versa. LPLU will not be activated unless the
818 * device autonegotiation advertisement meets standards of
819 * either 10 or 10/100 or 10/100/1000 at all duplexes.
820 * This is a function pointer entry point only called by
821 * PHY setup routines.
823 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
825 struct e1000_phy_info *phy = &hw->phy;
828 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
830 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
833 data |= E1000_82580_PM_D0_LPLU;
835 /* When LPLU is enabled, we should disable SmartSpeed */
836 data &= ~E1000_82580_PM_SPD;
838 data &= ~E1000_82580_PM_D0_LPLU;
841 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
842 * during Dx states where the power conservation is most
843 * important. During driver activity we should enable
844 * SmartSpeed, so performance is maintained.
846 if (phy->smart_speed == e1000_smart_speed_on)
847 data |= E1000_82580_PM_SPD;
848 else if (phy->smart_speed == e1000_smart_speed_off)
849 data &= ~E1000_82580_PM_SPD;
852 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
853 return E1000_SUCCESS;
857 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
858 * @hw: pointer to the HW structure
859 * @active: boolean used to enable/disable lplu
861 * Success returns 0, Failure returns 1
863 * The low power link up (lplu) state is set to the power management level D3
864 * and SmartSpeed is disabled when active is true, else clear lplu for D3
865 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
866 * is used during Dx states where the power conservation is most important.
867 * During driver activity, SmartSpeed should be enabled so performance is
870 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
872 struct e1000_phy_info *phy = &hw->phy;
875 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
877 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
880 data &= ~E1000_82580_PM_D3_LPLU;
882 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
883 * during Dx states where the power conservation is most
884 * important. During driver activity we should enable
885 * SmartSpeed, so performance is maintained.
887 if (phy->smart_speed == e1000_smart_speed_on)
888 data |= E1000_82580_PM_SPD;
889 else if (phy->smart_speed == e1000_smart_speed_off)
890 data &= ~E1000_82580_PM_SPD;
891 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
892 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
893 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
894 data |= E1000_82580_PM_D3_LPLU;
895 /* When LPLU is enabled, we should disable SmartSpeed */
896 data &= ~E1000_82580_PM_SPD;
899 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
900 return E1000_SUCCESS;
904 * e1000_acquire_nvm_82575 - Request for access to EEPROM
905 * @hw: pointer to the HW structure
907 * Acquire the necessary semaphores for exclusive access to the EEPROM.
908 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
909 * Return successful if access grant bit set, else clear the request for
910 * EEPROM access and return -E1000_ERR_NVM (-1).
912 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
914 s32 ret_val = E1000_SUCCESS;
916 DEBUGFUNC("e1000_acquire_nvm_82575");
918 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
923 * Check if there is some access
924 * error this access may hook on
926 if (hw->mac.type == e1000_i350) {
927 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
928 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
929 E1000_EECD_TIMEOUT)) {
930 /* Clear all access error flags */
931 E1000_WRITE_REG(hw, E1000_EECD, eecd |
932 E1000_EECD_ERROR_CLR);
933 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
937 if (hw->mac.type == e1000_82580) {
938 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
939 if (eecd & E1000_EECD_BLOCKED) {
940 /* Clear access error flag */
941 E1000_WRITE_REG(hw, E1000_EECD, eecd |
943 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
947 ret_val = e1000_acquire_nvm_generic(hw);
949 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
956 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
957 * @hw: pointer to the HW structure
959 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
960 * then release the semaphores acquired.
962 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
964 DEBUGFUNC("e1000_release_nvm_82575");
966 e1000_release_nvm_generic(hw);
968 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
972 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
973 * @hw: pointer to the HW structure
974 * @mask: specifies which semaphore to acquire
976 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
977 * will also specify which port we're acquiring the lock for.
979 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
983 u32 fwmask = mask << 16;
984 s32 ret_val = E1000_SUCCESS;
985 s32 i = 0, timeout = 200;
987 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
989 while (i < timeout) {
990 if (e1000_get_hw_semaphore_generic(hw)) {
991 ret_val = -E1000_ERR_SWFW_SYNC;
995 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
996 if (!(swfw_sync & (fwmask | swmask)))
1000 * Firmware currently using resource (fwmask)
1001 * or other software thread using resource (swmask)
1003 e1000_put_hw_semaphore_generic(hw);
1009 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1010 ret_val = -E1000_ERR_SWFW_SYNC;
1014 swfw_sync |= swmask;
1015 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1017 e1000_put_hw_semaphore_generic(hw);
1024 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1025 * @hw: pointer to the HW structure
1026 * @mask: specifies which semaphore to acquire
1028 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1029 * will also specify which port we're releasing the lock for.
1031 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1035 DEBUGFUNC("e1000_release_swfw_sync_82575");
1037 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1040 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1041 swfw_sync &= (u32)~mask;
1042 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1044 e1000_put_hw_semaphore_generic(hw);
1048 * e1000_get_cfg_done_82575 - Read config done bit
1049 * @hw: pointer to the HW structure
1051 * Read the management control register for the config done bit for
1052 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1053 * to read the config done bit, so an error is *ONLY* logged and returns
1054 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1055 * would not be able to be reset or change link.
1057 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1059 s32 timeout = PHY_CFG_TIMEOUT;
1060 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1062 DEBUGFUNC("e1000_get_cfg_done_82575");
1064 if (hw->bus.func == E1000_FUNC_1)
1065 mask = E1000_NVM_CFG_DONE_PORT_1;
1066 else if (hw->bus.func == E1000_FUNC_2)
1067 mask = E1000_NVM_CFG_DONE_PORT_2;
1068 else if (hw->bus.func == E1000_FUNC_3)
1069 mask = E1000_NVM_CFG_DONE_PORT_3;
1071 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1077 DEBUGOUT("MNG configuration cycle has not completed.\n");
1079 /* If EEPROM is not marked present, init the PHY manually */
1080 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1081 (hw->phy.type == e1000_phy_igp_3))
1082 e1000_phy_init_script_igp3(hw);
1084 return E1000_SUCCESS;
1088 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1089 * @hw: pointer to the HW structure
1090 * @speed: stores the current speed
1091 * @duplex: stores the current duplex
1093 * This is a wrapper function, if using the serial gigabit media independent
1094 * interface, use PCS to retrieve the link speed and duplex information.
1095 * Otherwise, use the generic function to get the link speed and duplex info.
1097 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1102 DEBUGFUNC("e1000_get_link_up_info_82575");
1104 if (hw->phy.media_type != e1000_media_type_copper)
1105 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1108 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1115 * e1000_check_for_link_82575 - Check for link
1116 * @hw: pointer to the HW structure
1118 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1119 * use the generic interface for determining link.
1121 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1126 DEBUGFUNC("e1000_check_for_link_82575");
1128 if (hw->phy.media_type != e1000_media_type_copper) {
1129 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1132 * Use this flag to determine if link needs to be checked or
1133 * not. If we have link clear the flag so that we do not
1134 * continue to check for link.
1136 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1139 * Configure Flow Control now that Auto-Neg has completed.
1140 * First, we need to restore the desired flow control
1141 * settings because we may have had to re-autoneg with a
1142 * different link partner.
1144 ret_val = e1000_config_fc_after_link_up_generic(hw);
1146 DEBUGOUT("Error configuring flow control\n");
1148 ret_val = e1000_check_for_copper_link_generic(hw);
1155 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1156 * @hw: pointer to the HW structure
1158 * Poll the M88E1112 interfaces to see which interface achieved link.
1160 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1162 struct e1000_phy_info *phy = &hw->phy;
1167 DEBUGFUNC("e1000_check_for_link_media_swap");
1169 /* Check for copper. */
1170 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1174 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1178 if (data & E1000_M88E1112_STATUS_LINK)
1179 port = E1000_MEDIA_PORT_COPPER;
1181 /* Check for other. */
1182 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1186 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1190 if (data & E1000_M88E1112_STATUS_LINK)
1191 port = E1000_MEDIA_PORT_OTHER;
1193 /* Determine if a swap needs to happen. */
1194 if (port && (hw->dev_spec._82575.media_port != port)) {
1195 hw->dev_spec._82575.media_port = port;
1196 hw->dev_spec._82575.media_changed = true;
1199 if (port == E1000_MEDIA_PORT_COPPER) {
1200 /* reset page to 0 */
1201 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1204 e1000_check_for_link_82575(hw);
1206 e1000_check_for_link_82575(hw);
1207 /* reset page to 0 */
1208 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1213 return E1000_SUCCESS;
1217 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1218 * @hw: pointer to the HW structure
1220 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1224 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1226 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1227 !e1000_sgmii_active_82575(hw))
1230 /* Enable PCS to turn on link */
1231 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1232 reg |= E1000_PCS_CFG_PCS_EN;
1233 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1235 /* Power up the laser */
1236 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1237 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1238 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1240 /* flush the write to verify completion */
1241 E1000_WRITE_FLUSH(hw);
1246 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1247 * @hw: pointer to the HW structure
1248 * @speed: stores the current speed
1249 * @duplex: stores the current duplex
1251 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1252 * duplex, then store the values in the pointers provided.
1254 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1255 u16 *speed, u16 *duplex)
1257 struct e1000_mac_info *mac = &hw->mac;
1261 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1264 * Read the PCS Status register for link state. For non-copper mode,
1265 * the status register is not accurate. The PCS status register is
1268 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1271 * The link up bit determines when link is up on autoneg.
1273 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1274 mac->serdes_has_link = true;
1276 /* Detect and store PCS speed */
1277 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1278 *speed = SPEED_1000;
1279 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1284 /* Detect and store PCS duplex */
1285 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1286 *duplex = FULL_DUPLEX;
1288 *duplex = HALF_DUPLEX;
1290 /* Check if it is an I354 2.5Gb backplane connection. */
1291 if (mac->type == e1000_i354) {
1292 status = E1000_READ_REG(hw, E1000_STATUS);
1293 if ((status & E1000_STATUS_2P5_SKU) &&
1294 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1295 *speed = SPEED_2500;
1296 *duplex = FULL_DUPLEX;
1297 DEBUGOUT("2500 Mbs, ");
1298 DEBUGOUT("Full Duplex\n");
1303 mac->serdes_has_link = false;
1308 return E1000_SUCCESS;
1312 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1313 * @hw: pointer to the HW structure
1315 * In the case of serdes shut down sfp and PCS on driver unload
1316 * when management pass thru is not enabled.
1318 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1322 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1324 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1325 !e1000_sgmii_active_82575(hw))
1328 if (!e1000_enable_mng_pass_thru(hw)) {
1329 /* Disable PCS to turn off link */
1330 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1331 reg &= ~E1000_PCS_CFG_PCS_EN;
1332 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1334 /* shutdown the laser */
1335 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1336 reg |= E1000_CTRL_EXT_SDP3_DATA;
1337 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1339 /* flush the write to verify completion */
1340 E1000_WRITE_FLUSH(hw);
1348 * e1000_reset_hw_82575 - Reset hardware
1349 * @hw: pointer to the HW structure
1351 * This resets the hardware into a known state.
1353 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1358 DEBUGFUNC("e1000_reset_hw_82575");
1361 * Prevent the PCI-E bus from sticking if there is no TLP connection
1362 * on the last TLP read/write transaction when MAC is reset.
1364 ret_val = e1000_disable_pcie_master_generic(hw);
1366 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1368 /* set the completion timeout for interface */
1369 ret_val = e1000_set_pcie_completion_timeout(hw);
1371 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1373 DEBUGOUT("Masking off all interrupts\n");
1374 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1376 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1377 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1378 E1000_WRITE_FLUSH(hw);
1382 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1384 DEBUGOUT("Issuing a global reset to MAC\n");
1385 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1387 ret_val = e1000_get_auto_rd_done_generic(hw);
1390 * When auto config read does not complete, do not
1391 * return with an error. This can happen in situations
1392 * where there is no eeprom and prevents getting link.
1394 DEBUGOUT("Auto Read Done did not complete\n");
1397 /* If EEPROM is not present, run manual init scripts */
1398 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1399 e1000_reset_init_script_82575(hw);
1401 /* Clear any pending interrupt events. */
1402 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1403 E1000_READ_REG(hw, E1000_ICR);
1405 /* Install any alternate MAC address into RAR0 */
1406 ret_val = e1000_check_alt_mac_addr_generic(hw);
1412 * e1000_init_hw_82575 - Initialize hardware
1413 * @hw: pointer to the HW structure
1415 * This inits the hardware readying it for operation.
1417 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)
1419 struct e1000_mac_info *mac = &hw->mac;
1422 DEBUGFUNC("e1000_init_hw_82575");
1424 /* Initialize identification LED */
1425 ret_val = mac->ops.id_led_init(hw);
1427 DEBUGOUT("Error initializing identification LED\n");
1428 /* This is not fatal and we should not stop init due to this */
1431 /* Disabling VLAN filtering */
1432 DEBUGOUT("Initializing the IEEE VLAN\n");
1433 mac->ops.clear_vfta(hw);
1435 ret_val = e1000_init_hw_base(hw);
1437 /* Set the default MTU size */
1438 hw->dev_spec._82575.mtu = 1500;
1440 /* Clear all of the statistics registers (clear on read). It is
1441 * important that we do this after we have tried to establish link
1442 * because the symbol error count will increment wildly if there
1445 e1000_clear_hw_cntrs_82575(hw);
1450 * e1000_setup_copper_link_82575 - Configure copper link settings
1451 * @hw: pointer to the HW structure
1453 * Configures the link for auto-neg or forced speed and duplex. Then we check
1454 * for link, once link is established calls to configure collision distance
1455 * and flow control are called.
1457 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1463 DEBUGFUNC("e1000_setup_copper_link_82575");
1465 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1466 ctrl |= E1000_CTRL_SLU;
1467 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1468 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1470 /* Clear Go Link Disconnect bit on supported devices */
1471 switch (hw->mac.type) {
1476 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1477 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1478 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1484 ret_val = e1000_setup_serdes_link_82575(hw);
1488 if (e1000_sgmii_active_82575(hw)) {
1489 /* allow time for SFP cage time to power up phy */
1492 ret_val = hw->phy.ops.reset(hw);
1494 DEBUGOUT("Error resetting the PHY.\n");
1498 switch (hw->phy.type) {
1499 case e1000_phy_i210:
1502 switch (hw->phy.id) {
1503 case I347AT4_E_PHY_ID:
1505 case M88E1112_E_PHY_ID:
1507 case M88E1340M_E_PHY_ID:
1509 case M88E1543_E_PHY_ID:
1511 case M88E1512_E_PHY_ID:
1515 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1518 ret_val = e1000_copper_link_setup_m88(hw);
1522 case e1000_phy_igp_3:
1523 ret_val = e1000_copper_link_setup_igp(hw);
1525 case e1000_phy_82580:
1526 ret_val = e1000_copper_link_setup_82577(hw);
1529 ret_val = -E1000_ERR_PHY;
1536 ret_val = e1000_setup_copper_link_generic(hw);
1542 * e1000_setup_serdes_link_82575 - Setup link for serdes
1543 * @hw: pointer to the HW structure
1545 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1546 * used on copper connections where the serialized gigabit media independent
1547 * interface (sgmii), or serdes fiber is being used. Configures the link
1548 * for auto-negotiation or forces speed/duplex.
1550 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1552 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1554 s32 ret_val = E1000_SUCCESS;
1557 DEBUGFUNC("e1000_setup_serdes_link_82575");
1559 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1560 !e1000_sgmii_active_82575(hw))
1564 * On the 82575, SerDes loopback mode persists until it is
1565 * explicitly turned off or a power cycle is performed. A read to
1566 * the register does not indicate its status. Therefore, we ensure
1567 * loopback mode is disabled during initialization.
1569 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1571 /* power on the sfp cage if present */
1572 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1573 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1574 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1576 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1577 ctrl_reg |= E1000_CTRL_SLU;
1579 /* set both sw defined pins on 82575/82576*/
1580 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1581 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1583 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1585 /* default pcs_autoneg to the same setting as mac autoneg */
1586 pcs_autoneg = hw->mac.autoneg;
1588 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1589 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1590 /* sgmii mode lets the phy handle forcing speed/duplex */
1592 /* autoneg time out should be disabled for SGMII mode */
1593 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1595 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1596 /* disable PCS autoneg and support parallel detect only */
1597 pcs_autoneg = false;
1600 if (hw->mac.type == e1000_82575 ||
1601 hw->mac.type == e1000_82576) {
1602 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1604 DEBUGOUT("NVM Read Error\n");
1608 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1609 pcs_autoneg = false;
1613 * non-SGMII modes only supports a speed of 1000/Full for the
1614 * link so it is best to just force the MAC and let the pcs
1615 * link either autoneg or be forced to 1000/Full
1617 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1618 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1620 /* set speed of 1000/Full if speed/duplex is forced */
1621 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1625 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1628 * New SerDes mode allows for forcing speed or autonegotiating speed
1629 * at 1gb. Autoneg should be default set by most drivers. This is the
1630 * mode that will be compatible with older link partners and switches.
1631 * However, both are supported by the hardware and some drivers/tools.
1633 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1634 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1637 /* Set PCS register for autoneg */
1638 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1639 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1641 /* Disable force flow control for autoneg */
1642 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1644 /* Configure flow control advertisement for autoneg */
1645 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1646 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1648 switch (hw->fc.requested_mode) {
1650 case e1000_fc_rx_pause:
1651 anadv_reg |= E1000_TXCW_ASM_DIR;
1652 anadv_reg |= E1000_TXCW_PAUSE;
1654 case e1000_fc_tx_pause:
1655 anadv_reg |= E1000_TXCW_ASM_DIR;
1661 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1663 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1665 /* Set PCS register for forced link */
1666 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1668 /* Force flow control for forced link */
1669 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1671 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1674 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1676 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1677 e1000_force_mac_fc_generic(hw);
1683 * e1000_get_media_type_82575 - derives current media type.
1684 * @hw: pointer to the HW structure
1686 * The media type is chosen reflecting few settings.
1687 * The following are taken into account:
1688 * - link mode set in the current port Init Control Word #3
1689 * - current link mode settings in CSR register
1690 * - MDIO vs. I2C PHY control interface chosen
1691 * - SFP module media type
1693 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1695 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1696 s32 ret_val = E1000_SUCCESS;
1700 /* Set internal phy as default */
1701 dev_spec->sgmii_active = false;
1702 dev_spec->module_plugged = false;
1704 /* Get CSR setting */
1705 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1707 /* extract link mode setting */
1708 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1710 switch (link_mode) {
1711 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1712 hw->phy.media_type = e1000_media_type_internal_serdes;
1714 case E1000_CTRL_EXT_LINK_MODE_GMII:
1715 hw->phy.media_type = e1000_media_type_copper;
1717 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1718 /* Get phy control interface type set (MDIO vs. I2C)*/
1719 if (e1000_sgmii_uses_mdio_82575(hw)) {
1720 hw->phy.media_type = e1000_media_type_copper;
1721 dev_spec->sgmii_active = true;
1724 /* Fall through for I2C based SGMII */
1725 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1726 /* read media type from SFP EEPROM */
1727 ret_val = e1000_set_sfp_media_type_82575(hw);
1728 if ((ret_val != E1000_SUCCESS) ||
1729 (hw->phy.media_type == e1000_media_type_unknown)) {
1731 * If media type was not identified then return media
1732 * type defined by the CTRL_EXT settings.
1734 hw->phy.media_type = e1000_media_type_internal_serdes;
1736 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1737 hw->phy.media_type = e1000_media_type_copper;
1738 dev_spec->sgmii_active = true;
1744 /* do not change link mode for 100BaseFX */
1745 if (dev_spec->eth_flags.e100_base_fx)
1748 /* change current link mode setting */
1749 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1751 if (hw->phy.media_type == e1000_media_type_copper)
1752 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1754 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1756 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1765 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1766 * @hw: pointer to the HW structure
1768 * The media type is chosen based on SFP module.
1769 * compatibility flags retrieved from SFP ID EEPROM.
1771 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1773 s32 ret_val = E1000_ERR_CONFIG;
1775 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1776 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1777 u8 tranceiver_type = 0;
1780 /* Turn I2C interface ON and power on sfp cage */
1781 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1782 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1783 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1785 E1000_WRITE_FLUSH(hw);
1787 /* Read SFP module data */
1789 ret_val = e1000_read_sfp_data_byte(hw,
1790 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1792 if (ret_val == E1000_SUCCESS)
1797 if (ret_val != E1000_SUCCESS)
1800 ret_val = e1000_read_sfp_data_byte(hw,
1801 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1803 if (ret_val != E1000_SUCCESS)
1806 /* Check if there is some SFP module plugged and powered */
1807 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1808 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1809 dev_spec->module_plugged = true;
1810 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1811 hw->phy.media_type = e1000_media_type_internal_serdes;
1812 } else if (eth_flags->e100_base_fx) {
1813 dev_spec->sgmii_active = true;
1814 hw->phy.media_type = e1000_media_type_internal_serdes;
1815 } else if (eth_flags->e1000_base_t) {
1816 dev_spec->sgmii_active = true;
1817 hw->phy.media_type = e1000_media_type_copper;
1819 hw->phy.media_type = e1000_media_type_unknown;
1820 DEBUGOUT("PHY module has not been recognized\n");
1824 hw->phy.media_type = e1000_media_type_unknown;
1826 ret_val = E1000_SUCCESS;
1828 /* Restore I2C interface setting */
1829 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1834 * e1000_valid_led_default_82575 - Verify a valid default LED config
1835 * @hw: pointer to the HW structure
1836 * @data: pointer to the NVM (EEPROM)
1838 * Read the EEPROM for the current default LED configuration. If the
1839 * LED configuration is not valid, set to a valid LED configuration.
1841 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1845 DEBUGFUNC("e1000_valid_led_default_82575");
1847 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1849 DEBUGOUT("NVM Read Error\n");
1853 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1854 switch (hw->phy.media_type) {
1855 case e1000_media_type_internal_serdes:
1856 *data = ID_LED_DEFAULT_82575_SERDES;
1858 case e1000_media_type_copper:
1860 *data = ID_LED_DEFAULT;
1869 * e1000_sgmii_active_82575 - Return sgmii state
1870 * @hw: pointer to the HW structure
1872 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1873 * which can be enabled for use in the embedded applications. Simply
1874 * return the current state of the sgmii interface.
1876 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1878 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1879 return dev_spec->sgmii_active;
1883 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1884 * @hw: pointer to the HW structure
1886 * Inits recommended HW defaults after a reset when there is no EEPROM
1887 * detected. This is only for the 82575.
1889 s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1891 DEBUGFUNC("e1000_reset_init_script_82575");
1893 if (hw->mac.type == e1000_82575) {
1894 DEBUGOUT("Running reset init script for 82575\n");
1895 /* SerDes configuration via SERDESCTRL */
1896 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1897 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1898 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1899 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1901 /* CCM configuration via CCMCTL register */
1902 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1903 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1905 /* PCIe lanes configuration */
1906 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1907 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1908 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1909 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1911 /* PCIe PLL Configuration */
1912 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1913 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1914 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1917 return E1000_SUCCESS;
1921 * e1000_read_mac_addr_82575 - Read device MAC address
1922 * @hw: pointer to the HW structure
1924 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1928 DEBUGFUNC("e1000_read_mac_addr_82575");
1931 * If there's an alternate MAC address place it in RAR0
1932 * so that it will override the Si installed default perm
1935 ret_val = e1000_check_alt_mac_addr_generic(hw);
1939 ret_val = e1000_read_mac_addr_generic(hw);
1946 * e1000_config_collision_dist_82575 - Configure collision distance
1947 * @hw: pointer to the HW structure
1949 * Configures the collision distance to the default value and is used
1950 * during link setup.
1952 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1956 DEBUGFUNC("e1000_config_collision_dist_82575");
1958 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1960 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1961 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1963 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1964 E1000_WRITE_FLUSH(hw);
1968 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1969 * @hw: pointer to the HW structure
1971 * Clears the hardware counters by reading the counter registers.
1973 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1975 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1977 e1000_clear_hw_cntrs_base_generic(hw);
1979 E1000_READ_REG(hw, E1000_PRC64);
1980 E1000_READ_REG(hw, E1000_PRC127);
1981 E1000_READ_REG(hw, E1000_PRC255);
1982 E1000_READ_REG(hw, E1000_PRC511);
1983 E1000_READ_REG(hw, E1000_PRC1023);
1984 E1000_READ_REG(hw, E1000_PRC1522);
1985 E1000_READ_REG(hw, E1000_PTC64);
1986 E1000_READ_REG(hw, E1000_PTC127);
1987 E1000_READ_REG(hw, E1000_PTC255);
1988 E1000_READ_REG(hw, E1000_PTC511);
1989 E1000_READ_REG(hw, E1000_PTC1023);
1990 E1000_READ_REG(hw, E1000_PTC1522);
1992 E1000_READ_REG(hw, E1000_ALGNERRC);
1993 E1000_READ_REG(hw, E1000_RXERRC);
1994 E1000_READ_REG(hw, E1000_TNCRS);
1995 E1000_READ_REG(hw, E1000_CEXTERR);
1996 E1000_READ_REG(hw, E1000_TSCTC);
1997 E1000_READ_REG(hw, E1000_TSCTFC);
1999 E1000_READ_REG(hw, E1000_MGTPRC);
2000 E1000_READ_REG(hw, E1000_MGTPDC);
2001 E1000_READ_REG(hw, E1000_MGTPTC);
2003 E1000_READ_REG(hw, E1000_IAC);
2004 E1000_READ_REG(hw, E1000_ICRXOC);
2006 E1000_READ_REG(hw, E1000_ICRXPTC);
2007 E1000_READ_REG(hw, E1000_ICRXATC);
2008 E1000_READ_REG(hw, E1000_ICTXPTC);
2009 E1000_READ_REG(hw, E1000_ICTXATC);
2010 E1000_READ_REG(hw, E1000_ICTXQEC);
2011 E1000_READ_REG(hw, E1000_ICTXQMTC);
2012 E1000_READ_REG(hw, E1000_ICRXDMTC);
2014 E1000_READ_REG(hw, E1000_CBTMPC);
2015 E1000_READ_REG(hw, E1000_HTDPMC);
2016 E1000_READ_REG(hw, E1000_CBRMPC);
2017 E1000_READ_REG(hw, E1000_RPTHC);
2018 E1000_READ_REG(hw, E1000_HGPTC);
2019 E1000_READ_REG(hw, E1000_HTCBDPC);
2020 E1000_READ_REG(hw, E1000_HGORCL);
2021 E1000_READ_REG(hw, E1000_HGORCH);
2022 E1000_READ_REG(hw, E1000_HGOTCL);
2023 E1000_READ_REG(hw, E1000_HGOTCH);
2024 E1000_READ_REG(hw, E1000_LENERRS);
2026 /* This register should not be read in copper configurations */
2027 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2028 e1000_sgmii_active_82575(hw))
2029 E1000_READ_REG(hw, E1000_SCVPC);
2033 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2034 * @hw: pointer to the HW structure
2036 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2037 * however the hardware default for these parts is 500us to 1ms which is less
2038 * than the 10ms recommended by the pci-e spec. To address this we need to
2039 * increase the value to either 10ms to 200ms for capability version 1 config,
2040 * or 16ms to 55ms for version 2.
2042 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2044 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2045 s32 ret_val = E1000_SUCCESS;
2048 /* only take action if timeout value is defaulted to 0 */
2049 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2053 * if capababilities version is type 1 we can write the
2054 * timeout of 10ms to 200ms through the GCR register
2056 if (!(gcr & E1000_GCR_CAP_VER2)) {
2057 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2062 * for version 2 capabilities we need to write the config space
2063 * directly in order to set the completion timeout value for
2066 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2071 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2073 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2076 /* disable completion timeout resend */
2077 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2079 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2084 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2085 * @hw: pointer to the hardware struct
2086 * @enable: state to enter, either enabled or disabled
2087 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2089 * enables/disables L2 switch anti-spoofing functionality.
2091 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2093 u32 reg_val, reg_offset;
2095 switch (hw->mac.type) {
2097 reg_offset = E1000_DTXSWC;
2101 reg_offset = E1000_TXSWC;
2107 reg_val = E1000_READ_REG(hw, reg_offset);
2109 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2110 E1000_DTXSWC_VLAN_SPOOF_MASK);
2111 /* The PF can spoof - it has to in order to
2112 * support emulation mode NICs
2114 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2116 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2117 E1000_DTXSWC_VLAN_SPOOF_MASK);
2119 E1000_WRITE_REG(hw, reg_offset, reg_val);
2123 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2124 * @hw: pointer to the hardware struct
2125 * @enable: state to enter, either enabled or disabled
2127 * enables/disables L2 switch loopback functionality.
2129 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2133 switch (hw->mac.type) {
2135 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2137 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2139 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2140 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2144 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2146 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2148 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2149 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2152 /* Currently no other hardware supports loopback */
2160 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2161 * @hw: pointer to the hardware struct
2162 * @enable: state to enter, either enabled or disabled
2164 * enables/disables replication of packets across multiple pools.
2166 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2168 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2171 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2173 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2175 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2179 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2180 * @hw: pointer to the HW structure
2181 * @offset: register offset to be read
2182 * @data: pointer to the read data
2184 * Reads the MDI control register in the PHY at offset and stores the
2185 * information read to data.
2187 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2191 DEBUGFUNC("e1000_read_phy_reg_82580");
2193 ret_val = hw->phy.ops.acquire(hw);
2197 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2199 hw->phy.ops.release(hw);
2206 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2207 * @hw: pointer to the HW structure
2208 * @offset: register offset to write to
2209 * @data: data to write to register at offset
2211 * Writes data to MDI control register in the PHY at offset.
2213 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2217 DEBUGFUNC("e1000_write_phy_reg_82580");
2219 ret_val = hw->phy.ops.acquire(hw);
2223 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2225 hw->phy.ops.release(hw);
2232 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2233 * @hw: pointer to the HW structure
2235 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2236 * the values found in the EEPROM. This addresses an issue in which these
2237 * bits are not restored from EEPROM after reset.
2239 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2241 s32 ret_val = E1000_SUCCESS;
2245 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2247 if (hw->mac.type != e1000_82580)
2249 if (!e1000_sgmii_active_82575(hw))
2252 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2253 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2256 DEBUGOUT("NVM Read Error\n");
2260 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2261 if (nvm_data & NVM_WORD24_EXT_MDIO)
2262 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2263 if (nvm_data & NVM_WORD24_COM_MDIO)
2264 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2265 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2271 * e1000_reset_hw_82580 - Reset hardware
2272 * @hw: pointer to the HW structure
2274 * This resets function or entire device (all ports, etc.)
2277 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2279 s32 ret_val = E1000_SUCCESS;
2280 /* BH SW mailbox bit in SW_FW_SYNC */
2281 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2283 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2285 DEBUGFUNC("e1000_reset_hw_82580");
2287 hw->dev_spec._82575.global_device_reset = false;
2289 /* 82580 does not reliably do global_device_reset due to hw errata */
2290 if (hw->mac.type == e1000_82580)
2291 global_device_reset = false;
2293 /* Get current control state. */
2294 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2297 * Prevent the PCI-E bus from sticking if there is no TLP connection
2298 * on the last TLP read/write transaction when MAC is reset.
2300 ret_val = e1000_disable_pcie_master_generic(hw);
2302 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2304 DEBUGOUT("Masking off all interrupts\n");
2305 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2306 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2307 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2308 E1000_WRITE_FLUSH(hw);
2312 /* Determine whether or not a global dev reset is requested */
2313 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2315 global_device_reset = false;
2317 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2318 E1000_STAT_DEV_RST_SET))
2319 ctrl |= E1000_CTRL_DEV_RST;
2321 ctrl |= E1000_CTRL_RST;
2323 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2325 switch (hw->device_id) {
2326 case E1000_DEV_ID_DH89XXCC_SGMII:
2329 E1000_WRITE_FLUSH(hw);
2333 /* Add delay to insure DEV_RST or RST has time to complete */
2336 ret_val = e1000_get_auto_rd_done_generic(hw);
2339 * When auto config read does not complete, do not
2340 * return with an error. This can happen in situations
2341 * where there is no eeprom and prevents getting link.
2343 DEBUGOUT("Auto Read Done did not complete\n");
2346 /* clear global device reset status bit */
2347 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2349 /* Clear any pending interrupt events. */
2350 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2351 E1000_READ_REG(hw, E1000_ICR);
2353 ret_val = e1000_reset_mdicnfg_82580(hw);
2355 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2357 /* Install any alternate MAC address into RAR0 */
2358 ret_val = e1000_check_alt_mac_addr_generic(hw);
2360 /* Release semaphore */
2361 if (global_device_reset)
2362 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2368 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2369 * @data: data received by reading RXPBS register
2371 * The 82580 uses a table based approach for packet buffer allocation sizes.
2372 * This function converts the retrieved value into the correct table value
2373 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2374 * 0x0 36 72 144 1 2 4 8 16
2375 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2377 u16 e1000_rxpbs_adjust_82580(u32 data)
2381 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2382 ret_val = e1000_82580_rxpbs_table[data];
2388 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2390 * @hw: pointer to the HW structure
2391 * @offset: offset in words of the checksum protected region
2393 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2394 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2396 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2398 s32 ret_val = E1000_SUCCESS;
2402 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2404 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2405 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2407 DEBUGOUT("NVM Read Error\n");
2410 checksum += nvm_data;
2413 if (checksum != (u16) NVM_SUM) {
2414 DEBUGOUT("NVM Checksum Invalid\n");
2415 ret_val = -E1000_ERR_NVM;
2424 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2426 * @hw: pointer to the HW structure
2427 * @offset: offset in words of the checksum protected region
2429 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2430 * up to the checksum. Then calculates the EEPROM checksum and writes the
2431 * value to the EEPROM.
2433 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2439 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2441 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2442 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2444 DEBUGOUT("NVM Read Error while updating checksum.\n");
2447 checksum += nvm_data;
2449 checksum = (u16) NVM_SUM - checksum;
2450 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2453 DEBUGOUT("NVM Write Error while updating checksum.\n");
2460 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2461 * @hw: pointer to the HW structure
2463 * Calculates the EEPROM section checksum by reading/adding each word of
2464 * the EEPROM and then verifies that the sum of the EEPROM is
2467 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2470 u16 eeprom_regions_count = 1;
2474 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2476 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2478 DEBUGOUT("NVM Read Error\n");
2482 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2483 /* if chekcsums compatibility bit is set validate checksums
2484 * for all 4 ports. */
2485 eeprom_regions_count = 4;
2488 for (j = 0; j < eeprom_regions_count; j++) {
2489 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2490 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2492 if (ret_val != E1000_SUCCESS)
2501 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2502 * @hw: pointer to the HW structure
2504 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2505 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2506 * checksum and writes the value to the EEPROM.
2508 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2514 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2516 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2518 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2522 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2523 /* set compatibility bit to validate checksums appropriately */
2524 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2525 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2528 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2533 for (j = 0; j < 4; j++) {
2534 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2535 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2545 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2546 * @hw: pointer to the HW structure
2548 * Calculates the EEPROM section checksum by reading/adding each word of
2549 * the EEPROM and then verifies that the sum of the EEPROM is
2552 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2554 s32 ret_val = E1000_SUCCESS;
2558 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2560 for (j = 0; j < 4; j++) {
2561 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2562 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2564 if (ret_val != E1000_SUCCESS)
2573 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2574 * @hw: pointer to the HW structure
2576 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2577 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2578 * checksum and writes the value to the EEPROM.
2580 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2582 s32 ret_val = E1000_SUCCESS;
2586 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2588 for (j = 0; j < 4; j++) {
2589 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2590 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2591 if (ret_val != E1000_SUCCESS)
2600 * __e1000_access_emi_reg - Read/write EMI register
2601 * @hw: pointer to the HW structure
2602 * @address: EMI address to program
2603 * @data: pointer to value to read/write from/to the EMI address
2604 * @read: boolean flag to indicate read or write
2606 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2607 u16 *data, bool read)
2611 DEBUGFUNC("__e1000_access_emi_reg");
2613 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2618 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2620 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2626 * e1000_read_emi_reg - Read Extended Management Interface register
2627 * @hw: pointer to the HW structure
2628 * @addr: EMI address to program
2629 * @data: value to be read from the EMI address
2631 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2633 DEBUGFUNC("e1000_read_emi_reg");
2635 return __e1000_access_emi_reg(hw, addr, data, true);
2639 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2640 * @hw: pointer to the HW structure
2642 * Initialize Marvell 1512 to work correctly with Avoton.
2644 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2646 struct e1000_phy_info *phy = &hw->phy;
2647 s32 ret_val = E1000_SUCCESS;
2649 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2651 /* Check if this is correct PHY. */
2652 if (phy->id != M88E1512_E_PHY_ID)
2655 /* Switch to PHY page 0xFF. */
2656 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2660 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2664 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2668 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2672 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2676 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2680 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2684 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2688 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2692 /* Switch to PHY page 0xFB. */
2693 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2697 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2701 /* Switch to PHY page 0x12. */
2702 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2706 /* Change mode to SGMII-to-Copper */
2707 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2711 /* Return the PHY to page 0. */
2712 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2716 ret_val = phy->ops.commit(hw);
2718 DEBUGOUT("Error committing the PHY changes\n");
2728 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2729 * @hw: pointer to the HW structure
2731 * Initialize Marvell 1543 to work correctly with Avoton.
2733 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2735 struct e1000_phy_info *phy = &hw->phy;
2736 s32 ret_val = E1000_SUCCESS;
2738 DEBUGFUNC("e1000_initialize_M88E1543_phy");
2740 /* Check if this is correct PHY. */
2741 if (phy->id != M88E1543_E_PHY_ID)
2744 /* Switch to PHY page 0xFF. */
2745 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2749 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2753 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2757 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2761 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2765 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2769 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2773 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2777 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2781 /* Switch to PHY page 0xFB. */
2782 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2786 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2790 /* Switch to PHY page 0x12. */
2791 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2795 /* Change mode to SGMII-to-Copper */
2796 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2800 /* Switch to PHY page 1. */
2801 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2805 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2806 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2810 /* Return the PHY to page 0. */
2811 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2815 ret_val = phy->ops.commit(hw);
2817 DEBUGOUT("Error committing the PHY changes\n");
2827 * e1000_set_eee_i350 - Enable/disable EEE support
2828 * @hw: pointer to the HW structure
2829 * @adv1G: boolean flag enabling 1G EEE advertisement
2830 * @adv100M: boolean flag enabling 100M EEE advertisement
2832 * Enable/disable EEE based on setting in dev_spec structure.
2835 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2839 DEBUGFUNC("e1000_set_eee_i350");
2841 if ((hw->mac.type < e1000_i350) ||
2842 (hw->phy.media_type != e1000_media_type_copper))
2844 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2845 eeer = E1000_READ_REG(hw, E1000_EEER);
2847 /* enable or disable per user setting */
2848 if (!(hw->dev_spec._82575.eee_disable)) {
2849 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2852 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2854 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2857 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2859 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2861 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2864 /* This bit should not be set in normal operation. */
2865 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2866 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2868 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2869 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2872 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2873 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2874 E1000_READ_REG(hw, E1000_IPCNFG);
2875 E1000_READ_REG(hw, E1000_EEER);
2878 return E1000_SUCCESS;
2882 * e1000_set_eee_i354 - Enable/disable EEE support
2883 * @hw: pointer to the HW structure
2884 * @adv1G: boolean flag enabling 1G EEE advertisement
2885 * @adv100M: boolean flag enabling 100M EEE advertisement
2887 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2890 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2892 struct e1000_phy_info *phy = &hw->phy;
2893 s32 ret_val = E1000_SUCCESS;
2896 DEBUGFUNC("e1000_set_eee_i354");
2898 if ((hw->phy.media_type != e1000_media_type_copper) ||
2899 ((phy->id != M88E1543_E_PHY_ID) &&
2900 (phy->id != M88E1512_E_PHY_ID)))
2903 if (!hw->dev_spec._82575.eee_disable) {
2904 /* Switch to PHY page 18. */
2905 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2909 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2914 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2915 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2920 /* Return the PHY to page 0. */
2921 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2925 /* Turn on EEE advertisement. */
2926 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2927 E1000_EEE_ADV_DEV_I354,
2933 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2935 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2938 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2940 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2942 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2943 E1000_EEE_ADV_DEV_I354,
2946 /* Turn off EEE advertisement. */
2947 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2948 E1000_EEE_ADV_DEV_I354,
2953 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2954 E1000_EEE_ADV_1000_SUPPORTED);
2955 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2956 E1000_EEE_ADV_DEV_I354,
2965 * e1000_get_eee_status_i354 - Get EEE status
2966 * @hw: pointer to the HW structure
2967 * @status: EEE status
2969 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2972 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2974 struct e1000_phy_info *phy = &hw->phy;
2975 s32 ret_val = E1000_SUCCESS;
2978 DEBUGFUNC("e1000_get_eee_status_i354");
2980 /* Check if EEE is supported on this device. */
2981 if ((hw->phy.media_type != e1000_media_type_copper) ||
2982 ((phy->id != M88E1543_E_PHY_ID) &&
2983 (phy->id != M88E1512_E_PHY_ID)))
2986 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2987 E1000_PCS_STATUS_DEV_I354,
2992 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2993 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2999 /* Due to a hw errata, if the host tries to configure the VFTA register
3000 * while performing queries from the BMC or DMA, then the VFTA in some
3001 * cases won't be written.
3005 * e1000_clear_vfta_i350 - Clear VLAN filter table
3006 * @hw: pointer to the HW structure
3008 * Clears the register array which contains the VLAN filter table by
3009 * setting all the values to 0.
3011 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3016 DEBUGFUNC("e1000_clear_vfta_350");
3018 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3019 for (i = 0; i < 10; i++)
3020 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3022 E1000_WRITE_FLUSH(hw);
3027 * e1000_write_vfta_i350 - Write value to VLAN filter table
3028 * @hw: pointer to the HW structure
3029 * @offset: register offset in VLAN filter table
3030 * @value: register value written to VLAN filter table
3032 * Writes value at the given offset in the register array which stores
3033 * the VLAN filter table.
3035 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3039 DEBUGFUNC("e1000_write_vfta_350");
3041 for (i = 0; i < 10; i++)
3042 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3044 E1000_WRITE_FLUSH(hw);
3049 * e1000_set_i2c_bb - Enable I2C bit-bang
3050 * @hw: pointer to the HW structure
3052 * Enable I2C bit-bang interface
3055 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3057 s32 ret_val = E1000_SUCCESS;
3058 u32 ctrl_ext, i2cparams;
3060 DEBUGFUNC("e1000_set_i2c_bb");
3062 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3063 ctrl_ext |= E1000_CTRL_I2C_ENA;
3064 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3065 E1000_WRITE_FLUSH(hw);
3067 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3068 i2cparams |= E1000_I2CBB_EN;
3069 i2cparams |= E1000_I2C_DATA_OE_N;
3070 i2cparams |= E1000_I2C_CLK_OE_N;
3071 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3072 E1000_WRITE_FLUSH(hw);
3078 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3079 * @hw: pointer to hardware structure
3080 * @byte_offset: byte offset to read
3081 * @dev_addr: device address
3084 * Performs byte read operation over I2C interface at
3085 * a specified device address.
3087 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3088 u8 dev_addr, u8 *data)
3090 s32 status = E1000_SUCCESS;
3097 DEBUGFUNC("e1000_read_i2c_byte_generic");
3099 swfw_mask = E1000_SWFW_PHY0_SM;
3102 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3104 status = E1000_ERR_SWFW_SYNC;
3108 e1000_i2c_start(hw);
3110 /* Device Address and write indication */
3111 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3112 if (status != E1000_SUCCESS)
3115 status = e1000_get_i2c_ack(hw);
3116 if (status != E1000_SUCCESS)
3119 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3120 if (status != E1000_SUCCESS)
3123 status = e1000_get_i2c_ack(hw);
3124 if (status != E1000_SUCCESS)
3127 e1000_i2c_start(hw);
3129 /* Device Address and read indication */
3130 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3131 if (status != E1000_SUCCESS)
3134 status = e1000_get_i2c_ack(hw);
3135 if (status != E1000_SUCCESS)
3138 e1000_clock_in_i2c_byte(hw, data);
3140 status = e1000_clock_out_i2c_bit(hw, nack);
3141 if (status != E1000_SUCCESS)
3148 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3150 e1000_i2c_bus_clear(hw);
3152 if (retry < max_retry)
3153 DEBUGOUT("I2C byte read error - Retrying.\n");
3155 DEBUGOUT("I2C byte read error.\n");
3157 } while (retry < max_retry);
3159 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3167 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3168 * @hw: pointer to hardware structure
3169 * @byte_offset: byte offset to write
3170 * @dev_addr: device address
3171 * @data: value to write
3173 * Performs byte write operation over I2C interface at
3174 * a specified device address.
3176 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3177 u8 dev_addr, u8 data)
3179 s32 status = E1000_SUCCESS;
3184 DEBUGFUNC("e1000_write_i2c_byte_generic");
3186 swfw_mask = E1000_SWFW_PHY0_SM;
3188 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3189 status = E1000_ERR_SWFW_SYNC;
3190 goto write_byte_out;
3194 e1000_i2c_start(hw);
3196 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3197 if (status != E1000_SUCCESS)
3200 status = e1000_get_i2c_ack(hw);
3201 if (status != E1000_SUCCESS)
3204 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3205 if (status != E1000_SUCCESS)
3208 status = e1000_get_i2c_ack(hw);
3209 if (status != E1000_SUCCESS)
3212 status = e1000_clock_out_i2c_byte(hw, data);
3213 if (status != E1000_SUCCESS)
3216 status = e1000_get_i2c_ack(hw);
3217 if (status != E1000_SUCCESS)
3224 e1000_i2c_bus_clear(hw);
3226 if (retry < max_retry)
3227 DEBUGOUT("I2C byte write error - Retrying.\n");
3229 DEBUGOUT("I2C byte write error.\n");
3230 } while (retry < max_retry);
3232 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3240 * e1000_i2c_start - Sets I2C start condition
3241 * @hw: pointer to hardware structure
3243 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3245 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3247 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3249 DEBUGFUNC("e1000_i2c_start");
3251 /* Start condition must begin with data and clock high */
3252 e1000_set_i2c_data(hw, &i2cctl, 1);
3253 e1000_raise_i2c_clk(hw, &i2cctl);
3255 /* Setup time for start condition (4.7us) */
3256 usec_delay(E1000_I2C_T_SU_STA);
3258 e1000_set_i2c_data(hw, &i2cctl, 0);
3260 /* Hold time for start condition (4us) */
3261 usec_delay(E1000_I2C_T_HD_STA);
3263 e1000_lower_i2c_clk(hw, &i2cctl);
3265 /* Minimum low period of clock is 4.7 us */
3266 usec_delay(E1000_I2C_T_LOW);
3271 * e1000_i2c_stop - Sets I2C stop condition
3272 * @hw: pointer to hardware structure
3274 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3276 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3278 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3280 DEBUGFUNC("e1000_i2c_stop");
3282 /* Stop condition must begin with data low and clock high */
3283 e1000_set_i2c_data(hw, &i2cctl, 0);
3284 e1000_raise_i2c_clk(hw, &i2cctl);
3286 /* Setup time for stop condition (4us) */
3287 usec_delay(E1000_I2C_T_SU_STO);
3289 e1000_set_i2c_data(hw, &i2cctl, 1);
3291 /* bus free time between stop and start (4.7us)*/
3292 usec_delay(E1000_I2C_T_BUF);
3296 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3297 * @hw: pointer to hardware structure
3298 * @data: data byte to clock in
3300 * Clocks in one byte data via I2C data/clock
3302 STATIC void e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3307 DEBUGFUNC("e1000_clock_in_i2c_byte");
3310 for (i = 7; i >= 0; i--) {
3311 e1000_clock_in_i2c_bit(hw, &bit);
3317 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3318 * @hw: pointer to hardware structure
3319 * @data: data byte clocked out
3321 * Clocks out one byte data via I2C data/clock
3323 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3325 s32 status = E1000_SUCCESS;
3330 DEBUGFUNC("e1000_clock_out_i2c_byte");
3332 for (i = 7; i >= 0; i--) {
3333 bit = (data >> i) & 0x1;
3334 status = e1000_clock_out_i2c_bit(hw, bit);
3336 if (status != E1000_SUCCESS)
3340 /* Release SDA line (set high) */
3341 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3343 i2cctl |= E1000_I2C_DATA_OE_N;
3344 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3345 E1000_WRITE_FLUSH(hw);
3351 * e1000_get_i2c_ack - Polls for I2C ACK
3352 * @hw: pointer to hardware structure
3354 * Clocks in/out one bit via I2C data/clock
3356 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3358 s32 status = E1000_SUCCESS;
3360 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3364 DEBUGFUNC("e1000_get_i2c_ack");
3366 e1000_raise_i2c_clk(hw, &i2cctl);
3368 /* Minimum high period of clock is 4us */
3369 usec_delay(E1000_I2C_T_HIGH);
3371 /* Wait until SCL returns high */
3372 for (i = 0; i < timeout; i++) {
3374 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3375 if (i2cctl & E1000_I2C_CLK_IN)
3378 if (!(i2cctl & E1000_I2C_CLK_IN))
3379 return E1000_ERR_I2C;
3381 ack = e1000_get_i2c_data(&i2cctl);
3383 DEBUGOUT("I2C ack was not received.\n");
3384 status = E1000_ERR_I2C;
3387 e1000_lower_i2c_clk(hw, &i2cctl);
3389 /* Minimum low period of clock is 4.7 us */
3390 usec_delay(E1000_I2C_T_LOW);
3396 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3397 * @hw: pointer to hardware structure
3398 * @data: read data value
3400 * Clocks in one bit via I2C data/clock
3402 STATIC void e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3404 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3406 DEBUGFUNC("e1000_clock_in_i2c_bit");
3408 e1000_raise_i2c_clk(hw, &i2cctl);
3410 /* Minimum high period of clock is 4us */
3411 usec_delay(E1000_I2C_T_HIGH);
3413 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3414 *data = e1000_get_i2c_data(&i2cctl);
3416 e1000_lower_i2c_clk(hw, &i2cctl);
3418 /* Minimum low period of clock is 4.7 us */
3419 usec_delay(E1000_I2C_T_LOW);
3423 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3424 * @hw: pointer to hardware structure
3425 * @data: data value to write
3427 * Clocks out one bit via I2C data/clock
3429 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3432 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3434 DEBUGFUNC("e1000_clock_out_i2c_bit");
3436 status = e1000_set_i2c_data(hw, &i2cctl, data);
3437 if (status == E1000_SUCCESS) {
3438 e1000_raise_i2c_clk(hw, &i2cctl);
3440 /* Minimum high period of clock is 4us */
3441 usec_delay(E1000_I2C_T_HIGH);
3443 e1000_lower_i2c_clk(hw, &i2cctl);
3445 /* Minimum low period of clock is 4.7 us.
3446 * This also takes care of the data hold time.
3448 usec_delay(E1000_I2C_T_LOW);
3450 status = E1000_ERR_I2C;
3451 DEBUGOUT1("I2C data was not set to %X\n", data);
3457 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3458 * @hw: pointer to hardware structure
3459 * @i2cctl: Current value of I2CCTL register
3461 * Raises the I2C clock line '0'->'1'
3463 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3465 DEBUGFUNC("e1000_raise_i2c_clk");
3467 *i2cctl |= E1000_I2C_CLK_OUT;
3468 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3469 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3470 E1000_WRITE_FLUSH(hw);
3472 /* SCL rise time (1000ns) */
3473 usec_delay(E1000_I2C_T_RISE);
3477 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3478 * @hw: pointer to hardware structure
3479 * @i2cctl: Current value of I2CCTL register
3481 * Lowers the I2C clock line '1'->'0'
3483 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3486 DEBUGFUNC("e1000_lower_i2c_clk");
3488 *i2cctl &= ~E1000_I2C_CLK_OUT;
3489 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3490 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3491 E1000_WRITE_FLUSH(hw);
3493 /* SCL fall time (300ns) */
3494 usec_delay(E1000_I2C_T_FALL);
3498 * e1000_set_i2c_data - Sets the I2C data bit
3499 * @hw: pointer to hardware structure
3500 * @i2cctl: Current value of I2CCTL register
3501 * @data: I2C data value (0 or 1) to set
3503 * Sets the I2C data bit
3505 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3507 s32 status = E1000_SUCCESS;
3509 DEBUGFUNC("e1000_set_i2c_data");
3512 *i2cctl |= E1000_I2C_DATA_OUT;
3514 *i2cctl &= ~E1000_I2C_DATA_OUT;
3516 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3517 *i2cctl |= E1000_I2C_CLK_OE_N;
3518 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3519 E1000_WRITE_FLUSH(hw);
3521 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3522 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3524 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3525 if (data != e1000_get_i2c_data(i2cctl)) {
3526 status = E1000_ERR_I2C;
3527 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3534 * e1000_get_i2c_data - Reads the I2C SDA data bit
3535 * @i2cctl: Current value of I2CCTL register
3537 * Returns the I2C data bit value
3539 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3543 DEBUGFUNC("e1000_get_i2c_data");
3545 if (*i2cctl & E1000_I2C_DATA_IN)
3554 * e1000_i2c_bus_clear - Clears the I2C bus
3555 * @hw: pointer to hardware structure
3557 * Clears the I2C bus by sending nine clock pulses.
3558 * Used when data line is stuck low.
3560 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3562 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3565 DEBUGFUNC("e1000_i2c_bus_clear");
3567 e1000_i2c_start(hw);
3569 e1000_set_i2c_data(hw, &i2cctl, 1);
3571 for (i = 0; i < 9; i++) {
3572 e1000_raise_i2c_clk(hw, &i2cctl);
3574 /* Min high period of clock is 4us */
3575 usec_delay(E1000_I2C_T_HIGH);
3577 e1000_lower_i2c_clk(hw, &i2cctl);
3579 /* Min low period of clock is 4.7us*/
3580 usec_delay(E1000_I2C_T_LOW);
3583 e1000_i2c_start(hw);
3585 /* Put the i2c bus back to default state */