drivers/net/e1000/base/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  * 82580 Gigabit Network Connection
  41  * I350 Gigabit Network Connection
  42  */
  43
  44 #include "e1000_api.h"
  45 #include "e1000_i210.h"
  46
  47 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  49 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  51 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  53 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  54 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  56 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  57                                          u16 *duplex);
  58 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  60                                            u16 *data);
  61 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  62 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  63 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  64                                      u32 offset, u16 *data);
  65 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  66                                       u32 offset, u16 data);
  67 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  68                                           bool active);
  69 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  70                                           bool active);
  71 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  72                                           bool active);
  73 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  74 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  75 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  76 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  77 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  78 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  79                                             u32 offset, u16 data);
  80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  81 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  82 STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  83                                                  u16 *speed, u16 *duplex);
  84 STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  87 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  88 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  98                                                  u16 offset);
  99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 100                                                    u16 offset);
 101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
 105
 106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
 107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
 108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
 117
 118 STATIC const u16 e1000_82580_rxpbs_table[] = {
 119         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 120 #define E1000_82580_RXPBS_TABLE_SIZE \
 121         (sizeof(e1000_82580_rxpbs_table) / \
 122          sizeof(e1000_82580_rxpbs_table[0]))
 123
 124
 125 /**
 126  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 127  *  @hw: pointer to the HW structure
 128  *
 129  *  Called to determine if the I2C pins are being used for I2C or as an
 130  *  external MDIO interface since the two options are mutually exclusive.
 131  **/
 132 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 133 {
 134         u32 reg = 0;
 135         bool ext_mdio = false;
 136
 137         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 138
 139         switch (hw->mac.type) {
 140         case e1000_82575:
 141         case e1000_82576:
 142                 reg = E1000_READ_REG(hw, E1000_MDIC);
 143                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 144                 break;
 145         case e1000_82580:
 146         case e1000_i350:
 147         case e1000_i354:
 148         case e1000_i210:
 149         case e1000_i211:
 150                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 151                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 152                 break;
 153         default:
 154                 break;
 155         }
 156         return ext_mdio;
 157 }
 158
 159 /**
 160  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 161  *  @hw: pointer to the HW structure
 162  **/
 163 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 164 {
 165         struct e1000_phy_info *phy = &hw->phy;
 166         s32 ret_val = E1000_SUCCESS;
 167         u32 ctrl_ext;
 168
 169         DEBUGFUNC("e1000_init_phy_params_82575");
 170
 171         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 172         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 173
 174         if (hw->phy.media_type != e1000_media_type_copper) {
 175                 phy->type = e1000_phy_none;
 176                 goto out;
 177         }
 178
 179         phy->ops.power_up   = e1000_power_up_phy_copper;
 180         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 181
 182         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 183         phy->reset_delay_us     = 100;
 184
 185         phy->ops.acquire        = e1000_acquire_phy_82575;
 186         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 187         phy->ops.commit         = e1000_phy_sw_reset_generic;
 188         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 189         phy->ops.release        = e1000_release_phy_82575;
 190
 191         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 192
 193         if (e1000_sgmii_active_82575(hw)) {
 194                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 195                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 196         } else {
 197                 phy->ops.reset = e1000_phy_hw_reset_generic;
 198                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 199         }
 200
 201         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 202         e1000_reset_mdicnfg_82580(hw);
 203
 204         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 205                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 206                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 207         } else {
 208                 switch (hw->mac.type) {
 209                 case e1000_82580:
 210                 case e1000_i350:
 211                 case e1000_i354:
 212                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 213                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 214                         break;
 215                 case e1000_i210:
 216                 case e1000_i211:
 217                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 218                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 219                         break;
 220                 default:
 221                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 222                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 223                 }
 224         }
 225
 226         /* Set phy->phy_addr and phy->id. */
 227         ret_val = e1000_get_phy_id_82575(hw);
 228
 229         /* Verify phy id and set remaining function pointers */
 230         switch (phy->id) {
 231         case M88E1543_E_PHY_ID:
 232         case M88E1512_E_PHY_ID:
 233         case I347AT4_E_PHY_ID:
 234         case M88E1112_E_PHY_ID:
 235         case M88E1340M_E_PHY_ID:
 236         case M88E1111_I_PHY_ID:
 237                 phy->type               = e1000_phy_m88;
 238                 phy->ops.check_polarity = e1000_check_polarity_m88;
 239                 phy->ops.get_info       = e1000_get_phy_info_m88;
 240                 if (phy->id == I347AT4_E_PHY_ID ||
 241                     phy->id == M88E1112_E_PHY_ID ||
 242                     phy->id == M88E1340M_E_PHY_ID)
 243                         phy->ops.get_cable_length =
 244                                          e1000_get_cable_length_m88_gen2;
 245                 else if (phy->id == M88E1543_E_PHY_ID ||
 246                          phy->id == M88E1512_E_PHY_ID)
 247                         phy->ops.get_cable_length =
 248                                          e1000_get_cable_length_m88_gen2;
 249                 else
 250                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 251                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 252                 /* Check if this PHY is confgured for media swap. */
 253                 if (phy->id == M88E1112_E_PHY_ID) {
 254                         u16 data;
 255
 256                         ret_val = phy->ops.write_reg(hw,
 257                                                      E1000_M88E1112_PAGE_ADDR,
 258                                                      2);
 259                         if (ret_val)
 260                                 goto out;
 261
 262                         ret_val = phy->ops.read_reg(hw,
 263                                                     E1000_M88E1112_MAC_CTRL_1,
 264                                                     &data);
 265                         if (ret_val)
 266                                 goto out;
 267
 268                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 269                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 270                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 271                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 272                                 hw->mac.ops.check_for_link =
 273                                                 e1000_check_for_link_media_swap;
 274                 }
 275                 if (phy->id == M88E1512_E_PHY_ID) {
 276                         ret_val = e1000_initialize_M88E1512_phy(hw);
 277                         if (ret_val)
 278                                 goto out;
 279                 }
 280                 break;
 281         case IGP03E1000_E_PHY_ID:
 282         case IGP04E1000_E_PHY_ID:
 283                 phy->type = e1000_phy_igp_3;
 284                 phy->ops.check_polarity = e1000_check_polarity_igp;
 285                 phy->ops.get_info = e1000_get_phy_info_igp;
 286                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 287                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 288                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 289                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 290                 break;
 291         case I82580_I_PHY_ID:
 292         case I350_I_PHY_ID:
 293                 phy->type = e1000_phy_82580;
 294                 phy->ops.check_polarity = e1000_check_polarity_82577;
 295                 phy->ops.force_speed_duplex =
 296                                          e1000_phy_force_speed_duplex_82577;
 297                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 298                 phy->ops.get_info = e1000_get_phy_info_82577;
 299                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 300                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 301                 break;
 302         case I210_I_PHY_ID:
 303                 phy->type               = e1000_phy_i210;
 304                 phy->ops.check_polarity = e1000_check_polarity_m88;
 305                 phy->ops.get_info       = e1000_get_phy_info_m88;
 306                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 307                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 308                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 309                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 310                 break;
 311         default:
 312                 ret_val = -E1000_ERR_PHY;
 313                 goto out;
 314         }
 315
 316 out:
 317         return ret_val;
 318 }
 319
 320 /**
 321  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 322  *  @hw: pointer to the HW structure
 323  **/
 324 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 325 {
 326         struct e1000_nvm_info *nvm = &hw->nvm;
 327         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 328         u16 size;
 329
 330         DEBUGFUNC("e1000_init_nvm_params_82575");
 331
 332         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 333                      E1000_EECD_SIZE_EX_SHIFT);
 334         /*
 335          * Added to a constant, "size" becomes the left-shift value
 336          * for setting word_size.
 337          */
 338         size += NVM_WORD_SIZE_BASE_SHIFT;
 339
 340         /* Just in case size is out of range, cap it to the largest
 341          * EEPROM size supported
 342          */
 343         if (size > 15)
 344                 size = 15;
 345
 346         nvm->word_size = 1 << size;
 347         if (hw->mac.type < e1000_i210) {
 348                 nvm->opcode_bits = 8;
 349                 nvm->delay_usec = 1;
 350
 351                 switch (nvm->override) {
 352                 case e1000_nvm_override_spi_large:
 353                         nvm->page_size = 32;
 354                         nvm->address_bits = 16;
 355                         break;
 356                 case e1000_nvm_override_spi_small:
 357                         nvm->page_size = 8;
 358                         nvm->address_bits = 8;
 359                         break;
 360                 default:
 361                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 362                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 363                                             16 : 8;
 364                         break;
 365                 }
 366                 if (nvm->word_size == (1 << 15))
 367                         nvm->page_size = 128;
 368
 369                 nvm->type = e1000_nvm_eeprom_spi;
 370         } else {
 371                 nvm->type = e1000_nvm_flash_hw;
 372         }
 373
 374         /* Function Pointers */
 375         nvm->ops.acquire = e1000_acquire_nvm_82575;
 376         nvm->ops.release = e1000_release_nvm_82575;
 377         if (nvm->word_size < (1 << 15))
 378                 nvm->ops.read = e1000_read_nvm_eerd;
 379         else
 380                 nvm->ops.read = e1000_read_nvm_spi;
 381
 382         nvm->ops.write = e1000_write_nvm_spi;
 383         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 384         nvm->ops.update = e1000_update_nvm_checksum_generic;
 385         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 386
 387         /* override generic family function pointers for specific descendants */
 388         switch (hw->mac.type) {
 389         case e1000_82580:
 390                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 391                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 392                 break;
 393         case e1000_i350:
 394         case e1000_i354:
 395                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 396                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 397                 break;
 398         default:
 399                 break;
 400         }
 401
 402         return E1000_SUCCESS;
 403 }
 404
 405 /**
 406  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 407  *  @hw: pointer to the HW structure
 408  **/
 409 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 410 {
 411         struct e1000_mac_info *mac = &hw->mac;
 412         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 413
 414         DEBUGFUNC("e1000_init_mac_params_82575");
 415
 416         /* Derives media type */
 417         e1000_get_media_type_82575(hw);
 418         /* Set mta register count */
 419         mac->mta_reg_count = 128;
 420         /* Set uta register count */
 421         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 422         /* Set rar entry count */
 423         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 424         if (mac->type == e1000_82576)
 425                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 426         if (mac->type == e1000_82580)
 427                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 428         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 429                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 430
 431         /* Enable EEE default settings for EEE supported devices */
 432         if (mac->type >= e1000_i350)
 433                 dev_spec->eee_disable = false;
 434
 435         /* Allow a single clear of the SW semaphore on I210 and newer */
 436         if (mac->type >= e1000_i210)
 437                 dev_spec->clear_semaphore_once = true;
 438
 439         /* Set if part includes ASF firmware */
 440         mac->asf_firmware_present = true;
 441         /* FWSM register */
 442         mac->has_fwsm = true;
 443         /* ARC supported; valid only if manageability features are enabled. */
 444         mac->arc_subsystem_valid =
 445                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 446
 447         /* Function pointers */
 448
 449         /* bus type/speed/width */
 450         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 451         /* reset */
 452         if (mac->type >= e1000_82580)
 453                 mac->ops.reset_hw = e1000_reset_hw_82580;
 454         else
 455         mac->ops.reset_hw = e1000_reset_hw_82575;
 456         /* hw initialization */
 457         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 458                 mac->ops.init_hw = e1000_init_hw_i210;
 459         else
 460         mac->ops.init_hw = e1000_init_hw_82575;
 461         /* link setup */
 462         mac->ops.setup_link = e1000_setup_link_generic;
 463         /* physical interface link setup */
 464         mac->ops.setup_physical_interface =
 465                 (hw->phy.media_type == e1000_media_type_copper)
 466                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 467         /* physical interface shutdown */
 468         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 469         /* physical interface power up */
 470         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 471         /* check for link */
 472         mac->ops.check_for_link = e1000_check_for_link_82575;
 473         /* read mac address */
 474         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 475         /* configure collision distance */
 476         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 477         /* multicast address update */
 478         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 479         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 480                 /* writing VFTA */
 481                 mac->ops.write_vfta = e1000_write_vfta_i350;
 482                 /* clearing VFTA */
 483                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 484         } else {
 485                 /* writing VFTA */
 486                 mac->ops.write_vfta = e1000_write_vfta_generic;
 487                 /* clearing VFTA */
 488                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 489         }
 490         if (hw->mac.type >= e1000_82580)
 491                 mac->ops.validate_mdi_setting =
 492                                 e1000_validate_mdi_setting_crossover_generic;
 493         /* ID LED init */
 494         mac->ops.id_led_init = e1000_id_led_init_generic;
 495         /* blink LED */
 496         mac->ops.blink_led = e1000_blink_led_generic;
 497         /* setup LED */
 498         mac->ops.setup_led = e1000_setup_led_generic;
 499         /* cleanup LED */
 500         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 501         /* turn on/off LED */
 502         mac->ops.led_on = e1000_led_on_generic;
 503         mac->ops.led_off = e1000_led_off_generic;
 504         /* clear hardware counters */
 505         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 506         /* link info */
 507         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 508         /* acquire SW_FW sync */
 509         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 510         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 511         if (mac->type >= e1000_i210) {
 512                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 513                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 514         }
 515
 516         /* set lan id for port to determine which phy lock to use */
 517         hw->mac.ops.set_lan_id(hw);
 518
 519         return E1000_SUCCESS;
 520 }
 521
 522 /**
 523  *  e1000_init_function_pointers_82575 - Init func ptrs.
 524  *  @hw: pointer to the HW structure
 525  *
 526  *  Called to initialize all function pointers and parameters.
 527  **/
 528 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 529 {
 530         DEBUGFUNC("e1000_init_function_pointers_82575");
 531
 532         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 533         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 534         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 535         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 536 }
 537
 538 /**
 539  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 540  *  @hw: pointer to the HW structure
 541  *
 542  *  Acquire access rights to the correct PHY.
 543  **/
 544 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 545 {
 546         u16 mask = E1000_SWFW_PHY0_SM;
 547
 548         DEBUGFUNC("e1000_acquire_phy_82575");
 549
 550         if (hw->bus.func == E1000_FUNC_1)
 551                 mask = E1000_SWFW_PHY1_SM;
 552         else if (hw->bus.func == E1000_FUNC_2)
 553                 mask = E1000_SWFW_PHY2_SM;
 554         else if (hw->bus.func == E1000_FUNC_3)
 555                 mask = E1000_SWFW_PHY3_SM;
 556
 557         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 558 }
 559
 560 /**
 561  *  e1000_release_phy_82575 - Release rights to access PHY
 562  *  @hw: pointer to the HW structure
 563  *
 564  *  A wrapper to release access rights to the correct PHY.
 565  **/
 566 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 567 {
 568         u16 mask = E1000_SWFW_PHY0_SM;
 569
 570         DEBUGFUNC("e1000_release_phy_82575");
 571
 572         if (hw->bus.func == E1000_FUNC_1)
 573                 mask = E1000_SWFW_PHY1_SM;
 574         else if (hw->bus.func == E1000_FUNC_2)
 575                 mask = E1000_SWFW_PHY2_SM;
 576         else if (hw->bus.func == E1000_FUNC_3)
 577                 mask = E1000_SWFW_PHY3_SM;
 578
 579         hw->mac.ops.release_swfw_sync(hw, mask);
 580 }
 581
 582 /**
 583  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 584  *  @hw: pointer to the HW structure
 585  *  @offset: register offset to be read
 586  *  @data: pointer to the read data
 587  *
 588  *  Reads the PHY register at offset using the serial gigabit media independent
 589  *  interface and stores the retrieved information in data.
 590  **/
 591 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 592                                           u16 *data)
 593 {
 594         s32 ret_val = -E1000_ERR_PARAM;
 595
 596         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 597
 598         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 599                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 600                 goto out;
 601         }
 602
 603         ret_val = hw->phy.ops.acquire(hw);
 604         if (ret_val)
 605                 goto out;
 606
 607         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 608
 609         hw->phy.ops.release(hw);
 610
 611 out:
 612         return ret_val;
 613 }
 614
 615 /**
 616  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 617  *  @hw: pointer to the HW structure
 618  *  @offset: register offset to write to
 619  *  @data: data to write at register offset
 620  *
 621  *  Writes the data to PHY register at the offset using the serial gigabit
 622  *  media independent interface.
 623  **/
 624 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 625                                            u16 data)
 626 {
 627         s32 ret_val = -E1000_ERR_PARAM;
 628
 629         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 630
 631         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 632                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 633                 goto out;
 634         }
 635
 636         ret_val = hw->phy.ops.acquire(hw);
 637         if (ret_val)
 638                 goto out;
 639
 640         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 641
 642         hw->phy.ops.release(hw);
 643
 644 out:
 645         return ret_val;
 646 }
 647
 648 /**
 649  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 650  *  @hw: pointer to the HW structure
 651  *
 652  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 653  *  sgmi interface.
 654  **/
 655 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 656 {
 657         struct e1000_phy_info *phy = &hw->phy;
 658         s32  ret_val = E1000_SUCCESS;
 659         u16 phy_id;
 660         u32 ctrl_ext;
 661         u32 mdic;
 662
 663         DEBUGFUNC("e1000_get_phy_id_82575");
 664
 665         /* some i354 devices need an extra read for phy id */
 666         if (hw->mac.type == e1000_i354)
 667                 e1000_get_phy_id(hw);
 668
 669         /*
 670          * For SGMII PHYs, we try the list of possible addresses until
 671          * we find one that works.  For non-SGMII PHYs
 672          * (e.g. integrated copper PHYs), an address of 1 should
 673          * work.  The result of this function should mean phy->phy_addr
 674          * and phy->id are set correctly.
 675          */
 676         if (!e1000_sgmii_active_82575(hw)) {
 677                 phy->addr = 1;
 678                 ret_val = e1000_get_phy_id(hw);
 679                 goto out;
 680         }
 681
 682         if (e1000_sgmii_uses_mdio_82575(hw)) {
 683                 switch (hw->mac.type) {
 684                 case e1000_82575:
 685                 case e1000_82576:
 686                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 687                         mdic &= E1000_MDIC_PHY_MASK;
 688                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 689                         break;
 690                 case e1000_82580:
 691                 case e1000_i350:
 692                 case e1000_i354:
 693                 case e1000_i210:
 694                 case e1000_i211:
 695                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 696                         mdic &= E1000_MDICNFG_PHY_MASK;
 697                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 698                         break;
 699                 default:
 700                         ret_val = -E1000_ERR_PHY;
 701                         goto out;
 702                         break;
 703                 }
 704                 ret_val = e1000_get_phy_id(hw);
 705                 goto out;
 706         }
 707
 708         /* Power on sgmii phy if it is disabled */
 709         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 710         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 711                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 712         E1000_WRITE_FLUSH(hw);
 713         msec_delay(300);
 714
 715         /*
 716          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 717          * Therefore, we need to test 1-7
 718          */
 719         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 720                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 721                 if (ret_val == E1000_SUCCESS) {
 722                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 723                                   phy_id, phy->addr);
 724                         /*
 725                          * At the time of this writing, The M88 part is
 726                          * the only supported SGMII PHY product.
 727                          */
 728                         if (phy_id == M88_VENDOR)
 729                                 break;
 730                 } else {
 731                         DEBUGOUT1("PHY address %u was unreadable\n",
 732                                   phy->addr);
 733                 }
 734         }
 735
 736         /* A valid PHY type couldn't be found. */
 737         if (phy->addr == 8) {
 738                 phy->addr = 0;
 739                 ret_val = -E1000_ERR_PHY;
 740         } else {
 741                 ret_val = e1000_get_phy_id(hw);
 742         }
 743
 744         /* restore previous sfp cage power state */
 745         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 746
 747 out:
 748         return ret_val;
 749 }
 750
 751 /**
 752  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 753  *  @hw: pointer to the HW structure
 754  *
 755  *  Resets the PHY using the serial gigabit media independent interface.
 756  **/
 757 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 758 {
 759         s32 ret_val = E1000_SUCCESS;
 760         struct e1000_phy_info *phy = &hw->phy;
 761
 762         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 763
 764         /*
 765          * This isn't a true "hard" reset, but is the only reset
 766          * available to us at this time.
 767          */
 768
 769         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 770
 771         if (!(hw->phy.ops.write_reg))
 772                 goto out;
 773
 774         /*
 775          * SFP documentation requires the following to configure the SPF module
 776          * to work on SGMII.  No further documentation is given.
 777          */
 778         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 779         if (ret_val)
 780                 goto out;
 781
 782         ret_val = hw->phy.ops.commit(hw);
 783         if (ret_val)
 784                 goto out;
 785
 786         if (phy->id == M88E1512_E_PHY_ID)
 787                 ret_val = e1000_initialize_M88E1512_phy(hw);
 788 out:
 789         return ret_val;
 790 }
 791
 792 /**
 793  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 794  *  @hw: pointer to the HW structure
 795  *  @active: true to enable LPLU, false to disable
 796  *
 797  *  Sets the LPLU D0 state according to the active flag.  When
 798  *  activating LPLU this function also disables smart speed
 799  *  and vice versa.  LPLU will not be activated unless the
 800  *  device autonegotiation advertisement meets standards of
 801  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 802  *  This is a function pointer entry point only called by
 803  *  PHY setup routines.
 804  **/
 805 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 806 {
 807         struct e1000_phy_info *phy = &hw->phy;
 808         s32 ret_val = E1000_SUCCESS;
 809         u16 data;
 810
 811         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 812
 813         if (!(hw->phy.ops.read_reg))
 814                 goto out;
 815
 816         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 817         if (ret_val)
 818                 goto out;
 819
 820         if (active) {
 821                 data |= IGP02E1000_PM_D0_LPLU;
 822                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 823                                              data);
 824                 if (ret_val)
 825                         goto out;
 826
 827                 /* When LPLU is enabled, we should disable SmartSpeed */
 828                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 829                                             &data);
 830                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 831                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 832                                              data);
 833                 if (ret_val)
 834                         goto out;
 835         } else {
 836                 data &= ~IGP02E1000_PM_D0_LPLU;
 837                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 838                                              data);
 839                 /*
 840                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 841                  * during Dx states where the power conservation is most
 842                  * important.  During driver activity we should enable
 843                  * SmartSpeed, so performance is maintained.
 844                  */
 845                 if (phy->smart_speed == e1000_smart_speed_on) {
 846                         ret_val = phy->ops.read_reg(hw,
 847                                                     IGP01E1000_PHY_PORT_CONFIG,
 848                                                     &data);
 849                         if (ret_val)
 850                                 goto out;
 851
 852                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 853                         ret_val = phy->ops.write_reg(hw,
 854                                                      IGP01E1000_PHY_PORT_CONFIG,
 855                                                      data);
 856                         if (ret_val)
 857                                 goto out;
 858                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 859                         ret_val = phy->ops.read_reg(hw,
 860                                                     IGP01E1000_PHY_PORT_CONFIG,
 861                                                     &data);
 862                         if (ret_val)
 863                                 goto out;
 864
 865                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 866                         ret_val = phy->ops.write_reg(hw,
 867                                                      IGP01E1000_PHY_PORT_CONFIG,
 868                                                      data);
 869                         if (ret_val)
 870                                 goto out;
 871                 }
 872         }
 873
 874 out:
 875         return ret_val;
 876 }
 877
 878 /**
 879  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 880  *  @hw: pointer to the HW structure
 881  *  @active: true to enable LPLU, false to disable
 882  *
 883  *  Sets the LPLU D0 state according to the active flag.  When
 884  *  activating LPLU this function also disables smart speed
 885  *  and vice versa.  LPLU will not be activated unless the
 886  *  device autonegotiation advertisement meets standards of
 887  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 888  *  This is a function pointer entry point only called by
 889  *  PHY setup routines.
 890  **/
 891 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 892 {
 893         struct e1000_phy_info *phy = &hw->phy;
 894         u32 data;
 895
 896         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 897
 898         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 899
 900         if (active) {
 901                 data |= E1000_82580_PM_D0_LPLU;
 902
 903                 /* When LPLU is enabled, we should disable SmartSpeed */
 904                 data &= ~E1000_82580_PM_SPD;
 905         } else {
 906                 data &= ~E1000_82580_PM_D0_LPLU;
 907
 908                 /*
 909                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 910                  * during Dx states where the power conservation is most
 911                  * important.  During driver activity we should enable
 912                  * SmartSpeed, so performance is maintained.
 913                  */
 914                 if (phy->smart_speed == e1000_smart_speed_on)
 915                         data |= E1000_82580_PM_SPD;
 916                 else if (phy->smart_speed == e1000_smart_speed_off)
 917                         data &= ~E1000_82580_PM_SPD;
 918         }
 919
 920         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 921         return E1000_SUCCESS;
 922 }
 923
 924 /**
 925  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 926  *  @hw: pointer to the HW structure
 927  *  @active: boolean used to enable/disable lplu
 928  *
 929  *  Success returns 0, Failure returns 1
 930  *
 931  *  The low power link up (lplu) state is set to the power management level D3
 932  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 933  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 934  *  is used during Dx states where the power conservation is most important.
 935  *  During driver activity, SmartSpeed should be enabled so performance is
 936  *  maintained.
 937  **/
 938 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 939 {
 940         struct e1000_phy_info *phy = &hw->phy;
 941         u32 data;
 942
 943         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 944
 945         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 946
 947         if (!active) {
 948                 data &= ~E1000_82580_PM_D3_LPLU;
 949                 /*
 950                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 951                  * during Dx states where the power conservation is most
 952                  * important.  During driver activity we should enable
 953                  * SmartSpeed, so performance is maintained.
 954                  */
 955                 if (phy->smart_speed == e1000_smart_speed_on)
 956                         data |= E1000_82580_PM_SPD;
 957                 else if (phy->smart_speed == e1000_smart_speed_off)
 958                         data &= ~E1000_82580_PM_SPD;
 959         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 960                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 961                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 962                 data |= E1000_82580_PM_D3_LPLU;
 963                 /* When LPLU is enabled, we should disable SmartSpeed */
 964                 data &= ~E1000_82580_PM_SPD;
 965         }
 966
 967         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 968         return E1000_SUCCESS;
 969 }
 970
 971 /**
 972  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 973  *  @hw: pointer to the HW structure
 974  *
 975  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 976  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 977  *  Return successful if access grant bit set, else clear the request for
 978  *  EEPROM access and return -E1000_ERR_NVM (-1).
 979  **/
 980 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 981 {
 982         s32 ret_val = E1000_SUCCESS;
 983
 984         DEBUGFUNC("e1000_acquire_nvm_82575");
 985
 986         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 987         if (ret_val)
 988                 goto out;
 989
 990         /*
 991          * Check if there is some access
 992          * error this access may hook on
 993          */
 994         if (hw->mac.type == e1000_i350) {
 995                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 996                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 997                     E1000_EECD_TIMEOUT)) {
 998                         /* Clear all access error flags */
 999                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1000                                         E1000_EECD_ERROR_CLR);
1001                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1002                 }
1003         }
1004
1005         if (hw->mac.type == e1000_82580) {
1006                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1007                 if (eecd & E1000_EECD_BLOCKED) {
1008                         /* Clear access error flag */
1009                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1010                                         E1000_EECD_BLOCKED);
1011                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1012                 }
1013         }
1014
1015         ret_val = e1000_acquire_nvm_generic(hw);
1016         if (ret_val)
1017                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1018
1019 out:
1020         return ret_val;
1021 }
1022
1023 /**
1024  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1025  *  @hw: pointer to the HW structure
1026  *
1027  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1028  *  then release the semaphores acquired.
1029  **/
1030 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1031 {
1032         DEBUGFUNC("e1000_release_nvm_82575");
1033
1034         e1000_release_nvm_generic(hw);
1035
1036         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1037 }
1038
1039 /**
1040  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1041  *  @hw: pointer to the HW structure
1042  *  @mask: specifies which semaphore to acquire
1043  *
1044  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1045  *  will also specify which port we're acquiring the lock for.
1046  **/
1047 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1048 {
1049         u32 swfw_sync;
1050         u32 swmask = mask;
1051         u32 fwmask = mask << 16;
1052         s32 ret_val = E1000_SUCCESS;
1053         s32 i = 0, timeout = 200;
1054
1055         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1056
1057         while (i < timeout) {
1058                 if (e1000_get_hw_semaphore_generic(hw)) {
1059                         ret_val = -E1000_ERR_SWFW_SYNC;
1060                         goto out;
1061                 }
1062
1063                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1064                 if (!(swfw_sync & (fwmask | swmask)))
1065                         break;
1066
1067                 /*
1068                  * Firmware currently using resource (fwmask)
1069                  * or other software thread using resource (swmask)
1070                  */
1071                 e1000_put_hw_semaphore_generic(hw);
1072                 msec_delay_irq(5);
1073                 i++;
1074         }
1075
1076         if (i == timeout) {
1077                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1078                 ret_val = -E1000_ERR_SWFW_SYNC;
1079                 goto out;
1080         }
1081
1082         swfw_sync |= swmask;
1083         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1084
1085         e1000_put_hw_semaphore_generic(hw);
1086
1087 out:
1088         return ret_val;
1089 }
1090
1091 /**
1092  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1093  *  @hw: pointer to the HW structure
1094  *  @mask: specifies which semaphore to acquire
1095  *
1096  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1097  *  will also specify which port we're releasing the lock for.
1098  **/
1099 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1100 {
1101         u32 swfw_sync;
1102
1103         DEBUGFUNC("e1000_release_swfw_sync_82575");
1104
1105         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1106                 ; /* Empty */
1107
1108         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1109         swfw_sync &= ~mask;
1110         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1111
1112         e1000_put_hw_semaphore_generic(hw);
1113 }
1114
1115 /**
1116  *  e1000_get_cfg_done_82575 - Read config done bit
1117  *  @hw: pointer to the HW structure
1118  *
1119  *  Read the management control register for the config done bit for
1120  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1121  *  to read the config done bit, so an error is *ONLY* logged and returns
1122  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1123  *  would not be able to be reset or change link.
1124  **/
1125 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1126 {
1127         s32 timeout = PHY_CFG_TIMEOUT;
1128         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1129
1130         DEBUGFUNC("e1000_get_cfg_done_82575");
1131
1132         if (hw->bus.func == E1000_FUNC_1)
1133                 mask = E1000_NVM_CFG_DONE_PORT_1;
1134         else if (hw->bus.func == E1000_FUNC_2)
1135                 mask = E1000_NVM_CFG_DONE_PORT_2;
1136         else if (hw->bus.func == E1000_FUNC_3)
1137                 mask = E1000_NVM_CFG_DONE_PORT_3;
1138         while (timeout) {
1139                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1140                         break;
1141                 msec_delay(1);
1142                 timeout--;
1143         }
1144         if (!timeout)
1145                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1146
1147         /* If EEPROM is not marked present, init the PHY manually */
1148         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1149             (hw->phy.type == e1000_phy_igp_3))
1150                 e1000_phy_init_script_igp3(hw);
1151
1152         return E1000_SUCCESS;
1153 }
1154
1155 /**
1156  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1157  *  @hw: pointer to the HW structure
1158  *  @speed: stores the current speed
1159  *  @duplex: stores the current duplex
1160  *
1161  *  This is a wrapper function, if using the serial gigabit media independent
1162  *  interface, use PCS to retrieve the link speed and duplex information.
1163  *  Otherwise, use the generic function to get the link speed and duplex info.
1164  **/
1165 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1166                                         u16 *duplex)
1167 {
1168         s32 ret_val;
1169
1170         DEBUGFUNC("e1000_get_link_up_info_82575");
1171
1172         if (hw->phy.media_type != e1000_media_type_copper)
1173                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1174                                                                duplex);
1175         else
1176                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1177                                                                     duplex);
1178
1179         return ret_val;
1180 }
1181
1182 /**
1183  *  e1000_check_for_link_82575 - Check for link
1184  *  @hw: pointer to the HW structure
1185  *
1186  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1187  *  use the generic interface for determining link.
1188  **/
1189 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1190 {
1191         s32 ret_val;
1192         u16 speed, duplex;
1193
1194         DEBUGFUNC("e1000_check_for_link_82575");
1195
1196         if (hw->phy.media_type != e1000_media_type_copper) {
1197                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1198                                                                &duplex);
1199                 /*
1200                  * Use this flag to determine if link needs to be checked or
1201                  * not.  If we have link clear the flag so that we do not
1202                  * continue to check for link.
1203                  */
1204                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1205
1206                 /*
1207                  * Configure Flow Control now that Auto-Neg has completed.
1208                  * First, we need to restore the desired flow control
1209                  * settings because we may have had to re-autoneg with a
1210                  * different link partner.
1211                  */
1212                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1213                 if (ret_val)
1214                         DEBUGOUT("Error configuring flow control\n");
1215         } else {
1216                 ret_val = e1000_check_for_copper_link_generic(hw);
1217         }
1218
1219         return ret_val;
1220 }
1221
1222 /**
1223  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1224  *  @hw: pointer to the HW structure
1225  *
1226  *  Poll the M88E1112 interfaces to see which interface achieved link.
1227  */
1228 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1229 {
1230         struct e1000_phy_info *phy = &hw->phy;
1231         s32 ret_val;
1232         u16 data;
1233         u8 port = 0;
1234
1235         DEBUGFUNC("e1000_check_for_link_media_swap");
1236
1237         /* Check the copper medium. */
1238         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1239         if (ret_val)
1240                 return ret_val;
1241
1242         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1243         if (ret_val)
1244                 return ret_val;
1245
1246         if (data & E1000_M88E1112_STATUS_LINK)
1247                 port = E1000_MEDIA_PORT_COPPER;
1248
1249         /* Check the other medium. */
1250         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1251         if (ret_val)
1252                 return ret_val;
1253
1254         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1255         if (ret_val)
1256                 return ret_val;
1257
1258         /* reset page to 0 */
1259         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1260         if (ret_val)
1261                 return ret_val;
1262
1263         if (data & E1000_M88E1112_STATUS_LINK)
1264                 port = E1000_MEDIA_PORT_OTHER;
1265
1266         /* Determine if a swap needs to happen. */
1267         if (port && (hw->dev_spec._82575.media_port != port)) {
1268                 hw->dev_spec._82575.media_port = port;
1269                 hw->dev_spec._82575.media_changed = true;
1270         } else {
1271                 ret_val = e1000_check_for_link_82575(hw);
1272         }
1273
1274         return E1000_SUCCESS;
1275 }
1276
1277 /**
1278  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1279  *  @hw: pointer to the HW structure
1280  **/
1281 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1282 {
1283         u32 reg;
1284
1285         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1286
1287         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1288             !e1000_sgmii_active_82575(hw))
1289                 return;
1290
1291         /* Enable PCS to turn on link */
1292         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1293         reg |= E1000_PCS_CFG_PCS_EN;
1294         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1295
1296         /* Power up the laser */
1297         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1298         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1299         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1300
1301         /* flush the write to verify completion */
1302         E1000_WRITE_FLUSH(hw);
1303         msec_delay(1);
1304 }
1305
1306 /**
1307  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1308  *  @hw: pointer to the HW structure
1309  *  @speed: stores the current speed
1310  *  @duplex: stores the current duplex
1311  *
1312  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1313  *  duplex, then store the values in the pointers provided.
1314  **/
1315 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1316                                                 u16 *speed, u16 *duplex)
1317 {
1318         struct e1000_mac_info *mac = &hw->mac;
1319         u32 pcs;
1320         u32 status;
1321
1322         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1323
1324         /*
1325          * Read the PCS Status register for link state. For non-copper mode,
1326          * the status register is not accurate. The PCS status register is
1327          * used instead.
1328          */
1329         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1330
1331         /*
1332          * The link up bit determines when link is up on autoneg.
1333          */
1334         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1335                 mac->serdes_has_link = true;
1336
1337                 /* Detect and store PCS speed */
1338                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1339                         *speed = SPEED_1000;
1340                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1341                         *speed = SPEED_100;
1342                 else
1343                         *speed = SPEED_10;
1344
1345                 /* Detect and store PCS duplex */
1346                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1347                         *duplex = FULL_DUPLEX;
1348                 else
1349                         *duplex = HALF_DUPLEX;
1350
1351                 /* Check if it is an I354 2.5Gb backplane connection. */
1352                 if (mac->type == e1000_i354) {
1353                         status = E1000_READ_REG(hw, E1000_STATUS);
1354                         if ((status & E1000_STATUS_2P5_SKU) &&
1355                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1356                                 *speed = SPEED_2500;
1357                                 *duplex = FULL_DUPLEX;
1358                                 DEBUGOUT("2500 Mbs, ");
1359                                 DEBUGOUT("Full Duplex\n");
1360                         }
1361                 }
1362
1363         } else {
1364                 mac->serdes_has_link = false;
1365                 *speed = 0;
1366                 *duplex = 0;
1367         }
1368
1369         return E1000_SUCCESS;
1370 }
1371
1372 /**
1373  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1374  *  @hw: pointer to the HW structure
1375  *
1376  *  In the case of serdes shut down sfp and PCS on driver unload
1377  *  when management pass thru is not enabled.
1378  **/
1379 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1380 {
1381         u32 reg;
1382
1383         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1384
1385         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1386             !e1000_sgmii_active_82575(hw))
1387                 return;
1388
1389         if (!e1000_enable_mng_pass_thru(hw)) {
1390                 /* Disable PCS to turn off link */
1391                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1392                 reg &= ~E1000_PCS_CFG_PCS_EN;
1393                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1394
1395                 /* shutdown the laser */
1396                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1397                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1398                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1399
1400                 /* flush the write to verify completion */
1401                 E1000_WRITE_FLUSH(hw);
1402                 msec_delay(1);
1403         }
1404
1405         return;
1406 }
1407
1408 /**
1409  *  e1000_reset_hw_82575 - Reset hardware
1410  *  @hw: pointer to the HW structure
1411  *
1412  *  This resets the hardware into a known state.
1413  **/
1414 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1415 {
1416         u32 ctrl;
1417         s32 ret_val;
1418
1419         DEBUGFUNC("e1000_reset_hw_82575");
1420
1421         /*
1422          * Prevent the PCI-E bus from sticking if there is no TLP connection
1423          * on the last TLP read/write transaction when MAC is reset.
1424          */
1425         ret_val = e1000_disable_pcie_master_generic(hw);
1426         if (ret_val)
1427                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1428
1429         /* set the completion timeout for interface */
1430         ret_val = e1000_set_pcie_completion_timeout(hw);
1431         if (ret_val)
1432                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1433
1434         DEBUGOUT("Masking off all interrupts\n");
1435         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1436
1437         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1438         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1439         E1000_WRITE_FLUSH(hw);
1440
1441         msec_delay(10);
1442
1443         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1444
1445         DEBUGOUT("Issuing a global reset to MAC\n");
1446         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1447
1448         ret_val = e1000_get_auto_rd_done_generic(hw);
1449         if (ret_val) {
1450                 /*
1451                  * When auto config read does not complete, do not
1452                  * return with an error. This can happen in situations
1453                  * where there is no eeprom and prevents getting link.
1454                  */
1455                 DEBUGOUT("Auto Read Done did not complete\n");
1456         }
1457
1458         /* If EEPROM is not present, run manual init scripts */
1459         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1460                 e1000_reset_init_script_82575(hw);
1461
1462         /* Clear any pending interrupt events. */
1463         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1464         E1000_READ_REG(hw, E1000_ICR);
1465
1466         /* Install any alternate MAC address into RAR0 */
1467         ret_val = e1000_check_alt_mac_addr_generic(hw);
1468
1469         return ret_val;
1470 }
1471
1472 /**
1473  *  e1000_init_hw_82575 - Initialize hardware
1474  *  @hw: pointer to the HW structure
1475  *
1476  *  This inits the hardware readying it for operation.
1477  **/
1478 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1479 {
1480         struct e1000_mac_info *mac = &hw->mac;
1481         s32 ret_val;
1482         u16 i, rar_count = mac->rar_entry_count;
1483
1484         DEBUGFUNC("e1000_init_hw_82575");
1485
1486         /* Initialize identification LED */
1487         ret_val = mac->ops.id_led_init(hw);
1488         if (ret_val) {
1489                 DEBUGOUT("Error initializing identification LED\n");
1490                 /* This is not fatal and we should not stop init due to this */
1491         }
1492
1493         /* Disabling VLAN filtering */
1494         DEBUGOUT("Initializing the IEEE VLAN\n");
1495         mac->ops.clear_vfta(hw);
1496
1497         /* Setup the receive address */
1498         e1000_init_rx_addrs_generic(hw, rar_count);
1499
1500         /* Zero out the Multicast HASH table */
1501         DEBUGOUT("Zeroing the MTA\n");
1502         for (i = 0; i < mac->mta_reg_count; i++)
1503                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1504
1505         /* Zero out the Unicast HASH table */
1506         DEBUGOUT("Zeroing the UTA\n");
1507         for (i = 0; i < mac->uta_reg_count; i++)
1508                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1509
1510         /* Setup link and flow control */
1511         ret_val = mac->ops.setup_link(hw);
1512
1513         /* Set the default MTU size */
1514         hw->dev_spec._82575.mtu = 1500;
1515
1516         /*
1517          * Clear all of the statistics registers (clear on read).  It is
1518          * important that we do this after we have tried to establish link
1519          * because the symbol error count will increment wildly if there
1520          * is no link.
1521          */
1522         e1000_clear_hw_cntrs_82575(hw);
1523
1524         return ret_val;
1525 }
1526
1527 /**
1528  *  e1000_setup_copper_link_82575 - Configure copper link settings
1529  *  @hw: pointer to the HW structure
1530  *
1531  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1532  *  for link, once link is established calls to configure collision distance
1533  *  and flow control are called.
1534  **/
1535 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1536 {
1537         u32 ctrl;
1538         s32 ret_val;
1539         u32 phpm_reg;
1540
1541         DEBUGFUNC("e1000_setup_copper_link_82575");
1542
1543         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1544         ctrl |= E1000_CTRL_SLU;
1545         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1546         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1547
1548         /* Clear Go Link Disconnect bit on supported devices */
1549         switch (hw->mac.type) {
1550         case e1000_82580:
1551         case e1000_i350:
1552         case e1000_i210:
1553         case e1000_i211:
1554                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1555                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1556                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1557                 break;
1558         default:
1559                 break;
1560         }
1561
1562         ret_val = e1000_setup_serdes_link_82575(hw);
1563         if (ret_val)
1564                 goto out;
1565
1566         if (e1000_sgmii_active_82575(hw)) {
1567                 /* allow time for SFP cage time to power up phy */
1568                 msec_delay(300);
1569
1570                 ret_val = hw->phy.ops.reset(hw);
1571                 if (ret_val) {
1572                         DEBUGOUT("Error resetting the PHY.\n");
1573                         goto out;
1574                 }
1575         }
1576         switch (hw->phy.type) {
1577         case e1000_phy_i210:
1578         case e1000_phy_m88:
1579                 switch (hw->phy.id) {
1580                 case I347AT4_E_PHY_ID:
1581                 case M88E1112_E_PHY_ID:
1582                 case M88E1340M_E_PHY_ID:
1583                 case M88E1543_E_PHY_ID:
1584                 case M88E1512_E_PHY_ID:
1585                 case I210_I_PHY_ID:
1586                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1587                         break;
1588                 default:
1589                         ret_val = e1000_copper_link_setup_m88(hw);
1590                         break;
1591                 }
1592                 break;
1593         case e1000_phy_igp_3:
1594                 ret_val = e1000_copper_link_setup_igp(hw);
1595                 break;
1596         case e1000_phy_82580:
1597                 ret_val = e1000_copper_link_setup_82577(hw);
1598                 break;
1599         default:
1600                 ret_val = -E1000_ERR_PHY;
1601                 break;
1602         }
1603
1604         if (ret_val)
1605                 goto out;
1606
1607         ret_val = e1000_setup_copper_link_generic(hw);
1608 out:
1609         return ret_val;
1610 }
1611
1612 /**
1613  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1614  *  @hw: pointer to the HW structure
1615  *
1616  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1617  *  used on copper connections where the serialized gigabit media independent
1618  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1619  *  for auto-negotiation or forces speed/duplex.
1620  **/
1621 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1622 {
1623         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1624         bool pcs_autoneg;
1625         s32 ret_val = E1000_SUCCESS;
1626         u16 data;
1627
1628         DEBUGFUNC("e1000_setup_serdes_link_82575");
1629
1630         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1631             !e1000_sgmii_active_82575(hw))
1632                 return ret_val;
1633
1634         /*
1635          * On the 82575, SerDes loopback mode persists until it is
1636          * explicitly turned off or a power cycle is performed.  A read to
1637          * the register does not indicate its status.  Therefore, we ensure
1638          * loopback mode is disabled during initialization.
1639          */
1640         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1641
1642         /* power on the sfp cage if present */
1643         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1644         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1645         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1646
1647         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1648         ctrl_reg |= E1000_CTRL_SLU;
1649
1650         /* set both sw defined pins on 82575/82576*/
1651         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1652                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1653
1654         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1655
1656         /* default pcs_autoneg to the same setting as mac autoneg */
1657         pcs_autoneg = hw->mac.autoneg;
1658
1659         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1660         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1661                 /* sgmii mode lets the phy handle forcing speed/duplex */
1662                 pcs_autoneg = true;
1663                 /* autoneg time out should be disabled for SGMII mode */
1664                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1665                 break;
1666         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1667                 /* disable PCS autoneg and support parallel detect only */
1668                 pcs_autoneg = false;
1669                 /* fall through to default case */
1670         default:
1671                 if (hw->mac.type == e1000_82575 ||
1672                     hw->mac.type == e1000_82576) {
1673                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1674                         if (ret_val) {
1675                                 DEBUGOUT("NVM Read Error\n");
1676                                 return ret_val;
1677                         }
1678
1679                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1680                                 pcs_autoneg = false;
1681                 }
1682
1683                 /*
1684                  * non-SGMII modes only supports a speed of 1000/Full for the
1685                  * link so it is best to just force the MAC and let the pcs
1686                  * link either autoneg or be forced to 1000/Full
1687                  */
1688                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1689                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1690
1691                 /* set speed of 1000/Full if speed/duplex is forced */
1692                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1693                 break;
1694         }
1695
1696         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1697
1698         /*
1699          * New SerDes mode allows for forcing speed or autonegotiating speed
1700          * at 1gb. Autoneg should be default set by most drivers. This is the
1701          * mode that will be compatible with older link partners and switches.
1702          * However, both are supported by the hardware and some drivers/tools.
1703          */
1704         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1705                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1706
1707         if (pcs_autoneg) {
1708                 /* Set PCS register for autoneg */
1709                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1710                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1711
1712                 /* Disable force flow control for autoneg */
1713                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1714
1715                 /* Configure flow control advertisement for autoneg */
1716                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1717                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1718
1719                 switch (hw->fc.requested_mode) {
1720                 case e1000_fc_full:
1721                 case e1000_fc_rx_pause:
1722                         anadv_reg |= E1000_TXCW_ASM_DIR;
1723                         anadv_reg |= E1000_TXCW_PAUSE;
1724                         break;
1725                 case e1000_fc_tx_pause:
1726                         anadv_reg |= E1000_TXCW_ASM_DIR;
1727                         break;
1728                 default:
1729                         break;
1730                 }
1731
1732                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1733
1734                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1735         } else {
1736                 /* Set PCS register for forced link */
1737                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1738
1739                 /* Force flow control for forced link */
1740                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1741
1742                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1743         }
1744
1745         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1746
1747         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1748                 e1000_force_mac_fc_generic(hw);
1749
1750         return ret_val;
1751 }
1752
1753 /**
1754  *  e1000_get_media_type_82575 - derives current media type.
1755  *  @hw: pointer to the HW structure
1756  *
1757  *  The media type is chosen reflecting few settings.
1758  *  The following are taken into account:
1759  *  - link mode set in the current port Init Control Word #3
1760  *  - current link mode settings in CSR register
1761  *  - MDIO vs. I2C PHY control interface chosen
1762  *  - SFP module media type
1763  **/
1764 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1765 {
1766         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1767         s32 ret_val = E1000_SUCCESS;
1768         u32 ctrl_ext = 0;
1769         u32 link_mode = 0;
1770
1771         /* Set internal phy as default */
1772         dev_spec->sgmii_active = false;
1773         dev_spec->module_plugged = false;
1774
1775         /* Get CSR setting */
1776         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1777
1778         /* extract link mode setting */
1779         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1780
1781         switch (link_mode) {
1782         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1783                 hw->phy.media_type = e1000_media_type_internal_serdes;
1784                 break;
1785         case E1000_CTRL_EXT_LINK_MODE_GMII:
1786                 hw->phy.media_type = e1000_media_type_copper;
1787                 break;
1788         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1789                 /* Get phy control interface type set (MDIO vs. I2C)*/
1790                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1791                         hw->phy.media_type = e1000_media_type_copper;
1792                         dev_spec->sgmii_active = true;
1793                         break;
1794                 }
1795                 /* fall through for I2C based SGMII */
1796         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1797                 /* read media type from SFP EEPROM */
1798                 ret_val = e1000_set_sfp_media_type_82575(hw);
1799                 if ((ret_val != E1000_SUCCESS) ||
1800                     (hw->phy.media_type == e1000_media_type_unknown)) {
1801                         /*
1802                          * If media type was not identified then return media
1803                          * type defined by the CTRL_EXT settings.
1804                          */
1805                         hw->phy.media_type = e1000_media_type_internal_serdes;
1806
1807                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1808                                 hw->phy.media_type = e1000_media_type_copper;
1809                                 dev_spec->sgmii_active = true;
1810                         }
1811
1812                         break;
1813                 }
1814
1815                 /* do not change link mode for 100BaseFX */
1816                 if (dev_spec->eth_flags.e100_base_fx)
1817                         break;
1818
1819                 /* change current link mode setting */
1820                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1821
1822                 if (hw->phy.media_type == e1000_media_type_copper)
1823                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1824                 else
1825                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1826
1827                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1828
1829                 break;
1830         }
1831
1832         return ret_val;
1833 }
1834
1835 /**
1836  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1837  *  @hw: pointer to the HW structure
1838  *
1839  *  The media type is chosen based on SFP module.
1840  *  compatibility flags retrieved from SFP ID EEPROM.
1841  **/
1842 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1843 {
1844         s32 ret_val = E1000_ERR_CONFIG;
1845         u32 ctrl_ext = 0;
1846         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1847         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1848         u8 tranceiver_type = 0;
1849         s32 timeout = 3;
1850
1851         /* Turn I2C interface ON and power on sfp cage */
1852         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1853         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1854         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1855
1856         E1000_WRITE_FLUSH(hw);
1857
1858         /* Read SFP module data */
1859         while (timeout) {
1860                 ret_val = e1000_read_sfp_data_byte(hw,
1861                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1862                         &tranceiver_type);
1863                 if (ret_val == E1000_SUCCESS)
1864                         break;
1865                 msec_delay(100);
1866                 timeout--;
1867         }
1868         if (ret_val != E1000_SUCCESS)
1869                 goto out;
1870
1871         ret_val = e1000_read_sfp_data_byte(hw,
1872                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1873                         (u8 *)eth_flags);
1874         if (ret_val != E1000_SUCCESS)
1875                 goto out;
1876
1877         /* Check if there is some SFP module plugged and powered */
1878         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1879             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1880                 dev_spec->module_plugged = true;
1881                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1882                         hw->phy.media_type = e1000_media_type_internal_serdes;
1883                 } else if (eth_flags->e100_base_fx) {
1884                         dev_spec->sgmii_active = true;
1885                         hw->phy.media_type = e1000_media_type_internal_serdes;
1886                 } else if (eth_flags->e1000_base_t) {
1887                         dev_spec->sgmii_active = true;
1888                         hw->phy.media_type = e1000_media_type_copper;
1889                 } else {
1890                         hw->phy.media_type = e1000_media_type_unknown;
1891                         DEBUGOUT("PHY module has not been recognized\n");
1892                         goto out;
1893                 }
1894         } else {
1895                 hw->phy.media_type = e1000_media_type_unknown;
1896         }
1897         ret_val = E1000_SUCCESS;
1898 out:
1899         /* Restore I2C interface setting */
1900         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1901         return ret_val;
1902 }
1903
1904 /**
1905  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1906  *  @hw: pointer to the HW structure
1907  *  @data: pointer to the NVM (EEPROM)
1908  *
1909  *  Read the EEPROM for the current default LED configuration.  If the
1910  *  LED configuration is not valid, set to a valid LED configuration.
1911  **/
1912 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1913 {
1914         s32 ret_val;
1915
1916         DEBUGFUNC("e1000_valid_led_default_82575");
1917
1918         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1919         if (ret_val) {
1920                 DEBUGOUT("NVM Read Error\n");
1921                 goto out;
1922         }
1923
1924         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1925                 switch (hw->phy.media_type) {
1926                 case e1000_media_type_internal_serdes:
1927                         *data = ID_LED_DEFAULT_82575_SERDES;
1928                         break;
1929                 case e1000_media_type_copper:
1930                 default:
1931                         *data = ID_LED_DEFAULT;
1932                         break;
1933                 }
1934         }
1935 out:
1936         return ret_val;
1937 }
1938
1939 /**
1940  *  e1000_sgmii_active_82575 - Return sgmii state
1941  *  @hw: pointer to the HW structure
1942  *
1943  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1944  *  which can be enabled for use in the embedded applications.  Simply
1945  *  return the current state of the sgmii interface.
1946  **/
1947 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1948 {
1949         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1950         return dev_spec->sgmii_active;
1951 }
1952
1953 /**
1954  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1955  *  @hw: pointer to the HW structure
1956  *
1957  *  Inits recommended HW defaults after a reset when there is no EEPROM
1958  *  detected. This is only for the 82575.
1959  **/
1960 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1961 {
1962         DEBUGFUNC("e1000_reset_init_script_82575");
1963
1964         if (hw->mac.type == e1000_82575) {
1965                 DEBUGOUT("Running reset init script for 82575\n");
1966                 /* SerDes configuration via SERDESCTRL */
1967                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1968                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1969                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1970                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1971
1972                 /* CCM configuration via CCMCTL register */
1973                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1974                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1975
1976                 /* PCIe lanes configuration */
1977                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1978                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1979                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1980                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1981
1982                 /* PCIe PLL Configuration */
1983                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1984                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1985                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1986         }
1987
1988         return E1000_SUCCESS;
1989 }
1990
1991 /**
1992  *  e1000_read_mac_addr_82575 - Read device MAC address
1993  *  @hw: pointer to the HW structure
1994  **/
1995 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1996 {
1997         s32 ret_val;
1998
1999         DEBUGFUNC("e1000_read_mac_addr_82575");
2000
2001         /*
2002          * If there's an alternate MAC address place it in RAR0
2003          * so that it will override the Si installed default perm
2004          * address.
2005          */
2006         ret_val = e1000_check_alt_mac_addr_generic(hw);
2007         if (ret_val)
2008                 goto out;
2009
2010         ret_val = e1000_read_mac_addr_generic(hw);
2011
2012 out:
2013         return ret_val;
2014 }
2015
2016 /**
2017  *  e1000_config_collision_dist_82575 - Configure collision distance
2018  *  @hw: pointer to the HW structure
2019  *
2020  *  Configures the collision distance to the default value and is used
2021  *  during link setup.
2022  **/
2023 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2024 {
2025         u32 tctl_ext;
2026
2027         DEBUGFUNC("e1000_config_collision_dist_82575");
2028
2029         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2030
2031         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2032         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2033
2034         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2035         E1000_WRITE_FLUSH(hw);
2036 }
2037
2038 /**
2039  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2040  * @hw: pointer to the HW structure
2041  *
2042  * In the case of a PHY power down to save power, or to turn off link during a
2043  * driver unload, or wake on lan is not enabled, remove the link.
2044  **/
2045 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2046 {
2047         struct e1000_phy_info *phy = &hw->phy;
2048
2049         if (!(phy->ops.check_reset_block))
2050                 return;
2051
2052         /* If the management interface is not enabled, then power down */
2053         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2054                 e1000_power_down_phy_copper(hw);
2055
2056         return;
2057 }
2058
2059 /**
2060  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2061  *  @hw: pointer to the HW structure
2062  *
2063  *  Clears the hardware counters by reading the counter registers.
2064  **/
2065 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2066 {
2067         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2068
2069         e1000_clear_hw_cntrs_base_generic(hw);
2070
2071         E1000_READ_REG(hw, E1000_PRC64);
2072         E1000_READ_REG(hw, E1000_PRC127);
2073         E1000_READ_REG(hw, E1000_PRC255);
2074         E1000_READ_REG(hw, E1000_PRC511);
2075         E1000_READ_REG(hw, E1000_PRC1023);
2076         E1000_READ_REG(hw, E1000_PRC1522);
2077         E1000_READ_REG(hw, E1000_PTC64);
2078         E1000_READ_REG(hw, E1000_PTC127);
2079         E1000_READ_REG(hw, E1000_PTC255);
2080         E1000_READ_REG(hw, E1000_PTC511);
2081         E1000_READ_REG(hw, E1000_PTC1023);
2082         E1000_READ_REG(hw, E1000_PTC1522);
2083
2084         E1000_READ_REG(hw, E1000_ALGNERRC);
2085         E1000_READ_REG(hw, E1000_RXERRC);
2086         E1000_READ_REG(hw, E1000_TNCRS);
2087         E1000_READ_REG(hw, E1000_CEXTERR);
2088         E1000_READ_REG(hw, E1000_TSCTC);
2089         E1000_READ_REG(hw, E1000_TSCTFC);
2090
2091         E1000_READ_REG(hw, E1000_MGTPRC);
2092         E1000_READ_REG(hw, E1000_MGTPDC);
2093         E1000_READ_REG(hw, E1000_MGTPTC);
2094
2095         E1000_READ_REG(hw, E1000_IAC);
2096         E1000_READ_REG(hw, E1000_ICRXOC);
2097
2098         E1000_READ_REG(hw, E1000_ICRXPTC);
2099         E1000_READ_REG(hw, E1000_ICRXATC);
2100         E1000_READ_REG(hw, E1000_ICTXPTC);
2101         E1000_READ_REG(hw, E1000_ICTXATC);
2102         E1000_READ_REG(hw, E1000_ICTXQEC);
2103         E1000_READ_REG(hw, E1000_ICTXQMTC);
2104         E1000_READ_REG(hw, E1000_ICRXDMTC);
2105
2106         E1000_READ_REG(hw, E1000_CBTMPC);
2107         E1000_READ_REG(hw, E1000_HTDPMC);
2108         E1000_READ_REG(hw, E1000_CBRMPC);
2109         E1000_READ_REG(hw, E1000_RPTHC);
2110         E1000_READ_REG(hw, E1000_HGPTC);
2111         E1000_READ_REG(hw, E1000_HTCBDPC);
2112         E1000_READ_REG(hw, E1000_HGORCL);
2113         E1000_READ_REG(hw, E1000_HGORCH);
2114         E1000_READ_REG(hw, E1000_HGOTCL);
2115         E1000_READ_REG(hw, E1000_HGOTCH);
2116         E1000_READ_REG(hw, E1000_LENERRS);
2117
2118         /* This register should not be read in copper configurations */
2119         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2120             e1000_sgmii_active_82575(hw))
2121                 E1000_READ_REG(hw, E1000_SCVPC);
2122 }
2123
2124 /**
2125  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2126  *  @hw: pointer to the HW structure
2127  *
2128  *  After rx enable if managability is enabled then there is likely some
2129  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2130  *  function clears the fifos and flushes any packets that came in as rx was
2131  *  being enabled.
2132  **/
2133 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2134 {
2135         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2136         int i, ms_wait;
2137
2138         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2139         if (hw->mac.type != e1000_82575 ||
2140             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2141                 return;
2142
2143         /* Disable all Rx queues */
2144         for (i = 0; i < 4; i++) {
2145                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2146                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2147                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2148         }
2149         /* Poll all queues to verify they have shut down */
2150         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2151                 msec_delay(1);
2152                 rx_enabled = 0;
2153                 for (i = 0; i < 4; i++)
2154                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2155                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2156                         break;
2157         }
2158
2159         if (ms_wait == 10)
2160                 DEBUGOUT("Queue disable timed out after 10ms\n");
2161
2162         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2163          * incoming packets are rejected.  Set enable and wait 2ms so that
2164          * any packet that was coming in as RCTL.EN was set is flushed
2165          */
2166         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2167         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2168
2169         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2170         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2171
2172         rctl = E1000_READ_REG(hw, E1000_RCTL);
2173         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2174         temp_rctl |= E1000_RCTL_LPE;
2175
2176         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2177         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2178         E1000_WRITE_FLUSH(hw);
2179         msec_delay(2);
2180
2181         /* Enable Rx queues that were previously enabled and restore our
2182          * previous state
2183          */
2184         for (i = 0; i < 4; i++)
2185                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2186         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2187         E1000_WRITE_FLUSH(hw);
2188
2189         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2190         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2191
2192         /* Flush receive errors generated by workaround */
2193         E1000_READ_REG(hw, E1000_ROC);
2194         E1000_READ_REG(hw, E1000_RNBC);
2195         E1000_READ_REG(hw, E1000_MPC);
2196 }
2197
2198 /**
2199  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2200  *  @hw: pointer to the HW structure
2201  *
2202  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2203  *  however the hardware default for these parts is 500us to 1ms which is less
2204  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2205  *  increase the value to either 10ms to 200ms for capability version 1 config,
2206  *  or 16ms to 55ms for version 2.
2207  **/
2208 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2209 {
2210         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2211         s32 ret_val = E1000_SUCCESS;
2212         u16 pcie_devctl2;
2213
2214         /* only take action if timeout value is defaulted to 0 */
2215         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2216                 goto out;
2217
2218         /*
2219          * if capababilities version is type 1 we can write the
2220          * timeout of 10ms to 200ms through the GCR register
2221          */
2222         if (!(gcr & E1000_GCR_CAP_VER2)) {
2223                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2224                 goto out;
2225         }
2226
2227         /*
2228          * for version 2 capabilities we need to write the config space
2229          * directly in order to set the completion timeout value for
2230          * 16ms to 55ms
2231          */
2232         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2233                                           &pcie_devctl2);
2234         if (ret_val)
2235                 goto out;
2236
2237         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2238
2239         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2240                                            &pcie_devctl2);
2241 out:
2242         /* disable completion timeout resend */
2243         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2244
2245         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2246         return ret_val;
2247 }
2248
2249 /**
2250  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2251  *  @hw: pointer to the hardware struct
2252  *  @enable: state to enter, either enabled or disabled
2253  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2254  *
2255  *  enables/disables L2 switch anti-spoofing functionality.
2256  **/
2257 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2258 {
2259         u32 reg_val, reg_offset;
2260
2261         switch (hw->mac.type) {
2262         case e1000_82576:
2263                 reg_offset = E1000_DTXSWC;
2264                 break;
2265         case e1000_i350:
2266         case e1000_i354:
2267                 reg_offset = E1000_TXSWC;
2268                 break;
2269         default:
2270                 return;
2271         }
2272
2273         reg_val = E1000_READ_REG(hw, reg_offset);
2274         if (enable) {
2275                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2276                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2277                 /* The PF can spoof - it has to in order to
2278                  * support emulation mode NICs
2279                  */
2280                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2281         } else {
2282                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2283                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2284         }
2285         E1000_WRITE_REG(hw, reg_offset, reg_val);
2286 }
2287
2288 /**
2289  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2290  *  @hw: pointer to the hardware struct
2291  *  @enable: state to enter, either enabled or disabled
2292  *
2293  *  enables/disables L2 switch loopback functionality.
2294  **/
2295 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2296 {
2297         u32 dtxswc;
2298
2299         switch (hw->mac.type) {
2300         case e1000_82576:
2301                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2302                 if (enable)
2303                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2304                 else
2305                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2306                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2307                 break;
2308         case e1000_i350:
2309         case e1000_i354:
2310                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2311                 if (enable)
2312                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2313                 else
2314                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2315                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2316                 break;
2317         default:
2318                 /* Currently no other hardware supports loopback */
2319                 break;
2320         }
2321
2322
2323 }
2324
2325 /**
2326  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2327  *  @hw: pointer to the hardware struct
2328  *  @enable: state to enter, either enabled or disabled
2329  *
2330  *  enables/disables replication of packets across multiple pools.
2331  **/
2332 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2333 {
2334         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2335
2336         if (enable)
2337                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2338         else
2339                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2340
2341         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2342 }
2343
2344 /**
2345  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2346  *  @hw: pointer to the HW structure
2347  *  @offset: register offset to be read
2348  *  @data: pointer to the read data
2349  *
2350  *  Reads the MDI control register in the PHY at offset and stores the
2351  *  information read to data.
2352  **/
2353 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2354 {
2355         s32 ret_val;
2356
2357         DEBUGFUNC("e1000_read_phy_reg_82580");
2358
2359         ret_val = hw->phy.ops.acquire(hw);
2360         if (ret_val)
2361                 goto out;
2362
2363         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2364
2365         hw->phy.ops.release(hw);
2366
2367 out:
2368         return ret_val;
2369 }
2370
2371 /**
2372  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2373  *  @hw: pointer to the HW structure
2374  *  @offset: register offset to write to
2375  *  @data: data to write to register at offset
2376  *
2377  *  Writes data to MDI control register in the PHY at offset.
2378  **/
2379 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2380 {
2381         s32 ret_val;
2382
2383         DEBUGFUNC("e1000_write_phy_reg_82580");
2384
2385         ret_val = hw->phy.ops.acquire(hw);
2386         if (ret_val)
2387                 goto out;
2388
2389         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2390
2391         hw->phy.ops.release(hw);
2392
2393 out:
2394         return ret_val;
2395 }
2396
2397 /**
2398  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2399  *  @hw: pointer to the HW structure
2400  *
2401  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2402  *  the values found in the EEPROM.  This addresses an issue in which these
2403  *  bits are not restored from EEPROM after reset.
2404  **/
2405 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2406 {
2407         s32 ret_val = E1000_SUCCESS;
2408         u32 mdicnfg;
2409         u16 nvm_data = 0;
2410
2411         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2412
2413         if (hw->mac.type != e1000_82580)
2414                 goto out;
2415         if (!e1000_sgmii_active_82575(hw))
2416                 goto out;
2417
2418         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2419                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2420                                    &nvm_data);
2421         if (ret_val) {
2422                 DEBUGOUT("NVM Read Error\n");
2423                 goto out;
2424         }
2425
2426         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2427         if (nvm_data & NVM_WORD24_EXT_MDIO)
2428                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2429         if (nvm_data & NVM_WORD24_COM_MDIO)
2430                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2431         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2432 out:
2433         return ret_val;
2434 }
2435
2436 /**
2437  *  e1000_reset_hw_82580 - Reset hardware
2438  *  @hw: pointer to the HW structure
2439  *
2440  *  This resets function or entire device (all ports, etc.)
2441  *  to a known state.
2442  **/
2443 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2444 {
2445         s32 ret_val = E1000_SUCCESS;
2446         /* BH SW mailbox bit in SW_FW_SYNC */
2447         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2448         u32 ctrl;
2449         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2450
2451         DEBUGFUNC("e1000_reset_hw_82580");
2452
2453         hw->dev_spec._82575.global_device_reset = false;
2454
2455         /* 82580 does not reliably do global_device_reset due to hw errata */
2456         if (hw->mac.type == e1000_82580)
2457                 global_device_reset = false;
2458
2459         /* Get current control state. */
2460         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2461
2462         /*
2463          * Prevent the PCI-E bus from sticking if there is no TLP connection
2464          * on the last TLP read/write transaction when MAC is reset.
2465          */
2466         ret_val = e1000_disable_pcie_master_generic(hw);
2467         if (ret_val)
2468                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2469
2470         DEBUGOUT("Masking off all interrupts\n");
2471         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2472         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2473         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2474         E1000_WRITE_FLUSH(hw);
2475
2476         msec_delay(10);
2477
2478         /* Determine whether or not a global dev reset is requested */
2479         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2480             swmbsw_mask))
2481                         global_device_reset = false;
2482
2483         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2484             E1000_STAT_DEV_RST_SET))
2485                 ctrl |= E1000_CTRL_DEV_RST;
2486         else
2487                 ctrl |= E1000_CTRL_RST;
2488
2489         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2490         E1000_WRITE_FLUSH(hw);
2491
2492         /* Add delay to insure DEV_RST has time to complete */
2493         if (global_device_reset)
2494                 msec_delay(5);
2495
2496         ret_val = e1000_get_auto_rd_done_generic(hw);
2497         if (ret_val) {
2498                 /*
2499                  * When auto config read does not complete, do not
2500                  * return with an error. This can happen in situations
2501                  * where there is no eeprom and prevents getting link.
2502                  */
2503                 DEBUGOUT("Auto Read Done did not complete\n");
2504         }
2505
2506         /* clear global device reset status bit */
2507         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2508
2509         /* Clear any pending interrupt events. */
2510         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2511         E1000_READ_REG(hw, E1000_ICR);
2512
2513         ret_val = e1000_reset_mdicnfg_82580(hw);
2514         if (ret_val)
2515                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2516
2517         /* Install any alternate MAC address into RAR0 */
2518         ret_val = e1000_check_alt_mac_addr_generic(hw);
2519
2520         /* Release semaphore */
2521         if (global_device_reset)
2522                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2523
2524         return ret_val;
2525 }
2526
2527 /**
2528  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2529  *  @data: data received by reading RXPBS register
2530  *
2531  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2532  *  This function converts the retrieved value into the correct table value
2533  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2534  *  0x0 36  72 144   1   2   4   8  16
2535  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2536  */
2537 u16 e1000_rxpbs_adjust_82580(u32 data)
2538 {
2539         u16 ret_val = 0;
2540
2541         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2542                 ret_val = e1000_82580_rxpbs_table[data];
2543
2544         return ret_val;
2545 }
2546
2547 /**
2548  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2549  *  checksum
2550  *  @hw: pointer to the HW structure
2551  *  @offset: offset in words of the checksum protected region
2552  *
2553  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2554  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2555  **/
2556 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2557 {
2558         s32 ret_val = E1000_SUCCESS;
2559         u16 checksum = 0;
2560         u16 i, nvm_data;
2561
2562         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2563
2564         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2565                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2566                 if (ret_val) {
2567                         DEBUGOUT("NVM Read Error\n");
2568                         goto out;
2569                 }
2570                 checksum += nvm_data;
2571         }
2572
2573         if (checksum != (u16) NVM_SUM) {
2574                 DEBUGOUT("NVM Checksum Invalid\n");
2575                 ret_val = -E1000_ERR_NVM;
2576                 goto out;
2577         }
2578
2579 out:
2580         return ret_val;
2581 }
2582
2583 /**
2584  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2585  *  checksum
2586  *  @hw: pointer to the HW structure
2587  *  @offset: offset in words of the checksum protected region
2588  *
2589  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2590  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2591  *  value to the EEPROM.
2592  **/
2593 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2594 {
2595         s32 ret_val;
2596         u16 checksum = 0;
2597         u16 i, nvm_data;
2598
2599         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2600
2601         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2602                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2603                 if (ret_val) {
2604                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2605                         goto out;
2606                 }
2607                 checksum += nvm_data;
2608         }
2609         checksum = (u16) NVM_SUM - checksum;
2610         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2611                                     &checksum);
2612         if (ret_val)
2613                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2614
2615 out:
2616         return ret_val;
2617 }
2618
2619 /**
2620  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2621  *  @hw: pointer to the HW structure
2622  *
2623  *  Calculates the EEPROM section checksum by reading/adding each word of
2624  *  the EEPROM and then verifies that the sum of the EEPROM is
2625  *  equal to 0xBABA.
2626  **/
2627 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2628 {
2629         s32 ret_val;
2630         u16 eeprom_regions_count = 1;
2631         u16 j, nvm_data;
2632         u16 nvm_offset;
2633
2634         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2635
2636         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2637         if (ret_val) {
2638                 DEBUGOUT("NVM Read Error\n");
2639                 goto out;
2640         }
2641
2642         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2643                 /* if chekcsums compatibility bit is set validate checksums
2644                  * for all 4 ports. */
2645                 eeprom_regions_count = 4;
2646         }
2647
2648         for (j = 0; j < eeprom_regions_count; j++) {
2649                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2650                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2651                                                                   nvm_offset);
2652                 if (ret_val != E1000_SUCCESS)
2653                         goto out;
2654         }
2655
2656 out:
2657         return ret_val;
2658 }
2659
2660 /**
2661  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2662  *  @hw: pointer to the HW structure
2663  *
2664  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2665  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2666  *  checksum and writes the value to the EEPROM.
2667  **/
2668 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2669 {
2670         s32 ret_val;
2671         u16 j, nvm_data;
2672         u16 nvm_offset;
2673
2674         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2675
2676         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2677         if (ret_val) {
2678                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2679                 goto out;
2680         }
2681
2682         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2683                 /* set compatibility bit to validate checksums appropriately */
2684                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2685                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2686                                             &nvm_data);
2687                 if (ret_val) {
2688                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2689                         goto out;
2690                 }
2691         }
2692
2693         for (j = 0; j < 4; j++) {
2694                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2695                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2696                 if (ret_val)
2697                         goto out;
2698         }
2699
2700 out:
2701         return ret_val;
2702 }
2703
2704 /**
2705  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2706  *  @hw: pointer to the HW structure
2707  *
2708  *  Calculates the EEPROM section checksum by reading/adding each word of
2709  *  the EEPROM and then verifies that the sum of the EEPROM is
2710  *  equal to 0xBABA.
2711  **/
2712 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2713 {
2714         s32 ret_val = E1000_SUCCESS;
2715         u16 j;
2716         u16 nvm_offset;
2717
2718         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2719
2720         for (j = 0; j < 4; j++) {
2721                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2722                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2723                                                                   nvm_offset);
2724                 if (ret_val != E1000_SUCCESS)
2725                         goto out;
2726         }
2727
2728 out:
2729         return ret_val;
2730 }
2731
2732 /**
2733  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2734  *  @hw: pointer to the HW structure
2735  *
2736  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2737  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2738  *  checksum and writes the value to the EEPROM.
2739  **/
2740 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2741 {
2742         s32 ret_val = E1000_SUCCESS;
2743         u16 j;
2744         u16 nvm_offset;
2745
2746         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2747
2748         for (j = 0; j < 4; j++) {
2749                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2750                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2751                 if (ret_val != E1000_SUCCESS)
2752                         goto out;
2753         }
2754
2755 out:
2756         return ret_val;
2757 }
2758
2759 /**
2760  *  __e1000_access_emi_reg - Read/write EMI register
2761  *  @hw: pointer to the HW structure
2762  *  @addr: EMI address to program
2763  *  @data: pointer to value to read/write from/to the EMI address
2764  *  @read: boolean flag to indicate read or write
2765  **/
2766 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2767                                   u16 *data, bool read)
2768 {
2769         s32 ret_val;
2770
2771         DEBUGFUNC("__e1000_access_emi_reg");
2772
2773         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2774         if (ret_val)
2775                 return ret_val;
2776
2777         if (read)
2778                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2779         else
2780                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2781
2782         return ret_val;
2783 }
2784
2785 /**
2786  *  e1000_read_emi_reg - Read Extended Management Interface register
2787  *  @hw: pointer to the HW structure
2788  *  @addr: EMI address to program
2789  *  @data: value to be read from the EMI address
2790  **/
2791 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2792 {
2793         DEBUGFUNC("e1000_read_emi_reg");
2794
2795         return __e1000_access_emi_reg(hw, addr, data, true);
2796 }
2797
2798 /**
2799  *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2800  *  @hw: pointer to the HW structure
2801  *
2802  *  Initialize Marverl 1512 to work correctly with Avoton.
2803  **/
2804 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2805 {
2806         struct e1000_phy_info *phy = &hw->phy;
2807         s32 ret_val = E1000_SUCCESS;
2808
2809         DEBUGFUNC("e1000_initialize_M88E1512_phy");
2810
2811         /* Check if this is correct PHY. */
2812         if (phy->id != M88E1512_E_PHY_ID)
2813                 goto out;
2814
2815         /* Switch to PHY page 0xFF. */
2816         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2817         if (ret_val)
2818                 goto out;
2819
2820         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2821         if (ret_val)
2822                 goto out;
2823
2824         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2825         if (ret_val)
2826                 goto out;
2827
2828         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2829         if (ret_val)
2830                 goto out;
2831
2832         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2833         if (ret_val)
2834                 goto out;
2835
2836         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2837         if (ret_val)
2838                 goto out;
2839
2840         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2841         if (ret_val)
2842                 goto out;
2843
2844         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2845         if (ret_val)
2846                 goto out;
2847
2848         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2849         if (ret_val)
2850                 goto out;
2851
2852         /* Switch to PHY page 0xFB. */
2853         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2854         if (ret_val)
2855                 goto out;
2856
2857         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2858         if (ret_val)
2859                 goto out;
2860
2861         /* Switch to PHY page 0x12. */
2862         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2863         if (ret_val)
2864                 goto out;
2865
2866         /* Change mode to SGMII-to-Copper */
2867         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2868         if (ret_val)
2869                 goto out;
2870
2871         /* Return the PHY to page 0. */
2872         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2873         if (ret_val)
2874                 goto out;
2875
2876         ret_val = phy->ops.commit(hw);
2877         if (ret_val) {
2878                 DEBUGOUT("Error committing the PHY changes\n");
2879                 return ret_val;
2880         }
2881
2882         msec_delay(1000);
2883 out:
2884         return ret_val;
2885 }
2886
2887 /**
2888  *  e1000_set_eee_i350 - Enable/disable EEE support
2889  *  @hw: pointer to the HW structure
2890  *
2891  *  Enable/disable EEE based on setting in dev_spec structure.
2892  *
2893  **/
2894 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2895 {
2896         s32 ret_val = E1000_SUCCESS;
2897         u32 ipcnfg, eeer;
2898
2899         DEBUGFUNC("e1000_set_eee_i350");
2900
2901         if ((hw->mac.type < e1000_i350) ||
2902             (hw->phy.media_type != e1000_media_type_copper))
2903                 goto out;
2904         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2905         eeer = E1000_READ_REG(hw, E1000_EEER);
2906
2907         /* enable or disable per user setting */
2908         if (!(hw->dev_spec._82575.eee_disable)) {
2909                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2910
2911                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2912                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2913                          E1000_EEER_LPI_FC);
2914
2915                 /* This bit should not be set in normal operation. */
2916                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2917                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2918         } else {
2919                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2920                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2921                           E1000_EEER_LPI_FC);
2922         }
2923         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2924         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2925         E1000_READ_REG(hw, E1000_IPCNFG);
2926         E1000_READ_REG(hw, E1000_EEER);
2927 out:
2928
2929         return ret_val;
2930 }
2931
2932 /**
2933  *  e1000_set_eee_i354 - Enable/disable EEE support
2934  *  @hw: pointer to the HW structure
2935  *
2936  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2937  *
2938  **/
2939 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2940 {
2941         struct e1000_phy_info *phy = &hw->phy;
2942         s32 ret_val = E1000_SUCCESS;
2943         u16 phy_data;
2944
2945         DEBUGFUNC("e1000_set_eee_i354");
2946
2947         if ((hw->phy.media_type != e1000_media_type_copper) ||
2948             ((phy->id != M88E1543_E_PHY_ID) &&
2949             (phy->id != M88E1512_E_PHY_ID)))
2950                 goto out;
2951
2952         if (!hw->dev_spec._82575.eee_disable) {
2953                 /* Switch to PHY page 18. */
2954                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2955                 if (ret_val)
2956                         goto out;
2957
2958                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2959                                             &phy_data);
2960                 if (ret_val)
2961                         goto out;
2962
2963                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2964                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2965                                              phy_data);
2966                 if (ret_val)
2967                         goto out;
2968
2969                 /* Return the PHY to page 0. */
2970                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2971                 if (ret_val)
2972                         goto out;
2973
2974                 /* Turn on EEE advertisement. */
2975                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2976                                                E1000_EEE_ADV_DEV_I354,
2977                                                &phy_data);
2978                 if (ret_val)
2979                         goto out;
2980
2981                 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2982                             E1000_EEE_ADV_1000_SUPPORTED;
2983                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2984                                                 E1000_EEE_ADV_DEV_I354,
2985                                                 phy_data);
2986         } else {
2987                 /* Turn off EEE advertisement. */
2988                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2989                                                E1000_EEE_ADV_DEV_I354,
2990                                                &phy_data);
2991                 if (ret_val)
2992                         goto out;
2993
2994                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2995                               E1000_EEE_ADV_1000_SUPPORTED);
2996                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2997                                                 E1000_EEE_ADV_DEV_I354,
2998                                                 phy_data);
2999         }
3000
3001 out:
3002         return ret_val;
3003 }
3004
3005 /**
3006  *  e1000_get_eee_status_i354 - Get EEE status
3007  *  @hw: pointer to the HW structure
3008  *  @status: EEE status
3009  *
3010  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3011  *  been received.
3012  **/
3013 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3014 {
3015         struct e1000_phy_info *phy = &hw->phy;
3016         s32 ret_val = E1000_SUCCESS;
3017         u16 phy_data;
3018
3019         DEBUGFUNC("e1000_get_eee_status_i354");
3020
3021         /* Check if EEE is supported on this device. */
3022         if ((hw->phy.media_type != e1000_media_type_copper) ||
3023             ((phy->id != M88E1543_E_PHY_ID) &&
3024             (phy->id != M88E1512_E_PHY_ID)))
3025                 goto out;
3026
3027         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3028                                        E1000_PCS_STATUS_DEV_I354,
3029                                        &phy_data);
3030         if (ret_val)
3031                 goto out;
3032
3033         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3034                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3035
3036 out:
3037         return ret_val;
3038 }
3039
3040 /* Due to a hw errata, if the host tries to  configure the VFTA register
3041  * while performing queries from the BMC or DMA, then the VFTA in some
3042  * cases won't be written.
3043  */
3044
3045 /**
3046  *  e1000_clear_vfta_i350 - Clear VLAN filter table
3047  *  @hw: pointer to the HW structure
3048  *
3049  *  Clears the register array which contains the VLAN filter table by
3050  *  setting all the values to 0.
3051  **/
3052 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3053 {
3054         u32 offset;
3055         int i;
3056
3057         DEBUGFUNC("e1000_clear_vfta_350");
3058
3059         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3060                 for (i = 0; i < 10; i++)
3061                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3062
3063                 E1000_WRITE_FLUSH(hw);
3064         }
3065 }
3066
3067 /**
3068  *  e1000_write_vfta_i350 - Write value to VLAN filter table
3069  *  @hw: pointer to the HW structure
3070  *  @offset: register offset in VLAN filter table
3071  *  @value: register value written to VLAN filter table
3072  *
3073  *  Writes value at the given offset in the register array which stores
3074  *  the VLAN filter table.
3075  **/
3076 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3077 {
3078         int i;
3079
3080         DEBUGFUNC("e1000_write_vfta_350");
3081
3082         for (i = 0; i < 10; i++)
3083                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3084
3085         E1000_WRITE_FLUSH(hw);
3086 }
3087
3088
3089 /**
3090  *  e1000_set_i2c_bb - Enable I2C bit-bang
3091  *  @hw: pointer to the HW structure
3092  *
3093  *  Enable I2C bit-bang interface
3094  *
3095  **/
3096 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3097 {
3098         s32 ret_val = E1000_SUCCESS;
3099         u32 ctrl_ext, i2cparams;
3100
3101         DEBUGFUNC("e1000_set_i2c_bb");
3102
3103         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3104         ctrl_ext |= E1000_CTRL_I2C_ENA;
3105         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3106         E1000_WRITE_FLUSH(hw);
3107
3108         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3109         i2cparams |= E1000_I2CBB_EN;
3110         i2cparams |= E1000_I2C_DATA_OE_N;
3111         i2cparams |= E1000_I2C_CLK_OE_N;
3112         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3113         E1000_WRITE_FLUSH(hw);
3114
3115         return ret_val;
3116 }
3117
3118 /**
3119  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3120  *  @hw: pointer to hardware structure
3121  *  @byte_offset: byte offset to read
3122  *  @dev_addr: device address
3123  *  @data: value read
3124  *
3125  *  Performs byte read operation over I2C interface at
3126  *  a specified device address.
3127  **/
3128 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3129                                 u8 dev_addr, u8 *data)
3130 {
3131         s32 status = E1000_SUCCESS;
3132         u32 max_retry = 10;
3133         u32 retry = 1;
3134         u16 swfw_mask = 0;
3135
3136         bool nack = true;
3137
3138         DEBUGFUNC("e1000_read_i2c_byte_generic");
3139
3140         swfw_mask = E1000_SWFW_PHY0_SM;
3141
3142         do {
3143                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3144                     != E1000_SUCCESS) {
3145                         status = E1000_ERR_SWFW_SYNC;
3146                         goto read_byte_out;
3147                 }
3148
3149                 e1000_i2c_start(hw);
3150
3151                 /* Device Address and write indication */
3152                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3153                 if (status != E1000_SUCCESS)
3154                         goto fail;
3155
3156                 status = e1000_get_i2c_ack(hw);
3157                 if (status != E1000_SUCCESS)
3158                         goto fail;
3159
3160                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3161                 if (status != E1000_SUCCESS)
3162                         goto fail;
3163
3164                 status = e1000_get_i2c_ack(hw);
3165                 if (status != E1000_SUCCESS)
3166                         goto fail;
3167
3168                 e1000_i2c_start(hw);
3169
3170                 /* Device Address and read indication */
3171                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3172                 if (status != E1000_SUCCESS)
3173                         goto fail;
3174
3175                 status = e1000_get_i2c_ack(hw);
3176                 if (status != E1000_SUCCESS)
3177                         goto fail;
3178
3179                 status = e1000_clock_in_i2c_byte(hw, data);
3180                 if (status != E1000_SUCCESS)
3181                         goto fail;
3182
3183                 status = e1000_clock_out_i2c_bit(hw, nack);
3184                 if (status != E1000_SUCCESS)
3185                         goto fail;
3186
3187                 e1000_i2c_stop(hw);
3188                 break;
3189
3190 fail:
3191                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3192                 msec_delay(100);
3193                 e1000_i2c_bus_clear(hw);
3194                 retry++;
3195                 if (retry < max_retry)
3196                         DEBUGOUT("I2C byte read error - Retrying.\n");
3197                 else
3198                         DEBUGOUT("I2C byte read error.\n");
3199
3200         } while (retry < max_retry);
3201
3202         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3203
3204 read_byte_out:
3205
3206         return status;
3207 }
3208
3209 /**
3210  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3211  *  @hw: pointer to hardware structure
3212  *  @byte_offset: byte offset to write
3213  *  @dev_addr: device address
3214  *  @data: value to write
3215  *
3216  *  Performs byte write operation over I2C interface at
3217  *  a specified device address.
3218  **/
3219 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3220                                  u8 dev_addr, u8 data)
3221 {
3222         s32 status = E1000_SUCCESS;
3223         u32 max_retry = 1;
3224         u32 retry = 0;
3225         u16 swfw_mask = 0;
3226
3227         DEBUGFUNC("e1000_write_i2c_byte_generic");
3228
3229         swfw_mask = E1000_SWFW_PHY0_SM;
3230
3231         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3232                 status = E1000_ERR_SWFW_SYNC;
3233                 goto write_byte_out;
3234         }
3235
3236         do {
3237                 e1000_i2c_start(hw);
3238
3239                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3240                 if (status != E1000_SUCCESS)
3241                         goto fail;
3242
3243                 status = e1000_get_i2c_ack(hw);
3244                 if (status != E1000_SUCCESS)
3245                         goto fail;
3246
3247                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3248                 if (status != E1000_SUCCESS)
3249                         goto fail;
3250
3251                 status = e1000_get_i2c_ack(hw);
3252                 if (status != E1000_SUCCESS)
3253                         goto fail;
3254
3255                 status = e1000_clock_out_i2c_byte(hw, data);
3256                 if (status != E1000_SUCCESS)
3257                         goto fail;
3258
3259                 status = e1000_get_i2c_ack(hw);
3260                 if (status != E1000_SUCCESS)
3261                         goto fail;
3262
3263                 e1000_i2c_stop(hw);
3264                 break;
3265
3266 fail:
3267                 e1000_i2c_bus_clear(hw);
3268                 retry++;
3269                 if (retry < max_retry)
3270                         DEBUGOUT("I2C byte write error - Retrying.\n");
3271                 else
3272                         DEBUGOUT("I2C byte write error.\n");
3273         } while (retry < max_retry);
3274
3275         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3276
3277 write_byte_out:
3278
3279         return status;
3280 }
3281
3282 /**
3283  *  e1000_i2c_start - Sets I2C start condition
3284  *  @hw: pointer to hardware structure
3285  *
3286  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3287  **/
3288 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3289 {
3290         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3291
3292         DEBUGFUNC("e1000_i2c_start");
3293
3294         /* Start condition must begin with data and clock high */
3295         e1000_set_i2c_data(hw, &i2cctl, 1);
3296         e1000_raise_i2c_clk(hw, &i2cctl);
3297
3298         /* Setup time for start condition (4.7us) */
3299         usec_delay(E1000_I2C_T_SU_STA);
3300
3301         e1000_set_i2c_data(hw, &i2cctl, 0);
3302
3303         /* Hold time for start condition (4us) */
3304         usec_delay(E1000_I2C_T_HD_STA);
3305
3306         e1000_lower_i2c_clk(hw, &i2cctl);
3307
3308         /* Minimum low period of clock is 4.7 us */
3309         usec_delay(E1000_I2C_T_LOW);
3310
3311 }
3312
3313 /**
3314  *  e1000_i2c_stop - Sets I2C stop condition
3315  *  @hw: pointer to hardware structure
3316  *
3317  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3318  **/
3319 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3320 {
3321         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3322
3323         DEBUGFUNC("e1000_i2c_stop");
3324
3325         /* Stop condition must begin with data low and clock high */
3326         e1000_set_i2c_data(hw, &i2cctl, 0);
3327         e1000_raise_i2c_clk(hw, &i2cctl);
3328
3329         /* Setup time for stop condition (4us) */
3330         usec_delay(E1000_I2C_T_SU_STO);
3331
3332         e1000_set_i2c_data(hw, &i2cctl, 1);
3333
3334         /* bus free time between stop and start (4.7us)*/
3335         usec_delay(E1000_I2C_T_BUF);
3336 }
3337
3338 /**
3339  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3340  *  @hw: pointer to hardware structure
3341  *  @data: data byte to clock in
3342  *
3343  *  Clocks in one byte data via I2C data/clock
3344  **/
3345 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3346 {
3347         s32 i;
3348         bool bit = 0;
3349
3350         DEBUGFUNC("e1000_clock_in_i2c_byte");
3351
3352         *data = 0;
3353         for (i = 7; i >= 0; i--) {
3354                 e1000_clock_in_i2c_bit(hw, &bit);
3355                 *data |= bit << i;
3356         }
3357
3358         return E1000_SUCCESS;
3359 }
3360
3361 /**
3362  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3363  *  @hw: pointer to hardware structure
3364  *  @data: data byte clocked out
3365  *
3366  *  Clocks out one byte data via I2C data/clock
3367  **/
3368 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3369 {
3370         s32 status = E1000_SUCCESS;
3371         s32 i;
3372         u32 i2cctl;
3373         bool bit = 0;
3374
3375         DEBUGFUNC("e1000_clock_out_i2c_byte");
3376
3377         for (i = 7; i >= 0; i--) {
3378                 bit = (data >> i) & 0x1;
3379                 status = e1000_clock_out_i2c_bit(hw, bit);
3380
3381                 if (status != E1000_SUCCESS)
3382                         break;
3383         }
3384
3385         /* Release SDA line (set high) */
3386         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3387
3388         i2cctl |= E1000_I2C_DATA_OE_N;
3389         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3390         E1000_WRITE_FLUSH(hw);
3391
3392         return status;
3393 }
3394
3395 /**
3396  *  e1000_get_i2c_ack - Polls for I2C ACK
3397  *  @hw: pointer to hardware structure
3398  *
3399  *  Clocks in/out one bit via I2C data/clock
3400  **/
3401 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3402 {
3403         s32 status = E1000_SUCCESS;
3404         u32 i = 0;
3405         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3406         u32 timeout = 10;
3407         bool ack = true;
3408
3409         DEBUGFUNC("e1000_get_i2c_ack");
3410
3411         e1000_raise_i2c_clk(hw, &i2cctl);
3412
3413         /* Minimum high period of clock is 4us */
3414         usec_delay(E1000_I2C_T_HIGH);
3415
3416         /* Wait until SCL returns high */
3417         for (i = 0; i < timeout; i++) {
3418                 usec_delay(1);
3419                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3420                 if (i2cctl & E1000_I2C_CLK_IN)
3421                         break;
3422         }
3423         if (!(i2cctl & E1000_I2C_CLK_IN))
3424                 return E1000_ERR_I2C;
3425
3426         ack = e1000_get_i2c_data(&i2cctl);
3427         if (ack) {
3428                 DEBUGOUT("I2C ack was not received.\n");
3429                 status = E1000_ERR_I2C;
3430         }
3431
3432         e1000_lower_i2c_clk(hw, &i2cctl);
3433
3434         /* Minimum low period of clock is 4.7 us */
3435         usec_delay(E1000_I2C_T_LOW);
3436
3437         return status;
3438 }
3439
3440 /**
3441  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3442  *  @hw: pointer to hardware structure
3443  *  @data: read data value
3444  *
3445  *  Clocks in one bit via I2C data/clock
3446  **/
3447 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3448 {
3449         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3450
3451         DEBUGFUNC("e1000_clock_in_i2c_bit");
3452
3453         e1000_raise_i2c_clk(hw, &i2cctl);
3454
3455         /* Minimum high period of clock is 4us */
3456         usec_delay(E1000_I2C_T_HIGH);
3457
3458         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3459         *data = e1000_get_i2c_data(&i2cctl);
3460
3461         e1000_lower_i2c_clk(hw, &i2cctl);
3462
3463         /* Minimum low period of clock is 4.7 us */
3464         usec_delay(E1000_I2C_T_LOW);
3465
3466         return E1000_SUCCESS;
3467 }
3468
3469 /**
3470  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3471  *  @hw: pointer to hardware structure
3472  *  @data: data value to write
3473  *
3474  *  Clocks out one bit via I2C data/clock
3475  **/
3476 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3477 {
3478         s32 status;
3479         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3480
3481         DEBUGFUNC("e1000_clock_out_i2c_bit");
3482
3483         status = e1000_set_i2c_data(hw, &i2cctl, data);
3484         if (status == E1000_SUCCESS) {
3485                 e1000_raise_i2c_clk(hw, &i2cctl);
3486
3487                 /* Minimum high period of clock is 4us */
3488                 usec_delay(E1000_I2C_T_HIGH);
3489
3490                 e1000_lower_i2c_clk(hw, &i2cctl);
3491
3492                 /* Minimum low period of clock is 4.7 us.
3493                  * This also takes care of the data hold time.
3494                  */
3495                 usec_delay(E1000_I2C_T_LOW);
3496         } else {
3497                 status = E1000_ERR_I2C;
3498                 DEBUGOUT1("I2C data was not set to %X\n", data);
3499         }
3500
3501         return status;
3502 }
3503 /**
3504  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3505  *  @hw: pointer to hardware structure
3506  *  @i2cctl: Current value of I2CCTL register
3507  *
3508  *  Raises the I2C clock line '0'->'1'
3509  **/
3510 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3511 {
3512         DEBUGFUNC("e1000_raise_i2c_clk");
3513
3514         *i2cctl |= E1000_I2C_CLK_OUT;
3515         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3516         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3517         E1000_WRITE_FLUSH(hw);
3518
3519         /* SCL rise time (1000ns) */
3520         usec_delay(E1000_I2C_T_RISE);
3521 }
3522
3523 /**
3524  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3525  *  @hw: pointer to hardware structure
3526  *  @i2cctl: Current value of I2CCTL register
3527  *
3528  *  Lowers the I2C clock line '1'->'0'
3529  **/
3530 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3531 {
3532
3533         DEBUGFUNC("e1000_lower_i2c_clk");
3534
3535         *i2cctl &= ~E1000_I2C_CLK_OUT;
3536         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3537         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3538         E1000_WRITE_FLUSH(hw);
3539
3540         /* SCL fall time (300ns) */
3541         usec_delay(E1000_I2C_T_FALL);
3542 }
3543
3544 /**
3545  *  e1000_set_i2c_data - Sets the I2C data bit
3546  *  @hw: pointer to hardware structure
3547  *  @i2cctl: Current value of I2CCTL register
3548  *  @data: I2C data value (0 or 1) to set
3549  *
3550  *  Sets the I2C data bit
3551  **/
3552 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3553 {
3554         s32 status = E1000_SUCCESS;
3555
3556         DEBUGFUNC("e1000_set_i2c_data");
3557
3558         if (data)
3559                 *i2cctl |= E1000_I2C_DATA_OUT;
3560         else
3561                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3562
3563         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3564         *i2cctl |= E1000_I2C_CLK_OE_N;
3565         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3566         E1000_WRITE_FLUSH(hw);
3567
3568         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3569         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3570
3571         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3572         if (data != e1000_get_i2c_data(i2cctl)) {
3573                 status = E1000_ERR_I2C;
3574                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3575         }
3576
3577         return status;
3578 }
3579
3580 /**
3581  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3582  *  @hw: pointer to hardware structure
3583  *  @i2cctl: Current value of I2CCTL register
3584  *
3585  *  Returns the I2C data bit value
3586  **/
3587 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3588 {
3589         bool data;
3590
3591         DEBUGFUNC("e1000_get_i2c_data");
3592
3593         if (*i2cctl & E1000_I2C_DATA_IN)
3594                 data = 1;
3595         else
3596                 data = 0;
3597
3598         return data;
3599 }
3600
3601 /**
3602  *  e1000_i2c_bus_clear - Clears the I2C bus
3603  *  @hw: pointer to hardware structure
3604  *
3605  *  Clears the I2C bus by sending nine clock pulses.
3606  *  Used when data line is stuck low.
3607  **/
3608 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3609 {
3610         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3611         u32 i;
3612
3613         DEBUGFUNC("e1000_i2c_bus_clear");
3614
3615         e1000_i2c_start(hw);
3616
3617         e1000_set_i2c_data(hw, &i2cctl, 1);
3618
3619         for (i = 0; i < 9; i++) {
3620                 e1000_raise_i2c_clk(hw, &i2cctl);
3621
3622                 /* Min high period of clock is 4us */
3623                 usec_delay(E1000_I2C_T_HIGH);
3624
3625                 e1000_lower_i2c_clk(hw, &i2cctl);
3626
3627                 /* Min low period of clock is 4.7us*/
3628                 usec_delay(E1000_I2C_T_LOW);
3629         }
3630
3631         e1000_i2c_start(hw);
3632
3633         /* Put the i2c bus back to default state */
3634         e1000_i2c_stop(hw);
3635 }
3636