drivers/net/e1000/base/e1000_82575.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 /*
   6  * 82575EB Gigabit Network Connection
   7  * 82575EB Gigabit Backplane Connection
   8  * 82575GB Gigabit Network Connection
   9  * 82576 Gigabit Network Connection
  10  * 82576 Quad Port Gigabit Mezzanine Adapter
  11  * 82580 Gigabit Network Connection
  12  * I350 Gigabit Network Connection
  13  */
  14
  15 #include "e1000_api.h"
  16 #include "e1000_i210.h"
  17
  18 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  19 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  20 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  21 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  22 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  23 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  24 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  25 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  26 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  27 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  28                                          u16 *duplex);
  29 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  30 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  31                                            u16 *data);
  32 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  33 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  34 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  35                                      u32 offset, u16 *data);
  36 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  37                                       u32 offset, u16 data);
  38 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  39                                           bool active);
  40 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  41                                           bool active);
  42 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  43                                           bool active);
  44 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  45 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  46 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  47 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  49 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  50                                             u32 offset, u16 data);
  51 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  52 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  53 STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  54                                                  u16 *speed, u16 *duplex);
  55 STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  56 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  57 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  58 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  60 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  61 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  62 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  63 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  64 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  65 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  66 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  67 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  68 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  69                                                  u16 offset);
  70 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
  71                                                    u16 offset);
  72 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
  73 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
  74 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
  75
  76 STATIC void e1000_i2c_start(struct e1000_hw *hw);
  77 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
  78 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
  79 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
  80 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
  81 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
  82 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
  83 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
  84 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
  85 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
  86 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
  87
  88 STATIC const u16 e1000_82580_rxpbs_table[] = {
  89         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
  90 #define E1000_82580_RXPBS_TABLE_SIZE \
  91         (sizeof(e1000_82580_rxpbs_table) / \
  92          sizeof(e1000_82580_rxpbs_table[0]))
  93
  94
  95 /**
  96  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
  97  *  @hw: pointer to the HW structure
  98  *
  99  *  Called to determine if the I2C pins are being used for I2C or as an
 100  *  external MDIO interface since the two options are mutually exclusive.
 101  **/
 102 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 103 {
 104         u32 reg = 0;
 105         bool ext_mdio = false;
 106
 107         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 108
 109         switch (hw->mac.type) {
 110         case e1000_82575:
 111         case e1000_82576:
 112                 reg = E1000_READ_REG(hw, E1000_MDIC);
 113                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 114                 break;
 115         case e1000_82580:
 116         case e1000_i350:
 117         case e1000_i354:
 118         case e1000_i210:
 119         case e1000_i211:
 120                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 121                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 122                 break;
 123         default:
 124                 break;
 125         }
 126         return ext_mdio;
 127 }
 128
 129 /**
 130  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 131  *  @hw: pointer to the HW structure
 132  **/
 133 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 134 {
 135         struct e1000_phy_info *phy = &hw->phy;
 136         s32 ret_val = E1000_SUCCESS;
 137         u32 ctrl_ext;
 138
 139         DEBUGFUNC("e1000_init_phy_params_82575");
 140
 141         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 142         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 143
 144         if (hw->phy.media_type != e1000_media_type_copper) {
 145                 phy->type = e1000_phy_none;
 146                 goto out;
 147         }
 148
 149         phy->ops.power_up   = e1000_power_up_phy_copper;
 150         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 151
 152         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 153         phy->reset_delay_us     = 100;
 154
 155         phy->ops.acquire        = e1000_acquire_phy_82575;
 156         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 157         phy->ops.commit         = e1000_phy_sw_reset_generic;
 158         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 159         phy->ops.release        = e1000_release_phy_82575;
 160
 161         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 162
 163         if (e1000_sgmii_active_82575(hw)) {
 164                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 165                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 166         } else {
 167                 phy->ops.reset = e1000_phy_hw_reset_generic;
 168                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 169         }
 170
 171         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 172         e1000_reset_mdicnfg_82580(hw);
 173
 174         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 175                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 176                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 177         } else {
 178                 switch (hw->mac.type) {
 179                 case e1000_82580:
 180                 case e1000_i350:
 181                 case e1000_i354:
 182                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 183                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 184                         break;
 185                 case e1000_i210:
 186                 case e1000_i211:
 187                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 188                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 189                         break;
 190                 default:
 191                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 192                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 193                 }
 194         }
 195
 196         /* Set phy->phy_addr and phy->id. */
 197         ret_val = e1000_get_phy_id_82575(hw);
 198
 199         /* Verify phy id and set remaining function pointers */
 200         switch (phy->id) {
 201         case M88E1543_E_PHY_ID:
 202         case M88E1512_E_PHY_ID:
 203         case I347AT4_E_PHY_ID:
 204         case M88E1112_E_PHY_ID:
 205         case M88E1340M_E_PHY_ID:
 206         case M88E1111_I_PHY_ID:
 207                 phy->type               = e1000_phy_m88;
 208                 phy->ops.check_polarity = e1000_check_polarity_m88;
 209                 phy->ops.get_info       = e1000_get_phy_info_m88;
 210                 if (phy->id == I347AT4_E_PHY_ID ||
 211                     phy->id == M88E1112_E_PHY_ID ||
 212                     phy->id == M88E1340M_E_PHY_ID)
 213                         phy->ops.get_cable_length =
 214                                          e1000_get_cable_length_m88_gen2;
 215                 else if (phy->id == M88E1543_E_PHY_ID ||
 216                          phy->id == M88E1512_E_PHY_ID)
 217                         phy->ops.get_cable_length =
 218                                          e1000_get_cable_length_m88_gen2;
 219                 else
 220                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 221                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 222                 /* Check if this PHY is confgured for media swap. */
 223                 if (phy->id == M88E1112_E_PHY_ID) {
 224                         u16 data;
 225
 226                         ret_val = phy->ops.write_reg(hw,
 227                                                      E1000_M88E1112_PAGE_ADDR,
 228                                                      2);
 229                         if (ret_val)
 230                                 goto out;
 231
 232                         ret_val = phy->ops.read_reg(hw,
 233                                                     E1000_M88E1112_MAC_CTRL_1,
 234                                                     &data);
 235                         if (ret_val)
 236                                 goto out;
 237
 238                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 239                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 240                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 241                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 242                                 hw->mac.ops.check_for_link =
 243                                                 e1000_check_for_link_media_swap;
 244                 }
 245                 if (phy->id == M88E1512_E_PHY_ID) {
 246                         ret_val = e1000_initialize_M88E1512_phy(hw);
 247                         if (ret_val)
 248                                 goto out;
 249                 }
 250                 if (phy->id == M88E1543_E_PHY_ID) {
 251                         ret_val = e1000_initialize_M88E1543_phy(hw);
 252                         if (ret_val)
 253                                 goto out;
 254                 }
 255                 break;
 256         case IGP03E1000_E_PHY_ID:
 257         case IGP04E1000_E_PHY_ID:
 258                 phy->type = e1000_phy_igp_3;
 259                 phy->ops.check_polarity = e1000_check_polarity_igp;
 260                 phy->ops.get_info = e1000_get_phy_info_igp;
 261                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 262                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 263                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 264                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 265                 break;
 266         case I82580_I_PHY_ID:
 267         case I350_I_PHY_ID:
 268                 phy->type = e1000_phy_82580;
 269                 phy->ops.check_polarity = e1000_check_polarity_82577;
 270                 phy->ops.force_speed_duplex =
 271                                          e1000_phy_force_speed_duplex_82577;
 272                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 273                 phy->ops.get_info = e1000_get_phy_info_82577;
 274                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 275                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 276                 break;
 277         case I210_I_PHY_ID:
 278                 phy->type               = e1000_phy_i210;
 279                 phy->ops.check_polarity = e1000_check_polarity_m88;
 280                 phy->ops.get_info       = e1000_get_phy_info_m88;
 281                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 282                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 283                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 284                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 285                 break;
 286         case BCM54616_E_PHY_ID:
 287                 phy->type               = e1000_phy_none;
 288                 break;
 289         default:
 290                 ret_val = -E1000_ERR_PHY;
 291                 goto out;
 292         }
 293
 294 out:
 295         return ret_val;
 296 }
 297
 298 /**
 299  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 300  *  @hw: pointer to the HW structure
 301  **/
 302 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 303 {
 304         struct e1000_nvm_info *nvm = &hw->nvm;
 305         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 306         u16 size;
 307
 308         DEBUGFUNC("e1000_init_nvm_params_82575");
 309
 310         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 311                      E1000_EECD_SIZE_EX_SHIFT);
 312         /*
 313          * Added to a constant, "size" becomes the left-shift value
 314          * for setting word_size.
 315          */
 316         size += NVM_WORD_SIZE_BASE_SHIFT;
 317
 318         /* Just in case size is out of range, cap it to the largest
 319          * EEPROM size supported
 320          */
 321         if (size > 15)
 322                 size = 15;
 323
 324         nvm->word_size = 1 << size;
 325         if (hw->mac.type < e1000_i210) {
 326                 nvm->opcode_bits = 8;
 327                 nvm->delay_usec = 1;
 328
 329                 switch (nvm->override) {
 330                 case e1000_nvm_override_spi_large:
 331                         nvm->page_size = 32;
 332                         nvm->address_bits = 16;
 333                         break;
 334                 case e1000_nvm_override_spi_small:
 335                         nvm->page_size = 8;
 336                         nvm->address_bits = 8;
 337                         break;
 338                 default:
 339                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 340                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 341                                             16 : 8;
 342                         break;
 343                 }
 344                 if (nvm->word_size == (1 << 15))
 345                         nvm->page_size = 128;
 346
 347                 nvm->type = e1000_nvm_eeprom_spi;
 348         } else {
 349                 nvm->type = e1000_nvm_flash_hw;
 350         }
 351
 352         /* Function Pointers */
 353         nvm->ops.acquire = e1000_acquire_nvm_82575;
 354         nvm->ops.release = e1000_release_nvm_82575;
 355         if (nvm->word_size < (1 << 15))
 356                 nvm->ops.read = e1000_read_nvm_eerd;
 357         else
 358                 nvm->ops.read = e1000_read_nvm_spi;
 359
 360         nvm->ops.write = e1000_write_nvm_spi;
 361         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 362         nvm->ops.update = e1000_update_nvm_checksum_generic;
 363         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 364
 365         /* override generic family function pointers for specific descendants */
 366         switch (hw->mac.type) {
 367         case e1000_82580:
 368                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 369                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 370                 break;
 371         case e1000_i350:
 372         case e1000_i354:
 373                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 374                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 375                 break;
 376         default:
 377                 break;
 378         }
 379
 380         return E1000_SUCCESS;
 381 }
 382
 383 /**
 384  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 385  *  @hw: pointer to the HW structure
 386  **/
 387 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 388 {
 389         struct e1000_mac_info *mac = &hw->mac;
 390         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 391
 392         DEBUGFUNC("e1000_init_mac_params_82575");
 393
 394         /* Derives media type */
 395         e1000_get_media_type_82575(hw);
 396         /* Set mta register count */
 397         mac->mta_reg_count = 128;
 398         /* Set uta register count */
 399         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 400         /* Set rar entry count */
 401         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 402         if (mac->type == e1000_82576)
 403                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 404         if (mac->type == e1000_82580)
 405                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 406         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 407                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 408
 409         /* Enable EEE default settings for EEE supported devices */
 410         if (mac->type >= e1000_i350)
 411                 dev_spec->eee_disable = false;
 412
 413         /* Allow a single clear of the SW semaphore on I210 and newer */
 414         if (mac->type >= e1000_i210)
 415                 dev_spec->clear_semaphore_once = true;
 416
 417         /* Set if part includes ASF firmware */
 418         mac->asf_firmware_present = true;
 419         /* FWSM register */
 420         mac->has_fwsm = true;
 421         /* ARC supported; valid only if manageability features are enabled. */
 422         mac->arc_subsystem_valid =
 423                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 424
 425         /* Function pointers */
 426
 427         /* bus type/speed/width */
 428         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 429         /* reset */
 430         if (mac->type >= e1000_82580)
 431                 mac->ops.reset_hw = e1000_reset_hw_82580;
 432         else
 433         mac->ops.reset_hw = e1000_reset_hw_82575;
 434         /* hw initialization */
 435         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 436                 mac->ops.init_hw = e1000_init_hw_i210;
 437         else
 438                 mac->ops.init_hw = e1000_init_hw_82575;
 439         /* link setup */
 440         mac->ops.setup_link = e1000_setup_link_generic;
 441         /* physical interface link setup */
 442         mac->ops.setup_physical_interface =
 443                 (hw->phy.media_type == e1000_media_type_copper)
 444                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 445         /* physical interface shutdown */
 446         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 447         /* physical interface power up */
 448         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 449         /* check for link */
 450         mac->ops.check_for_link = e1000_check_for_link_82575;
 451         /* read mac address */
 452         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 453         /* configure collision distance */
 454         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 455         /* multicast address update */
 456         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 457         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 458                 /* writing VFTA */
 459                 mac->ops.write_vfta = e1000_write_vfta_i350;
 460                 /* clearing VFTA */
 461                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 462         } else {
 463                 /* writing VFTA */
 464                 mac->ops.write_vfta = e1000_write_vfta_generic;
 465                 /* clearing VFTA */
 466                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 467         }
 468         if (hw->mac.type >= e1000_82580)
 469                 mac->ops.validate_mdi_setting =
 470                                 e1000_validate_mdi_setting_crossover_generic;
 471         /* ID LED init */
 472         mac->ops.id_led_init = e1000_id_led_init_generic;
 473         /* blink LED */
 474         mac->ops.blink_led = e1000_blink_led_generic;
 475         /* setup LED */
 476         mac->ops.setup_led = e1000_setup_led_generic;
 477         /* cleanup LED */
 478         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 479         /* turn on/off LED */
 480         mac->ops.led_on = e1000_led_on_generic;
 481         mac->ops.led_off = e1000_led_off_generic;
 482         /* clear hardware counters */
 483         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 484         /* link info */
 485         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 486         /* acquire SW_FW sync */
 487         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 488         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 489         if (mac->type == e1000_i210 || mac->type == e1000_i211) {
 490                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 491                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 492         }
 493
 494         /* set lan id for port to determine which phy lock to use */
 495         hw->mac.ops.set_lan_id(hw);
 496
 497         return E1000_SUCCESS;
 498 }
 499
 500 /**
 501  *  e1000_init_function_pointers_82575 - Init func ptrs.
 502  *  @hw: pointer to the HW structure
 503  *
 504  *  Called to initialize all function pointers and parameters.
 505  **/
 506 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 507 {
 508         DEBUGFUNC("e1000_init_function_pointers_82575");
 509
 510         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 511         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 512         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 513         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 514 }
 515
 516 /**
 517  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 518  *  @hw: pointer to the HW structure
 519  *
 520  *  Acquire access rights to the correct PHY.
 521  **/
 522 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 523 {
 524         u16 mask = E1000_SWFW_PHY0_SM;
 525
 526         DEBUGFUNC("e1000_acquire_phy_82575");
 527
 528         if (hw->bus.func == E1000_FUNC_1)
 529                 mask = E1000_SWFW_PHY1_SM;
 530         else if (hw->bus.func == E1000_FUNC_2)
 531                 mask = E1000_SWFW_PHY2_SM;
 532         else if (hw->bus.func == E1000_FUNC_3)
 533                 mask = E1000_SWFW_PHY3_SM;
 534
 535         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 536 }
 537
 538 /**
 539  *  e1000_release_phy_82575 - Release rights to access PHY
 540  *  @hw: pointer to the HW structure
 541  *
 542  *  A wrapper to release access rights to the correct PHY.
 543  **/
 544 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 545 {
 546         u16 mask = E1000_SWFW_PHY0_SM;
 547
 548         DEBUGFUNC("e1000_release_phy_82575");
 549
 550         if (hw->bus.func == E1000_FUNC_1)
 551                 mask = E1000_SWFW_PHY1_SM;
 552         else if (hw->bus.func == E1000_FUNC_2)
 553                 mask = E1000_SWFW_PHY2_SM;
 554         else if (hw->bus.func == E1000_FUNC_3)
 555                 mask = E1000_SWFW_PHY3_SM;
 556
 557         hw->mac.ops.release_swfw_sync(hw, mask);
 558 }
 559
 560 /**
 561  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 562  *  @hw: pointer to the HW structure
 563  *  @offset: register offset to be read
 564  *  @data: pointer to the read data
 565  *
 566  *  Reads the PHY register at offset using the serial gigabit media independent
 567  *  interface and stores the retrieved information in data.
 568  **/
 569 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 570                                           u16 *data)
 571 {
 572         s32 ret_val = -E1000_ERR_PARAM;
 573
 574         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 575
 576         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 577                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 578                 goto out;
 579         }
 580
 581         ret_val = hw->phy.ops.acquire(hw);
 582         if (ret_val)
 583                 goto out;
 584
 585         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 586
 587         hw->phy.ops.release(hw);
 588
 589 out:
 590         return ret_val;
 591 }
 592
 593 /**
 594  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 595  *  @hw: pointer to the HW structure
 596  *  @offset: register offset to write to
 597  *  @data: data to write at register offset
 598  *
 599  *  Writes the data to PHY register at the offset using the serial gigabit
 600  *  media independent interface.
 601  **/
 602 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 603                                            u16 data)
 604 {
 605         s32 ret_val = -E1000_ERR_PARAM;
 606
 607         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 608
 609         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 610                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 611                 goto out;
 612         }
 613
 614         ret_val = hw->phy.ops.acquire(hw);
 615         if (ret_val)
 616                 goto out;
 617
 618         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 619
 620         hw->phy.ops.release(hw);
 621
 622 out:
 623         return ret_val;
 624 }
 625
 626 /**
 627  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 628  *  @hw: pointer to the HW structure
 629  *
 630  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 631  *  sgmi interface.
 632  **/
 633 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 634 {
 635         struct e1000_phy_info *phy = &hw->phy;
 636         s32  ret_val = E1000_SUCCESS;
 637         u16 phy_id;
 638         u32 ctrl_ext;
 639         u32 mdic;
 640
 641         DEBUGFUNC("e1000_get_phy_id_82575");
 642
 643         /* some i354 devices need an extra read for phy id */
 644         if (hw->mac.type == e1000_i354)
 645                 e1000_get_phy_id(hw);
 646
 647         /*
 648          * For SGMII PHYs, we try the list of possible addresses until
 649          * we find one that works.  For non-SGMII PHYs
 650          * (e.g. integrated copper PHYs), an address of 1 should
 651          * work.  The result of this function should mean phy->phy_addr
 652          * and phy->id are set correctly.
 653          */
 654         if (!e1000_sgmii_active_82575(hw)) {
 655                 phy->addr = 1;
 656                 ret_val = e1000_get_phy_id(hw);
 657                 goto out;
 658         }
 659
 660         if (e1000_sgmii_uses_mdio_82575(hw)) {
 661                 switch (hw->mac.type) {
 662                 case e1000_82575:
 663                 case e1000_82576:
 664                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 665                         mdic &= E1000_MDIC_PHY_MASK;
 666                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 667                         break;
 668                 case e1000_82580:
 669                 case e1000_i350:
 670                 case e1000_i354:
 671                 case e1000_i210:
 672                 case e1000_i211:
 673                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 674                         mdic &= E1000_MDICNFG_PHY_MASK;
 675                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 676                         break;
 677                 default:
 678                         ret_val = -E1000_ERR_PHY;
 679                         goto out;
 680                         break;
 681                 }
 682                 ret_val = e1000_get_phy_id(hw);
 683                 goto out;
 684         }
 685
 686         /* Power on sgmii phy if it is disabled */
 687         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 688         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 689                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 690         E1000_WRITE_FLUSH(hw);
 691         msec_delay(300);
 692
 693         /*
 694          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 695          * Therefore, we need to test 1-7
 696          */
 697         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 698                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 699                 if (ret_val == E1000_SUCCESS) {
 700                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 701                                   phy_id, phy->addr);
 702                         /*
 703                          * At the time of this writing, The M88 part is
 704                          * the only supported SGMII PHY product.
 705                          */
 706                         if (phy_id == M88_VENDOR)
 707                                 break;
 708                 } else {
 709                         DEBUGOUT1("PHY address %u was unreadable\n",
 710                                   phy->addr);
 711                 }
 712         }
 713
 714         /* A valid PHY type couldn't be found. */
 715         if (phy->addr == 8) {
 716                 phy->addr = 0;
 717                 ret_val = -E1000_ERR_PHY;
 718         } else {
 719                 ret_val = e1000_get_phy_id(hw);
 720         }
 721
 722         /* restore previous sfp cage power state */
 723         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 724
 725 out:
 726         return ret_val;
 727 }
 728
 729 /**
 730  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 731  *  @hw: pointer to the HW structure
 732  *
 733  *  Resets the PHY using the serial gigabit media independent interface.
 734  **/
 735 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 736 {
 737         s32 ret_val = E1000_SUCCESS;
 738         struct e1000_phy_info *phy = &hw->phy;
 739
 740         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 741
 742         /*
 743          * This isn't a true "hard" reset, but is the only reset
 744          * available to us at this time.
 745          */
 746
 747         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 748
 749         if (!(hw->phy.ops.write_reg))
 750                 goto out;
 751
 752         /*
 753          * SFP documentation requires the following to configure the SPF module
 754          * to work on SGMII.  No further documentation is given.
 755          */
 756         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 757         if (ret_val)
 758                 goto out;
 759
 760         ret_val = hw->phy.ops.commit(hw);
 761         if (ret_val)
 762                 goto out;
 763
 764         if (phy->id == M88E1512_E_PHY_ID)
 765                 ret_val = e1000_initialize_M88E1512_phy(hw);
 766 out:
 767         return ret_val;
 768 }
 769
 770 /**
 771  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 772  *  @hw: pointer to the HW structure
 773  *  @active: true to enable LPLU, false to disable
 774  *
 775  *  Sets the LPLU D0 state according to the active flag.  When
 776  *  activating LPLU this function also disables smart speed
 777  *  and vice versa.  LPLU will not be activated unless the
 778  *  device autonegotiation advertisement meets standards of
 779  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 780  *  This is a function pointer entry point only called by
 781  *  PHY setup routines.
 782  **/
 783 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 784 {
 785         struct e1000_phy_info *phy = &hw->phy;
 786         s32 ret_val = E1000_SUCCESS;
 787         u16 data;
 788
 789         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 790
 791         if (!(hw->phy.ops.read_reg))
 792                 goto out;
 793
 794         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 795         if (ret_val)
 796                 goto out;
 797
 798         if (active) {
 799                 data |= IGP02E1000_PM_D0_LPLU;
 800                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 801                                              data);
 802                 if (ret_val)
 803                         goto out;
 804
 805                 /* When LPLU is enabled, we should disable SmartSpeed */
 806                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 807                                             &data);
 808                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 809                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 810                                              data);
 811                 if (ret_val)
 812                         goto out;
 813         } else {
 814                 data &= ~IGP02E1000_PM_D0_LPLU;
 815                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 816                                              data);
 817                 /*
 818                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 819                  * during Dx states where the power conservation is most
 820                  * important.  During driver activity we should enable
 821                  * SmartSpeed, so performance is maintained.
 822                  */
 823                 if (phy->smart_speed == e1000_smart_speed_on) {
 824                         ret_val = phy->ops.read_reg(hw,
 825                                                     IGP01E1000_PHY_PORT_CONFIG,
 826                                                     &data);
 827                         if (ret_val)
 828                                 goto out;
 829
 830                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 831                         ret_val = phy->ops.write_reg(hw,
 832                                                      IGP01E1000_PHY_PORT_CONFIG,
 833                                                      data);
 834                         if (ret_val)
 835                                 goto out;
 836                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 837                         ret_val = phy->ops.read_reg(hw,
 838                                                     IGP01E1000_PHY_PORT_CONFIG,
 839                                                     &data);
 840                         if (ret_val)
 841                                 goto out;
 842
 843                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 844                         ret_val = phy->ops.write_reg(hw,
 845                                                      IGP01E1000_PHY_PORT_CONFIG,
 846                                                      data);
 847                         if (ret_val)
 848                                 goto out;
 849                 }
 850         }
 851
 852 out:
 853         return ret_val;
 854 }
 855
 856 /**
 857  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 858  *  @hw: pointer to the HW structure
 859  *  @active: true to enable LPLU, false to disable
 860  *
 861  *  Sets the LPLU D0 state according to the active flag.  When
 862  *  activating LPLU this function also disables smart speed
 863  *  and vice versa.  LPLU will not be activated unless the
 864  *  device autonegotiation advertisement meets standards of
 865  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 866  *  This is a function pointer entry point only called by
 867  *  PHY setup routines.
 868  **/
 869 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 870 {
 871         struct e1000_phy_info *phy = &hw->phy;
 872         u32 data;
 873
 874         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 875
 876         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 877
 878         if (active) {
 879                 data |= E1000_82580_PM_D0_LPLU;
 880
 881                 /* When LPLU is enabled, we should disable SmartSpeed */
 882                 data &= ~E1000_82580_PM_SPD;
 883         } else {
 884                 data &= ~E1000_82580_PM_D0_LPLU;
 885
 886                 /*
 887                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 888                  * during Dx states where the power conservation is most
 889                  * important.  During driver activity we should enable
 890                  * SmartSpeed, so performance is maintained.
 891                  */
 892                 if (phy->smart_speed == e1000_smart_speed_on)
 893                         data |= E1000_82580_PM_SPD;
 894                 else if (phy->smart_speed == e1000_smart_speed_off)
 895                         data &= ~E1000_82580_PM_SPD;
 896         }
 897
 898         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 899         return E1000_SUCCESS;
 900 }
 901
 902 /**
 903  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 904  *  @hw: pointer to the HW structure
 905  *  @active: boolean used to enable/disable lplu
 906  *
 907  *  Success returns 0, Failure returns 1
 908  *
 909  *  The low power link up (lplu) state is set to the power management level D3
 910  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 911  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 912  *  is used during Dx states where the power conservation is most important.
 913  *  During driver activity, SmartSpeed should be enabled so performance is
 914  *  maintained.
 915  **/
 916 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 917 {
 918         struct e1000_phy_info *phy = &hw->phy;
 919         u32 data;
 920
 921         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 922
 923         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 924
 925         if (!active) {
 926                 data &= ~E1000_82580_PM_D3_LPLU;
 927                 /*
 928                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 929                  * during Dx states where the power conservation is most
 930                  * important.  During driver activity we should enable
 931                  * SmartSpeed, so performance is maintained.
 932                  */
 933                 if (phy->smart_speed == e1000_smart_speed_on)
 934                         data |= E1000_82580_PM_SPD;
 935                 else if (phy->smart_speed == e1000_smart_speed_off)
 936                         data &= ~E1000_82580_PM_SPD;
 937         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 938                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 939                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 940                 data |= E1000_82580_PM_D3_LPLU;
 941                 /* When LPLU is enabled, we should disable SmartSpeed */
 942                 data &= ~E1000_82580_PM_SPD;
 943         }
 944
 945         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 946         return E1000_SUCCESS;
 947 }
 948
 949 /**
 950  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 951  *  @hw: pointer to the HW structure
 952  *
 953  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 954  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 955  *  Return successful if access grant bit set, else clear the request for
 956  *  EEPROM access and return -E1000_ERR_NVM (-1).
 957  **/
 958 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 959 {
 960         s32 ret_val = E1000_SUCCESS;
 961
 962         DEBUGFUNC("e1000_acquire_nvm_82575");
 963
 964         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 965         if (ret_val)
 966                 goto out;
 967
 968         /*
 969          * Check if there is some access
 970          * error this access may hook on
 971          */
 972         if (hw->mac.type == e1000_i350) {
 973                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 974                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 975                     E1000_EECD_TIMEOUT)) {
 976                         /* Clear all access error flags */
 977                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 978                                         E1000_EECD_ERROR_CLR);
 979                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 980                 }
 981         }
 982
 983         if (hw->mac.type == e1000_82580) {
 984                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 985                 if (eecd & E1000_EECD_BLOCKED) {
 986                         /* Clear access error flag */
 987                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 988                                         E1000_EECD_BLOCKED);
 989                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 990                 }
 991         }
 992
 993         ret_val = e1000_acquire_nvm_generic(hw);
 994         if (ret_val)
 995                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 996
 997 out:
 998         return ret_val;
 999 }
1000
1001 /**
1002  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1003  *  @hw: pointer to the HW structure
1004  *
1005  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1006  *  then release the semaphores acquired.
1007  **/
1008 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1009 {
1010         DEBUGFUNC("e1000_release_nvm_82575");
1011
1012         e1000_release_nvm_generic(hw);
1013
1014         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1015 }
1016
1017 /**
1018  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1019  *  @hw: pointer to the HW structure
1020  *  @mask: specifies which semaphore to acquire
1021  *
1022  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1023  *  will also specify which port we're acquiring the lock for.
1024  **/
1025 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1026 {
1027         u32 swfw_sync;
1028         u32 swmask = mask;
1029         u32 fwmask = mask << 16;
1030         s32 ret_val = E1000_SUCCESS;
1031         s32 i = 0, timeout = 200;
1032
1033         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1034
1035         while (i < timeout) {
1036                 if (e1000_get_hw_semaphore_generic(hw)) {
1037                         ret_val = -E1000_ERR_SWFW_SYNC;
1038                         goto out;
1039                 }
1040
1041                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1042                 if (!(swfw_sync & (fwmask | swmask)))
1043                         break;
1044
1045                 /*
1046                  * Firmware currently using resource (fwmask)
1047                  * or other software thread using resource (swmask)
1048                  */
1049                 e1000_put_hw_semaphore_generic(hw);
1050                 msec_delay_irq(5);
1051                 i++;
1052         }
1053
1054         if (i == timeout) {
1055                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1056                 ret_val = -E1000_ERR_SWFW_SYNC;
1057                 goto out;
1058         }
1059
1060         swfw_sync |= swmask;
1061         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1062
1063         e1000_put_hw_semaphore_generic(hw);
1064
1065 out:
1066         return ret_val;
1067 }
1068
1069 /**
1070  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1071  *  @hw: pointer to the HW structure
1072  *  @mask: specifies which semaphore to acquire
1073  *
1074  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1075  *  will also specify which port we're releasing the lock for.
1076  **/
1077 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1078 {
1079         u32 swfw_sync;
1080
1081         DEBUGFUNC("e1000_release_swfw_sync_82575");
1082
1083         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1084                 ; /* Empty */
1085
1086         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1087         swfw_sync &= ~mask;
1088         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1089
1090         e1000_put_hw_semaphore_generic(hw);
1091 }
1092
1093 /**
1094  *  e1000_get_cfg_done_82575 - Read config done bit
1095  *  @hw: pointer to the HW structure
1096  *
1097  *  Read the management control register for the config done bit for
1098  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1099  *  to read the config done bit, so an error is *ONLY* logged and returns
1100  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1101  *  would not be able to be reset or change link.
1102  **/
1103 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1104 {
1105         s32 timeout = PHY_CFG_TIMEOUT;
1106         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1107
1108         DEBUGFUNC("e1000_get_cfg_done_82575");
1109
1110         if (hw->bus.func == E1000_FUNC_1)
1111                 mask = E1000_NVM_CFG_DONE_PORT_1;
1112         else if (hw->bus.func == E1000_FUNC_2)
1113                 mask = E1000_NVM_CFG_DONE_PORT_2;
1114         else if (hw->bus.func == E1000_FUNC_3)
1115                 mask = E1000_NVM_CFG_DONE_PORT_3;
1116         while (timeout) {
1117                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1118                         break;
1119                 msec_delay(1);
1120                 timeout--;
1121         }
1122         if (!timeout)
1123                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1124
1125         /* If EEPROM is not marked present, init the PHY manually */
1126         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1127             (hw->phy.type == e1000_phy_igp_3))
1128                 e1000_phy_init_script_igp3(hw);
1129
1130         return E1000_SUCCESS;
1131 }
1132
1133 /**
1134  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1135  *  @hw: pointer to the HW structure
1136  *  @speed: stores the current speed
1137  *  @duplex: stores the current duplex
1138  *
1139  *  This is a wrapper function, if using the serial gigabit media independent
1140  *  interface, use PCS to retrieve the link speed and duplex information.
1141  *  Otherwise, use the generic function to get the link speed and duplex info.
1142  **/
1143 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1144                                         u16 *duplex)
1145 {
1146         s32 ret_val;
1147
1148         DEBUGFUNC("e1000_get_link_up_info_82575");
1149
1150         if (hw->phy.media_type != e1000_media_type_copper)
1151                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1152                                                                duplex);
1153         else
1154                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1155                                                                     duplex);
1156
1157         return ret_val;
1158 }
1159
1160 /**
1161  *  e1000_check_for_link_82575 - Check for link
1162  *  @hw: pointer to the HW structure
1163  *
1164  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1165  *  use the generic interface for determining link.
1166  **/
1167 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1168 {
1169         s32 ret_val;
1170         u16 speed, duplex;
1171
1172         DEBUGFUNC("e1000_check_for_link_82575");
1173
1174         if (hw->phy.media_type != e1000_media_type_copper) {
1175                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1176                                                                &duplex);
1177                 /*
1178                  * Use this flag to determine if link needs to be checked or
1179                  * not.  If we have link clear the flag so that we do not
1180                  * continue to check for link.
1181                  */
1182                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1183
1184                 /*
1185                  * Configure Flow Control now that Auto-Neg has completed.
1186                  * First, we need to restore the desired flow control
1187                  * settings because we may have had to re-autoneg with a
1188                  * different link partner.
1189                  */
1190                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1191                 if (ret_val)
1192                         DEBUGOUT("Error configuring flow control\n");
1193         } else {
1194                 ret_val = e1000_check_for_copper_link_generic(hw);
1195         }
1196
1197         return ret_val;
1198 }
1199
1200 /**
1201  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1202  *  @hw: pointer to the HW structure
1203  *
1204  *  Poll the M88E1112 interfaces to see which interface achieved link.
1205  */
1206 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1207 {
1208         struct e1000_phy_info *phy = &hw->phy;
1209         s32 ret_val;
1210         u16 data;
1211         u8 port = 0;
1212
1213         DEBUGFUNC("e1000_check_for_link_media_swap");
1214
1215         /* Check for copper. */
1216         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1217         if (ret_val)
1218                 return ret_val;
1219
1220         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1221         if (ret_val)
1222                 return ret_val;
1223
1224         if (data & E1000_M88E1112_STATUS_LINK)
1225                 port = E1000_MEDIA_PORT_COPPER;
1226
1227         /* Check for other. */
1228         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1229         if (ret_val)
1230                 return ret_val;
1231
1232         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1233         if (ret_val)
1234                 return ret_val;
1235
1236         if (data & E1000_M88E1112_STATUS_LINK)
1237                 port = E1000_MEDIA_PORT_OTHER;
1238
1239         /* Determine if a swap needs to happen. */
1240         if (port && (hw->dev_spec._82575.media_port != port)) {
1241                 hw->dev_spec._82575.media_port = port;
1242                 hw->dev_spec._82575.media_changed = true;
1243         }
1244
1245         if (port == E1000_MEDIA_PORT_COPPER) {
1246                 /* reset page to 0 */
1247                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1248                 if (ret_val)
1249                         return ret_val;
1250                 e1000_check_for_link_82575(hw);
1251         } else {
1252                 e1000_check_for_link_82575(hw);
1253                 /* reset page to 0 */
1254                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1255                 if (ret_val)
1256                         return ret_val;
1257         }
1258
1259         return E1000_SUCCESS;
1260 }
1261
1262 /**
1263  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1264  *  @hw: pointer to the HW structure
1265  **/
1266 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1267 {
1268         u32 reg;
1269
1270         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1271
1272         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1273             !e1000_sgmii_active_82575(hw))
1274                 return;
1275
1276         /* Enable PCS to turn on link */
1277         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1278         reg |= E1000_PCS_CFG_PCS_EN;
1279         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1280
1281         /* Power up the laser */
1282         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1283         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1284         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1285
1286         /* flush the write to verify completion */
1287         E1000_WRITE_FLUSH(hw);
1288         msec_delay(1);
1289 }
1290
1291 /**
1292  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1293  *  @hw: pointer to the HW structure
1294  *  @speed: stores the current speed
1295  *  @duplex: stores the current duplex
1296  *
1297  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1298  *  duplex, then store the values in the pointers provided.
1299  **/
1300 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1301                                                 u16 *speed, u16 *duplex)
1302 {
1303         struct e1000_mac_info *mac = &hw->mac;
1304         u32 pcs;
1305         u32 status;
1306
1307         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1308
1309         /*
1310          * Read the PCS Status register for link state. For non-copper mode,
1311          * the status register is not accurate. The PCS status register is
1312          * used instead.
1313          */
1314         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1315
1316         /*
1317          * The link up bit determines when link is up on autoneg.
1318          */
1319         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1320                 mac->serdes_has_link = true;
1321
1322                 /* Detect and store PCS speed */
1323                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1324                         *speed = SPEED_1000;
1325                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1326                         *speed = SPEED_100;
1327                 else
1328                         *speed = SPEED_10;
1329
1330                 /* Detect and store PCS duplex */
1331                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1332                         *duplex = FULL_DUPLEX;
1333                 else
1334                         *duplex = HALF_DUPLEX;
1335
1336                 /* Check if it is an I354 2.5Gb backplane connection. */
1337                 if (mac->type == e1000_i354) {
1338                         status = E1000_READ_REG(hw, E1000_STATUS);
1339                         if ((status & E1000_STATUS_2P5_SKU) &&
1340                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1341                                 *speed = SPEED_2500;
1342                                 *duplex = FULL_DUPLEX;
1343                                 DEBUGOUT("2500 Mbs, ");
1344                                 DEBUGOUT("Full Duplex\n");
1345                         }
1346                 }
1347
1348         } else {
1349                 mac->serdes_has_link = false;
1350                 *speed = 0;
1351                 *duplex = 0;
1352         }
1353
1354         return E1000_SUCCESS;
1355 }
1356
1357 /**
1358  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1359  *  @hw: pointer to the HW structure
1360  *
1361  *  In the case of serdes shut down sfp and PCS on driver unload
1362  *  when management pass thru is not enabled.
1363  **/
1364 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1365 {
1366         u32 reg;
1367
1368         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1369
1370         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1371             !e1000_sgmii_active_82575(hw))
1372                 return;
1373
1374         if (!e1000_enable_mng_pass_thru(hw)) {
1375                 /* Disable PCS to turn off link */
1376                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1377                 reg &= ~E1000_PCS_CFG_PCS_EN;
1378                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1379
1380                 /* shutdown the laser */
1381                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1382                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1383                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1384
1385                 /* flush the write to verify completion */
1386                 E1000_WRITE_FLUSH(hw);
1387                 msec_delay(1);
1388         }
1389
1390         return;
1391 }
1392
1393 /**
1394  *  e1000_reset_hw_82575 - Reset hardware
1395  *  @hw: pointer to the HW structure
1396  *
1397  *  This resets the hardware into a known state.
1398  **/
1399 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1400 {
1401         u32 ctrl;
1402         s32 ret_val;
1403
1404         DEBUGFUNC("e1000_reset_hw_82575");
1405
1406         /*
1407          * Prevent the PCI-E bus from sticking if there is no TLP connection
1408          * on the last TLP read/write transaction when MAC is reset.
1409          */
1410         ret_val = e1000_disable_pcie_master_generic(hw);
1411         if (ret_val)
1412                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1413
1414         /* set the completion timeout for interface */
1415         ret_val = e1000_set_pcie_completion_timeout(hw);
1416         if (ret_val)
1417                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1418
1419         DEBUGOUT("Masking off all interrupts\n");
1420         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1421
1422         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1423         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1424         E1000_WRITE_FLUSH(hw);
1425
1426         msec_delay(10);
1427
1428         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1429
1430         DEBUGOUT("Issuing a global reset to MAC\n");
1431         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1432
1433         ret_val = e1000_get_auto_rd_done_generic(hw);
1434         if (ret_val) {
1435                 /*
1436                  * When auto config read does not complete, do not
1437                  * return with an error. This can happen in situations
1438                  * where there is no eeprom and prevents getting link.
1439                  */
1440                 DEBUGOUT("Auto Read Done did not complete\n");
1441         }
1442
1443         /* If EEPROM is not present, run manual init scripts */
1444         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1445                 e1000_reset_init_script_82575(hw);
1446
1447         /* Clear any pending interrupt events. */
1448         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1449         E1000_READ_REG(hw, E1000_ICR);
1450
1451         /* Install any alternate MAC address into RAR0 */
1452         ret_val = e1000_check_alt_mac_addr_generic(hw);
1453
1454         return ret_val;
1455 }
1456
1457 /**
1458  *  e1000_init_hw_82575 - Initialize hardware
1459  *  @hw: pointer to the HW structure
1460  *
1461  *  This inits the hardware readying it for operation.
1462  **/
1463 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1464 {
1465         struct e1000_mac_info *mac = &hw->mac;
1466         s32 ret_val;
1467         u16 i, rar_count = mac->rar_entry_count;
1468
1469         DEBUGFUNC("e1000_init_hw_82575");
1470
1471         /* Initialize identification LED */
1472         ret_val = mac->ops.id_led_init(hw);
1473         if (ret_val) {
1474                 DEBUGOUT("Error initializing identification LED\n");
1475                 /* This is not fatal and we should not stop init due to this */
1476         }
1477
1478         /* Disabling VLAN filtering */
1479         DEBUGOUT("Initializing the IEEE VLAN\n");
1480         mac->ops.clear_vfta(hw);
1481
1482         /* Setup the receive address */
1483         e1000_init_rx_addrs_generic(hw, rar_count);
1484
1485         /* Zero out the Multicast HASH table */
1486         DEBUGOUT("Zeroing the MTA\n");
1487         for (i = 0; i < mac->mta_reg_count; i++)
1488                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1489
1490         /* Zero out the Unicast HASH table */
1491         DEBUGOUT("Zeroing the UTA\n");
1492         for (i = 0; i < mac->uta_reg_count; i++)
1493                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1494
1495         /* Setup link and flow control */
1496         ret_val = mac->ops.setup_link(hw);
1497
1498         /* Set the default MTU size */
1499         hw->dev_spec._82575.mtu = 1500;
1500
1501         /*
1502          * Clear all of the statistics registers (clear on read).  It is
1503          * important that we do this after we have tried to establish link
1504          * because the symbol error count will increment wildly if there
1505          * is no link.
1506          */
1507         e1000_clear_hw_cntrs_82575(hw);
1508
1509         return ret_val;
1510 }
1511
1512 /**
1513  *  e1000_setup_copper_link_82575 - Configure copper link settings
1514  *  @hw: pointer to the HW structure
1515  *
1516  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1517  *  for link, once link is established calls to configure collision distance
1518  *  and flow control are called.
1519  **/
1520 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1521 {
1522         u32 ctrl;
1523         s32 ret_val;
1524         u32 phpm_reg;
1525
1526         DEBUGFUNC("e1000_setup_copper_link_82575");
1527
1528         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1529         ctrl |= E1000_CTRL_SLU;
1530         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1531         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1532
1533         /* Clear Go Link Disconnect bit on supported devices */
1534         switch (hw->mac.type) {
1535         case e1000_82580:
1536         case e1000_i350:
1537         case e1000_i210:
1538         case e1000_i211:
1539                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1540                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1541                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1542                 break;
1543         default:
1544                 break;
1545         }
1546
1547         ret_val = e1000_setup_serdes_link_82575(hw);
1548         if (ret_val)
1549                 goto out;
1550
1551         if (e1000_sgmii_active_82575(hw)) {
1552                 /* allow time for SFP cage time to power up phy */
1553                 msec_delay(300);
1554
1555                 ret_val = hw->phy.ops.reset(hw);
1556                 if (ret_val) {
1557                         DEBUGOUT("Error resetting the PHY.\n");
1558                         goto out;
1559                 }
1560         }
1561         switch (hw->phy.type) {
1562         case e1000_phy_i210:
1563         /* Fall through */
1564         case e1000_phy_m88:
1565                 switch (hw->phy.id) {
1566                 case I347AT4_E_PHY_ID:
1567                 /* Fall through */
1568                 case M88E1112_E_PHY_ID:
1569                 /* Fall through */
1570                 case M88E1340M_E_PHY_ID:
1571                 /* Fall through */
1572                 case M88E1543_E_PHY_ID:
1573                 /* Fall through */
1574                 case M88E1512_E_PHY_ID:
1575                 /* Fall through */
1576                 case I210_I_PHY_ID:
1577                 /* Fall through */
1578                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1579                         break;
1580                 default:
1581                         ret_val = e1000_copper_link_setup_m88(hw);
1582                         break;
1583                 }
1584                 break;
1585         case e1000_phy_igp_3:
1586                 ret_val = e1000_copper_link_setup_igp(hw);
1587                 break;
1588         case e1000_phy_82580:
1589                 ret_val = e1000_copper_link_setup_82577(hw);
1590                 break;
1591         case e1000_phy_none:
1592                 break;
1593         default:
1594                 ret_val = -E1000_ERR_PHY;
1595                 break;
1596         }
1597
1598         if (ret_val)
1599                 goto out;
1600
1601         ret_val = e1000_setup_copper_link_generic(hw);
1602 out:
1603         return ret_val;
1604 }
1605
1606 /**
1607  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1608  *  @hw: pointer to the HW structure
1609  *
1610  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1611  *  used on copper connections where the serialized gigabit media independent
1612  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1613  *  for auto-negotiation or forces speed/duplex.
1614  **/
1615 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1616 {
1617         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1618         bool pcs_autoneg;
1619         s32 ret_val = E1000_SUCCESS;
1620         u16 data;
1621
1622         DEBUGFUNC("e1000_setup_serdes_link_82575");
1623
1624         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1625             !e1000_sgmii_active_82575(hw))
1626                 return ret_val;
1627
1628         /*
1629          * On the 82575, SerDes loopback mode persists until it is
1630          * explicitly turned off or a power cycle is performed.  A read to
1631          * the register does not indicate its status.  Therefore, we ensure
1632          * loopback mode is disabled during initialization.
1633          */
1634         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1635
1636         /* power on the sfp cage if present */
1637         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1638         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1639         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1640
1641         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1642         ctrl_reg |= E1000_CTRL_SLU;
1643
1644         /* set both sw defined pins on 82575/82576*/
1645         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1646                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1647
1648         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1649
1650         /* default pcs_autoneg to the same setting as mac autoneg */
1651         pcs_autoneg = hw->mac.autoneg;
1652
1653         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1654         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1655                 /* sgmii mode lets the phy handle forcing speed/duplex */
1656                 pcs_autoneg = true;
1657                 /* autoneg time out should be disabled for SGMII mode */
1658                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1659                 break;
1660         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1661                 /* disable PCS autoneg and support parallel detect only */
1662                 pcs_autoneg = false;
1663                 /* Fall through */
1664         default:
1665                 if (hw->mac.type == e1000_82575 ||
1666                     hw->mac.type == e1000_82576) {
1667                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1668                         if (ret_val) {
1669                                 DEBUGOUT("NVM Read Error\n");
1670                                 return ret_val;
1671                         }
1672
1673                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1674                                 pcs_autoneg = false;
1675                 }
1676
1677                 /*
1678                  * non-SGMII modes only supports a speed of 1000/Full for the
1679                  * link so it is best to just force the MAC and let the pcs
1680                  * link either autoneg or be forced to 1000/Full
1681                  */
1682                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1683                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1684
1685                 /* set speed of 1000/Full if speed/duplex is forced */
1686                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1687                 break;
1688         }
1689
1690         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1691
1692         /*
1693          * New SerDes mode allows for forcing speed or autonegotiating speed
1694          * at 1gb. Autoneg should be default set by most drivers. This is the
1695          * mode that will be compatible with older link partners and switches.
1696          * However, both are supported by the hardware and some drivers/tools.
1697          */
1698         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1699                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1700
1701         if (pcs_autoneg) {
1702                 /* Set PCS register for autoneg */
1703                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1704                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1705
1706                 /* Disable force flow control for autoneg */
1707                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1708
1709                 /* Configure flow control advertisement for autoneg */
1710                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1711                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1712
1713                 switch (hw->fc.requested_mode) {
1714                 case e1000_fc_full:
1715                 case e1000_fc_rx_pause:
1716                         anadv_reg |= E1000_TXCW_ASM_DIR;
1717                         anadv_reg |= E1000_TXCW_PAUSE;
1718                         break;
1719                 case e1000_fc_tx_pause:
1720                         anadv_reg |= E1000_TXCW_ASM_DIR;
1721                         break;
1722                 default:
1723                         break;
1724                 }
1725
1726                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1727
1728                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1729         } else {
1730                 /* Set PCS register for forced link */
1731                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1732
1733                 /* Force flow control for forced link */
1734                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1735
1736                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1737         }
1738
1739         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1740
1741         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1742                 e1000_force_mac_fc_generic(hw);
1743
1744         return ret_val;
1745 }
1746
1747 /**
1748  *  e1000_get_media_type_82575 - derives current media type.
1749  *  @hw: pointer to the HW structure
1750  *
1751  *  The media type is chosen reflecting few settings.
1752  *  The following are taken into account:
1753  *  - link mode set in the current port Init Control Word #3
1754  *  - current link mode settings in CSR register
1755  *  - MDIO vs. I2C PHY control interface chosen
1756  *  - SFP module media type
1757  **/
1758 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1759 {
1760         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1761         s32 ret_val = E1000_SUCCESS;
1762         u32 ctrl_ext = 0;
1763         u32 link_mode = 0;
1764
1765         /* Set internal phy as default */
1766         dev_spec->sgmii_active = false;
1767         dev_spec->module_plugged = false;
1768
1769         /* Get CSR setting */
1770         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1771
1772         /* extract link mode setting */
1773         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1774
1775         switch (link_mode) {
1776         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1777                 hw->phy.media_type = e1000_media_type_internal_serdes;
1778                 break;
1779         case E1000_CTRL_EXT_LINK_MODE_GMII:
1780                 hw->phy.media_type = e1000_media_type_copper;
1781                 break;
1782         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1783                 /* Get phy control interface type set (MDIO vs. I2C)*/
1784                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1785                         hw->phy.media_type = e1000_media_type_copper;
1786                         dev_spec->sgmii_active = true;
1787                         break;
1788                 }
1789                 /* Fall through for I2C based SGMII */
1790         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1791                 /* read media type from SFP EEPROM */
1792                 ret_val = e1000_set_sfp_media_type_82575(hw);
1793                 if ((ret_val != E1000_SUCCESS) ||
1794                     (hw->phy.media_type == e1000_media_type_unknown)) {
1795                         /*
1796                          * If media type was not identified then return media
1797                          * type defined by the CTRL_EXT settings.
1798                          */
1799                         hw->phy.media_type = e1000_media_type_internal_serdes;
1800
1801                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1802                                 hw->phy.media_type = e1000_media_type_copper;
1803                                 dev_spec->sgmii_active = true;
1804                         }
1805
1806                         break;
1807                 }
1808
1809                 /* do not change link mode for 100BaseFX */
1810                 if (dev_spec->eth_flags.e100_base_fx)
1811                         break;
1812
1813                 /* change current link mode setting */
1814                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1815
1816                 if (hw->phy.media_type == e1000_media_type_copper)
1817                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1818                 else
1819                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1820
1821                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1822
1823                 break;
1824         }
1825
1826         return ret_val;
1827 }
1828
1829 /**
1830  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1831  *  @hw: pointer to the HW structure
1832  *
1833  *  The media type is chosen based on SFP module.
1834  *  compatibility flags retrieved from SFP ID EEPROM.
1835  **/
1836 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1837 {
1838         s32 ret_val = E1000_ERR_CONFIG;
1839         u32 ctrl_ext = 0;
1840         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1841         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1842         u8 tranceiver_type = 0;
1843         s32 timeout = 3;
1844
1845         /* Turn I2C interface ON and power on sfp cage */
1846         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1847         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1848         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1849
1850         E1000_WRITE_FLUSH(hw);
1851
1852         /* Read SFP module data */
1853         while (timeout) {
1854                 ret_val = e1000_read_sfp_data_byte(hw,
1855                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1856                         &tranceiver_type);
1857                 if (ret_val == E1000_SUCCESS)
1858                         break;
1859                 msec_delay(100);
1860                 timeout--;
1861         }
1862         if (ret_val != E1000_SUCCESS)
1863                 goto out;
1864
1865         ret_val = e1000_read_sfp_data_byte(hw,
1866                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1867                         (u8 *)eth_flags);
1868         if (ret_val != E1000_SUCCESS)
1869                 goto out;
1870
1871         /* Check if there is some SFP module plugged and powered */
1872         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1873             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1874                 dev_spec->module_plugged = true;
1875                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1876                         hw->phy.media_type = e1000_media_type_internal_serdes;
1877                 } else if (eth_flags->e100_base_fx) {
1878                         dev_spec->sgmii_active = true;
1879                         hw->phy.media_type = e1000_media_type_internal_serdes;
1880                 } else if (eth_flags->e1000_base_t) {
1881                         dev_spec->sgmii_active = true;
1882                         hw->phy.media_type = e1000_media_type_copper;
1883                 } else {
1884                         hw->phy.media_type = e1000_media_type_unknown;
1885                         DEBUGOUT("PHY module has not been recognized\n");
1886                         goto out;
1887                 }
1888         } else {
1889                 hw->phy.media_type = e1000_media_type_unknown;
1890         }
1891         ret_val = E1000_SUCCESS;
1892 out:
1893         /* Restore I2C interface setting */
1894         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1895         return ret_val;
1896 }
1897
1898 /**
1899  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1900  *  @hw: pointer to the HW structure
1901  *  @data: pointer to the NVM (EEPROM)
1902  *
1903  *  Read the EEPROM for the current default LED configuration.  If the
1904  *  LED configuration is not valid, set to a valid LED configuration.
1905  **/
1906 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1907 {
1908         s32 ret_val;
1909
1910         DEBUGFUNC("e1000_valid_led_default_82575");
1911
1912         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1913         if (ret_val) {
1914                 DEBUGOUT("NVM Read Error\n");
1915                 goto out;
1916         }
1917
1918         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1919                 switch (hw->phy.media_type) {
1920                 case e1000_media_type_internal_serdes:
1921                         *data = ID_LED_DEFAULT_82575_SERDES;
1922                         break;
1923                 case e1000_media_type_copper:
1924                 default:
1925                         *data = ID_LED_DEFAULT;
1926                         break;
1927                 }
1928         }
1929 out:
1930         return ret_val;
1931 }
1932
1933 /**
1934  *  e1000_sgmii_active_82575 - Return sgmii state
1935  *  @hw: pointer to the HW structure
1936  *
1937  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1938  *  which can be enabled for use in the embedded applications.  Simply
1939  *  return the current state of the sgmii interface.
1940  **/
1941 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1942 {
1943         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1944         return dev_spec->sgmii_active;
1945 }
1946
1947 /**
1948  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1949  *  @hw: pointer to the HW structure
1950  *
1951  *  Inits recommended HW defaults after a reset when there is no EEPROM
1952  *  detected. This is only for the 82575.
1953  **/
1954 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1955 {
1956         DEBUGFUNC("e1000_reset_init_script_82575");
1957
1958         if (hw->mac.type == e1000_82575) {
1959                 DEBUGOUT("Running reset init script for 82575\n");
1960                 /* SerDes configuration via SERDESCTRL */
1961                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1962                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1963                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1964                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1965
1966                 /* CCM configuration via CCMCTL register */
1967                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1968                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1969
1970                 /* PCIe lanes configuration */
1971                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1972                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1973                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1974                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1975
1976                 /* PCIe PLL Configuration */
1977                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1978                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1979                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1980         }
1981
1982         return E1000_SUCCESS;
1983 }
1984
1985 /**
1986  *  e1000_read_mac_addr_82575 - Read device MAC address
1987  *  @hw: pointer to the HW structure
1988  **/
1989 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1990 {
1991         s32 ret_val;
1992
1993         DEBUGFUNC("e1000_read_mac_addr_82575");
1994
1995         /*
1996          * If there's an alternate MAC address place it in RAR0
1997          * so that it will override the Si installed default perm
1998          * address.
1999          */
2000         ret_val = e1000_check_alt_mac_addr_generic(hw);
2001         if (ret_val)
2002                 goto out;
2003
2004         ret_val = e1000_read_mac_addr_generic(hw);
2005
2006 out:
2007         return ret_val;
2008 }
2009
2010 /**
2011  *  e1000_config_collision_dist_82575 - Configure collision distance
2012  *  @hw: pointer to the HW structure
2013  *
2014  *  Configures the collision distance to the default value and is used
2015  *  during link setup.
2016  **/
2017 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2018 {
2019         u32 tctl_ext;
2020
2021         DEBUGFUNC("e1000_config_collision_dist_82575");
2022
2023         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2024
2025         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2026         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2027
2028         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2029         E1000_WRITE_FLUSH(hw);
2030 }
2031
2032 /**
2033  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2034  * @hw: pointer to the HW structure
2035  *
2036  * In the case of a PHY power down to save power, or to turn off link during a
2037  * driver unload, or wake on lan is not enabled, remove the link.
2038  **/
2039 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2040 {
2041         struct e1000_phy_info *phy = &hw->phy;
2042
2043         if (!(phy->ops.check_reset_block))
2044                 return;
2045
2046         /* If the management interface is not enabled, then power down */
2047         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2048                 e1000_power_down_phy_copper(hw);
2049
2050         return;
2051 }
2052
2053 /**
2054  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2055  *  @hw: pointer to the HW structure
2056  *
2057  *  Clears the hardware counters by reading the counter registers.
2058  **/
2059 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2060 {
2061         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2062
2063         e1000_clear_hw_cntrs_base_generic(hw);
2064
2065         E1000_READ_REG(hw, E1000_PRC64);
2066         E1000_READ_REG(hw, E1000_PRC127);
2067         E1000_READ_REG(hw, E1000_PRC255);
2068         E1000_READ_REG(hw, E1000_PRC511);
2069         E1000_READ_REG(hw, E1000_PRC1023);
2070         E1000_READ_REG(hw, E1000_PRC1522);
2071         E1000_READ_REG(hw, E1000_PTC64);
2072         E1000_READ_REG(hw, E1000_PTC127);
2073         E1000_READ_REG(hw, E1000_PTC255);
2074         E1000_READ_REG(hw, E1000_PTC511);
2075         E1000_READ_REG(hw, E1000_PTC1023);
2076         E1000_READ_REG(hw, E1000_PTC1522);
2077
2078         E1000_READ_REG(hw, E1000_ALGNERRC);
2079         E1000_READ_REG(hw, E1000_RXERRC);
2080         E1000_READ_REG(hw, E1000_TNCRS);
2081         E1000_READ_REG(hw, E1000_CEXTERR);
2082         E1000_READ_REG(hw, E1000_TSCTC);
2083         E1000_READ_REG(hw, E1000_TSCTFC);
2084
2085         E1000_READ_REG(hw, E1000_MGTPRC);
2086         E1000_READ_REG(hw, E1000_MGTPDC);
2087         E1000_READ_REG(hw, E1000_MGTPTC);
2088
2089         E1000_READ_REG(hw, E1000_IAC);
2090         E1000_READ_REG(hw, E1000_ICRXOC);
2091
2092         E1000_READ_REG(hw, E1000_ICRXPTC);
2093         E1000_READ_REG(hw, E1000_ICRXATC);
2094         E1000_READ_REG(hw, E1000_ICTXPTC);
2095         E1000_READ_REG(hw, E1000_ICTXATC);
2096         E1000_READ_REG(hw, E1000_ICTXQEC);
2097         E1000_READ_REG(hw, E1000_ICTXQMTC);
2098         E1000_READ_REG(hw, E1000_ICRXDMTC);
2099
2100         E1000_READ_REG(hw, E1000_CBTMPC);
2101         E1000_READ_REG(hw, E1000_HTDPMC);
2102         E1000_READ_REG(hw, E1000_CBRMPC);
2103         E1000_READ_REG(hw, E1000_RPTHC);
2104         E1000_READ_REG(hw, E1000_HGPTC);
2105         E1000_READ_REG(hw, E1000_HTCBDPC);
2106         E1000_READ_REG(hw, E1000_HGORCL);
2107         E1000_READ_REG(hw, E1000_HGORCH);
2108         E1000_READ_REG(hw, E1000_HGOTCL);
2109         E1000_READ_REG(hw, E1000_HGOTCH);
2110         E1000_READ_REG(hw, E1000_LENERRS);
2111
2112         /* This register should not be read in copper configurations */
2113         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2114             e1000_sgmii_active_82575(hw))
2115                 E1000_READ_REG(hw, E1000_SCVPC);
2116 }
2117
2118 /**
2119  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2120  *  @hw: pointer to the HW structure
2121  *
2122  *  After Rx enable, if manageability is enabled then there is likely some
2123  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2124  *  function clears the fifos and flushes any packets that came in as rx was
2125  *  being enabled.
2126  **/
2127 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2128 {
2129         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2130         int i, ms_wait;
2131
2132         DEBUGFUNC("e1000_rx_fifo_flush_82575");
2133
2134         /* disable IPv6 options as per hardware errata */
2135         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2136         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
2137         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2138
2139         if (hw->mac.type != e1000_82575 ||
2140             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2141                 return;
2142
2143         /* Disable all Rx queues */
2144         for (i = 0; i < 4; i++) {
2145                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2146                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2147                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2148         }
2149         /* Poll all queues to verify they have shut down */
2150         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2151                 msec_delay(1);
2152                 rx_enabled = 0;
2153                 for (i = 0; i < 4; i++)
2154                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2155                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2156                         break;
2157         }
2158
2159         if (ms_wait == 10)
2160                 DEBUGOUT("Queue disable timed out after 10ms\n");
2161
2162         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2163          * incoming packets are rejected.  Set enable and wait 2ms so that
2164          * any packet that was coming in as RCTL.EN was set is flushed
2165          */
2166         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2167
2168         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2169         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2170
2171         rctl = E1000_READ_REG(hw, E1000_RCTL);
2172         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2173         temp_rctl |= E1000_RCTL_LPE;
2174
2175         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2176         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2177         E1000_WRITE_FLUSH(hw);
2178         msec_delay(2);
2179
2180         /* Enable Rx queues that were previously enabled and restore our
2181          * previous state
2182          */
2183         for (i = 0; i < 4; i++)
2184                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2185         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2186         E1000_WRITE_FLUSH(hw);
2187
2188         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2189         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2190
2191         /* Flush receive errors generated by workaround */
2192         E1000_READ_REG(hw, E1000_ROC);
2193         E1000_READ_REG(hw, E1000_RNBC);
2194         E1000_READ_REG(hw, E1000_MPC);
2195 }
2196
2197 /**
2198  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2199  *  @hw: pointer to the HW structure
2200  *
2201  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2202  *  however the hardware default for these parts is 500us to 1ms which is less
2203  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2204  *  increase the value to either 10ms to 200ms for capability version 1 config,
2205  *  or 16ms to 55ms for version 2.
2206  **/
2207 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2208 {
2209         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2210         s32 ret_val = E1000_SUCCESS;
2211         u16 pcie_devctl2;
2212
2213         /* only take action if timeout value is defaulted to 0 */
2214         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2215                 goto out;
2216
2217         /*
2218          * if capababilities version is type 1 we can write the
2219          * timeout of 10ms to 200ms through the GCR register
2220          */
2221         if (!(gcr & E1000_GCR_CAP_VER2)) {
2222                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2223                 goto out;
2224         }
2225
2226         /*
2227          * for version 2 capabilities we need to write the config space
2228          * directly in order to set the completion timeout value for
2229          * 16ms to 55ms
2230          */
2231         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2232                                           &pcie_devctl2);
2233         if (ret_val)
2234                 goto out;
2235
2236         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2237
2238         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2239                                            &pcie_devctl2);
2240 out:
2241         /* disable completion timeout resend */
2242         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2243
2244         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2245         return ret_val;
2246 }
2247
2248 /**
2249  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2250  *  @hw: pointer to the hardware struct
2251  *  @enable: state to enter, either enabled or disabled
2252  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2253  *
2254  *  enables/disables L2 switch anti-spoofing functionality.
2255  **/
2256 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2257 {
2258         u32 reg_val, reg_offset;
2259
2260         switch (hw->mac.type) {
2261         case e1000_82576:
2262                 reg_offset = E1000_DTXSWC;
2263                 break;
2264         case e1000_i350:
2265         case e1000_i354:
2266                 reg_offset = E1000_TXSWC;
2267                 break;
2268         default:
2269                 return;
2270         }
2271
2272         reg_val = E1000_READ_REG(hw, reg_offset);
2273         if (enable) {
2274                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2275                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2276                 /* The PF can spoof - it has to in order to
2277                  * support emulation mode NICs
2278                  */
2279                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2280         } else {
2281                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2282                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2283         }
2284         E1000_WRITE_REG(hw, reg_offset, reg_val);
2285 }
2286
2287 /**
2288  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2289  *  @hw: pointer to the hardware struct
2290  *  @enable: state to enter, either enabled or disabled
2291  *
2292  *  enables/disables L2 switch loopback functionality.
2293  **/
2294 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2295 {
2296         u32 dtxswc;
2297
2298         switch (hw->mac.type) {
2299         case e1000_82576:
2300                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2301                 if (enable)
2302                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2303                 else
2304                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2305                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2306                 break;
2307         case e1000_i350:
2308         case e1000_i354:
2309                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2310                 if (enable)
2311                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2312                 else
2313                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2314                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2315                 break;
2316         default:
2317                 /* Currently no other hardware supports loopback */
2318                 break;
2319         }
2320
2321
2322 }
2323
2324 /**
2325  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2326  *  @hw: pointer to the hardware struct
2327  *  @enable: state to enter, either enabled or disabled
2328  *
2329  *  enables/disables replication of packets across multiple pools.
2330  **/
2331 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2332 {
2333         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2334
2335         if (enable)
2336                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2337         else
2338                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2339
2340         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2341 }
2342
2343 /**
2344  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2345  *  @hw: pointer to the HW structure
2346  *  @offset: register offset to be read
2347  *  @data: pointer to the read data
2348  *
2349  *  Reads the MDI control register in the PHY at offset and stores the
2350  *  information read to data.
2351  **/
2352 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2353 {
2354         s32 ret_val;
2355
2356         DEBUGFUNC("e1000_read_phy_reg_82580");
2357
2358         ret_val = hw->phy.ops.acquire(hw);
2359         if (ret_val)
2360                 goto out;
2361
2362         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2363
2364         hw->phy.ops.release(hw);
2365
2366 out:
2367         return ret_val;
2368 }
2369
2370 /**
2371  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2372  *  @hw: pointer to the HW structure
2373  *  @offset: register offset to write to
2374  *  @data: data to write to register at offset
2375  *
2376  *  Writes data to MDI control register in the PHY at offset.
2377  **/
2378 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2379 {
2380         s32 ret_val;
2381
2382         DEBUGFUNC("e1000_write_phy_reg_82580");
2383
2384         ret_val = hw->phy.ops.acquire(hw);
2385         if (ret_val)
2386                 goto out;
2387
2388         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2389
2390         hw->phy.ops.release(hw);
2391
2392 out:
2393         return ret_val;
2394 }
2395
2396 /**
2397  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2398  *  @hw: pointer to the HW structure
2399  *
2400  *  This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2401  *  the values found in the EEPROM.  This addresses an issue in which these
2402  *  bits are not restored from EEPROM after reset.
2403  **/
2404 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2405 {
2406         s32 ret_val = E1000_SUCCESS;
2407         u32 mdicnfg;
2408         u16 nvm_data = 0;
2409
2410         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2411
2412         if (hw->mac.type != e1000_82580)
2413                 goto out;
2414         if (!e1000_sgmii_active_82575(hw))
2415                 goto out;
2416
2417         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2418                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2419                                    &nvm_data);
2420         if (ret_val) {
2421                 DEBUGOUT("NVM Read Error\n");
2422                 goto out;
2423         }
2424
2425         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2426         if (nvm_data & NVM_WORD24_EXT_MDIO)
2427                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2428         if (nvm_data & NVM_WORD24_COM_MDIO)
2429                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2430         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2431 out:
2432         return ret_val;
2433 }
2434
2435 /**
2436  *  e1000_reset_hw_82580 - Reset hardware
2437  *  @hw: pointer to the HW structure
2438  *
2439  *  This resets function or entire device (all ports, etc.)
2440  *  to a known state.
2441  **/
2442 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2443 {
2444         s32 ret_val = E1000_SUCCESS;
2445         /* BH SW mailbox bit in SW_FW_SYNC */
2446         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2447         u32 ctrl;
2448         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2449
2450         DEBUGFUNC("e1000_reset_hw_82580");
2451
2452         hw->dev_spec._82575.global_device_reset = false;
2453
2454         /* 82580 does not reliably do global_device_reset due to hw errata */
2455         if (hw->mac.type == e1000_82580)
2456                 global_device_reset = false;
2457
2458         /* Get current control state. */
2459         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2460
2461         /*
2462          * Prevent the PCI-E bus from sticking if there is no TLP connection
2463          * on the last TLP read/write transaction when MAC is reset.
2464          */
2465         ret_val = e1000_disable_pcie_master_generic(hw);
2466         if (ret_val)
2467                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2468
2469         DEBUGOUT("Masking off all interrupts\n");
2470         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2471         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2472         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2473         E1000_WRITE_FLUSH(hw);
2474
2475         msec_delay(10);
2476
2477         /* Determine whether or not a global dev reset is requested */
2478         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2479             swmbsw_mask))
2480                         global_device_reset = false;
2481
2482         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2483             E1000_STAT_DEV_RST_SET))
2484                 ctrl |= E1000_CTRL_DEV_RST;
2485         else
2486                 ctrl |= E1000_CTRL_RST;
2487
2488         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2489
2490         switch (hw->device_id) {
2491         case E1000_DEV_ID_DH89XXCC_SGMII:
2492                 break;
2493         default:
2494                 E1000_WRITE_FLUSH(hw);
2495                 break;
2496         }
2497
2498         /* Add delay to insure DEV_RST or RST has time to complete */
2499         msec_delay(5);
2500
2501         ret_val = e1000_get_auto_rd_done_generic(hw);
2502         if (ret_val) {
2503                 /*
2504                  * When auto config read does not complete, do not
2505                  * return with an error. This can happen in situations
2506                  * where there is no eeprom and prevents getting link.
2507                  */
2508                 DEBUGOUT("Auto Read Done did not complete\n");
2509         }
2510
2511         /* clear global device reset status bit */
2512         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2513
2514         /* Clear any pending interrupt events. */
2515         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2516         E1000_READ_REG(hw, E1000_ICR);
2517
2518         ret_val = e1000_reset_mdicnfg_82580(hw);
2519         if (ret_val)
2520                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2521
2522         /* Install any alternate MAC address into RAR0 */
2523         ret_val = e1000_check_alt_mac_addr_generic(hw);
2524
2525         /* Release semaphore */
2526         if (global_device_reset)
2527                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2528
2529         return ret_val;
2530 }
2531
2532 /**
2533  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2534  *  @data: data received by reading RXPBS register
2535  *
2536  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2537  *  This function converts the retrieved value into the correct table value
2538  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2539  *  0x0 36  72 144   1   2   4   8  16
2540  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2541  */
2542 u16 e1000_rxpbs_adjust_82580(u32 data)
2543 {
2544         u16 ret_val = 0;
2545
2546         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2547                 ret_val = e1000_82580_rxpbs_table[data];
2548
2549         return ret_val;
2550 }
2551
2552 /**
2553  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2554  *  checksum
2555  *  @hw: pointer to the HW structure
2556  *  @offset: offset in words of the checksum protected region
2557  *
2558  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2559  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2560  **/
2561 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2562 {
2563         s32 ret_val = E1000_SUCCESS;
2564         u16 checksum = 0;
2565         u16 i, nvm_data;
2566
2567         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2568
2569         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2570                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2571                 if (ret_val) {
2572                         DEBUGOUT("NVM Read Error\n");
2573                         goto out;
2574                 }
2575                 checksum += nvm_data;
2576         }
2577
2578         if (checksum != (u16) NVM_SUM) {
2579                 DEBUGOUT("NVM Checksum Invalid\n");
2580                 ret_val = -E1000_ERR_NVM;
2581                 goto out;
2582         }
2583
2584 out:
2585         return ret_val;
2586 }
2587
2588 /**
2589  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2590  *  checksum
2591  *  @hw: pointer to the HW structure
2592  *  @offset: offset in words of the checksum protected region
2593  *
2594  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2595  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2596  *  value to the EEPROM.
2597  **/
2598 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2599 {
2600         s32 ret_val;
2601         u16 checksum = 0;
2602         u16 i, nvm_data;
2603
2604         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2605
2606         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2607                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2608                 if (ret_val) {
2609                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2610                         goto out;
2611                 }
2612                 checksum += nvm_data;
2613         }
2614         checksum = (u16) NVM_SUM - checksum;
2615         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2616                                     &checksum);
2617         if (ret_val)
2618                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2619
2620 out:
2621         return ret_val;
2622 }
2623
2624 /**
2625  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2626  *  @hw: pointer to the HW structure
2627  *
2628  *  Calculates the EEPROM section checksum by reading/adding each word of
2629  *  the EEPROM and then verifies that the sum of the EEPROM is
2630  *  equal to 0xBABA.
2631  **/
2632 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2633 {
2634         s32 ret_val;
2635         u16 eeprom_regions_count = 1;
2636         u16 j, nvm_data;
2637         u16 nvm_offset;
2638
2639         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2640
2641         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2642         if (ret_val) {
2643                 DEBUGOUT("NVM Read Error\n");
2644                 goto out;
2645         }
2646
2647         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2648                 /* if chekcsums compatibility bit is set validate checksums
2649                  * for all 4 ports. */
2650                 eeprom_regions_count = 4;
2651         }
2652
2653         for (j = 0; j < eeprom_regions_count; j++) {
2654                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2655                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2656                                                                   nvm_offset);
2657                 if (ret_val != E1000_SUCCESS)
2658                         goto out;
2659         }
2660
2661 out:
2662         return ret_val;
2663 }
2664
2665 /**
2666  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2667  *  @hw: pointer to the HW structure
2668  *
2669  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2670  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2671  *  checksum and writes the value to the EEPROM.
2672  **/
2673 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2674 {
2675         s32 ret_val;
2676         u16 j, nvm_data;
2677         u16 nvm_offset;
2678
2679         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2680
2681         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2682         if (ret_val) {
2683                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2684                 goto out;
2685         }
2686
2687         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2688                 /* set compatibility bit to validate checksums appropriately */
2689                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2690                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2691                                             &nvm_data);
2692                 if (ret_val) {
2693                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2694                         goto out;
2695                 }
2696         }
2697
2698         for (j = 0; j < 4; j++) {
2699                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2700                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2701                 if (ret_val)
2702                         goto out;
2703         }
2704
2705 out:
2706         return ret_val;
2707 }
2708
2709 /**
2710  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2711  *  @hw: pointer to the HW structure
2712  *
2713  *  Calculates the EEPROM section checksum by reading/adding each word of
2714  *  the EEPROM and then verifies that the sum of the EEPROM is
2715  *  equal to 0xBABA.
2716  **/
2717 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2718 {
2719         s32 ret_val = E1000_SUCCESS;
2720         u16 j;
2721         u16 nvm_offset;
2722
2723         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2724
2725         for (j = 0; j < 4; j++) {
2726                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2727                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2728                                                                   nvm_offset);
2729                 if (ret_val != E1000_SUCCESS)
2730                         goto out;
2731         }
2732
2733 out:
2734         return ret_val;
2735 }
2736
2737 /**
2738  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2739  *  @hw: pointer to the HW structure
2740  *
2741  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2742  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2743  *  checksum and writes the value to the EEPROM.
2744  **/
2745 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2746 {
2747         s32 ret_val = E1000_SUCCESS;
2748         u16 j;
2749         u16 nvm_offset;
2750
2751         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2752
2753         for (j = 0; j < 4; j++) {
2754                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2755                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2756                 if (ret_val != E1000_SUCCESS)
2757                         goto out;
2758         }
2759
2760 out:
2761         return ret_val;
2762 }
2763
2764 /**
2765  *  __e1000_access_emi_reg - Read/write EMI register
2766  *  @hw: pointer to the HW structure
2767  *  @address: EMI address to program
2768  *  @data: pointer to value to read/write from/to the EMI address
2769  *  @read: boolean flag to indicate read or write
2770  **/
2771 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2772                                   u16 *data, bool read)
2773 {
2774         s32 ret_val;
2775
2776         DEBUGFUNC("__e1000_access_emi_reg");
2777
2778         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2779         if (ret_val)
2780                 return ret_val;
2781
2782         if (read)
2783                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2784         else
2785                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2786
2787         return ret_val;
2788 }
2789
2790 /**
2791  *  e1000_read_emi_reg - Read Extended Management Interface register
2792  *  @hw: pointer to the HW structure
2793  *  @addr: EMI address to program
2794  *  @data: value to be read from the EMI address
2795  **/
2796 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2797 {
2798         DEBUGFUNC("e1000_read_emi_reg");
2799
2800         return __e1000_access_emi_reg(hw, addr, data, true);
2801 }
2802
2803 /**
2804  *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2805  *  @hw: pointer to the HW structure
2806  *
2807  *  Initialize Marvell 1512 to work correctly with Avoton.
2808  **/
2809 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2810 {
2811         struct e1000_phy_info *phy = &hw->phy;
2812         s32 ret_val = E1000_SUCCESS;
2813
2814         DEBUGFUNC("e1000_initialize_M88E1512_phy");
2815
2816         /* Check if this is correct PHY. */
2817         if (phy->id != M88E1512_E_PHY_ID)
2818                 goto out;
2819
2820         /* Switch to PHY page 0xFF. */
2821         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2822         if (ret_val)
2823                 goto out;
2824
2825         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2826         if (ret_val)
2827                 goto out;
2828
2829         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2830         if (ret_val)
2831                 goto out;
2832
2833         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2834         if (ret_val)
2835                 goto out;
2836
2837         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2838         if (ret_val)
2839                 goto out;
2840
2841         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2842         if (ret_val)
2843                 goto out;
2844
2845         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2846         if (ret_val)
2847                 goto out;
2848
2849         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2850         if (ret_val)
2851                 goto out;
2852
2853         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2854         if (ret_val)
2855                 goto out;
2856
2857         /* Switch to PHY page 0xFB. */
2858         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2859         if (ret_val)
2860                 goto out;
2861
2862         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2863         if (ret_val)
2864                 goto out;
2865
2866         /* Switch to PHY page 0x12. */
2867         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2868         if (ret_val)
2869                 goto out;
2870
2871         /* Change mode to SGMII-to-Copper */
2872         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2873         if (ret_val)
2874                 goto out;
2875
2876         /* Return the PHY to page 0. */
2877         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2878         if (ret_val)
2879                 goto out;
2880
2881         ret_val = phy->ops.commit(hw);
2882         if (ret_val) {
2883                 DEBUGOUT("Error committing the PHY changes\n");
2884                 return ret_val;
2885         }
2886
2887         msec_delay(1000);
2888 out:
2889         return ret_val;
2890 }
2891
2892 /**
2893  *  e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2894  *  @hw: pointer to the HW structure
2895  *
2896  *  Initialize Marvell 1543 to work correctly with Avoton.
2897  **/
2898 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2899 {
2900         struct e1000_phy_info *phy = &hw->phy;
2901         s32 ret_val = E1000_SUCCESS;
2902
2903         DEBUGFUNC("e1000_initialize_M88E1543_phy");
2904
2905         /* Check if this is correct PHY. */
2906         if (phy->id != M88E1543_E_PHY_ID)
2907                 goto out;
2908
2909         /* Switch to PHY page 0xFF. */
2910         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2911         if (ret_val)
2912                 goto out;
2913
2914         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2915         if (ret_val)
2916                 goto out;
2917
2918         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2919         if (ret_val)
2920                 goto out;
2921
2922         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2923         if (ret_val)
2924                 goto out;
2925
2926         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2927         if (ret_val)
2928                 goto out;
2929
2930         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2931         if (ret_val)
2932                 goto out;
2933
2934         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2935         if (ret_val)
2936                 goto out;
2937
2938         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2939         if (ret_val)
2940                 goto out;
2941
2942         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2943         if (ret_val)
2944                 goto out;
2945
2946         /* Switch to PHY page 0xFB. */
2947         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2948         if (ret_val)
2949                 goto out;
2950
2951         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2952         if (ret_val)
2953                 goto out;
2954
2955         /* Switch to PHY page 0x12. */
2956         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2957         if (ret_val)
2958                 goto out;
2959
2960         /* Change mode to SGMII-to-Copper */
2961         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2962         if (ret_val)
2963                 goto out;
2964
2965         /* Switch to PHY page 1. */
2966         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2967         if (ret_val)
2968                 goto out;
2969
2970         /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2971         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2972         if (ret_val)
2973                 goto out;
2974
2975         /* Return the PHY to page 0. */
2976         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2977         if (ret_val)
2978                 goto out;
2979
2980         ret_val = phy->ops.commit(hw);
2981         if (ret_val) {
2982                 DEBUGOUT("Error committing the PHY changes\n");
2983                 return ret_val;
2984         }
2985
2986         msec_delay(1000);
2987 out:
2988         return ret_val;
2989 }
2990
2991 /**
2992  *  e1000_set_eee_i350 - Enable/disable EEE support
2993  *  @hw: pointer to the HW structure
2994  *  @adv1G: boolean flag enabling 1G EEE advertisement
2995  *  @adv100M: boolean flag enabling 100M EEE advertisement
2996  *
2997  *  Enable/disable EEE based on setting in dev_spec structure.
2998  *
2999  **/
3000 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
3001 {
3002         u32 ipcnfg, eeer;
3003
3004         DEBUGFUNC("e1000_set_eee_i350");
3005
3006         if ((hw->mac.type < e1000_i350) ||
3007             (hw->phy.media_type != e1000_media_type_copper))
3008                 goto out;
3009         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
3010         eeer = E1000_READ_REG(hw, E1000_EEER);
3011
3012         /* enable or disable per user setting */
3013         if (!(hw->dev_spec._82575.eee_disable)) {
3014                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
3015
3016                 if (adv100M)
3017                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
3018                 else
3019                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
3020
3021                 if (adv1G)
3022                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
3023                 else
3024                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
3025
3026                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3027                          E1000_EEER_LPI_FC);
3028
3029                 /* This bit should not be set in normal operation. */
3030                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
3031                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
3032         } else {
3033                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
3034                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3035                           E1000_EEER_LPI_FC);
3036         }
3037         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
3038         E1000_WRITE_REG(hw, E1000_EEER, eeer);
3039         E1000_READ_REG(hw, E1000_IPCNFG);
3040         E1000_READ_REG(hw, E1000_EEER);
3041 out:
3042
3043         return E1000_SUCCESS;
3044 }
3045
3046 /**
3047  *  e1000_set_eee_i354 - Enable/disable EEE support
3048  *  @hw: pointer to the HW structure
3049  *  @adv1G: boolean flag enabling 1G EEE advertisement
3050  *  @adv100M: boolean flag enabling 100M EEE advertisement
3051  *
3052  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
3053  *
3054  **/
3055 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
3056 {
3057         struct e1000_phy_info *phy = &hw->phy;
3058         s32 ret_val = E1000_SUCCESS;
3059         u16 phy_data;
3060
3061         DEBUGFUNC("e1000_set_eee_i354");
3062
3063         if ((hw->phy.media_type != e1000_media_type_copper) ||
3064             ((phy->id != M88E1543_E_PHY_ID) &&
3065             (phy->id != M88E1512_E_PHY_ID)))
3066                 goto out;
3067
3068         if (!hw->dev_spec._82575.eee_disable) {
3069                 /* Switch to PHY page 18. */
3070                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3071                 if (ret_val)
3072                         goto out;
3073
3074                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3075                                             &phy_data);
3076                 if (ret_val)
3077                         goto out;
3078
3079                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
3080                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3081                                              phy_data);
3082                 if (ret_val)
3083                         goto out;
3084
3085                 /* Return the PHY to page 0. */
3086                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3087                 if (ret_val)
3088                         goto out;
3089
3090                 /* Turn on EEE advertisement. */
3091                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3092                                                E1000_EEE_ADV_DEV_I354,
3093                                                &phy_data);
3094                 if (ret_val)
3095                         goto out;
3096
3097                 if (adv100M)
3098                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
3099                 else
3100                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
3101
3102                 if (adv1G)
3103                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
3104                 else
3105                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
3106
3107                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3108                                                 E1000_EEE_ADV_DEV_I354,
3109                                                 phy_data);
3110         } else {
3111                 /* Turn off EEE advertisement. */
3112                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3113                                                E1000_EEE_ADV_DEV_I354,
3114                                                &phy_data);
3115                 if (ret_val)
3116                         goto out;
3117
3118                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3119                               E1000_EEE_ADV_1000_SUPPORTED);
3120                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3121                                                 E1000_EEE_ADV_DEV_I354,
3122                                                 phy_data);
3123         }
3124
3125 out:
3126         return ret_val;
3127 }
3128
3129 /**
3130  *  e1000_get_eee_status_i354 - Get EEE status
3131  *  @hw: pointer to the HW structure
3132  *  @status: EEE status
3133  *
3134  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3135  *  been received.
3136  **/
3137 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3138 {
3139         struct e1000_phy_info *phy = &hw->phy;
3140         s32 ret_val = E1000_SUCCESS;
3141         u16 phy_data;
3142
3143         DEBUGFUNC("e1000_get_eee_status_i354");
3144
3145         /* Check if EEE is supported on this device. */
3146         if ((hw->phy.media_type != e1000_media_type_copper) ||
3147             ((phy->id != M88E1543_E_PHY_ID) &&
3148             (phy->id != M88E1512_E_PHY_ID)))
3149                 goto out;
3150
3151         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3152                                        E1000_PCS_STATUS_DEV_I354,
3153                                        &phy_data);
3154         if (ret_val)
3155                 goto out;
3156
3157         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3158                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3159
3160 out:
3161         return ret_val;
3162 }
3163
3164 /* Due to a hw errata, if the host tries to  configure the VFTA register
3165  * while performing queries from the BMC or DMA, then the VFTA in some
3166  * cases won't be written.
3167  */
3168
3169 /**
3170  *  e1000_clear_vfta_i350 - Clear VLAN filter table
3171  *  @hw: pointer to the HW structure
3172  *
3173  *  Clears the register array which contains the VLAN filter table by
3174  *  setting all the values to 0.
3175  **/
3176 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3177 {
3178         u32 offset;
3179         int i;
3180
3181         DEBUGFUNC("e1000_clear_vfta_350");
3182
3183         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3184                 for (i = 0; i < 10; i++)
3185                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3186
3187                 E1000_WRITE_FLUSH(hw);
3188         }
3189 }
3190
3191 /**
3192  *  e1000_write_vfta_i350 - Write value to VLAN filter table
3193  *  @hw: pointer to the HW structure
3194  *  @offset: register offset in VLAN filter table
3195  *  @value: register value written to VLAN filter table
3196  *
3197  *  Writes value at the given offset in the register array which stores
3198  *  the VLAN filter table.
3199  **/
3200 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3201 {
3202         int i;
3203
3204         DEBUGFUNC("e1000_write_vfta_350");
3205
3206         for (i = 0; i < 10; i++)
3207                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3208
3209         E1000_WRITE_FLUSH(hw);
3210 }
3211
3212
3213 /**
3214  *  e1000_set_i2c_bb - Enable I2C bit-bang
3215  *  @hw: pointer to the HW structure
3216  *
3217  *  Enable I2C bit-bang interface
3218  *
3219  **/
3220 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3221 {
3222         s32 ret_val = E1000_SUCCESS;
3223         u32 ctrl_ext, i2cparams;
3224
3225         DEBUGFUNC("e1000_set_i2c_bb");
3226
3227         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3228         ctrl_ext |= E1000_CTRL_I2C_ENA;
3229         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3230         E1000_WRITE_FLUSH(hw);
3231
3232         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3233         i2cparams |= E1000_I2CBB_EN;
3234         i2cparams |= E1000_I2C_DATA_OE_N;
3235         i2cparams |= E1000_I2C_CLK_OE_N;
3236         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3237         E1000_WRITE_FLUSH(hw);
3238
3239         return ret_val;
3240 }
3241
3242 /**
3243  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3244  *  @hw: pointer to hardware structure
3245  *  @byte_offset: byte offset to read
3246  *  @dev_addr: device address
3247  *  @data: value read
3248  *
3249  *  Performs byte read operation over I2C interface at
3250  *  a specified device address.
3251  **/
3252 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3253                                 u8 dev_addr, u8 *data)
3254 {
3255         s32 status = E1000_SUCCESS;
3256         u32 max_retry = 10;
3257         u32 retry = 1;
3258         u16 swfw_mask = 0;
3259
3260         bool nack = true;
3261
3262         DEBUGFUNC("e1000_read_i2c_byte_generic");
3263
3264         swfw_mask = E1000_SWFW_PHY0_SM;
3265
3266         do {
3267                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3268                     != E1000_SUCCESS) {
3269                         status = E1000_ERR_SWFW_SYNC;
3270                         goto read_byte_out;
3271                 }
3272
3273                 e1000_i2c_start(hw);
3274
3275                 /* Device Address and write indication */
3276                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3277                 if (status != E1000_SUCCESS)
3278                         goto fail;
3279
3280                 status = e1000_get_i2c_ack(hw);
3281                 if (status != E1000_SUCCESS)
3282                         goto fail;
3283
3284                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3285                 if (status != E1000_SUCCESS)
3286                         goto fail;
3287
3288                 status = e1000_get_i2c_ack(hw);
3289                 if (status != E1000_SUCCESS)
3290                         goto fail;
3291
3292                 e1000_i2c_start(hw);
3293
3294                 /* Device Address and read indication */
3295                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3296                 if (status != E1000_SUCCESS)
3297                         goto fail;
3298
3299                 status = e1000_get_i2c_ack(hw);
3300                 if (status != E1000_SUCCESS)
3301                         goto fail;
3302
3303                 status = e1000_clock_in_i2c_byte(hw, data);
3304                 if (status != E1000_SUCCESS)
3305                         goto fail;
3306
3307                 status = e1000_clock_out_i2c_bit(hw, nack);
3308                 if (status != E1000_SUCCESS)
3309                         goto fail;
3310
3311                 e1000_i2c_stop(hw);
3312                 break;
3313
3314 fail:
3315                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3316                 msec_delay(100);
3317                 e1000_i2c_bus_clear(hw);
3318                 retry++;
3319                 if (retry < max_retry)
3320                         DEBUGOUT("I2C byte read error - Retrying.\n");
3321                 else
3322                         DEBUGOUT("I2C byte read error.\n");
3323
3324         } while (retry < max_retry);
3325
3326         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3327
3328 read_byte_out:
3329
3330         return status;
3331 }
3332
3333 /**
3334  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3335  *  @hw: pointer to hardware structure
3336  *  @byte_offset: byte offset to write
3337  *  @dev_addr: device address
3338  *  @data: value to write
3339  *
3340  *  Performs byte write operation over I2C interface at
3341  *  a specified device address.
3342  **/
3343 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3344                                  u8 dev_addr, u8 data)
3345 {
3346         s32 status = E1000_SUCCESS;
3347         u32 max_retry = 1;
3348         u32 retry = 0;
3349         u16 swfw_mask = 0;
3350
3351         DEBUGFUNC("e1000_write_i2c_byte_generic");
3352
3353         swfw_mask = E1000_SWFW_PHY0_SM;
3354
3355         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3356                 status = E1000_ERR_SWFW_SYNC;
3357                 goto write_byte_out;
3358         }
3359
3360         do {
3361                 e1000_i2c_start(hw);
3362
3363                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3364                 if (status != E1000_SUCCESS)
3365                         goto fail;
3366
3367                 status = e1000_get_i2c_ack(hw);
3368                 if (status != E1000_SUCCESS)
3369                         goto fail;
3370
3371                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3372                 if (status != E1000_SUCCESS)
3373                         goto fail;
3374
3375                 status = e1000_get_i2c_ack(hw);
3376                 if (status != E1000_SUCCESS)
3377                         goto fail;
3378
3379                 status = e1000_clock_out_i2c_byte(hw, data);
3380                 if (status != E1000_SUCCESS)
3381                         goto fail;
3382
3383                 status = e1000_get_i2c_ack(hw);
3384                 if (status != E1000_SUCCESS)
3385                         goto fail;
3386
3387                 e1000_i2c_stop(hw);
3388                 break;
3389
3390 fail:
3391                 e1000_i2c_bus_clear(hw);
3392                 retry++;
3393                 if (retry < max_retry)
3394                         DEBUGOUT("I2C byte write error - Retrying.\n");
3395                 else
3396                         DEBUGOUT("I2C byte write error.\n");
3397         } while (retry < max_retry);
3398
3399         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3400
3401 write_byte_out:
3402
3403         return status;
3404 }
3405
3406 /**
3407  *  e1000_i2c_start - Sets I2C start condition
3408  *  @hw: pointer to hardware structure
3409  *
3410  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3411  **/
3412 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3413 {
3414         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3415
3416         DEBUGFUNC("e1000_i2c_start");
3417
3418         /* Start condition must begin with data and clock high */
3419         e1000_set_i2c_data(hw, &i2cctl, 1);
3420         e1000_raise_i2c_clk(hw, &i2cctl);
3421
3422         /* Setup time for start condition (4.7us) */
3423         usec_delay(E1000_I2C_T_SU_STA);
3424
3425         e1000_set_i2c_data(hw, &i2cctl, 0);
3426
3427         /* Hold time for start condition (4us) */
3428         usec_delay(E1000_I2C_T_HD_STA);
3429
3430         e1000_lower_i2c_clk(hw, &i2cctl);
3431
3432         /* Minimum low period of clock is 4.7 us */
3433         usec_delay(E1000_I2C_T_LOW);
3434
3435 }
3436
3437 /**
3438  *  e1000_i2c_stop - Sets I2C stop condition
3439  *  @hw: pointer to hardware structure
3440  *
3441  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3442  **/
3443 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3444 {
3445         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3446
3447         DEBUGFUNC("e1000_i2c_stop");
3448
3449         /* Stop condition must begin with data low and clock high */
3450         e1000_set_i2c_data(hw, &i2cctl, 0);
3451         e1000_raise_i2c_clk(hw, &i2cctl);
3452
3453         /* Setup time for stop condition (4us) */
3454         usec_delay(E1000_I2C_T_SU_STO);
3455
3456         e1000_set_i2c_data(hw, &i2cctl, 1);
3457
3458         /* bus free time between stop and start (4.7us)*/
3459         usec_delay(E1000_I2C_T_BUF);
3460 }
3461
3462 /**
3463  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3464  *  @hw: pointer to hardware structure
3465  *  @data: data byte to clock in
3466  *
3467  *  Clocks in one byte data via I2C data/clock
3468  **/
3469 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3470 {
3471         s32 i;
3472         bool bit = 0;
3473
3474         DEBUGFUNC("e1000_clock_in_i2c_byte");
3475
3476         *data = 0;
3477         for (i = 7; i >= 0; i--) {
3478                 e1000_clock_in_i2c_bit(hw, &bit);
3479                 *data |= bit << i;
3480         }
3481
3482         return E1000_SUCCESS;
3483 }
3484
3485 /**
3486  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3487  *  @hw: pointer to hardware structure
3488  *  @data: data byte clocked out
3489  *
3490  *  Clocks out one byte data via I2C data/clock
3491  **/
3492 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3493 {
3494         s32 status = E1000_SUCCESS;
3495         s32 i;
3496         u32 i2cctl;
3497         bool bit = 0;
3498
3499         DEBUGFUNC("e1000_clock_out_i2c_byte");
3500
3501         for (i = 7; i >= 0; i--) {
3502                 bit = (data >> i) & 0x1;
3503                 status = e1000_clock_out_i2c_bit(hw, bit);
3504
3505                 if (status != E1000_SUCCESS)
3506                         break;
3507         }
3508
3509         /* Release SDA line (set high) */
3510         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3511
3512         i2cctl |= E1000_I2C_DATA_OE_N;
3513         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3514         E1000_WRITE_FLUSH(hw);
3515
3516         return status;
3517 }
3518
3519 /**
3520  *  e1000_get_i2c_ack - Polls for I2C ACK
3521  *  @hw: pointer to hardware structure
3522  *
3523  *  Clocks in/out one bit via I2C data/clock
3524  **/
3525 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3526 {
3527         s32 status = E1000_SUCCESS;
3528         u32 i = 0;
3529         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3530         u32 timeout = 10;
3531         bool ack = true;
3532
3533         DEBUGFUNC("e1000_get_i2c_ack");
3534
3535         e1000_raise_i2c_clk(hw, &i2cctl);
3536
3537         /* Minimum high period of clock is 4us */
3538         usec_delay(E1000_I2C_T_HIGH);
3539
3540         /* Wait until SCL returns high */
3541         for (i = 0; i < timeout; i++) {
3542                 usec_delay(1);
3543                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3544                 if (i2cctl & E1000_I2C_CLK_IN)
3545                         break;
3546         }
3547         if (!(i2cctl & E1000_I2C_CLK_IN))
3548                 return E1000_ERR_I2C;
3549
3550         ack = e1000_get_i2c_data(&i2cctl);
3551         if (ack) {
3552                 DEBUGOUT("I2C ack was not received.\n");
3553                 status = E1000_ERR_I2C;
3554         }
3555
3556         e1000_lower_i2c_clk(hw, &i2cctl);
3557
3558         /* Minimum low period of clock is 4.7 us */
3559         usec_delay(E1000_I2C_T_LOW);
3560
3561         return status;
3562 }
3563
3564 /**
3565  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3566  *  @hw: pointer to hardware structure
3567  *  @data: read data value
3568  *
3569  *  Clocks in one bit via I2C data/clock
3570  **/
3571 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3572 {
3573         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3574
3575         DEBUGFUNC("e1000_clock_in_i2c_bit");
3576
3577         e1000_raise_i2c_clk(hw, &i2cctl);
3578
3579         /* Minimum high period of clock is 4us */
3580         usec_delay(E1000_I2C_T_HIGH);
3581
3582         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3583         *data = e1000_get_i2c_data(&i2cctl);
3584
3585         e1000_lower_i2c_clk(hw, &i2cctl);
3586
3587         /* Minimum low period of clock is 4.7 us */
3588         usec_delay(E1000_I2C_T_LOW);
3589
3590         return E1000_SUCCESS;
3591 }
3592
3593 /**
3594  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3595  *  @hw: pointer to hardware structure
3596  *  @data: data value to write
3597  *
3598  *  Clocks out one bit via I2C data/clock
3599  **/
3600 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3601 {
3602         s32 status;
3603         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3604
3605         DEBUGFUNC("e1000_clock_out_i2c_bit");
3606
3607         status = e1000_set_i2c_data(hw, &i2cctl, data);
3608         if (status == E1000_SUCCESS) {
3609                 e1000_raise_i2c_clk(hw, &i2cctl);
3610
3611                 /* Minimum high period of clock is 4us */
3612                 usec_delay(E1000_I2C_T_HIGH);
3613
3614                 e1000_lower_i2c_clk(hw, &i2cctl);
3615
3616                 /* Minimum low period of clock is 4.7 us.
3617                  * This also takes care of the data hold time.
3618                  */
3619                 usec_delay(E1000_I2C_T_LOW);
3620         } else {
3621                 status = E1000_ERR_I2C;
3622                 DEBUGOUT1("I2C data was not set to %X\n", data);
3623         }
3624
3625         return status;
3626 }
3627 /**
3628  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3629  *  @hw: pointer to hardware structure
3630  *  @i2cctl: Current value of I2CCTL register
3631  *
3632  *  Raises the I2C clock line '0'->'1'
3633  **/
3634 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3635 {
3636         DEBUGFUNC("e1000_raise_i2c_clk");
3637
3638         *i2cctl |= E1000_I2C_CLK_OUT;
3639         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3640         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3641         E1000_WRITE_FLUSH(hw);
3642
3643         /* SCL rise time (1000ns) */
3644         usec_delay(E1000_I2C_T_RISE);
3645 }
3646
3647 /**
3648  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3649  *  @hw: pointer to hardware structure
3650  *  @i2cctl: Current value of I2CCTL register
3651  *
3652  *  Lowers the I2C clock line '1'->'0'
3653  **/
3654 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3655 {
3656
3657         DEBUGFUNC("e1000_lower_i2c_clk");
3658
3659         *i2cctl &= ~E1000_I2C_CLK_OUT;
3660         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3661         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3662         E1000_WRITE_FLUSH(hw);
3663
3664         /* SCL fall time (300ns) */
3665         usec_delay(E1000_I2C_T_FALL);
3666 }
3667
3668 /**
3669  *  e1000_set_i2c_data - Sets the I2C data bit
3670  *  @hw: pointer to hardware structure
3671  *  @i2cctl: Current value of I2CCTL register
3672  *  @data: I2C data value (0 or 1) to set
3673  *
3674  *  Sets the I2C data bit
3675  **/
3676 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3677 {
3678         s32 status = E1000_SUCCESS;
3679
3680         DEBUGFUNC("e1000_set_i2c_data");
3681
3682         if (data)
3683                 *i2cctl |= E1000_I2C_DATA_OUT;
3684         else
3685                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3686
3687         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3688         *i2cctl |= E1000_I2C_CLK_OE_N;
3689         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3690         E1000_WRITE_FLUSH(hw);
3691
3692         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3693         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3694
3695         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3696         if (data != e1000_get_i2c_data(i2cctl)) {
3697                 status = E1000_ERR_I2C;
3698                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3699         }
3700
3701         return status;
3702 }
3703
3704 /**
3705  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3706  *  @i2cctl: Current value of I2CCTL register
3707  *
3708  *  Returns the I2C data bit value
3709  **/
3710 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3711 {
3712         bool data;
3713
3714         DEBUGFUNC("e1000_get_i2c_data");
3715
3716         if (*i2cctl & E1000_I2C_DATA_IN)
3717                 data = 1;
3718         else
3719                 data = 0;
3720
3721         return data;
3722 }
3723
3724 /**
3725  *  e1000_i2c_bus_clear - Clears the I2C bus
3726  *  @hw: pointer to hardware structure
3727  *
3728  *  Clears the I2C bus by sending nine clock pulses.
3729  *  Used when data line is stuck low.
3730  **/
3731 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3732 {
3733         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3734         u32 i;
3735
3736         DEBUGFUNC("e1000_i2c_bus_clear");
3737
3738         e1000_i2c_start(hw);
3739
3740         e1000_set_i2c_data(hw, &i2cctl, 1);
3741
3742         for (i = 0; i < 9; i++) {
3743                 e1000_raise_i2c_clk(hw, &i2cctl);
3744
3745                 /* Min high period of clock is 4us */
3746                 usec_delay(E1000_I2C_T_HIGH);
3747
3748                 e1000_lower_i2c_clk(hw, &i2cctl);
3749
3750                 /* Min low period of clock is 4.7us*/
3751                 usec_delay(E1000_I2C_T_LOW);
3752         }
3753
3754         e1000_i2c_start(hw);
3755
3756         /* Put the i2c bus back to default state */
3757         e1000_i2c_stop(hw);
3758 }
3759