drivers/net/e1000/base/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  * 82580 Gigabit Network Connection
  41  * I350 Gigabit Network Connection
  42  */
  43
  44 #include "e1000_api.h"
  45 #include "e1000_i210.h"
  46
  47 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  49 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  51 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  53 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  54 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  56 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  57                                          u16 *duplex);
  58 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  60                                            u16 *data);
  61 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  62 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  63 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  64                                      u32 offset, u16 *data);
  65 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  66                                       u32 offset, u16 data);
  67 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  68                                           bool active);
  69 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  70                                           bool active);
  71 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  72                                           bool active);
  73 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  74 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  75 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  76 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  77 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  78 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  79                                             u32 offset, u16 data);
  80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  81 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  82 STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  83                                                  u16 *speed, u16 *duplex);
  84 STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  87 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  88 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  98                                                  u16 offset);
  99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 100                                                    u16 offset);
 101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
 105
 106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
 107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
 108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
 117
 118 STATIC const u16 e1000_82580_rxpbs_table[] = {
 119         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 120 #define E1000_82580_RXPBS_TABLE_SIZE \
 121         (sizeof(e1000_82580_rxpbs_table) / \
 122          sizeof(e1000_82580_rxpbs_table[0]))
 123
 124
 125 /**
 126  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 127  *  @hw: pointer to the HW structure
 128  *
 129  *  Called to determine if the I2C pins are being used for I2C or as an
 130  *  external MDIO interface since the two options are mutually exclusive.
 131  **/
 132 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 133 {
 134         u32 reg = 0;
 135         bool ext_mdio = false;
 136
 137         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 138
 139         switch (hw->mac.type) {
 140         case e1000_82575:
 141         case e1000_82576:
 142                 reg = E1000_READ_REG(hw, E1000_MDIC);
 143                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 144                 break;
 145         case e1000_82580:
 146         case e1000_i350:
 147         case e1000_i354:
 148         case e1000_i210:
 149         case e1000_i211:
 150                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 151                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 152                 break;
 153         default:
 154                 break;
 155         }
 156         return ext_mdio;
 157 }
 158
 159 /**
 160  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 161  *  @hw: pointer to the HW structure
 162  **/
 163 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 164 {
 165         struct e1000_phy_info *phy = &hw->phy;
 166         s32 ret_val = E1000_SUCCESS;
 167         u32 ctrl_ext;
 168
 169         DEBUGFUNC("e1000_init_phy_params_82575");
 170
 171         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 172         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 173
 174         if (hw->phy.media_type != e1000_media_type_copper) {
 175                 phy->type = e1000_phy_none;
 176                 goto out;
 177         }
 178
 179         phy->ops.power_up   = e1000_power_up_phy_copper;
 180         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 181
 182         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 183         phy->reset_delay_us     = 100;
 184
 185         phy->ops.acquire        = e1000_acquire_phy_82575;
 186         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 187         phy->ops.commit         = e1000_phy_sw_reset_generic;
 188         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 189         phy->ops.release        = e1000_release_phy_82575;
 190
 191         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 192
 193         if (e1000_sgmii_active_82575(hw)) {
 194                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 195                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 196         } else {
 197                 phy->ops.reset = e1000_phy_hw_reset_generic;
 198                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 199         }
 200
 201         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 202         e1000_reset_mdicnfg_82580(hw);
 203
 204         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 205                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 206                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 207         } else {
 208                 switch (hw->mac.type) {
 209                 case e1000_82580:
 210                 case e1000_i350:
 211                 case e1000_i354:
 212                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 213                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 214                         break;
 215                 case e1000_i210:
 216                 case e1000_i211:
 217                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 218                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 219                         break;
 220                 default:
 221                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 222                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 223                 }
 224         }
 225
 226         /* Set phy->phy_addr and phy->id. */
 227         ret_val = e1000_get_phy_id_82575(hw);
 228
 229         /* Verify phy id and set remaining function pointers */
 230         switch (phy->id) {
 231         case M88E1543_E_PHY_ID:
 232         case M88E1512_E_PHY_ID:
 233         case I347AT4_E_PHY_ID:
 234         case M88E1112_E_PHY_ID:
 235         case M88E1340M_E_PHY_ID:
 236         case M88E1111_I_PHY_ID:
 237                 phy->type               = e1000_phy_m88;
 238                 phy->ops.check_polarity = e1000_check_polarity_m88;
 239                 phy->ops.get_info       = e1000_get_phy_info_m88;
 240                 if (phy->id == I347AT4_E_PHY_ID ||
 241                     phy->id == M88E1112_E_PHY_ID ||
 242                     phy->id == M88E1340M_E_PHY_ID)
 243                         phy->ops.get_cable_length =
 244                                          e1000_get_cable_length_m88_gen2;
 245                 else if (phy->id == M88E1543_E_PHY_ID ||
 246                          phy->id == M88E1512_E_PHY_ID)
 247                         phy->ops.get_cable_length =
 248                                          e1000_get_cable_length_m88_gen2;
 249                 else
 250                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 251                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 252                 /* Check if this PHY is confgured for media swap. */
 253                 if (phy->id == M88E1112_E_PHY_ID) {
 254                         u16 data;
 255
 256                         ret_val = phy->ops.write_reg(hw,
 257                                                      E1000_M88E1112_PAGE_ADDR,
 258                                                      2);
 259                         if (ret_val)
 260                                 goto out;
 261
 262                         ret_val = phy->ops.read_reg(hw,
 263                                                     E1000_M88E1112_MAC_CTRL_1,
 264                                                     &data);
 265                         if (ret_val)
 266                                 goto out;
 267
 268                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 269                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 270                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 271                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 272                                 hw->mac.ops.check_for_link =
 273                                                 e1000_check_for_link_media_swap;
 274                 }
 275                 if (phy->id == M88E1512_E_PHY_ID) {
 276                         ret_val = e1000_initialize_M88E1512_phy(hw);
 277                         if (ret_val)
 278                                 goto out;
 279                 }
 280                 break;
 281         case IGP03E1000_E_PHY_ID:
 282         case IGP04E1000_E_PHY_ID:
 283                 phy->type = e1000_phy_igp_3;
 284                 phy->ops.check_polarity = e1000_check_polarity_igp;
 285                 phy->ops.get_info = e1000_get_phy_info_igp;
 286                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 287                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 288                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 289                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 290                 break;
 291         case I82580_I_PHY_ID:
 292         case I350_I_PHY_ID:
 293                 phy->type = e1000_phy_82580;
 294                 phy->ops.check_polarity = e1000_check_polarity_82577;
 295                 phy->ops.force_speed_duplex =
 296                                          e1000_phy_force_speed_duplex_82577;
 297                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 298                 phy->ops.get_info = e1000_get_phy_info_82577;
 299                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 300                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 301                 break;
 302         case I210_I_PHY_ID:
 303                 phy->type               = e1000_phy_i210;
 304                 phy->ops.check_polarity = e1000_check_polarity_m88;
 305                 phy->ops.get_info       = e1000_get_phy_info_m88;
 306                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 307                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 308                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 309                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 310                 break;
 311         default:
 312                 ret_val = -E1000_ERR_PHY;
 313                 goto out;
 314         }
 315
 316 out:
 317         return ret_val;
 318 }
 319
 320 /**
 321  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 322  *  @hw: pointer to the HW structure
 323  **/
 324 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 325 {
 326         struct e1000_nvm_info *nvm = &hw->nvm;
 327         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 328         u16 size;
 329
 330         DEBUGFUNC("e1000_init_nvm_params_82575");
 331
 332         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 333                      E1000_EECD_SIZE_EX_SHIFT);
 334         /*
 335          * Added to a constant, "size" becomes the left-shift value
 336          * for setting word_size.
 337          */
 338         size += NVM_WORD_SIZE_BASE_SHIFT;
 339
 340         /* Just in case size is out of range, cap it to the largest
 341          * EEPROM size supported
 342          */
 343         if (size > 15)
 344                 size = 15;
 345
 346         nvm->word_size = 1 << size;
 347         if (hw->mac.type < e1000_i210) {
 348                 nvm->opcode_bits = 8;
 349                 nvm->delay_usec = 1;
 350
 351                 switch (nvm->override) {
 352                 case e1000_nvm_override_spi_large:
 353                         nvm->page_size = 32;
 354                         nvm->address_bits = 16;
 355                         break;
 356                 case e1000_nvm_override_spi_small:
 357                         nvm->page_size = 8;
 358                         nvm->address_bits = 8;
 359                         break;
 360                 default:
 361                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 362                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 363                                             16 : 8;
 364                         break;
 365                 }
 366                 if (nvm->word_size == (1 << 15))
 367                         nvm->page_size = 128;
 368
 369                 nvm->type = e1000_nvm_eeprom_spi;
 370         } else {
 371                 nvm->type = e1000_nvm_flash_hw;
 372         }
 373
 374         /* Function Pointers */
 375         nvm->ops.acquire = e1000_acquire_nvm_82575;
 376         nvm->ops.release = e1000_release_nvm_82575;
 377         if (nvm->word_size < (1 << 15))
 378                 nvm->ops.read = e1000_read_nvm_eerd;
 379         else
 380                 nvm->ops.read = e1000_read_nvm_spi;
 381
 382         nvm->ops.write = e1000_write_nvm_spi;
 383         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 384         nvm->ops.update = e1000_update_nvm_checksum_generic;
 385         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 386
 387         /* override generic family function pointers for specific descendants */
 388         switch (hw->mac.type) {
 389         case e1000_82580:
 390                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 391                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 392                 break;
 393         case e1000_i350:
 394         case e1000_i354:
 395                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 396                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 397                 break;
 398         default:
 399                 break;
 400         }
 401
 402         return E1000_SUCCESS;
 403 }
 404
 405 /**
 406  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 407  *  @hw: pointer to the HW structure
 408  **/
 409 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 410 {
 411         struct e1000_mac_info *mac = &hw->mac;
 412         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 413
 414         DEBUGFUNC("e1000_init_mac_params_82575");
 415
 416         /* Derives media type */
 417         e1000_get_media_type_82575(hw);
 418         /* Set mta register count */
 419         mac->mta_reg_count = 128;
 420         /* Set uta register count */
 421         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 422         /* Set rar entry count */
 423         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 424         if (mac->type == e1000_82576)
 425                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 426         if (mac->type == e1000_82580)
 427                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 428         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 429                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 430
 431         /* Enable EEE default settings for EEE supported devices */
 432         if (mac->type >= e1000_i350)
 433                 dev_spec->eee_disable = false;
 434
 435         /* Allow a single clear of the SW semaphore on I210 and newer */
 436         if (mac->type >= e1000_i210)
 437                 dev_spec->clear_semaphore_once = true;
 438
 439         /* Set if part includes ASF firmware */
 440         mac->asf_firmware_present = true;
 441         /* FWSM register */
 442         mac->has_fwsm = true;
 443         /* ARC supported; valid only if manageability features are enabled. */
 444         mac->arc_subsystem_valid =
 445                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 446
 447         /* Function pointers */
 448
 449         /* bus type/speed/width */
 450         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 451         /* reset */
 452         if (mac->type >= e1000_82580)
 453                 mac->ops.reset_hw = e1000_reset_hw_82580;
 454         else
 455         mac->ops.reset_hw = e1000_reset_hw_82575;
 456         /* hw initialization */
 457         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 458                 mac->ops.init_hw = e1000_init_hw_i210;
 459         else
 460         mac->ops.init_hw = e1000_init_hw_82575;
 461         /* link setup */
 462         mac->ops.setup_link = e1000_setup_link_generic;
 463         /* physical interface link setup */
 464         mac->ops.setup_physical_interface =
 465                 (hw->phy.media_type == e1000_media_type_copper)
 466                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 467         /* physical interface shutdown */
 468         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 469         /* physical interface power up */
 470         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 471         /* check for link */
 472         mac->ops.check_for_link = e1000_check_for_link_82575;
 473         /* read mac address */
 474         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 475         /* configure collision distance */
 476         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 477         /* multicast address update */
 478         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 479         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 480                 /* writing VFTA */
 481                 mac->ops.write_vfta = e1000_write_vfta_i350;
 482                 /* clearing VFTA */
 483                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 484         } else {
 485                 /* writing VFTA */
 486                 mac->ops.write_vfta = e1000_write_vfta_generic;
 487                 /* clearing VFTA */
 488                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 489         }
 490         if (hw->mac.type >= e1000_82580)
 491                 mac->ops.validate_mdi_setting =
 492                                 e1000_validate_mdi_setting_crossover_generic;
 493         /* ID LED init */
 494         mac->ops.id_led_init = e1000_id_led_init_generic;
 495         /* blink LED */
 496         mac->ops.blink_led = e1000_blink_led_generic;
 497         /* setup LED */
 498         mac->ops.setup_led = e1000_setup_led_generic;
 499         /* cleanup LED */
 500         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 501         /* turn on/off LED */
 502         mac->ops.led_on = e1000_led_on_generic;
 503         mac->ops.led_off = e1000_led_off_generic;
 504         /* clear hardware counters */
 505         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 506         /* link info */
 507         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 508         /* acquire SW_FW sync */
 509         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 510         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 511         if (mac->type >= e1000_i210) {
 512                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 513                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 514         }
 515
 516         /* set lan id for port to determine which phy lock to use */
 517         hw->mac.ops.set_lan_id(hw);
 518
 519         return E1000_SUCCESS;
 520 }
 521
 522 /**
 523  *  e1000_init_function_pointers_82575 - Init func ptrs.
 524  *  @hw: pointer to the HW structure
 525  *
 526  *  Called to initialize all function pointers and parameters.
 527  **/
 528 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 529 {
 530         DEBUGFUNC("e1000_init_function_pointers_82575");
 531
 532         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 533         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 534         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 535         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 536 }
 537
 538 /**
 539  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 540  *  @hw: pointer to the HW structure
 541  *
 542  *  Acquire access rights to the correct PHY.
 543  **/
 544 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 545 {
 546         u16 mask = E1000_SWFW_PHY0_SM;
 547
 548         DEBUGFUNC("e1000_acquire_phy_82575");
 549
 550         if (hw->bus.func == E1000_FUNC_1)
 551                 mask = E1000_SWFW_PHY1_SM;
 552         else if (hw->bus.func == E1000_FUNC_2)
 553                 mask = E1000_SWFW_PHY2_SM;
 554         else if (hw->bus.func == E1000_FUNC_3)
 555                 mask = E1000_SWFW_PHY3_SM;
 556
 557         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 558 }
 559
 560 /**
 561  *  e1000_release_phy_82575 - Release rights to access PHY
 562  *  @hw: pointer to the HW structure
 563  *
 564  *  A wrapper to release access rights to the correct PHY.
 565  **/
 566 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 567 {
 568         u16 mask = E1000_SWFW_PHY0_SM;
 569
 570         DEBUGFUNC("e1000_release_phy_82575");
 571
 572         if (hw->bus.func == E1000_FUNC_1)
 573                 mask = E1000_SWFW_PHY1_SM;
 574         else if (hw->bus.func == E1000_FUNC_2)
 575                 mask = E1000_SWFW_PHY2_SM;
 576         else if (hw->bus.func == E1000_FUNC_3)
 577                 mask = E1000_SWFW_PHY3_SM;
 578
 579         hw->mac.ops.release_swfw_sync(hw, mask);
 580 }
 581
 582 /**
 583  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 584  *  @hw: pointer to the HW structure
 585  *  @offset: register offset to be read
 586  *  @data: pointer to the read data
 587  *
 588  *  Reads the PHY register at offset using the serial gigabit media independent
 589  *  interface and stores the retrieved information in data.
 590  **/
 591 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 592                                           u16 *data)
 593 {
 594         s32 ret_val = -E1000_ERR_PARAM;
 595
 596         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 597
 598         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 599                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 600                 goto out;
 601         }
 602
 603         ret_val = hw->phy.ops.acquire(hw);
 604         if (ret_val)
 605                 goto out;
 606
 607         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 608
 609         hw->phy.ops.release(hw);
 610
 611 out:
 612         return ret_val;
 613 }
 614
 615 /**
 616  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 617  *  @hw: pointer to the HW structure
 618  *  @offset: register offset to write to
 619  *  @data: data to write at register offset
 620  *
 621  *  Writes the data to PHY register at the offset using the serial gigabit
 622  *  media independent interface.
 623  **/
 624 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 625                                            u16 data)
 626 {
 627         s32 ret_val = -E1000_ERR_PARAM;
 628
 629         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 630
 631         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 632                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 633                 goto out;
 634         }
 635
 636         ret_val = hw->phy.ops.acquire(hw);
 637         if (ret_val)
 638                 goto out;
 639
 640         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 641
 642         hw->phy.ops.release(hw);
 643
 644 out:
 645         return ret_val;
 646 }
 647
 648 /**
 649  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 650  *  @hw: pointer to the HW structure
 651  *
 652  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 653  *  sgmi interface.
 654  **/
 655 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 656 {
 657         struct e1000_phy_info *phy = &hw->phy;
 658         s32  ret_val = E1000_SUCCESS;
 659         u16 phy_id;
 660         u32 ctrl_ext;
 661         u32 mdic;
 662
 663         DEBUGFUNC("e1000_get_phy_id_82575");
 664
 665         /* some i354 devices need an extra read for phy id */
 666         if (hw->mac.type == e1000_i354)
 667                 e1000_get_phy_id(hw);
 668
 669         /*
 670          * For SGMII PHYs, we try the list of possible addresses until
 671          * we find one that works.  For non-SGMII PHYs
 672          * (e.g. integrated copper PHYs), an address of 1 should
 673          * work.  The result of this function should mean phy->phy_addr
 674          * and phy->id are set correctly.
 675          */
 676         if (!e1000_sgmii_active_82575(hw)) {
 677                 phy->addr = 1;
 678                 ret_val = e1000_get_phy_id(hw);
 679                 goto out;
 680         }
 681
 682         if (e1000_sgmii_uses_mdio_82575(hw)) {
 683                 switch (hw->mac.type) {
 684                 case e1000_82575:
 685                 case e1000_82576:
 686                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 687                         mdic &= E1000_MDIC_PHY_MASK;
 688                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 689                         break;
 690                 case e1000_82580:
 691                 case e1000_i350:
 692                 case e1000_i354:
 693                 case e1000_i210:
 694                 case e1000_i211:
 695                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 696                         mdic &= E1000_MDICNFG_PHY_MASK;
 697                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 698                         break;
 699                 default:
 700                         ret_val = -E1000_ERR_PHY;
 701                         goto out;
 702                         break;
 703                 }
 704                 ret_val = e1000_get_phy_id(hw);
 705                 goto out;
 706         }
 707
 708         /* Power on sgmii phy if it is disabled */
 709         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 710         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 711                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 712         E1000_WRITE_FLUSH(hw);
 713         msec_delay(300);
 714
 715         /*
 716          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 717          * Therefore, we need to test 1-7
 718          */
 719         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 720                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 721                 if (ret_val == E1000_SUCCESS) {
 722                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 723                                   phy_id, phy->addr);
 724                         /*
 725                          * At the time of this writing, The M88 part is
 726                          * the only supported SGMII PHY product.
 727                          */
 728                         if (phy_id == M88_VENDOR)
 729                                 break;
 730                 } else {
 731                         DEBUGOUT1("PHY address %u was unreadable\n",
 732                                   phy->addr);
 733                 }
 734         }
 735
 736         /* A valid PHY type couldn't be found. */
 737         if (phy->addr == 8) {
 738                 phy->addr = 0;
 739                 ret_val = -E1000_ERR_PHY;
 740         } else {
 741                 ret_val = e1000_get_phy_id(hw);
 742         }
 743
 744         /* restore previous sfp cage power state */
 745         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 746
 747 out:
 748         return ret_val;
 749 }
 750
 751 /**
 752  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 753  *  @hw: pointer to the HW structure
 754  *
 755  *  Resets the PHY using the serial gigabit media independent interface.
 756  **/
 757 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 758 {
 759         s32 ret_val = E1000_SUCCESS;
 760         struct e1000_phy_info *phy = &hw->phy;
 761
 762         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 763
 764         /*
 765          * This isn't a true "hard" reset, but is the only reset
 766          * available to us at this time.
 767          */
 768
 769         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 770
 771         if (!(hw->phy.ops.write_reg))
 772                 goto out;
 773
 774         /*
 775          * SFP documentation requires the following to configure the SPF module
 776          * to work on SGMII.  No further documentation is given.
 777          */
 778         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 779         if (ret_val)
 780                 goto out;
 781
 782         ret_val = hw->phy.ops.commit(hw);
 783         if (ret_val)
 784                 goto out;
 785
 786         if (phy->id == M88E1512_E_PHY_ID)
 787                 ret_val = e1000_initialize_M88E1512_phy(hw);
 788 out:
 789         return ret_val;
 790 }
 791
 792 /**
 793  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 794  *  @hw: pointer to the HW structure
 795  *  @active: true to enable LPLU, false to disable
 796  *
 797  *  Sets the LPLU D0 state according to the active flag.  When
 798  *  activating LPLU this function also disables smart speed
 799  *  and vice versa.  LPLU will not be activated unless the
 800  *  device autonegotiation advertisement meets standards of
 801  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 802  *  This is a function pointer entry point only called by
 803  *  PHY setup routines.
 804  **/
 805 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 806 {
 807         struct e1000_phy_info *phy = &hw->phy;
 808         s32 ret_val = E1000_SUCCESS;
 809         u16 data;
 810
 811         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 812
 813         if (!(hw->phy.ops.read_reg))
 814                 goto out;
 815
 816         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 817         if (ret_val)
 818                 goto out;
 819
 820         if (active) {
 821                 data |= IGP02E1000_PM_D0_LPLU;
 822                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 823                                              data);
 824                 if (ret_val)
 825                         goto out;
 826
 827                 /* When LPLU is enabled, we should disable SmartSpeed */
 828                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 829                                             &data);
 830                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 831                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 832                                              data);
 833                 if (ret_val)
 834                         goto out;
 835         } else {
 836                 data &= ~IGP02E1000_PM_D0_LPLU;
 837                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 838                                              data);
 839                 /*
 840                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 841                  * during Dx states where the power conservation is most
 842                  * important.  During driver activity we should enable
 843                  * SmartSpeed, so performance is maintained.
 844                  */
 845                 if (phy->smart_speed == e1000_smart_speed_on) {
 846                         ret_val = phy->ops.read_reg(hw,
 847                                                     IGP01E1000_PHY_PORT_CONFIG,
 848                                                     &data);
 849                         if (ret_val)
 850                                 goto out;
 851
 852                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 853                         ret_val = phy->ops.write_reg(hw,
 854                                                      IGP01E1000_PHY_PORT_CONFIG,
 855                                                      data);
 856                         if (ret_val)
 857                                 goto out;
 858                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 859                         ret_val = phy->ops.read_reg(hw,
 860                                                     IGP01E1000_PHY_PORT_CONFIG,
 861                                                     &data);
 862                         if (ret_val)
 863                                 goto out;
 864
 865                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 866                         ret_val = phy->ops.write_reg(hw,
 867                                                      IGP01E1000_PHY_PORT_CONFIG,
 868                                                      data);
 869                         if (ret_val)
 870                                 goto out;
 871                 }
 872         }
 873
 874 out:
 875         return ret_val;
 876 }
 877
 878 /**
 879  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 880  *  @hw: pointer to the HW structure
 881  *  @active: true to enable LPLU, false to disable
 882  *
 883  *  Sets the LPLU D0 state according to the active flag.  When
 884  *  activating LPLU this function also disables smart speed
 885  *  and vice versa.  LPLU will not be activated unless the
 886  *  device autonegotiation advertisement meets standards of
 887  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 888  *  This is a function pointer entry point only called by
 889  *  PHY setup routines.
 890  **/
 891 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 892 {
 893         struct e1000_phy_info *phy = &hw->phy;
 894         u32 data;
 895
 896         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 897
 898         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 899
 900         if (active) {
 901                 data |= E1000_82580_PM_D0_LPLU;
 902
 903                 /* When LPLU is enabled, we should disable SmartSpeed */
 904                 data &= ~E1000_82580_PM_SPD;
 905         } else {
 906                 data &= ~E1000_82580_PM_D0_LPLU;
 907
 908                 /*
 909                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 910                  * during Dx states where the power conservation is most
 911                  * important.  During driver activity we should enable
 912                  * SmartSpeed, so performance is maintained.
 913                  */
 914                 if (phy->smart_speed == e1000_smart_speed_on)
 915                         data |= E1000_82580_PM_SPD;
 916                 else if (phy->smart_speed == e1000_smart_speed_off)
 917                         data &= ~E1000_82580_PM_SPD;
 918         }
 919
 920         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 921         return E1000_SUCCESS;
 922 }
 923
 924 /**
 925  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 926  *  @hw: pointer to the HW structure
 927  *  @active: boolean used to enable/disable lplu
 928  *
 929  *  Success returns 0, Failure returns 1
 930  *
 931  *  The low power link up (lplu) state is set to the power management level D3
 932  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 933  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 934  *  is used during Dx states where the power conservation is most important.
 935  *  During driver activity, SmartSpeed should be enabled so performance is
 936  *  maintained.
 937  **/
 938 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 939 {
 940         struct e1000_phy_info *phy = &hw->phy;
 941         u32 data;
 942
 943         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 944
 945         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 946
 947         if (!active) {
 948                 data &= ~E1000_82580_PM_D3_LPLU;
 949                 /*
 950                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 951                  * during Dx states where the power conservation is most
 952                  * important.  During driver activity we should enable
 953                  * SmartSpeed, so performance is maintained.
 954                  */
 955                 if (phy->smart_speed == e1000_smart_speed_on)
 956                         data |= E1000_82580_PM_SPD;
 957                 else if (phy->smart_speed == e1000_smart_speed_off)
 958                         data &= ~E1000_82580_PM_SPD;
 959         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 960                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 961                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 962                 data |= E1000_82580_PM_D3_LPLU;
 963                 /* When LPLU is enabled, we should disable SmartSpeed */
 964                 data &= ~E1000_82580_PM_SPD;
 965         }
 966
 967         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 968         return E1000_SUCCESS;
 969 }
 970
 971 /**
 972  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 973  *  @hw: pointer to the HW structure
 974  *
 975  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 976  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 977  *  Return successful if access grant bit set, else clear the request for
 978  *  EEPROM access and return -E1000_ERR_NVM (-1).
 979  **/
 980 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 981 {
 982         s32 ret_val = E1000_SUCCESS;
 983
 984         DEBUGFUNC("e1000_acquire_nvm_82575");
 985
 986         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 987         if (ret_val)
 988                 goto out;
 989
 990         /*
 991          * Check if there is some access
 992          * error this access may hook on
 993          */
 994         if (hw->mac.type == e1000_i350) {
 995                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 996                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 997                     E1000_EECD_TIMEOUT)) {
 998                         /* Clear all access error flags */
 999                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1000                                         E1000_EECD_ERROR_CLR);
1001                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1002                 }
1003         }
1004
1005         if (hw->mac.type == e1000_82580) {
1006                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1007                 if (eecd & E1000_EECD_BLOCKED) {
1008                         /* Clear access error flag */
1009                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1010                                         E1000_EECD_BLOCKED);
1011                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1012                 }
1013         }
1014
1015         ret_val = e1000_acquire_nvm_generic(hw);
1016         if (ret_val)
1017                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1018
1019 out:
1020         return ret_val;
1021 }
1022
1023 /**
1024  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1025  *  @hw: pointer to the HW structure
1026  *
1027  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1028  *  then release the semaphores acquired.
1029  **/
1030 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1031 {
1032         DEBUGFUNC("e1000_release_nvm_82575");
1033
1034         e1000_release_nvm_generic(hw);
1035
1036         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1037 }
1038
1039 /**
1040  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1041  *  @hw: pointer to the HW structure
1042  *  @mask: specifies which semaphore to acquire
1043  *
1044  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1045  *  will also specify which port we're acquiring the lock for.
1046  **/
1047 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1048 {
1049         u32 swfw_sync;
1050         u32 swmask = mask;
1051         u32 fwmask = mask << 16;
1052         s32 ret_val = E1000_SUCCESS;
1053         s32 i = 0, timeout = 200;
1054
1055         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1056
1057         while (i < timeout) {
1058                 if (e1000_get_hw_semaphore_generic(hw)) {
1059                         ret_val = -E1000_ERR_SWFW_SYNC;
1060                         goto out;
1061                 }
1062
1063                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1064                 if (!(swfw_sync & (fwmask | swmask)))
1065                         break;
1066
1067                 /*
1068                  * Firmware currently using resource (fwmask)
1069                  * or other software thread using resource (swmask)
1070                  */
1071                 e1000_put_hw_semaphore_generic(hw);
1072                 msec_delay_irq(5);
1073                 i++;
1074         }
1075
1076         if (i == timeout) {
1077                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1078                 ret_val = -E1000_ERR_SWFW_SYNC;
1079                 goto out;
1080         }
1081
1082         swfw_sync |= swmask;
1083         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1084
1085         e1000_put_hw_semaphore_generic(hw);
1086
1087 out:
1088         return ret_val;
1089 }
1090
1091 /**
1092  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1093  *  @hw: pointer to the HW structure
1094  *  @mask: specifies which semaphore to acquire
1095  *
1096  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1097  *  will also specify which port we're releasing the lock for.
1098  **/
1099 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1100 {
1101         u32 swfw_sync;
1102
1103         DEBUGFUNC("e1000_release_swfw_sync_82575");
1104
1105         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1106                 ; /* Empty */
1107
1108         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1109         swfw_sync &= ~mask;
1110         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1111
1112         e1000_put_hw_semaphore_generic(hw);
1113 }
1114
1115 /**
1116  *  e1000_get_cfg_done_82575 - Read config done bit
1117  *  @hw: pointer to the HW structure
1118  *
1119  *  Read the management control register for the config done bit for
1120  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1121  *  to read the config done bit, so an error is *ONLY* logged and returns
1122  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1123  *  would not be able to be reset or change link.
1124  **/
1125 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1126 {
1127         s32 timeout = PHY_CFG_TIMEOUT;
1128         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1129
1130         DEBUGFUNC("e1000_get_cfg_done_82575");
1131
1132         if (hw->bus.func == E1000_FUNC_1)
1133                 mask = E1000_NVM_CFG_DONE_PORT_1;
1134         else if (hw->bus.func == E1000_FUNC_2)
1135                 mask = E1000_NVM_CFG_DONE_PORT_2;
1136         else if (hw->bus.func == E1000_FUNC_3)
1137                 mask = E1000_NVM_CFG_DONE_PORT_3;
1138         while (timeout) {
1139                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1140                         break;
1141                 msec_delay(1);
1142                 timeout--;
1143         }
1144         if (!timeout)
1145                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1146
1147         /* If EEPROM is not marked present, init the PHY manually */
1148         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1149             (hw->phy.type == e1000_phy_igp_3))
1150                 e1000_phy_init_script_igp3(hw);
1151
1152         return E1000_SUCCESS;
1153 }
1154
1155 /**
1156  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1157  *  @hw: pointer to the HW structure
1158  *  @speed: stores the current speed
1159  *  @duplex: stores the current duplex
1160  *
1161  *  This is a wrapper function, if using the serial gigabit media independent
1162  *  interface, use PCS to retrieve the link speed and duplex information.
1163  *  Otherwise, use the generic function to get the link speed and duplex info.
1164  **/
1165 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1166                                         u16 *duplex)
1167 {
1168         s32 ret_val;
1169
1170         DEBUGFUNC("e1000_get_link_up_info_82575");
1171
1172         if (hw->phy.media_type != e1000_media_type_copper)
1173                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1174                                                                duplex);
1175         else
1176                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1177                                                                     duplex);
1178
1179         return ret_val;
1180 }
1181
1182 /**
1183  *  e1000_check_for_link_82575 - Check for link
1184  *  @hw: pointer to the HW structure
1185  *
1186  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1187  *  use the generic interface for determining link.
1188  **/
1189 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1190 {
1191         s32 ret_val;
1192         u16 speed, duplex;
1193
1194         DEBUGFUNC("e1000_check_for_link_82575");
1195
1196         if (hw->phy.media_type != e1000_media_type_copper) {
1197                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1198                                                                &duplex);
1199                 /*
1200                  * Use this flag to determine if link needs to be checked or
1201                  * not.  If we have link clear the flag so that we do not
1202                  * continue to check for link.
1203                  */
1204                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1205
1206                 /*
1207                  * Configure Flow Control now that Auto-Neg has completed.
1208                  * First, we need to restore the desired flow control
1209                  * settings because we may have had to re-autoneg with a
1210                  * different link partner.
1211                  */
1212                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1213                 if (ret_val)
1214                         DEBUGOUT("Error configuring flow control\n");
1215         } else {
1216                 ret_val = e1000_check_for_copper_link_generic(hw);
1217         }
1218
1219         return ret_val;
1220 }
1221
1222 /**
1223  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1224  *  @hw: pointer to the HW structure
1225  *
1226  *  Poll the M88E1112 interfaces to see which interface achieved link.
1227  */
1228 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1229 {
1230         struct e1000_phy_info *phy = &hw->phy;
1231         s32 ret_val;
1232         u16 data;
1233         u8 port = 0;
1234
1235         DEBUGFUNC("e1000_check_for_link_media_swap");
1236
1237         /* Check for copper. */
1238         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1239         if (ret_val)
1240                 return ret_val;
1241
1242         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1243         if (ret_val)
1244                 return ret_val;
1245
1246         if (data & E1000_M88E1112_STATUS_LINK)
1247                 port = E1000_MEDIA_PORT_COPPER;
1248
1249         /* Check for other. */
1250         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1251         if (ret_val)
1252                 return ret_val;
1253
1254         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1255         if (ret_val)
1256                 return ret_val;
1257
1258         if (data & E1000_M88E1112_STATUS_LINK)
1259                 port = E1000_MEDIA_PORT_OTHER;
1260
1261         /* Determine if a swap needs to happen. */
1262         if (port && (hw->dev_spec._82575.media_port != port)) {
1263                 hw->dev_spec._82575.media_port = port;
1264                 hw->dev_spec._82575.media_changed = true;
1265         }
1266
1267         if (port == E1000_MEDIA_PORT_COPPER) {
1268                 /* reset page to 0 */
1269                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1270                 if (ret_val)
1271                         return ret_val;
1272                 e1000_check_for_link_82575(hw);
1273         } else {
1274                 e1000_check_for_link_82575(hw);
1275                 /* reset page to 0 */
1276                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1277                 if (ret_val)
1278                         return ret_val;
1279         }
1280
1281         return E1000_SUCCESS;
1282 }
1283
1284 /**
1285  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1286  *  @hw: pointer to the HW structure
1287  **/
1288 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1289 {
1290         u32 reg;
1291
1292         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1293
1294         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1295             !e1000_sgmii_active_82575(hw))
1296                 return;
1297
1298         /* Enable PCS to turn on link */
1299         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1300         reg |= E1000_PCS_CFG_PCS_EN;
1301         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1302
1303         /* Power up the laser */
1304         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1305         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1306         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1307
1308         /* flush the write to verify completion */
1309         E1000_WRITE_FLUSH(hw);
1310         msec_delay(1);
1311 }
1312
1313 /**
1314  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1315  *  @hw: pointer to the HW structure
1316  *  @speed: stores the current speed
1317  *  @duplex: stores the current duplex
1318  *
1319  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1320  *  duplex, then store the values in the pointers provided.
1321  **/
1322 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1323                                                 u16 *speed, u16 *duplex)
1324 {
1325         struct e1000_mac_info *mac = &hw->mac;
1326         u32 pcs;
1327         u32 status;
1328
1329         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1330
1331         /*
1332          * Read the PCS Status register for link state. For non-copper mode,
1333          * the status register is not accurate. The PCS status register is
1334          * used instead.
1335          */
1336         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1337
1338         /*
1339          * The link up bit determines when link is up on autoneg.
1340          */
1341         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1342                 mac->serdes_has_link = true;
1343
1344                 /* Detect and store PCS speed */
1345                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1346                         *speed = SPEED_1000;
1347                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1348                         *speed = SPEED_100;
1349                 else
1350                         *speed = SPEED_10;
1351
1352                 /* Detect and store PCS duplex */
1353                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1354                         *duplex = FULL_DUPLEX;
1355                 else
1356                         *duplex = HALF_DUPLEX;
1357
1358                 /* Check if it is an I354 2.5Gb backplane connection. */
1359                 if (mac->type == e1000_i354) {
1360                         status = E1000_READ_REG(hw, E1000_STATUS);
1361                         if ((status & E1000_STATUS_2P5_SKU) &&
1362                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1363                                 *speed = SPEED_2500;
1364                                 *duplex = FULL_DUPLEX;
1365                                 DEBUGOUT("2500 Mbs, ");
1366                                 DEBUGOUT("Full Duplex\n");
1367                         }
1368                 }
1369
1370         } else {
1371                 mac->serdes_has_link = false;
1372                 *speed = 0;
1373                 *duplex = 0;
1374         }
1375
1376         return E1000_SUCCESS;
1377 }
1378
1379 /**
1380  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1381  *  @hw: pointer to the HW structure
1382  *
1383  *  In the case of serdes shut down sfp and PCS on driver unload
1384  *  when management pass thru is not enabled.
1385  **/
1386 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1387 {
1388         u32 reg;
1389
1390         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1391
1392         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1393             !e1000_sgmii_active_82575(hw))
1394                 return;
1395
1396         if (!e1000_enable_mng_pass_thru(hw)) {
1397                 /* Disable PCS to turn off link */
1398                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1399                 reg &= ~E1000_PCS_CFG_PCS_EN;
1400                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1401
1402                 /* shutdown the laser */
1403                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1404                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1405                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1406
1407                 /* flush the write to verify completion */
1408                 E1000_WRITE_FLUSH(hw);
1409                 msec_delay(1);
1410         }
1411
1412         return;
1413 }
1414
1415 /**
1416  *  e1000_reset_hw_82575 - Reset hardware
1417  *  @hw: pointer to the HW structure
1418  *
1419  *  This resets the hardware into a known state.
1420  **/
1421 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1422 {
1423         u32 ctrl;
1424         s32 ret_val;
1425
1426         DEBUGFUNC("e1000_reset_hw_82575");
1427
1428         /*
1429          * Prevent the PCI-E bus from sticking if there is no TLP connection
1430          * on the last TLP read/write transaction when MAC is reset.
1431          */
1432         ret_val = e1000_disable_pcie_master_generic(hw);
1433         if (ret_val)
1434                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1435
1436         /* set the completion timeout for interface */
1437         ret_val = e1000_set_pcie_completion_timeout(hw);
1438         if (ret_val)
1439                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1440
1441         DEBUGOUT("Masking off all interrupts\n");
1442         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1443
1444         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1445         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1446         E1000_WRITE_FLUSH(hw);
1447
1448         msec_delay(10);
1449
1450         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1451
1452         DEBUGOUT("Issuing a global reset to MAC\n");
1453         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1454
1455         ret_val = e1000_get_auto_rd_done_generic(hw);
1456         if (ret_val) {
1457                 /*
1458                  * When auto config read does not complete, do not
1459                  * return with an error. This can happen in situations
1460                  * where there is no eeprom and prevents getting link.
1461                  */
1462                 DEBUGOUT("Auto Read Done did not complete\n");
1463         }
1464
1465         /* If EEPROM is not present, run manual init scripts */
1466         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1467                 e1000_reset_init_script_82575(hw);
1468
1469         /* Clear any pending interrupt events. */
1470         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1471         E1000_READ_REG(hw, E1000_ICR);
1472
1473         /* Install any alternate MAC address into RAR0 */
1474         ret_val = e1000_check_alt_mac_addr_generic(hw);
1475
1476         return ret_val;
1477 }
1478
1479 /**
1480  *  e1000_init_hw_82575 - Initialize hardware
1481  *  @hw: pointer to the HW structure
1482  *
1483  *  This inits the hardware readying it for operation.
1484  **/
1485 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1486 {
1487         struct e1000_mac_info *mac = &hw->mac;
1488         s32 ret_val;
1489         u16 i, rar_count = mac->rar_entry_count;
1490
1491         DEBUGFUNC("e1000_init_hw_82575");
1492
1493         /* Initialize identification LED */
1494         ret_val = mac->ops.id_led_init(hw);
1495         if (ret_val) {
1496                 DEBUGOUT("Error initializing identification LED\n");
1497                 /* This is not fatal and we should not stop init due to this */
1498         }
1499
1500         /* Disabling VLAN filtering */
1501         DEBUGOUT("Initializing the IEEE VLAN\n");
1502         mac->ops.clear_vfta(hw);
1503
1504         /* Setup the receive address */
1505         e1000_init_rx_addrs_generic(hw, rar_count);
1506
1507         /* Zero out the Multicast HASH table */
1508         DEBUGOUT("Zeroing the MTA\n");
1509         for (i = 0; i < mac->mta_reg_count; i++)
1510                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1511
1512         /* Zero out the Unicast HASH table */
1513         DEBUGOUT("Zeroing the UTA\n");
1514         for (i = 0; i < mac->uta_reg_count; i++)
1515                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1516
1517         /* Setup link and flow control */
1518         ret_val = mac->ops.setup_link(hw);
1519
1520         /* Set the default MTU size */
1521         hw->dev_spec._82575.mtu = 1500;
1522
1523         /*
1524          * Clear all of the statistics registers (clear on read).  It is
1525          * important that we do this after we have tried to establish link
1526          * because the symbol error count will increment wildly if there
1527          * is no link.
1528          */
1529         e1000_clear_hw_cntrs_82575(hw);
1530
1531         return ret_val;
1532 }
1533
1534 /**
1535  *  e1000_setup_copper_link_82575 - Configure copper link settings
1536  *  @hw: pointer to the HW structure
1537  *
1538  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1539  *  for link, once link is established calls to configure collision distance
1540  *  and flow control are called.
1541  **/
1542 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1543 {
1544         u32 ctrl;
1545         s32 ret_val;
1546         u32 phpm_reg;
1547
1548         DEBUGFUNC("e1000_setup_copper_link_82575");
1549
1550         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1551         ctrl |= E1000_CTRL_SLU;
1552         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1553         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1554
1555         /* Clear Go Link Disconnect bit on supported devices */
1556         switch (hw->mac.type) {
1557         case e1000_82580:
1558         case e1000_i350:
1559         case e1000_i210:
1560         case e1000_i211:
1561                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1562                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1563                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1564                 break;
1565         default:
1566                 break;
1567         }
1568
1569         ret_val = e1000_setup_serdes_link_82575(hw);
1570         if (ret_val)
1571                 goto out;
1572
1573         if (e1000_sgmii_active_82575(hw)) {
1574                 /* allow time for SFP cage time to power up phy */
1575                 msec_delay(300);
1576
1577                 ret_val = hw->phy.ops.reset(hw);
1578                 if (ret_val) {
1579                         DEBUGOUT("Error resetting the PHY.\n");
1580                         goto out;
1581                 }
1582         }
1583         switch (hw->phy.type) {
1584         case e1000_phy_i210:
1585         case e1000_phy_m88:
1586                 switch (hw->phy.id) {
1587                 case I347AT4_E_PHY_ID:
1588                 case M88E1112_E_PHY_ID:
1589                 case M88E1340M_E_PHY_ID:
1590                 case M88E1543_E_PHY_ID:
1591                 case M88E1512_E_PHY_ID:
1592                 case I210_I_PHY_ID:
1593                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1594                         break;
1595                 default:
1596                         ret_val = e1000_copper_link_setup_m88(hw);
1597                         break;
1598                 }
1599                 break;
1600         case e1000_phy_igp_3:
1601                 ret_val = e1000_copper_link_setup_igp(hw);
1602                 break;
1603         case e1000_phy_82580:
1604                 ret_val = e1000_copper_link_setup_82577(hw);
1605                 break;
1606         default:
1607                 ret_val = -E1000_ERR_PHY;
1608                 break;
1609         }
1610
1611         if (ret_val)
1612                 goto out;
1613
1614         ret_val = e1000_setup_copper_link_generic(hw);
1615 out:
1616         return ret_val;
1617 }
1618
1619 /**
1620  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1621  *  @hw: pointer to the HW structure
1622  *
1623  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1624  *  used on copper connections where the serialized gigabit media independent
1625  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1626  *  for auto-negotiation or forces speed/duplex.
1627  **/
1628 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1629 {
1630         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1631         bool pcs_autoneg;
1632         s32 ret_val = E1000_SUCCESS;
1633         u16 data;
1634
1635         DEBUGFUNC("e1000_setup_serdes_link_82575");
1636
1637         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1638             !e1000_sgmii_active_82575(hw))
1639                 return ret_val;
1640
1641         /*
1642          * On the 82575, SerDes loopback mode persists until it is
1643          * explicitly turned off or a power cycle is performed.  A read to
1644          * the register does not indicate its status.  Therefore, we ensure
1645          * loopback mode is disabled during initialization.
1646          */
1647         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1648
1649         /* power on the sfp cage if present */
1650         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1651         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1652         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1653
1654         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1655         ctrl_reg |= E1000_CTRL_SLU;
1656
1657         /* set both sw defined pins on 82575/82576*/
1658         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1659                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1660
1661         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1662
1663         /* default pcs_autoneg to the same setting as mac autoneg */
1664         pcs_autoneg = hw->mac.autoneg;
1665
1666         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1667         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1668                 /* sgmii mode lets the phy handle forcing speed/duplex */
1669                 pcs_autoneg = true;
1670                 /* autoneg time out should be disabled for SGMII mode */
1671                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1672                 break;
1673         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1674                 /* disable PCS autoneg and support parallel detect only */
1675                 pcs_autoneg = false;
1676                 /* fall through to default case */
1677         default:
1678                 if (hw->mac.type == e1000_82575 ||
1679                     hw->mac.type == e1000_82576) {
1680                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1681                         if (ret_val) {
1682                                 DEBUGOUT("NVM Read Error\n");
1683                                 return ret_val;
1684                         }
1685
1686                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1687                                 pcs_autoneg = false;
1688                 }
1689
1690                 /*
1691                  * non-SGMII modes only supports a speed of 1000/Full for the
1692                  * link so it is best to just force the MAC and let the pcs
1693                  * link either autoneg or be forced to 1000/Full
1694                  */
1695                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1696                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1697
1698                 /* set speed of 1000/Full if speed/duplex is forced */
1699                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1700                 break;
1701         }
1702
1703         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1704
1705         /*
1706          * New SerDes mode allows for forcing speed or autonegotiating speed
1707          * at 1gb. Autoneg should be default set by most drivers. This is the
1708          * mode that will be compatible with older link partners and switches.
1709          * However, both are supported by the hardware and some drivers/tools.
1710          */
1711         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1712                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1713
1714         if (pcs_autoneg) {
1715                 /* Set PCS register for autoneg */
1716                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1717                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1718
1719                 /* Disable force flow control for autoneg */
1720                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1721
1722                 /* Configure flow control advertisement for autoneg */
1723                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1724                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1725
1726                 switch (hw->fc.requested_mode) {
1727                 case e1000_fc_full:
1728                 case e1000_fc_rx_pause:
1729                         anadv_reg |= E1000_TXCW_ASM_DIR;
1730                         anadv_reg |= E1000_TXCW_PAUSE;
1731                         break;
1732                 case e1000_fc_tx_pause:
1733                         anadv_reg |= E1000_TXCW_ASM_DIR;
1734                         break;
1735                 default:
1736                         break;
1737                 }
1738
1739                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1740
1741                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1742         } else {
1743                 /* Set PCS register for forced link */
1744                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1745
1746                 /* Force flow control for forced link */
1747                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1748
1749                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1750         }
1751
1752         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1753
1754         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1755                 e1000_force_mac_fc_generic(hw);
1756
1757         return ret_val;
1758 }
1759
1760 /**
1761  *  e1000_get_media_type_82575 - derives current media type.
1762  *  @hw: pointer to the HW structure
1763  *
1764  *  The media type is chosen reflecting few settings.
1765  *  The following are taken into account:
1766  *  - link mode set in the current port Init Control Word #3
1767  *  - current link mode settings in CSR register
1768  *  - MDIO vs. I2C PHY control interface chosen
1769  *  - SFP module media type
1770  **/
1771 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1772 {
1773         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1774         s32 ret_val = E1000_SUCCESS;
1775         u32 ctrl_ext = 0;
1776         u32 link_mode = 0;
1777
1778         /* Set internal phy as default */
1779         dev_spec->sgmii_active = false;
1780         dev_spec->module_plugged = false;
1781
1782         /* Get CSR setting */
1783         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1784
1785         /* extract link mode setting */
1786         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1787
1788         switch (link_mode) {
1789         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1790                 hw->phy.media_type = e1000_media_type_internal_serdes;
1791                 break;
1792         case E1000_CTRL_EXT_LINK_MODE_GMII:
1793                 hw->phy.media_type = e1000_media_type_copper;
1794                 break;
1795         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1796                 /* Get phy control interface type set (MDIO vs. I2C)*/
1797                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1798                         hw->phy.media_type = e1000_media_type_copper;
1799                         dev_spec->sgmii_active = true;
1800                         break;
1801                 }
1802                 /* fall through for I2C based SGMII */
1803         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1804                 /* read media type from SFP EEPROM */
1805                 ret_val = e1000_set_sfp_media_type_82575(hw);
1806                 if ((ret_val != E1000_SUCCESS) ||
1807                     (hw->phy.media_type == e1000_media_type_unknown)) {
1808                         /*
1809                          * If media type was not identified then return media
1810                          * type defined by the CTRL_EXT settings.
1811                          */
1812                         hw->phy.media_type = e1000_media_type_internal_serdes;
1813
1814                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1815                                 hw->phy.media_type = e1000_media_type_copper;
1816                                 dev_spec->sgmii_active = true;
1817                         }
1818
1819                         break;
1820                 }
1821
1822                 /* do not change link mode for 100BaseFX */
1823                 if (dev_spec->eth_flags.e100_base_fx)
1824                         break;
1825
1826                 /* change current link mode setting */
1827                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1828
1829                 if (hw->phy.media_type == e1000_media_type_copper)
1830                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1831                 else
1832                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1833
1834                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1835
1836                 break;
1837         }
1838
1839         return ret_val;
1840 }
1841
1842 /**
1843  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1844  *  @hw: pointer to the HW structure
1845  *
1846  *  The media type is chosen based on SFP module.
1847  *  compatibility flags retrieved from SFP ID EEPROM.
1848  **/
1849 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1850 {
1851         s32 ret_val = E1000_ERR_CONFIG;
1852         u32 ctrl_ext = 0;
1853         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1854         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1855         u8 tranceiver_type = 0;
1856         s32 timeout = 3;
1857
1858         /* Turn I2C interface ON and power on sfp cage */
1859         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1860         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1861         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1862
1863         E1000_WRITE_FLUSH(hw);
1864
1865         /* Read SFP module data */
1866         while (timeout) {
1867                 ret_val = e1000_read_sfp_data_byte(hw,
1868                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1869                         &tranceiver_type);
1870                 if (ret_val == E1000_SUCCESS)
1871                         break;
1872                 msec_delay(100);
1873                 timeout--;
1874         }
1875         if (ret_val != E1000_SUCCESS)
1876                 goto out;
1877
1878         ret_val = e1000_read_sfp_data_byte(hw,
1879                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1880                         (u8 *)eth_flags);
1881         if (ret_val != E1000_SUCCESS)
1882                 goto out;
1883
1884         /* Check if there is some SFP module plugged and powered */
1885         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1886             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1887                 dev_spec->module_plugged = true;
1888                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1889                         hw->phy.media_type = e1000_media_type_internal_serdes;
1890                 } else if (eth_flags->e100_base_fx) {
1891                         dev_spec->sgmii_active = true;
1892                         hw->phy.media_type = e1000_media_type_internal_serdes;
1893                 } else if (eth_flags->e1000_base_t) {
1894                         dev_spec->sgmii_active = true;
1895                         hw->phy.media_type = e1000_media_type_copper;
1896                 } else {
1897                         hw->phy.media_type = e1000_media_type_unknown;
1898                         DEBUGOUT("PHY module has not been recognized\n");
1899                         goto out;
1900                 }
1901         } else {
1902                 hw->phy.media_type = e1000_media_type_unknown;
1903         }
1904         ret_val = E1000_SUCCESS;
1905 out:
1906         /* Restore I2C interface setting */
1907         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1908         return ret_val;
1909 }
1910
1911 /**
1912  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1913  *  @hw: pointer to the HW structure
1914  *  @data: pointer to the NVM (EEPROM)
1915  *
1916  *  Read the EEPROM for the current default LED configuration.  If the
1917  *  LED configuration is not valid, set to a valid LED configuration.
1918  **/
1919 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1920 {
1921         s32 ret_val;
1922
1923         DEBUGFUNC("e1000_valid_led_default_82575");
1924
1925         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1926         if (ret_val) {
1927                 DEBUGOUT("NVM Read Error\n");
1928                 goto out;
1929         }
1930
1931         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1932                 switch (hw->phy.media_type) {
1933                 case e1000_media_type_internal_serdes:
1934                         *data = ID_LED_DEFAULT_82575_SERDES;
1935                         break;
1936                 case e1000_media_type_copper:
1937                 default:
1938                         *data = ID_LED_DEFAULT;
1939                         break;
1940                 }
1941         }
1942 out:
1943         return ret_val;
1944 }
1945
1946 /**
1947  *  e1000_sgmii_active_82575 - Return sgmii state
1948  *  @hw: pointer to the HW structure
1949  *
1950  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1951  *  which can be enabled for use in the embedded applications.  Simply
1952  *  return the current state of the sgmii interface.
1953  **/
1954 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1955 {
1956         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1957         return dev_spec->sgmii_active;
1958 }
1959
1960 /**
1961  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1962  *  @hw: pointer to the HW structure
1963  *
1964  *  Inits recommended HW defaults after a reset when there is no EEPROM
1965  *  detected. This is only for the 82575.
1966  **/
1967 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1968 {
1969         DEBUGFUNC("e1000_reset_init_script_82575");
1970
1971         if (hw->mac.type == e1000_82575) {
1972                 DEBUGOUT("Running reset init script for 82575\n");
1973                 /* SerDes configuration via SERDESCTRL */
1974                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1975                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1976                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1977                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1978
1979                 /* CCM configuration via CCMCTL register */
1980                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1981                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1982
1983                 /* PCIe lanes configuration */
1984                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1985                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1986                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1987                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1988
1989                 /* PCIe PLL Configuration */
1990                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1991                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1992                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1993         }
1994
1995         return E1000_SUCCESS;
1996 }
1997
1998 /**
1999  *  e1000_read_mac_addr_82575 - Read device MAC address
2000  *  @hw: pointer to the HW structure
2001  **/
2002 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
2003 {
2004         s32 ret_val;
2005
2006         DEBUGFUNC("e1000_read_mac_addr_82575");
2007
2008         /*
2009          * If there's an alternate MAC address place it in RAR0
2010          * so that it will override the Si installed default perm
2011          * address.
2012          */
2013         ret_val = e1000_check_alt_mac_addr_generic(hw);
2014         if (ret_val)
2015                 goto out;
2016
2017         ret_val = e1000_read_mac_addr_generic(hw);
2018
2019 out:
2020         return ret_val;
2021 }
2022
2023 /**
2024  *  e1000_config_collision_dist_82575 - Configure collision distance
2025  *  @hw: pointer to the HW structure
2026  *
2027  *  Configures the collision distance to the default value and is used
2028  *  during link setup.
2029  **/
2030 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2031 {
2032         u32 tctl_ext;
2033
2034         DEBUGFUNC("e1000_config_collision_dist_82575");
2035
2036         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2037
2038         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2039         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2040
2041         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2042         E1000_WRITE_FLUSH(hw);
2043 }
2044
2045 /**
2046  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2047  * @hw: pointer to the HW structure
2048  *
2049  * In the case of a PHY power down to save power, or to turn off link during a
2050  * driver unload, or wake on lan is not enabled, remove the link.
2051  **/
2052 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2053 {
2054         struct e1000_phy_info *phy = &hw->phy;
2055
2056         if (!(phy->ops.check_reset_block))
2057                 return;
2058
2059         /* If the management interface is not enabled, then power down */
2060         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2061                 e1000_power_down_phy_copper(hw);
2062
2063         return;
2064 }
2065
2066 /**
2067  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2068  *  @hw: pointer to the HW structure
2069  *
2070  *  Clears the hardware counters by reading the counter registers.
2071  **/
2072 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2073 {
2074         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2075
2076         e1000_clear_hw_cntrs_base_generic(hw);
2077
2078         E1000_READ_REG(hw, E1000_PRC64);
2079         E1000_READ_REG(hw, E1000_PRC127);
2080         E1000_READ_REG(hw, E1000_PRC255);
2081         E1000_READ_REG(hw, E1000_PRC511);
2082         E1000_READ_REG(hw, E1000_PRC1023);
2083         E1000_READ_REG(hw, E1000_PRC1522);
2084         E1000_READ_REG(hw, E1000_PTC64);
2085         E1000_READ_REG(hw, E1000_PTC127);
2086         E1000_READ_REG(hw, E1000_PTC255);
2087         E1000_READ_REG(hw, E1000_PTC511);
2088         E1000_READ_REG(hw, E1000_PTC1023);
2089         E1000_READ_REG(hw, E1000_PTC1522);
2090
2091         E1000_READ_REG(hw, E1000_ALGNERRC);
2092         E1000_READ_REG(hw, E1000_RXERRC);
2093         E1000_READ_REG(hw, E1000_TNCRS);
2094         E1000_READ_REG(hw, E1000_CEXTERR);
2095         E1000_READ_REG(hw, E1000_TSCTC);
2096         E1000_READ_REG(hw, E1000_TSCTFC);
2097
2098         E1000_READ_REG(hw, E1000_MGTPRC);
2099         E1000_READ_REG(hw, E1000_MGTPDC);
2100         E1000_READ_REG(hw, E1000_MGTPTC);
2101
2102         E1000_READ_REG(hw, E1000_IAC);
2103         E1000_READ_REG(hw, E1000_ICRXOC);
2104
2105         E1000_READ_REG(hw, E1000_ICRXPTC);
2106         E1000_READ_REG(hw, E1000_ICRXATC);
2107         E1000_READ_REG(hw, E1000_ICTXPTC);
2108         E1000_READ_REG(hw, E1000_ICTXATC);
2109         E1000_READ_REG(hw, E1000_ICTXQEC);
2110         E1000_READ_REG(hw, E1000_ICTXQMTC);
2111         E1000_READ_REG(hw, E1000_ICRXDMTC);
2112
2113         E1000_READ_REG(hw, E1000_CBTMPC);
2114         E1000_READ_REG(hw, E1000_HTDPMC);
2115         E1000_READ_REG(hw, E1000_CBRMPC);
2116         E1000_READ_REG(hw, E1000_RPTHC);
2117         E1000_READ_REG(hw, E1000_HGPTC);
2118         E1000_READ_REG(hw, E1000_HTCBDPC);
2119         E1000_READ_REG(hw, E1000_HGORCL);
2120         E1000_READ_REG(hw, E1000_HGORCH);
2121         E1000_READ_REG(hw, E1000_HGOTCL);
2122         E1000_READ_REG(hw, E1000_HGOTCH);
2123         E1000_READ_REG(hw, E1000_LENERRS);
2124
2125         /* This register should not be read in copper configurations */
2126         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2127             e1000_sgmii_active_82575(hw))
2128                 E1000_READ_REG(hw, E1000_SCVPC);
2129 }
2130
2131 /**
2132  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2133  *  @hw: pointer to the HW structure
2134  *
2135  *  After Rx enable, if manageability is enabled then there is likely some
2136  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2137  *  function clears the fifos and flushes any packets that came in as rx was
2138  *  being enabled.
2139  **/
2140 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2141 {
2142         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2143         int i, ms_wait;
2144
2145         DEBUGFUNC("e1000_rx_fifo_flush_82575");
2146
2147         /* disable IPv6 options as per hardware errata */
2148         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2149         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
2150         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2151
2152         if (hw->mac.type != e1000_82575 ||
2153             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2154                 return;
2155
2156         /* Disable all Rx queues */
2157         for (i = 0; i < 4; i++) {
2158                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2159                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2160                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2161         }
2162         /* Poll all queues to verify they have shut down */
2163         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2164                 msec_delay(1);
2165                 rx_enabled = 0;
2166                 for (i = 0; i < 4; i++)
2167                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2168                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2169                         break;
2170         }
2171
2172         if (ms_wait == 10)
2173                 DEBUGOUT("Queue disable timed out after 10ms\n");
2174
2175         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2176          * incoming packets are rejected.  Set enable and wait 2ms so that
2177          * any packet that was coming in as RCTL.EN was set is flushed
2178          */
2179         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2180
2181         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2182         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2183
2184         rctl = E1000_READ_REG(hw, E1000_RCTL);
2185         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2186         temp_rctl |= E1000_RCTL_LPE;
2187
2188         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2189         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2190         E1000_WRITE_FLUSH(hw);
2191         msec_delay(2);
2192
2193         /* Enable Rx queues that were previously enabled and restore our
2194          * previous state
2195          */
2196         for (i = 0; i < 4; i++)
2197                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2198         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2199         E1000_WRITE_FLUSH(hw);
2200
2201         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2202         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2203
2204         /* Flush receive errors generated by workaround */
2205         E1000_READ_REG(hw, E1000_ROC);
2206         E1000_READ_REG(hw, E1000_RNBC);
2207         E1000_READ_REG(hw, E1000_MPC);
2208 }
2209
2210 /**
2211  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2212  *  @hw: pointer to the HW structure
2213  *
2214  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2215  *  however the hardware default for these parts is 500us to 1ms which is less
2216  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2217  *  increase the value to either 10ms to 200ms for capability version 1 config,
2218  *  or 16ms to 55ms for version 2.
2219  **/
2220 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2221 {
2222         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2223         s32 ret_val = E1000_SUCCESS;
2224         u16 pcie_devctl2;
2225
2226         /* only take action if timeout value is defaulted to 0 */
2227         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2228                 goto out;
2229
2230         /*
2231          * if capababilities version is type 1 we can write the
2232          * timeout of 10ms to 200ms through the GCR register
2233          */
2234         if (!(gcr & E1000_GCR_CAP_VER2)) {
2235                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2236                 goto out;
2237         }
2238
2239         /*
2240          * for version 2 capabilities we need to write the config space
2241          * directly in order to set the completion timeout value for
2242          * 16ms to 55ms
2243          */
2244         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2245                                           &pcie_devctl2);
2246         if (ret_val)
2247                 goto out;
2248
2249         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2250
2251         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2252                                            &pcie_devctl2);
2253 out:
2254         /* disable completion timeout resend */
2255         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2256
2257         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2258         return ret_val;
2259 }
2260
2261 /**
2262  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2263  *  @hw: pointer to the hardware struct
2264  *  @enable: state to enter, either enabled or disabled
2265  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2266  *
2267  *  enables/disables L2 switch anti-spoofing functionality.
2268  **/
2269 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2270 {
2271         u32 reg_val, reg_offset;
2272
2273         switch (hw->mac.type) {
2274         case e1000_82576:
2275                 reg_offset = E1000_DTXSWC;
2276                 break;
2277         case e1000_i350:
2278         case e1000_i354:
2279                 reg_offset = E1000_TXSWC;
2280                 break;
2281         default:
2282                 return;
2283         }
2284
2285         reg_val = E1000_READ_REG(hw, reg_offset);
2286         if (enable) {
2287                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2288                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2289                 /* The PF can spoof - it has to in order to
2290                  * support emulation mode NICs
2291                  */
2292                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2293         } else {
2294                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2295                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2296         }
2297         E1000_WRITE_REG(hw, reg_offset, reg_val);
2298 }
2299
2300 /**
2301  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2302  *  @hw: pointer to the hardware struct
2303  *  @enable: state to enter, either enabled or disabled
2304  *
2305  *  enables/disables L2 switch loopback functionality.
2306  **/
2307 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2308 {
2309         u32 dtxswc;
2310
2311         switch (hw->mac.type) {
2312         case e1000_82576:
2313                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2314                 if (enable)
2315                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2316                 else
2317                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2318                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2319                 break;
2320         case e1000_i350:
2321         case e1000_i354:
2322                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2323                 if (enable)
2324                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2325                 else
2326                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2327                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2328                 break;
2329         default:
2330                 /* Currently no other hardware supports loopback */
2331                 break;
2332         }
2333
2334
2335 }
2336
2337 /**
2338  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2339  *  @hw: pointer to the hardware struct
2340  *  @enable: state to enter, either enabled or disabled
2341  *
2342  *  enables/disables replication of packets across multiple pools.
2343  **/
2344 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2345 {
2346         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2347
2348         if (enable)
2349                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2350         else
2351                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2352
2353         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2354 }
2355
2356 /**
2357  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2358  *  @hw: pointer to the HW structure
2359  *  @offset: register offset to be read
2360  *  @data: pointer to the read data
2361  *
2362  *  Reads the MDI control register in the PHY at offset and stores the
2363  *  information read to data.
2364  **/
2365 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2366 {
2367         s32 ret_val;
2368
2369         DEBUGFUNC("e1000_read_phy_reg_82580");
2370
2371         ret_val = hw->phy.ops.acquire(hw);
2372         if (ret_val)
2373                 goto out;
2374
2375         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2376
2377         hw->phy.ops.release(hw);
2378
2379 out:
2380         return ret_val;
2381 }
2382
2383 /**
2384  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2385  *  @hw: pointer to the HW structure
2386  *  @offset: register offset to write to
2387  *  @data: data to write to register at offset
2388  *
2389  *  Writes data to MDI control register in the PHY at offset.
2390  **/
2391 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2392 {
2393         s32 ret_val;
2394
2395         DEBUGFUNC("e1000_write_phy_reg_82580");
2396
2397         ret_val = hw->phy.ops.acquire(hw);
2398         if (ret_val)
2399                 goto out;
2400
2401         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2402
2403         hw->phy.ops.release(hw);
2404
2405 out:
2406         return ret_val;
2407 }
2408
2409 /**
2410  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2411  *  @hw: pointer to the HW structure
2412  *
2413  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2414  *  the values found in the EEPROM.  This addresses an issue in which these
2415  *  bits are not restored from EEPROM after reset.
2416  **/
2417 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2418 {
2419         s32 ret_val = E1000_SUCCESS;
2420         u32 mdicnfg;
2421         u16 nvm_data = 0;
2422
2423         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2424
2425         if (hw->mac.type != e1000_82580)
2426                 goto out;
2427         if (!e1000_sgmii_active_82575(hw))
2428                 goto out;
2429
2430         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2431                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2432                                    &nvm_data);
2433         if (ret_val) {
2434                 DEBUGOUT("NVM Read Error\n");
2435                 goto out;
2436         }
2437
2438         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2439         if (nvm_data & NVM_WORD24_EXT_MDIO)
2440                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2441         if (nvm_data & NVM_WORD24_COM_MDIO)
2442                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2443         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2444 out:
2445         return ret_val;
2446 }
2447
2448 /**
2449  *  e1000_reset_hw_82580 - Reset hardware
2450  *  @hw: pointer to the HW structure
2451  *
2452  *  This resets function or entire device (all ports, etc.)
2453  *  to a known state.
2454  **/
2455 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2456 {
2457         s32 ret_val = E1000_SUCCESS;
2458         /* BH SW mailbox bit in SW_FW_SYNC */
2459         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2460         u32 ctrl;
2461         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2462
2463         DEBUGFUNC("e1000_reset_hw_82580");
2464
2465         hw->dev_spec._82575.global_device_reset = false;
2466
2467         /* 82580 does not reliably do global_device_reset due to hw errata */
2468         if (hw->mac.type == e1000_82580)
2469                 global_device_reset = false;
2470
2471         /* Get current control state. */
2472         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2473
2474         /*
2475          * Prevent the PCI-E bus from sticking if there is no TLP connection
2476          * on the last TLP read/write transaction when MAC is reset.
2477          */
2478         ret_val = e1000_disable_pcie_master_generic(hw);
2479         if (ret_val)
2480                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2481
2482         DEBUGOUT("Masking off all interrupts\n");
2483         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2484         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2485         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2486         E1000_WRITE_FLUSH(hw);
2487
2488         msec_delay(10);
2489
2490         /* Determine whether or not a global dev reset is requested */
2491         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2492             swmbsw_mask))
2493                         global_device_reset = false;
2494
2495         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2496             E1000_STAT_DEV_RST_SET))
2497                 ctrl |= E1000_CTRL_DEV_RST;
2498         else
2499                 ctrl |= E1000_CTRL_RST;
2500
2501         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2502
2503         switch (hw->device_id) {
2504         case E1000_DEV_ID_DH89XXCC_SGMII:
2505                 break;
2506         default:
2507                 E1000_WRITE_FLUSH(hw);
2508                 break;
2509         }
2510
2511         /* Add delay to insure DEV_RST or RST has time to complete */
2512         msec_delay(5);
2513
2514         ret_val = e1000_get_auto_rd_done_generic(hw);
2515         if (ret_val) {
2516                 /*
2517                  * When auto config read does not complete, do not
2518                  * return with an error. This can happen in situations
2519                  * where there is no eeprom and prevents getting link.
2520                  */
2521                 DEBUGOUT("Auto Read Done did not complete\n");
2522         }
2523
2524         /* clear global device reset status bit */
2525         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2526
2527         /* Clear any pending interrupt events. */
2528         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2529         E1000_READ_REG(hw, E1000_ICR);
2530
2531         ret_val = e1000_reset_mdicnfg_82580(hw);
2532         if (ret_val)
2533                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2534
2535         /* Install any alternate MAC address into RAR0 */
2536         ret_val = e1000_check_alt_mac_addr_generic(hw);
2537
2538         /* Release semaphore */
2539         if (global_device_reset)
2540                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2541
2542         return ret_val;
2543 }
2544
2545 /**
2546  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2547  *  @data: data received by reading RXPBS register
2548  *
2549  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2550  *  This function converts the retrieved value into the correct table value
2551  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2552  *  0x0 36  72 144   1   2   4   8  16
2553  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2554  */
2555 u16 e1000_rxpbs_adjust_82580(u32 data)
2556 {
2557         u16 ret_val = 0;
2558
2559         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2560                 ret_val = e1000_82580_rxpbs_table[data];
2561
2562         return ret_val;
2563 }
2564
2565 /**
2566  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2567  *  checksum
2568  *  @hw: pointer to the HW structure
2569  *  @offset: offset in words of the checksum protected region
2570  *
2571  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2572  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2573  **/
2574 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2575 {
2576         s32 ret_val = E1000_SUCCESS;
2577         u16 checksum = 0;
2578         u16 i, nvm_data;
2579
2580         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2581
2582         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2583                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2584                 if (ret_val) {
2585                         DEBUGOUT("NVM Read Error\n");
2586                         goto out;
2587                 }
2588                 checksum += nvm_data;
2589         }
2590
2591         if (checksum != (u16) NVM_SUM) {
2592                 DEBUGOUT("NVM Checksum Invalid\n");
2593                 ret_val = -E1000_ERR_NVM;
2594                 goto out;
2595         }
2596
2597 out:
2598         return ret_val;
2599 }
2600
2601 /**
2602  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2603  *  checksum
2604  *  @hw: pointer to the HW structure
2605  *  @offset: offset in words of the checksum protected region
2606  *
2607  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2608  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2609  *  value to the EEPROM.
2610  **/
2611 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2612 {
2613         s32 ret_val;
2614         u16 checksum = 0;
2615         u16 i, nvm_data;
2616
2617         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2618
2619         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2620                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2621                 if (ret_val) {
2622                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2623                         goto out;
2624                 }
2625                 checksum += nvm_data;
2626         }
2627         checksum = (u16) NVM_SUM - checksum;
2628         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2629                                     &checksum);
2630         if (ret_val)
2631                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2632
2633 out:
2634         return ret_val;
2635 }
2636
2637 /**
2638  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2639  *  @hw: pointer to the HW structure
2640  *
2641  *  Calculates the EEPROM section checksum by reading/adding each word of
2642  *  the EEPROM and then verifies that the sum of the EEPROM is
2643  *  equal to 0xBABA.
2644  **/
2645 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2646 {
2647         s32 ret_val;
2648         u16 eeprom_regions_count = 1;
2649         u16 j, nvm_data;
2650         u16 nvm_offset;
2651
2652         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2653
2654         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2655         if (ret_val) {
2656                 DEBUGOUT("NVM Read Error\n");
2657                 goto out;
2658         }
2659
2660         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2661                 /* if chekcsums compatibility bit is set validate checksums
2662                  * for all 4 ports. */
2663                 eeprom_regions_count = 4;
2664         }
2665
2666         for (j = 0; j < eeprom_regions_count; j++) {
2667                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2668                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2669                                                                   nvm_offset);
2670                 if (ret_val != E1000_SUCCESS)
2671                         goto out;
2672         }
2673
2674 out:
2675         return ret_val;
2676 }
2677
2678 /**
2679  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2680  *  @hw: pointer to the HW structure
2681  *
2682  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2683  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2684  *  checksum and writes the value to the EEPROM.
2685  **/
2686 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2687 {
2688         s32 ret_val;
2689         u16 j, nvm_data;
2690         u16 nvm_offset;
2691
2692         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2693
2694         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2695         if (ret_val) {
2696                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2697                 goto out;
2698         }
2699
2700         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2701                 /* set compatibility bit to validate checksums appropriately */
2702                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2703                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2704                                             &nvm_data);
2705                 if (ret_val) {
2706                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2707                         goto out;
2708                 }
2709         }
2710
2711         for (j = 0; j < 4; j++) {
2712                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2713                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2714                 if (ret_val)
2715                         goto out;
2716         }
2717
2718 out:
2719         return ret_val;
2720 }
2721
2722 /**
2723  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2724  *  @hw: pointer to the HW structure
2725  *
2726  *  Calculates the EEPROM section checksum by reading/adding each word of
2727  *  the EEPROM and then verifies that the sum of the EEPROM is
2728  *  equal to 0xBABA.
2729  **/
2730 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2731 {
2732         s32 ret_val = E1000_SUCCESS;
2733         u16 j;
2734         u16 nvm_offset;
2735
2736         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2737
2738         for (j = 0; j < 4; j++) {
2739                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2740                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2741                                                                   nvm_offset);
2742                 if (ret_val != E1000_SUCCESS)
2743                         goto out;
2744         }
2745
2746 out:
2747         return ret_val;
2748 }
2749
2750 /**
2751  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2752  *  @hw: pointer to the HW structure
2753  *
2754  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2755  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2756  *  checksum and writes the value to the EEPROM.
2757  **/
2758 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2759 {
2760         s32 ret_val = E1000_SUCCESS;
2761         u16 j;
2762         u16 nvm_offset;
2763
2764         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2765
2766         for (j = 0; j < 4; j++) {
2767                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2768                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2769                 if (ret_val != E1000_SUCCESS)
2770                         goto out;
2771         }
2772
2773 out:
2774         return ret_val;
2775 }
2776
2777 /**
2778  *  __e1000_access_emi_reg - Read/write EMI register
2779  *  @hw: pointer to the HW structure
2780  *  @addr: EMI address to program
2781  *  @data: pointer to value to read/write from/to the EMI address
2782  *  @read: boolean flag to indicate read or write
2783  **/
2784 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2785                                   u16 *data, bool read)
2786 {
2787         s32 ret_val;
2788
2789         DEBUGFUNC("__e1000_access_emi_reg");
2790
2791         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2792         if (ret_val)
2793                 return ret_val;
2794
2795         if (read)
2796                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2797         else
2798                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2799
2800         return ret_val;
2801 }
2802
2803 /**
2804  *  e1000_read_emi_reg - Read Extended Management Interface register
2805  *  @hw: pointer to the HW structure
2806  *  @addr: EMI address to program
2807  *  @data: value to be read from the EMI address
2808  **/
2809 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2810 {
2811         DEBUGFUNC("e1000_read_emi_reg");
2812
2813         return __e1000_access_emi_reg(hw, addr, data, true);
2814 }
2815
2816 /**
2817  *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2818  *  @hw: pointer to the HW structure
2819  *
2820  *  Initialize Marverl 1512 to work correctly with Avoton.
2821  **/
2822 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2823 {
2824         struct e1000_phy_info *phy = &hw->phy;
2825         s32 ret_val = E1000_SUCCESS;
2826
2827         DEBUGFUNC("e1000_initialize_M88E1512_phy");
2828
2829         /* Check if this is correct PHY. */
2830         if (phy->id != M88E1512_E_PHY_ID)
2831                 goto out;
2832
2833         /* Switch to PHY page 0xFF. */
2834         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2835         if (ret_val)
2836                 goto out;
2837
2838         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2839         if (ret_val)
2840                 goto out;
2841
2842         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2843         if (ret_val)
2844                 goto out;
2845
2846         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2847         if (ret_val)
2848                 goto out;
2849
2850         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2851         if (ret_val)
2852                 goto out;
2853
2854         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2855         if (ret_val)
2856                 goto out;
2857
2858         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2859         if (ret_val)
2860                 goto out;
2861
2862         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2863         if (ret_val)
2864                 goto out;
2865
2866         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2867         if (ret_val)
2868                 goto out;
2869
2870         /* Switch to PHY page 0xFB. */
2871         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2872         if (ret_val)
2873                 goto out;
2874
2875         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2876         if (ret_val)
2877                 goto out;
2878
2879         /* Switch to PHY page 0x12. */
2880         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2881         if (ret_val)
2882                 goto out;
2883
2884         /* Change mode to SGMII-to-Copper */
2885         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2886         if (ret_val)
2887                 goto out;
2888
2889         /* Return the PHY to page 0. */
2890         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2891         if (ret_val)
2892                 goto out;
2893
2894         ret_val = phy->ops.commit(hw);
2895         if (ret_val) {
2896                 DEBUGOUT("Error committing the PHY changes\n");
2897                 return ret_val;
2898         }
2899
2900         msec_delay(1000);
2901 out:
2902         return ret_val;
2903 }
2904
2905 /**
2906  *  e1000_set_eee_i350 - Enable/disable EEE support
2907  *  @hw: pointer to the HW structure
2908  *  @adv1g: boolean flag enabling 1G EEE advertisement
2909  *  @adv100m: boolean flag enabling 100M EEE advertisement
2910  *
2911  *  Enable/disable EEE based on setting in dev_spec structure.
2912  *
2913  **/
2914 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2915 {
2916         u32 ipcnfg, eeer;
2917
2918         DEBUGFUNC("e1000_set_eee_i350");
2919
2920         if ((hw->mac.type < e1000_i350) ||
2921             (hw->phy.media_type != e1000_media_type_copper))
2922                 goto out;
2923         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2924         eeer = E1000_READ_REG(hw, E1000_EEER);
2925
2926         /* enable or disable per user setting */
2927         if (!(hw->dev_spec._82575.eee_disable)) {
2928                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2929
2930                 if (adv100M)
2931                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2932                 else
2933                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2934
2935                 if (adv1G)
2936                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2937                 else
2938                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2939
2940                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2941                          E1000_EEER_LPI_FC);
2942
2943                 /* This bit should not be set in normal operation. */
2944                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2945                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2946         } else {
2947                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2948                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2949                           E1000_EEER_LPI_FC);
2950         }
2951         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2952         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2953         E1000_READ_REG(hw, E1000_IPCNFG);
2954         E1000_READ_REG(hw, E1000_EEER);
2955 out:
2956
2957         return E1000_SUCCESS;
2958 }
2959
2960 /**
2961  *  e1000_set_eee_i354 - Enable/disable EEE support
2962  *  @hw: pointer to the HW structure
2963  *  @adv1g: boolean flag enabling 1G EEE advertisement
2964  *  @adv100m: boolean flag enabling 100M EEE advertisement
2965  *
2966  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2967  *
2968  **/
2969 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2970 {
2971         struct e1000_phy_info *phy = &hw->phy;
2972         s32 ret_val = E1000_SUCCESS;
2973         u16 phy_data;
2974
2975         DEBUGFUNC("e1000_set_eee_i354");
2976
2977         if ((hw->phy.media_type != e1000_media_type_copper) ||
2978             ((phy->id != M88E1543_E_PHY_ID) &&
2979             (phy->id != M88E1512_E_PHY_ID)))
2980                 goto out;
2981
2982         if (!hw->dev_spec._82575.eee_disable) {
2983                 /* Switch to PHY page 18. */
2984                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2985                 if (ret_val)
2986                         goto out;
2987
2988                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2989                                             &phy_data);
2990                 if (ret_val)
2991                         goto out;
2992
2993                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2994                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2995                                              phy_data);
2996                 if (ret_val)
2997                         goto out;
2998
2999                 /* Return the PHY to page 0. */
3000                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3001                 if (ret_val)
3002                         goto out;
3003
3004                 /* Turn on EEE advertisement. */
3005                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3006                                                E1000_EEE_ADV_DEV_I354,
3007                                                &phy_data);
3008                 if (ret_val)
3009                         goto out;
3010
3011                 if (adv100M)
3012                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
3013                 else
3014                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
3015
3016                 if (adv1G)
3017                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
3018                 else
3019                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
3020
3021                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3022                                                 E1000_EEE_ADV_DEV_I354,
3023                                                 phy_data);
3024         } else {
3025                 /* Turn off EEE advertisement. */
3026                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3027                                                E1000_EEE_ADV_DEV_I354,
3028                                                &phy_data);
3029                 if (ret_val)
3030                         goto out;
3031
3032                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3033                               E1000_EEE_ADV_1000_SUPPORTED);
3034                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3035                                                 E1000_EEE_ADV_DEV_I354,
3036                                                 phy_data);
3037         }
3038
3039 out:
3040         return ret_val;
3041 }
3042
3043 /**
3044  *  e1000_get_eee_status_i354 - Get EEE status
3045  *  @hw: pointer to the HW structure
3046  *  @status: EEE status
3047  *
3048  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3049  *  been received.
3050  **/
3051 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3052 {
3053         struct e1000_phy_info *phy = &hw->phy;
3054         s32 ret_val = E1000_SUCCESS;
3055         u16 phy_data;
3056
3057         DEBUGFUNC("e1000_get_eee_status_i354");
3058
3059         /* Check if EEE is supported on this device. */
3060         if ((hw->phy.media_type != e1000_media_type_copper) ||
3061             ((phy->id != M88E1543_E_PHY_ID) &&
3062             (phy->id != M88E1512_E_PHY_ID)))
3063                 goto out;
3064
3065         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3066                                        E1000_PCS_STATUS_DEV_I354,
3067                                        &phy_data);
3068         if (ret_val)
3069                 goto out;
3070
3071         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3072                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3073
3074 out:
3075         return ret_val;
3076 }
3077
3078 /* Due to a hw errata, if the host tries to  configure the VFTA register
3079  * while performing queries from the BMC or DMA, then the VFTA in some
3080  * cases won't be written.
3081  */
3082
3083 /**
3084  *  e1000_clear_vfta_i350 - Clear VLAN filter table
3085  *  @hw: pointer to the HW structure
3086  *
3087  *  Clears the register array which contains the VLAN filter table by
3088  *  setting all the values to 0.
3089  **/
3090 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3091 {
3092         u32 offset;
3093         int i;
3094
3095         DEBUGFUNC("e1000_clear_vfta_350");
3096
3097         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3098                 for (i = 0; i < 10; i++)
3099                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3100
3101                 E1000_WRITE_FLUSH(hw);
3102         }
3103 }
3104
3105 /**
3106  *  e1000_write_vfta_i350 - Write value to VLAN filter table
3107  *  @hw: pointer to the HW structure
3108  *  @offset: register offset in VLAN filter table
3109  *  @value: register value written to VLAN filter table
3110  *
3111  *  Writes value at the given offset in the register array which stores
3112  *  the VLAN filter table.
3113  **/
3114 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3115 {
3116         int i;
3117
3118         DEBUGFUNC("e1000_write_vfta_350");
3119
3120         for (i = 0; i < 10; i++)
3121                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3122
3123         E1000_WRITE_FLUSH(hw);
3124 }
3125
3126
3127 /**
3128  *  e1000_set_i2c_bb - Enable I2C bit-bang
3129  *  @hw: pointer to the HW structure
3130  *
3131  *  Enable I2C bit-bang interface
3132  *
3133  **/
3134 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3135 {
3136         s32 ret_val = E1000_SUCCESS;
3137         u32 ctrl_ext, i2cparams;
3138
3139         DEBUGFUNC("e1000_set_i2c_bb");
3140
3141         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3142         ctrl_ext |= E1000_CTRL_I2C_ENA;
3143         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3144         E1000_WRITE_FLUSH(hw);
3145
3146         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3147         i2cparams |= E1000_I2CBB_EN;
3148         i2cparams |= E1000_I2C_DATA_OE_N;
3149         i2cparams |= E1000_I2C_CLK_OE_N;
3150         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3151         E1000_WRITE_FLUSH(hw);
3152
3153         return ret_val;
3154 }
3155
3156 /**
3157  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3158  *  @hw: pointer to hardware structure
3159  *  @byte_offset: byte offset to read
3160  *  @dev_addr: device address
3161  *  @data: value read
3162  *
3163  *  Performs byte read operation over I2C interface at
3164  *  a specified device address.
3165  **/
3166 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3167                                 u8 dev_addr, u8 *data)
3168 {
3169         s32 status = E1000_SUCCESS;
3170         u32 max_retry = 10;
3171         u32 retry = 1;
3172         u16 swfw_mask = 0;
3173
3174         bool nack = true;
3175
3176         DEBUGFUNC("e1000_read_i2c_byte_generic");
3177
3178         swfw_mask = E1000_SWFW_PHY0_SM;
3179
3180         do {
3181                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3182                     != E1000_SUCCESS) {
3183                         status = E1000_ERR_SWFW_SYNC;
3184                         goto read_byte_out;
3185                 }
3186
3187                 e1000_i2c_start(hw);
3188
3189                 /* Device Address and write indication */
3190                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3191                 if (status != E1000_SUCCESS)
3192                         goto fail;
3193
3194                 status = e1000_get_i2c_ack(hw);
3195                 if (status != E1000_SUCCESS)
3196                         goto fail;
3197
3198                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3199                 if (status != E1000_SUCCESS)
3200                         goto fail;
3201
3202                 status = e1000_get_i2c_ack(hw);
3203                 if (status != E1000_SUCCESS)
3204                         goto fail;
3205
3206                 e1000_i2c_start(hw);
3207
3208                 /* Device Address and read indication */
3209                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3210                 if (status != E1000_SUCCESS)
3211                         goto fail;
3212
3213                 status = e1000_get_i2c_ack(hw);
3214                 if (status != E1000_SUCCESS)
3215                         goto fail;
3216
3217                 status = e1000_clock_in_i2c_byte(hw, data);
3218                 if (status != E1000_SUCCESS)
3219                         goto fail;
3220
3221                 status = e1000_clock_out_i2c_bit(hw, nack);
3222                 if (status != E1000_SUCCESS)
3223                         goto fail;
3224
3225                 e1000_i2c_stop(hw);
3226                 break;
3227
3228 fail:
3229                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3230                 msec_delay(100);
3231                 e1000_i2c_bus_clear(hw);
3232                 retry++;
3233                 if (retry < max_retry)
3234                         DEBUGOUT("I2C byte read error - Retrying.\n");
3235                 else
3236                         DEBUGOUT("I2C byte read error.\n");
3237
3238         } while (retry < max_retry);
3239
3240         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3241
3242 read_byte_out:
3243
3244         return status;
3245 }
3246
3247 /**
3248  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3249  *  @hw: pointer to hardware structure
3250  *  @byte_offset: byte offset to write
3251  *  @dev_addr: device address
3252  *  @data: value to write
3253  *
3254  *  Performs byte write operation over I2C interface at
3255  *  a specified device address.
3256  **/
3257 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3258                                  u8 dev_addr, u8 data)
3259 {
3260         s32 status = E1000_SUCCESS;
3261         u32 max_retry = 1;
3262         u32 retry = 0;
3263         u16 swfw_mask = 0;
3264
3265         DEBUGFUNC("e1000_write_i2c_byte_generic");
3266
3267         swfw_mask = E1000_SWFW_PHY0_SM;
3268
3269         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3270                 status = E1000_ERR_SWFW_SYNC;
3271                 goto write_byte_out;
3272         }
3273
3274         do {
3275                 e1000_i2c_start(hw);
3276
3277                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3278                 if (status != E1000_SUCCESS)
3279                         goto fail;
3280
3281                 status = e1000_get_i2c_ack(hw);
3282                 if (status != E1000_SUCCESS)
3283                         goto fail;
3284
3285                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3286                 if (status != E1000_SUCCESS)
3287                         goto fail;
3288
3289                 status = e1000_get_i2c_ack(hw);
3290                 if (status != E1000_SUCCESS)
3291                         goto fail;
3292
3293                 status = e1000_clock_out_i2c_byte(hw, data);
3294                 if (status != E1000_SUCCESS)
3295                         goto fail;
3296
3297                 status = e1000_get_i2c_ack(hw);
3298                 if (status != E1000_SUCCESS)
3299                         goto fail;
3300
3301                 e1000_i2c_stop(hw);
3302                 break;
3303
3304 fail:
3305                 e1000_i2c_bus_clear(hw);
3306                 retry++;
3307                 if (retry < max_retry)
3308                         DEBUGOUT("I2C byte write error - Retrying.\n");
3309                 else
3310                         DEBUGOUT("I2C byte write error.\n");
3311         } while (retry < max_retry);
3312
3313         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3314
3315 write_byte_out:
3316
3317         return status;
3318 }
3319
3320 /**
3321  *  e1000_i2c_start - Sets I2C start condition
3322  *  @hw: pointer to hardware structure
3323  *
3324  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3325  **/
3326 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3327 {
3328         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3329
3330         DEBUGFUNC("e1000_i2c_start");
3331
3332         /* Start condition must begin with data and clock high */
3333         e1000_set_i2c_data(hw, &i2cctl, 1);
3334         e1000_raise_i2c_clk(hw, &i2cctl);
3335
3336         /* Setup time for start condition (4.7us) */
3337         usec_delay(E1000_I2C_T_SU_STA);
3338
3339         e1000_set_i2c_data(hw, &i2cctl, 0);
3340
3341         /* Hold time for start condition (4us) */
3342         usec_delay(E1000_I2C_T_HD_STA);
3343
3344         e1000_lower_i2c_clk(hw, &i2cctl);
3345
3346         /* Minimum low period of clock is 4.7 us */
3347         usec_delay(E1000_I2C_T_LOW);
3348
3349 }
3350
3351 /**
3352  *  e1000_i2c_stop - Sets I2C stop condition
3353  *  @hw: pointer to hardware structure
3354  *
3355  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3356  **/
3357 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3358 {
3359         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3360
3361         DEBUGFUNC("e1000_i2c_stop");
3362
3363         /* Stop condition must begin with data low and clock high */
3364         e1000_set_i2c_data(hw, &i2cctl, 0);
3365         e1000_raise_i2c_clk(hw, &i2cctl);
3366
3367         /* Setup time for stop condition (4us) */
3368         usec_delay(E1000_I2C_T_SU_STO);
3369
3370         e1000_set_i2c_data(hw, &i2cctl, 1);
3371
3372         /* bus free time between stop and start (4.7us)*/
3373         usec_delay(E1000_I2C_T_BUF);
3374 }
3375
3376 /**
3377  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3378  *  @hw: pointer to hardware structure
3379  *  @data: data byte to clock in
3380  *
3381  *  Clocks in one byte data via I2C data/clock
3382  **/
3383 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3384 {
3385         s32 i;
3386         bool bit = 0;
3387
3388         DEBUGFUNC("e1000_clock_in_i2c_byte");
3389
3390         *data = 0;
3391         for (i = 7; i >= 0; i--) {
3392                 e1000_clock_in_i2c_bit(hw, &bit);
3393                 *data |= bit << i;
3394         }
3395
3396         return E1000_SUCCESS;
3397 }
3398
3399 /**
3400  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3401  *  @hw: pointer to hardware structure
3402  *  @data: data byte clocked out
3403  *
3404  *  Clocks out one byte data via I2C data/clock
3405  **/
3406 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3407 {
3408         s32 status = E1000_SUCCESS;
3409         s32 i;
3410         u32 i2cctl;
3411         bool bit = 0;
3412
3413         DEBUGFUNC("e1000_clock_out_i2c_byte");
3414
3415         for (i = 7; i >= 0; i--) {
3416                 bit = (data >> i) & 0x1;
3417                 status = e1000_clock_out_i2c_bit(hw, bit);
3418
3419                 if (status != E1000_SUCCESS)
3420                         break;
3421         }
3422
3423         /* Release SDA line (set high) */
3424         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3425
3426         i2cctl |= E1000_I2C_DATA_OE_N;
3427         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3428         E1000_WRITE_FLUSH(hw);
3429
3430         return status;
3431 }
3432
3433 /**
3434  *  e1000_get_i2c_ack - Polls for I2C ACK
3435  *  @hw: pointer to hardware structure
3436  *
3437  *  Clocks in/out one bit via I2C data/clock
3438  **/
3439 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3440 {
3441         s32 status = E1000_SUCCESS;
3442         u32 i = 0;
3443         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3444         u32 timeout = 10;
3445         bool ack = true;
3446
3447         DEBUGFUNC("e1000_get_i2c_ack");
3448
3449         e1000_raise_i2c_clk(hw, &i2cctl);
3450
3451         /* Minimum high period of clock is 4us */
3452         usec_delay(E1000_I2C_T_HIGH);
3453
3454         /* Wait until SCL returns high */
3455         for (i = 0; i < timeout; i++) {
3456                 usec_delay(1);
3457                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3458                 if (i2cctl & E1000_I2C_CLK_IN)
3459                         break;
3460         }
3461         if (!(i2cctl & E1000_I2C_CLK_IN))
3462                 return E1000_ERR_I2C;
3463
3464         ack = e1000_get_i2c_data(&i2cctl);
3465         if (ack) {
3466                 DEBUGOUT("I2C ack was not received.\n");
3467                 status = E1000_ERR_I2C;
3468         }
3469
3470         e1000_lower_i2c_clk(hw, &i2cctl);
3471
3472         /* Minimum low period of clock is 4.7 us */
3473         usec_delay(E1000_I2C_T_LOW);
3474
3475         return status;
3476 }
3477
3478 /**
3479  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3480  *  @hw: pointer to hardware structure
3481  *  @data: read data value
3482  *
3483  *  Clocks in one bit via I2C data/clock
3484  **/
3485 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3486 {
3487         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3488
3489         DEBUGFUNC("e1000_clock_in_i2c_bit");
3490
3491         e1000_raise_i2c_clk(hw, &i2cctl);
3492
3493         /* Minimum high period of clock is 4us */
3494         usec_delay(E1000_I2C_T_HIGH);
3495
3496         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3497         *data = e1000_get_i2c_data(&i2cctl);
3498
3499         e1000_lower_i2c_clk(hw, &i2cctl);
3500
3501         /* Minimum low period of clock is 4.7 us */
3502         usec_delay(E1000_I2C_T_LOW);
3503
3504         return E1000_SUCCESS;
3505 }
3506
3507 /**
3508  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3509  *  @hw: pointer to hardware structure
3510  *  @data: data value to write
3511  *
3512  *  Clocks out one bit via I2C data/clock
3513  **/
3514 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3515 {
3516         s32 status;
3517         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3518
3519         DEBUGFUNC("e1000_clock_out_i2c_bit");
3520
3521         status = e1000_set_i2c_data(hw, &i2cctl, data);
3522         if (status == E1000_SUCCESS) {
3523                 e1000_raise_i2c_clk(hw, &i2cctl);
3524
3525                 /* Minimum high period of clock is 4us */
3526                 usec_delay(E1000_I2C_T_HIGH);
3527
3528                 e1000_lower_i2c_clk(hw, &i2cctl);
3529
3530                 /* Minimum low period of clock is 4.7 us.
3531                  * This also takes care of the data hold time.
3532                  */
3533                 usec_delay(E1000_I2C_T_LOW);
3534         } else {
3535                 status = E1000_ERR_I2C;
3536                 DEBUGOUT1("I2C data was not set to %X\n", data);
3537         }
3538
3539         return status;
3540 }
3541 /**
3542  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3543  *  @hw: pointer to hardware structure
3544  *  @i2cctl: Current value of I2CCTL register
3545  *
3546  *  Raises the I2C clock line '0'->'1'
3547  **/
3548 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3549 {
3550         DEBUGFUNC("e1000_raise_i2c_clk");
3551
3552         *i2cctl |= E1000_I2C_CLK_OUT;
3553         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3554         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3555         E1000_WRITE_FLUSH(hw);
3556
3557         /* SCL rise time (1000ns) */
3558         usec_delay(E1000_I2C_T_RISE);
3559 }
3560
3561 /**
3562  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3563  *  @hw: pointer to hardware structure
3564  *  @i2cctl: Current value of I2CCTL register
3565  *
3566  *  Lowers the I2C clock line '1'->'0'
3567  **/
3568 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3569 {
3570
3571         DEBUGFUNC("e1000_lower_i2c_clk");
3572
3573         *i2cctl &= ~E1000_I2C_CLK_OUT;
3574         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3575         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3576         E1000_WRITE_FLUSH(hw);
3577
3578         /* SCL fall time (300ns) */
3579         usec_delay(E1000_I2C_T_FALL);
3580 }
3581
3582 /**
3583  *  e1000_set_i2c_data - Sets the I2C data bit
3584  *  @hw: pointer to hardware structure
3585  *  @i2cctl: Current value of I2CCTL register
3586  *  @data: I2C data value (0 or 1) to set
3587  *
3588  *  Sets the I2C data bit
3589  **/
3590 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3591 {
3592         s32 status = E1000_SUCCESS;
3593
3594         DEBUGFUNC("e1000_set_i2c_data");
3595
3596         if (data)
3597                 *i2cctl |= E1000_I2C_DATA_OUT;
3598         else
3599                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3600
3601         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3602         *i2cctl |= E1000_I2C_CLK_OE_N;
3603         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3604         E1000_WRITE_FLUSH(hw);
3605
3606         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3607         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3608
3609         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3610         if (data != e1000_get_i2c_data(i2cctl)) {
3611                 status = E1000_ERR_I2C;
3612                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3613         }
3614
3615         return status;
3616 }
3617
3618 /**
3619  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3620  *  @hw: pointer to hardware structure
3621  *  @i2cctl: Current value of I2CCTL register
3622  *
3623  *  Returns the I2C data bit value
3624  **/
3625 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3626 {
3627         bool data;
3628
3629         DEBUGFUNC("e1000_get_i2c_data");
3630
3631         if (*i2cctl & E1000_I2C_DATA_IN)
3632                 data = 1;
3633         else
3634                 data = 0;
3635
3636         return data;
3637 }
3638
3639 /**
3640  *  e1000_i2c_bus_clear - Clears the I2C bus
3641  *  @hw: pointer to hardware structure
3642  *
3643  *  Clears the I2C bus by sending nine clock pulses.
3644  *  Used when data line is stuck low.
3645  **/
3646 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3647 {
3648         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3649         u32 i;
3650
3651         DEBUGFUNC("e1000_i2c_bus_clear");
3652
3653         e1000_i2c_start(hw);
3654
3655         e1000_set_i2c_data(hw, &i2cctl, 1);
3656
3657         for (i = 0; i < 9; i++) {
3658                 e1000_raise_i2c_clk(hw, &i2cctl);
3659
3660                 /* Min high period of clock is 4us */
3661                 usec_delay(E1000_I2C_T_HIGH);
3662
3663                 e1000_lower_i2c_clk(hw, &i2cctl);
3664
3665                 /* Min low period of clock is 4.7us*/
3666                 usec_delay(E1000_I2C_T_LOW);
3667         }
3668
3669         e1000_i2c_start(hw);
3670
3671         /* Put the i2c bus back to default state */
3672         e1000_i2c_stop(hw);
3673 }
3674