1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
8 /* forward declaration */
9 s32 e1000_init_hw_base(struct e1000_hw *hw);
10 void e1000_power_down_phy_copper_base(struct e1000_hw *hw);
11 extern void e1000_rx_fifo_flush_base(struct e1000_hw *hw);
12 s32 e1000_acquire_phy_base(struct e1000_hw *hw);
13 void e1000_release_phy_base(struct e1000_hw *hw);
15 /* Transmit Descriptor - Advanced */
16 union e1000_adv_tx_desc {
18 __le64 buffer_addr; /* Address of descriptor's data buf */
23 __le64 rsvd; /* Reserved */
29 /* Context descriptors */
30 struct e1000_adv_tx_context_desc {
31 __le32 vlan_macip_lens;
36 __le32 type_tucmd_mlhl;
40 /* Adv Transmit Descriptor Config Masks */
41 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
42 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
43 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
44 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
45 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
46 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
47 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
48 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
49 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
50 #define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */
51 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */
52 #define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */
53 #define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
54 #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
55 #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
56 #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
57 /* 1st & Last TSO-full iSCSI PDU*/
58 #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800
59 #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
60 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
62 /* Advanced Transmit Context Descriptor Config */
63 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
64 #define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
65 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
66 #define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
67 #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
68 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
69 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
70 #define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
71 /* IPSec Encrypt Enable for ESP */
72 #define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
73 /* Req requires Markers and CRC */
74 #define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000
75 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
76 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
77 /* Adv ctxt IPSec SA IDX mask */
78 #define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF
79 /* Adv ctxt IPSec ESP len mask */
80 #define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF
82 #define E1000_RAR_ENTRIES_BASE 16
84 /* Receive Descriptor - Advanced */
85 union e1000_adv_rx_desc {
87 __le64 pkt_addr; /* Packet buffer address */
88 __le64 hdr_addr; /* Header buffer address */
95 __le16 pkt_info; /*RSS type, Pkt type*/
96 /* Split Header, header buffer len */
101 __le32 rss; /* RSS Hash */
103 __le16 ip_id; /* IP id */
104 __le16 csum; /* Packet Checksum */
109 __le32 status_error; /* ext status/error */
110 __le16 length; /* Packet length */
111 __le16 vlan; /* VLAN tag */
113 } wb; /* writeback */
116 /* Additional Transmit Descriptor Control definitions */
117 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
119 /* Additional Receive Descriptor Control definitions */
120 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
122 /* SRRCTL bit definitions */
123 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
124 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
125 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
127 #endif /* _E1000_BASE_H_ */