drivers/net/e1000/base/e1000_hw.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _E1000_HW_H_
  35 #define _E1000_HW_H_
  36
  37 #include "e1000_osdep.h"
  38 #include "e1000_regs.h"
  39 #include "e1000_defines.h"
  40
  41 struct e1000_hw;
  42
  43 #define E1000_DEV_ID_82542                      0x1000
  44 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  45 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  46 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  47 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  48 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  49 #define E1000_DEV_ID_82544GC_LOM                0x100D
  50 #define E1000_DEV_ID_82540EM                    0x100E
  51 #define E1000_DEV_ID_82540EM_LOM                0x1015
  52 #define E1000_DEV_ID_82540EP_LOM                0x1016
  53 #define E1000_DEV_ID_82540EP                    0x1017
  54 #define E1000_DEV_ID_82540EP_LP                 0x101E
  55 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  56 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  57 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  58 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  59 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  60 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  61 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  62 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  63 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  64 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  65 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  66 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  67 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  69 #define E1000_DEV_ID_82541EI                    0x1013
  70 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  71 #define E1000_DEV_ID_82541ER_LOM                0x1014
  72 #define E1000_DEV_ID_82541ER                    0x1078
  73 #define E1000_DEV_ID_82541GI                    0x1076
  74 #define E1000_DEV_ID_82541GI_LF                 0x107C
  75 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  76 #define E1000_DEV_ID_82547EI                    0x1019
  77 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  78 #define E1000_DEV_ID_82547GI                    0x1075
  79 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  80 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  81 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  82 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  83 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  84 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  85 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  86 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  87 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  88 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  89 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  90 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  91 #define E1000_DEV_ID_82572EI                    0x10B9
  92 #define E1000_DEV_ID_82573E                     0x108B
  93 #define E1000_DEV_ID_82573E_IAMT                0x108C
  94 #define E1000_DEV_ID_82573L                     0x109A
  95 #define E1000_DEV_ID_82574L                     0x10D3
  96 #define E1000_DEV_ID_82574LA                    0x10F6
  97 #define E1000_DEV_ID_82583V                     0x150C
  98 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
  99 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 102 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 103 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 104 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 105 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 106 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 107 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 108 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 109 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 110 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 111 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 112 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 113 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 114 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 115 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 116 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 117 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 118 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 119 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 120 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 121 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 122 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 123 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 124 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 125 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 126 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 127 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 128 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 129 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 130 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 131 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 132 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 133 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 134 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 135 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 136 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 137 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 138 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 139 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F /* Sunrise Point PCH */
 140 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570 /* Sunrise Point PCH */
 141 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7 /* Sunrise Point-H PCH */
 142 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8 /* Sunrise Point-H PCH */
 143 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9 /* LEWISBURG PCH */
 144 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
 145 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
 146 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
 147 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
 148 #define E1000_DEV_ID_82576                      0x10C9
 149 #define E1000_DEV_ID_82576_FIBER                0x10E6
 150 #define E1000_DEV_ID_82576_SERDES               0x10E7
 151 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 152 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 153 #define E1000_DEV_ID_82576_NS                   0x150A
 154 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 155 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 156 #define E1000_DEV_ID_82576_VF                   0x10CA
 157 #define E1000_DEV_ID_82576_VF_HV                0x152D
 158 #define E1000_DEV_ID_I350_VF                    0x1520
 159 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 160 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 161 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 162 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 163 #define E1000_DEV_ID_82580_COPPER               0x150E
 164 #define E1000_DEV_ID_82580_FIBER                0x150F
 165 #define E1000_DEV_ID_82580_SERDES               0x1510
 166 #define E1000_DEV_ID_82580_SGMII                0x1511
 167 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 168 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 169 #define E1000_DEV_ID_I350_COPPER                0x1521
 170 #define E1000_DEV_ID_I350_FIBER                 0x1522
 171 #define E1000_DEV_ID_I350_SERDES                0x1523
 172 #define E1000_DEV_ID_I350_SGMII                 0x1524
 173 #define E1000_DEV_ID_I350_DA4                   0x1546
 174 #define E1000_DEV_ID_I210_COPPER                0x1533
 175 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 176 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 177 #define E1000_DEV_ID_I210_FIBER                 0x1536
 178 #define E1000_DEV_ID_I210_SERDES                0x1537
 179 #define E1000_DEV_ID_I210_SGMII                 0x1538
 180 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 181 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 182 #define E1000_DEV_ID_I211_COPPER                0x1539
 183 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 184 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 185 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 186 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 187 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 188 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 189 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 190
 191 #define E1000_REVISION_0        0
 192 #define E1000_REVISION_1        1
 193 #define E1000_REVISION_2        2
 194 #define E1000_REVISION_3        3
 195 #define E1000_REVISION_4        4
 196
 197 #define E1000_FUNC_0            0
 198 #define E1000_FUNC_1            1
 199 #define E1000_FUNC_2            2
 200 #define E1000_FUNC_3            3
 201
 202 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 203 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 204 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 205 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 206
 207 enum e1000_mac_type {
 208         e1000_undefined = 0,
 209         e1000_82542,
 210         e1000_82543,
 211         e1000_82544,
 212         e1000_82540,
 213         e1000_82545,
 214         e1000_82545_rev_3,
 215         e1000_82546,
 216         e1000_82546_rev_3,
 217         e1000_82541,
 218         e1000_82541_rev_2,
 219         e1000_82547,
 220         e1000_82547_rev_2,
 221         e1000_82571,
 222         e1000_82572,
 223         e1000_82573,
 224         e1000_82574,
 225         e1000_82583,
 226         e1000_80003es2lan,
 227         e1000_ich8lan,
 228         e1000_ich9lan,
 229         e1000_ich10lan,
 230         e1000_pchlan,
 231         e1000_pch2lan,
 232         e1000_pch_lpt,
 233         e1000_pch_spt,
 234         e1000_82575,
 235         e1000_82576,
 236         e1000_82580,
 237         e1000_i350,
 238         e1000_i354,
 239         e1000_i210,
 240         e1000_i211,
 241         e1000_vfadapt,
 242         e1000_vfadapt_i350,
 243         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 244 };
 245
 246 enum e1000_media_type {
 247         e1000_media_type_unknown = 0,
 248         e1000_media_type_copper = 1,
 249         e1000_media_type_fiber = 2,
 250         e1000_media_type_internal_serdes = 3,
 251         e1000_num_media_types
 252 };
 253
 254 enum e1000_nvm_type {
 255         e1000_nvm_unknown = 0,
 256         e1000_nvm_none,
 257         e1000_nvm_eeprom_spi,
 258         e1000_nvm_eeprom_microwire,
 259         e1000_nvm_flash_hw,
 260         e1000_nvm_invm,
 261         e1000_nvm_flash_sw
 262 };
 263
 264 enum e1000_nvm_override {
 265         e1000_nvm_override_none = 0,
 266         e1000_nvm_override_spi_small,
 267         e1000_nvm_override_spi_large,
 268         e1000_nvm_override_microwire_small,
 269         e1000_nvm_override_microwire_large
 270 };
 271
 272 enum e1000_phy_type {
 273         e1000_phy_unknown = 0,
 274         e1000_phy_none,
 275         e1000_phy_m88,
 276         e1000_phy_igp,
 277         e1000_phy_igp_2,
 278         e1000_phy_gg82563,
 279         e1000_phy_igp_3,
 280         e1000_phy_ife,
 281         e1000_phy_bm,
 282         e1000_phy_82578,
 283         e1000_phy_82577,
 284         e1000_phy_82579,
 285         e1000_phy_i217,
 286         e1000_phy_82580,
 287         e1000_phy_vf,
 288         e1000_phy_i210,
 289 };
 290
 291 enum e1000_bus_type {
 292         e1000_bus_type_unknown = 0,
 293         e1000_bus_type_pci,
 294         e1000_bus_type_pcix,
 295         e1000_bus_type_pci_express,
 296         e1000_bus_type_reserved
 297 };
 298
 299 enum e1000_bus_speed {
 300         e1000_bus_speed_unknown = 0,
 301         e1000_bus_speed_33,
 302         e1000_bus_speed_66,
 303         e1000_bus_speed_100,
 304         e1000_bus_speed_120,
 305         e1000_bus_speed_133,
 306         e1000_bus_speed_2500,
 307         e1000_bus_speed_5000,
 308         e1000_bus_speed_reserved
 309 };
 310
 311 enum e1000_bus_width {
 312         e1000_bus_width_unknown = 0,
 313         e1000_bus_width_pcie_x1,
 314         e1000_bus_width_pcie_x2,
 315         e1000_bus_width_pcie_x4 = 4,
 316         e1000_bus_width_pcie_x8 = 8,
 317         e1000_bus_width_32,
 318         e1000_bus_width_64,
 319         e1000_bus_width_reserved
 320 };
 321
 322 enum e1000_1000t_rx_status {
 323         e1000_1000t_rx_status_not_ok = 0,
 324         e1000_1000t_rx_status_ok,
 325         e1000_1000t_rx_status_undefined = 0xFF
 326 };
 327
 328 enum e1000_rev_polarity {
 329         e1000_rev_polarity_normal = 0,
 330         e1000_rev_polarity_reversed,
 331         e1000_rev_polarity_undefined = 0xFF
 332 };
 333
 334 enum e1000_fc_mode {
 335         e1000_fc_none = 0,
 336         e1000_fc_rx_pause,
 337         e1000_fc_tx_pause,
 338         e1000_fc_full,
 339         e1000_fc_default = 0xFF
 340 };
 341
 342 enum e1000_ffe_config {
 343         e1000_ffe_config_enabled = 0,
 344         e1000_ffe_config_active,
 345         e1000_ffe_config_blocked
 346 };
 347
 348 enum e1000_dsp_config {
 349         e1000_dsp_config_disabled = 0,
 350         e1000_dsp_config_enabled,
 351         e1000_dsp_config_activated,
 352         e1000_dsp_config_undefined = 0xFF
 353 };
 354
 355 enum e1000_ms_type {
 356         e1000_ms_hw_default = 0,
 357         e1000_ms_force_master,
 358         e1000_ms_force_slave,
 359         e1000_ms_auto
 360 };
 361
 362 enum e1000_smart_speed {
 363         e1000_smart_speed_default = 0,
 364         e1000_smart_speed_on,
 365         e1000_smart_speed_off
 366 };
 367
 368 enum e1000_serdes_link_state {
 369         e1000_serdes_link_down = 0,
 370         e1000_serdes_link_autoneg_progress,
 371         e1000_serdes_link_autoneg_complete,
 372         e1000_serdes_link_forced_up
 373 };
 374
 375 #define __le16 u16
 376 #define __le32 u32
 377 #define __le64 u64
 378 /* Receive Descriptor */
 379 struct e1000_rx_desc {
 380         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 381         __le16 length;      /* Length of data DMAed into data buffer */
 382         __le16 csum; /* Packet checksum */
 383         u8  status;  /* Descriptor status */
 384         u8  errors;  /* Descriptor Errors */
 385         __le16 special;
 386 };
 387
 388 /* Receive Descriptor - Extended */
 389 union e1000_rx_desc_extended {
 390         struct {
 391                 __le64 buffer_addr;
 392                 __le64 reserved;
 393         } read;
 394         struct {
 395                 struct {
 396                         __le32 mrq; /* Multiple Rx Queues */
 397                         union {
 398                                 __le32 rss; /* RSS Hash */
 399                                 struct {
 400                                         __le16 ip_id;  /* IP id */
 401                                         __le16 csum;   /* Packet Checksum */
 402                                 } csum_ip;
 403                         } hi_dword;
 404                 } lower;
 405                 struct {
 406                         __le32 status_error;  /* ext status/error */
 407                         __le16 length;
 408                         __le16 vlan; /* VLAN tag */
 409                 } upper;
 410         } wb;  /* writeback */
 411 };
 412
 413 #define MAX_PS_BUFFERS 4
 414
 415 /* Number of packet split data buffers (not including the header buffer) */
 416 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 417
 418 /* Receive Descriptor - Packet Split */
 419 union e1000_rx_desc_packet_split {
 420         struct {
 421                 /* one buffer for protocol header(s), three data buffers */
 422                 __le64 buffer_addr[MAX_PS_BUFFERS];
 423         } read;
 424         struct {
 425                 struct {
 426                         __le32 mrq;  /* Multiple Rx Queues */
 427                         union {
 428                                 __le32 rss; /* RSS Hash */
 429                                 struct {
 430                                         __le16 ip_id;    /* IP id */
 431                                         __le16 csum;     /* Packet Checksum */
 432                                 } csum_ip;
 433                         } hi_dword;
 434                 } lower;
 435                 struct {
 436                         __le32 status_error;  /* ext status/error */
 437                         __le16 length0;  /* length of buffer 0 */
 438                         __le16 vlan;  /* VLAN tag */
 439                 } middle;
 440                 struct {
 441                         __le16 header_status;
 442                         /* length of buffers 1-3 */
 443                         __le16 length[PS_PAGE_BUFFERS];
 444                 } upper;
 445                 __le64 reserved;
 446         } wb; /* writeback */
 447 };
 448
 449 /* Transmit Descriptor */
 450 struct e1000_tx_desc {
 451         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 452         union {
 453                 __le32 data;
 454                 struct {
 455                         __le16 length;  /* Data buffer length */
 456                         u8 cso;  /* Checksum offset */
 457                         u8 cmd;  /* Descriptor control */
 458                 } flags;
 459         } lower;
 460         union {
 461                 __le32 data;
 462                 struct {
 463                         u8 status; /* Descriptor status */
 464                         u8 css;  /* Checksum start */
 465                         __le16 special;
 466                 } fields;
 467         } upper;
 468 };
 469
 470 /* Offload Context Descriptor */
 471 struct e1000_context_desc {
 472         union {
 473                 __le32 ip_config;
 474                 struct {
 475                         u8 ipcss;  /* IP checksum start */
 476                         u8 ipcso;  /* IP checksum offset */
 477                         __le16 ipcse;  /* IP checksum end */
 478                 } ip_fields;
 479         } lower_setup;
 480         union {
 481                 __le32 tcp_config;
 482                 struct {
 483                         u8 tucss;  /* TCP checksum start */
 484                         u8 tucso;  /* TCP checksum offset */
 485                         __le16 tucse;  /* TCP checksum end */
 486                 } tcp_fields;
 487         } upper_setup;
 488         __le32 cmd_and_length;
 489         union {
 490                 __le32 data;
 491                 struct {
 492                         u8 status;  /* Descriptor status */
 493                         u8 hdr_len;  /* Header length */
 494                         __le16 mss;  /* Maximum segment size */
 495                 } fields;
 496         } tcp_seg_setup;
 497 };
 498
 499 /* Offload data descriptor */
 500 struct e1000_data_desc {
 501         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 502         union {
 503                 __le32 data;
 504                 struct {
 505                         __le16 length;  /* Data buffer length */
 506                         u8 typ_len_ext;
 507                         u8 cmd;
 508                 } flags;
 509         } lower;
 510         union {
 511                 __le32 data;
 512                 struct {
 513                         u8 status;  /* Descriptor status */
 514                         u8 popts;  /* Packet Options */
 515                         __le16 special;
 516                 } fields;
 517         } upper;
 518 };
 519
 520 /* Statistics counters collected by the MAC */
 521 struct e1000_hw_stats {
 522         u64 crcerrs;
 523         u64 algnerrc;
 524         u64 symerrs;
 525         u64 rxerrc;
 526         u64 mpc;
 527         u64 scc;
 528         u64 ecol;
 529         u64 mcc;
 530         u64 latecol;
 531         u64 colc;
 532         u64 dc;
 533         u64 tncrs;
 534         u64 sec;
 535         u64 cexterr;
 536         u64 rlec;
 537         u64 xonrxc;
 538         u64 xontxc;
 539         u64 xoffrxc;
 540         u64 xofftxc;
 541         u64 fcruc;
 542         u64 prc64;
 543         u64 prc127;
 544         u64 prc255;
 545         u64 prc511;
 546         u64 prc1023;
 547         u64 prc1522;
 548         u64 gprc;
 549         u64 bprc;
 550         u64 mprc;
 551         u64 gptc;
 552         u64 gorc;
 553         u64 gotc;
 554         u64 rnbc;
 555         u64 ruc;
 556         u64 rfc;
 557         u64 roc;
 558         u64 rjc;
 559         u64 mgprc;
 560         u64 mgpdc;
 561         u64 mgptc;
 562         u64 tor;
 563         u64 tot;
 564         u64 tpr;
 565         u64 tpt;
 566         u64 ptc64;
 567         u64 ptc127;
 568         u64 ptc255;
 569         u64 ptc511;
 570         u64 ptc1023;
 571         u64 ptc1522;
 572         u64 mptc;
 573         u64 bptc;
 574         u64 tsctc;
 575         u64 tsctfc;
 576         u64 iac;
 577         u64 icrxptc;
 578         u64 icrxatc;
 579         u64 ictxptc;
 580         u64 ictxatc;
 581         u64 ictxqec;
 582         u64 ictxqmtc;
 583         u64 icrxdmtc;
 584         u64 icrxoc;
 585         u64 cbtmpc;
 586         u64 htdpmc;
 587         u64 cbrdpc;
 588         u64 cbrmpc;
 589         u64 rpthc;
 590         u64 hgptc;
 591         u64 htcbdpc;
 592         u64 hgorc;
 593         u64 hgotc;
 594         u64 lenerrs;
 595         u64 scvpc;
 596         u64 hrmpc;
 597         u64 doosync;
 598         u64 o2bgptc;
 599         u64 o2bspc;
 600         u64 b2ospc;
 601         u64 b2ogprc;
 602 };
 603
 604 struct e1000_vf_stats {
 605         u64 base_gprc;
 606         u64 base_gptc;
 607         u64 base_gorc;
 608         u64 base_gotc;
 609         u64 base_mprc;
 610         u64 base_gotlbc;
 611         u64 base_gptlbc;
 612         u64 base_gorlbc;
 613         u64 base_gprlbc;
 614
 615         u32 last_gprc;
 616         u32 last_gptc;
 617         u32 last_gorc;
 618         u32 last_gotc;
 619         u32 last_mprc;
 620         u32 last_gotlbc;
 621         u32 last_gptlbc;
 622         u32 last_gorlbc;
 623         u32 last_gprlbc;
 624
 625         u64 gprc;
 626         u64 gptc;
 627         u64 gorc;
 628         u64 gotc;
 629         u64 mprc;
 630         u64 gotlbc;
 631         u64 gptlbc;
 632         u64 gorlbc;
 633         u64 gprlbc;
 634 };
 635
 636 struct e1000_phy_stats {
 637         u32 idle_errors;
 638         u32 receive_errors;
 639 };
 640
 641 struct e1000_host_mng_dhcp_cookie {
 642         u32 signature;
 643         u8  status;
 644         u8  reserved0;
 645         u16 vlan_id;
 646         u32 reserved1;
 647         u16 reserved2;
 648         u8  reserved3;
 649         u8  checksum;
 650 };
 651
 652 /* Host Interface "Rev 1" */
 653 struct e1000_host_command_header {
 654         u8 command_id;
 655         u8 command_length;
 656         u8 command_options;
 657         u8 checksum;
 658 };
 659
 660 #define E1000_HI_MAX_DATA_LENGTH        252
 661 struct e1000_host_command_info {
 662         struct e1000_host_command_header command_header;
 663         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 664 };
 665
 666 /* Host Interface "Rev 2" */
 667 struct e1000_host_mng_command_header {
 668         u8  command_id;
 669         u8  checksum;
 670         u16 reserved1;
 671         u16 reserved2;
 672         u16 command_length;
 673 };
 674
 675 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 676 struct e1000_host_mng_command_info {
 677         struct e1000_host_mng_command_header command_header;
 678         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 679 };
 680
 681 #include "e1000_mac.h"
 682 #include "e1000_phy.h"
 683 #include "e1000_nvm.h"
 684 #include "e1000_manage.h"
 685 #include "e1000_mbx.h"
 686
 687 /* Function pointers for the MAC. */
 688 struct e1000_mac_operations {
 689         s32  (*init_params)(struct e1000_hw *);
 690         s32  (*id_led_init)(struct e1000_hw *);
 691         s32  (*blink_led)(struct e1000_hw *);
 692         bool (*check_mng_mode)(struct e1000_hw *);
 693         s32  (*check_for_link)(struct e1000_hw *);
 694         s32  (*cleanup_led)(struct e1000_hw *);
 695         void (*clear_hw_cntrs)(struct e1000_hw *);
 696         void (*clear_vfta)(struct e1000_hw *);
 697         s32  (*get_bus_info)(struct e1000_hw *);
 698         void (*set_lan_id)(struct e1000_hw *);
 699         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 700         s32  (*led_on)(struct e1000_hw *);
 701         s32  (*led_off)(struct e1000_hw *);
 702         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 703         s32  (*reset_hw)(struct e1000_hw *);
 704         s32  (*init_hw)(struct e1000_hw *);
 705         void (*shutdown_serdes)(struct e1000_hw *);
 706         void (*power_up_serdes)(struct e1000_hw *);
 707         s32  (*setup_link)(struct e1000_hw *);
 708         s32  (*setup_physical_interface)(struct e1000_hw *);
 709         s32  (*setup_led)(struct e1000_hw *);
 710         void (*write_vfta)(struct e1000_hw *, u32, u32);
 711         void (*config_collision_dist)(struct e1000_hw *);
 712         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 713         s32  (*read_mac_addr)(struct e1000_hw *);
 714         s32  (*validate_mdi_setting)(struct e1000_hw *);
 715         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 716         void (*release_swfw_sync)(struct e1000_hw *, u16);
 717 };
 718
 719 /* When to use various PHY register access functions:
 720  *
 721  *                 Func   Caller
 722  *   Function      Does   Does    When to use
 723  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 724  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 725  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 726  *                                on different pages
 727  *   X_reg_page    A      L,P     for multiple accesses of different regs
 728  *                                on the same page
 729  *
 730  * Where X=[read|write], L=locking, P=sets page, A=register access
 731  *
 732  */
 733 struct e1000_phy_operations {
 734         s32  (*init_params)(struct e1000_hw *);
 735         s32  (*acquire)(struct e1000_hw *);
 736         s32  (*cfg_on_link_up)(struct e1000_hw *);
 737         s32  (*check_polarity)(struct e1000_hw *);
 738         s32  (*check_reset_block)(struct e1000_hw *);
 739         s32  (*commit)(struct e1000_hw *);
 740         s32  (*force_speed_duplex)(struct e1000_hw *);
 741         s32  (*get_cfg_done)(struct e1000_hw *hw);
 742         s32  (*get_cable_length)(struct e1000_hw *);
 743         s32  (*get_info)(struct e1000_hw *);
 744         s32  (*set_page)(struct e1000_hw *, u16);
 745         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 746         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 747         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 748         void (*release)(struct e1000_hw *);
 749         s32  (*reset)(struct e1000_hw *);
 750         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 751         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 752         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 753         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 754         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 755         void (*power_up)(struct e1000_hw *);
 756         void (*power_down)(struct e1000_hw *);
 757         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 758         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 759 };
 760
 761 /* Function pointers for the NVM. */
 762 struct e1000_nvm_operations {
 763         s32  (*init_params)(struct e1000_hw *);
 764         s32  (*acquire)(struct e1000_hw *);
 765         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 766         void (*release)(struct e1000_hw *);
 767         void (*reload)(struct e1000_hw *);
 768         s32  (*update)(struct e1000_hw *);
 769         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 770         s32  (*validate)(struct e1000_hw *);
 771         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 772 };
 773
 774 struct e1000_mac_info {
 775         struct e1000_mac_operations ops;
 776         u8 addr[ETH_ADDR_LEN];
 777         u8 perm_addr[ETH_ADDR_LEN];
 778
 779         enum e1000_mac_type type;
 780
 781         u32 collision_delta;
 782         u32 ledctl_default;
 783         u32 ledctl_mode1;
 784         u32 ledctl_mode2;
 785         u32 mc_filter_type;
 786         u32 tx_packet_delta;
 787         u32 txcw;
 788
 789         u16 current_ifs_val;
 790         u16 ifs_max_val;
 791         u16 ifs_min_val;
 792         u16 ifs_ratio;
 793         u16 ifs_step_size;
 794         u16 mta_reg_count;
 795         u16 uta_reg_count;
 796
 797         /* Maximum size of the MTA register table in all supported adapters */
 798 #define MAX_MTA_REG 128
 799         u32 mta_shadow[MAX_MTA_REG];
 800         u16 rar_entry_count;
 801
 802         u8  forced_speed_duplex;
 803
 804         bool adaptive_ifs;
 805         bool has_fwsm;
 806         bool arc_subsystem_valid;
 807         bool asf_firmware_present;
 808         bool autoneg;
 809         bool autoneg_failed;
 810         bool get_link_status;
 811         bool in_ifs_mode;
 812         bool report_tx_early;
 813         enum e1000_serdes_link_state serdes_link_state;
 814         bool serdes_has_link;
 815         bool tx_pkt_filtering;
 816 };
 817
 818 struct e1000_phy_info {
 819         struct e1000_phy_operations ops;
 820         enum e1000_phy_type type;
 821
 822         enum e1000_1000t_rx_status local_rx;
 823         enum e1000_1000t_rx_status remote_rx;
 824         enum e1000_ms_type ms_type;
 825         enum e1000_ms_type original_ms_type;
 826         enum e1000_rev_polarity cable_polarity;
 827         enum e1000_smart_speed smart_speed;
 828
 829         u32 addr;
 830         u32 id;
 831         u32 reset_delay_us; /* in usec */
 832         u32 revision;
 833
 834         enum e1000_media_type media_type;
 835
 836         u16 autoneg_advertised;
 837         u16 autoneg_mask;
 838         u16 cable_length;
 839         u16 max_cable_length;
 840         u16 min_cable_length;
 841
 842         u8 mdix;
 843
 844         bool disable_polarity_correction;
 845         bool is_mdix;
 846         bool polarity_correction;
 847         bool speed_downgraded;
 848         bool autoneg_wait_to_complete;
 849 };
 850
 851 struct e1000_nvm_info {
 852         struct e1000_nvm_operations ops;
 853         enum e1000_nvm_type type;
 854         enum e1000_nvm_override override;
 855
 856         u32 flash_bank_size;
 857         u32 flash_base_addr;
 858
 859         u16 word_size;
 860         u16 delay_usec;
 861         u16 address_bits;
 862         u16 opcode_bits;
 863         u16 page_size;
 864 };
 865
 866 struct e1000_bus_info {
 867         enum e1000_bus_type type;
 868         enum e1000_bus_speed speed;
 869         enum e1000_bus_width width;
 870
 871         u16 func;
 872         u16 pci_cmd_word;
 873 };
 874
 875 struct e1000_fc_info {
 876         u32 high_water;  /* Flow control high-water mark */
 877         u32 low_water;  /* Flow control low-water mark */
 878         u16 pause_time;  /* Flow control pause timer */
 879         u16 refresh_time;  /* Flow control refresh timer */
 880         bool send_xon;  /* Flow control send XON */
 881         bool strict_ieee;  /* Strict IEEE mode */
 882         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 883         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 884 };
 885
 886 struct e1000_mbx_operations {
 887         s32 (*init_params)(struct e1000_hw *hw);
 888         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 889         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 890         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 891         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 892         s32 (*check_for_msg)(struct e1000_hw *, u16);
 893         s32 (*check_for_ack)(struct e1000_hw *, u16);
 894         s32 (*check_for_rst)(struct e1000_hw *, u16);
 895 };
 896
 897 struct e1000_mbx_stats {
 898         u32 msgs_tx;
 899         u32 msgs_rx;
 900
 901         u32 acks;
 902         u32 reqs;
 903         u32 rsts;
 904 };
 905
 906 struct e1000_mbx_info {
 907         struct e1000_mbx_operations ops;
 908         struct e1000_mbx_stats stats;
 909         u32 timeout;
 910         u32 usec_delay;
 911         u16 size;
 912 };
 913
 914 struct e1000_dev_spec_82541 {
 915         enum e1000_dsp_config dsp_config;
 916         enum e1000_ffe_config ffe_config;
 917         u16 spd_default;
 918         bool phy_init_script;
 919 };
 920
 921 struct e1000_dev_spec_82542 {
 922         bool dma_fairness;
 923 };
 924
 925 struct e1000_dev_spec_82543 {
 926         u32  tbi_compatibility;
 927         bool dma_fairness;
 928         bool init_phy_disabled;
 929 };
 930
 931 struct e1000_dev_spec_82571 {
 932         bool laa_is_present;
 933         u32 smb_counter;
 934         E1000_MUTEX swflag_mutex;
 935 };
 936
 937 struct e1000_dev_spec_80003es2lan {
 938         bool  mdic_wa_enable;
 939 };
 940
 941 struct e1000_shadow_ram {
 942         u16  value;
 943         bool modified;
 944 };
 945
 946 #define E1000_SHADOW_RAM_WORDS          2048
 947
 948 #ifdef ULP_SUPPORT
 949 /* I218 PHY Ultra Low Power (ULP) states */
 950 enum e1000_ulp_state {
 951         e1000_ulp_state_unknown,
 952         e1000_ulp_state_off,
 953         e1000_ulp_state_on,
 954 };
 955
 956 #endif /* ULP_SUPPORT */
 957 struct e1000_dev_spec_ich8lan {
 958         bool kmrn_lock_loss_workaround_enabled;
 959         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 960         E1000_MUTEX nvm_mutex;
 961         E1000_MUTEX swflag_mutex;
 962         bool nvm_k1_enabled;
 963         bool eee_disable;
 964         u16 eee_lp_ability;
 965 #ifdef ULP_SUPPORT
 966         enum e1000_ulp_state ulp_state;
 967         bool ulp_capability_disabled;
 968         bool during_suspend_flow;
 969         bool during_dpg_exit;
 970 #endif /* ULP_SUPPORT */
 971         u16 lat_enc;
 972         u16 max_ltr_enc;
 973         bool smbus_disable;
 974 };
 975
 976 struct e1000_dev_spec_82575 {
 977         bool sgmii_active;
 978         bool global_device_reset;
 979         bool eee_disable;
 980         bool module_plugged;
 981         bool clear_semaphore_once;
 982         u32 mtu;
 983         struct sfp_e1000_flags eth_flags;
 984         u8 media_port;
 985         bool media_changed;
 986 };
 987
 988 struct e1000_dev_spec_vf {
 989         u32 vf_number;
 990         u32 v2p_mailbox;
 991 };
 992
 993 struct e1000_hw {
 994         void *back;
 995
 996         u8 *hw_addr;
 997         u8 *flash_address;
 998         unsigned long io_base;
 999
1000         struct e1000_mac_info  mac;
1001         struct e1000_fc_info   fc;
1002         struct e1000_phy_info  phy;
1003         struct e1000_nvm_info  nvm;
1004         struct e1000_bus_info  bus;
1005         struct e1000_mbx_info mbx;
1006         struct e1000_host_mng_dhcp_cookie mng_cookie;
1007
1008         union {
1009                 struct e1000_dev_spec_82541 _82541;
1010                 struct e1000_dev_spec_82542 _82542;
1011                 struct e1000_dev_spec_82543 _82543;
1012                 struct e1000_dev_spec_82571 _82571;
1013                 struct e1000_dev_spec_80003es2lan _80003es2lan;
1014                 struct e1000_dev_spec_ich8lan ich8lan;
1015                 struct e1000_dev_spec_82575 _82575;
1016                 struct e1000_dev_spec_vf vf;
1017         } dev_spec;
1018
1019         u16 device_id;
1020         u16 subsystem_vendor_id;
1021         u16 subsystem_device_id;
1022         u16 vendor_id;
1023
1024         u8  revision_id;
1025 };
1026
1027 #include "e1000_82541.h"
1028 #include "e1000_82543.h"
1029 #include "e1000_82571.h"
1030 #include "e1000_80003es2lan.h"
1031 #include "e1000_ich8lan.h"
1032 #include "e1000_82575.h"
1033 #include "e1000_i210.h"
1034
1035 /* These functions must be implemented by drivers */
1036 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1037 void e1000_pci_set_mwi(struct e1000_hw *hw);
1038 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1039 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1040 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1041 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1042
1043 #endif