drivers/net/e1000/base/e1000_hw.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2020 Intel Corporation
   3  */
   4
   5 #ifndef _E1000_HW_H_
   6 #define _E1000_HW_H_
   7
   8 #include "e1000_osdep.h"
   9 #include "e1000_regs.h"
  10 #include "e1000_defines.h"
  11
  12 struct e1000_hw;
  13
  14 #define E1000_DEV_ID_82542                      0x1000
  15 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  16 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  17 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  18 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  19 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  20 #define E1000_DEV_ID_82544GC_LOM                0x100D
  21 #define E1000_DEV_ID_82540EM                    0x100E
  22 #define E1000_DEV_ID_82540EM_LOM                0x1015
  23 #define E1000_DEV_ID_82540EP_LOM                0x1016
  24 #define E1000_DEV_ID_82540EP                    0x1017
  25 #define E1000_DEV_ID_82540EP_LP                 0x101E
  26 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  27 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  28 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  29 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  30 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  31 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  32 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  33 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  34 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  35 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  36 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  37 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  38 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  39 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  40 #define E1000_DEV_ID_82541EI                    0x1013
  41 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  42 #define E1000_DEV_ID_82541ER_LOM                0x1014
  43 #define E1000_DEV_ID_82541ER                    0x1078
  44 #define E1000_DEV_ID_82541GI                    0x1076
  45 #define E1000_DEV_ID_82541GI_LF                 0x107C
  46 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  47 #define E1000_DEV_ID_82547EI                    0x1019
  48 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  49 #define E1000_DEV_ID_82547GI                    0x1075
  50 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  51 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  52 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  53 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  54 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  55 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  56 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  57 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  58 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  59 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  60 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  61 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  62 #define E1000_DEV_ID_82572EI                    0x10B9
  63 #define E1000_DEV_ID_82573E                     0x108B
  64 #define E1000_DEV_ID_82573E_IAMT                0x108C
  65 #define E1000_DEV_ID_82573L                     0x109A
  66 #define E1000_DEV_ID_82574L                     0x10D3
  67 #define E1000_DEV_ID_82574LA                    0x10F6
  68 #define E1000_DEV_ID_82583V                     0x150C
  69 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
  70 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
  71 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
  72 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
  73 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
  74 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
  75 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
  76 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
  77 #define E1000_DEV_ID_ICH8_IFE                   0x104C
  78 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
  79 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
  80 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
  81 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
  82 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
  83 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
  84 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
  85 #define E1000_DEV_ID_ICH9_BM                    0x10E5
  86 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
  87 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
  88 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
  89 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
  90 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
  91 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
  92 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
  93 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
  94 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
  95 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
  96 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
  97 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
  98 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
  99 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 100 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 101 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 102 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 103 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 104 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 105 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 106 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 107 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 108 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 109 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 110 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F /* Sunrise Point PCH */
 111 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570 /* Sunrise Point PCH */
 112 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7 /* Sunrise Point-H PCH */
 113 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8 /* Sunrise Point-H PCH */
 114 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9 /* LEWISBURG PCH */
 115 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
 116 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
 117 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
 118 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
 119 #define E1000_DEV_ID_PCH_CNP_I219_LM6           0x15BD
 120 #define E1000_DEV_ID_PCH_CNP_I219_V6            0x15BE
 121 #define E1000_DEV_ID_PCH_CNP_I219_LM7           0x15BB
 122 #define E1000_DEV_ID_PCH_CNP_I219_V7            0x15BC
 123 #define E1000_DEV_ID_PCH_ICP_I219_LM8           0x15DF
 124 #define E1000_DEV_ID_PCH_ICP_I219_V8            0x15E0
 125 #define E1000_DEV_ID_PCH_ICP_I219_LM9           0x15E1
 126 #define E1000_DEV_ID_PCH_ICP_I219_V9            0x15E2
 127 #define E1000_DEV_ID_PCH_ADL_I219_LM16          0x1A1E
 128 #define E1000_DEV_ID_PCH_ADL_I219_V16           0x1A1F
 129 #define E1000_DEV_ID_PCH_ADL_I219_LM17          0x1A1C
 130 #define E1000_DEV_ID_PCH_ADL_I219_V17           0x1A1D
 131 #define E1000_DEV_ID_82576                      0x10C9
 132 #define E1000_DEV_ID_82576_FIBER                0x10E6
 133 #define E1000_DEV_ID_82576_SERDES               0x10E7
 134 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 135 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 136 #define E1000_DEV_ID_82576_NS                   0x150A
 137 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 138 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 139 #define E1000_DEV_ID_82576_VF                   0x10CA
 140 #define E1000_DEV_ID_82576_VF_HV                0x152D
 141 #define E1000_DEV_ID_I350_VF                    0x1520
 142 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 143 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 144 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 145 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 146 #define E1000_DEV_ID_82580_COPPER               0x150E
 147 #define E1000_DEV_ID_82580_FIBER                0x150F
 148 #define E1000_DEV_ID_82580_SERDES               0x1510
 149 #define E1000_DEV_ID_82580_SGMII                0x1511
 150 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 151 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 152 #define E1000_DEV_ID_I350_COPPER                0x1521
 153 #define E1000_DEV_ID_I350_FIBER                 0x1522
 154 #define E1000_DEV_ID_I350_SERDES                0x1523
 155 #define E1000_DEV_ID_I350_SGMII                 0x1524
 156 #define E1000_DEV_ID_I350_DA4                   0x1546
 157 #define E1000_DEV_ID_I210_COPPER                0x1533
 158 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 159 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 160 #define E1000_DEV_ID_I210_FIBER                 0x1536
 161 #define E1000_DEV_ID_I210_SERDES                0x1537
 162 #define E1000_DEV_ID_I210_SGMII                 0x1538
 163 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 164 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 165 #define E1000_DEV_ID_I210_SGMII_FLASHLESS       0x15F6
 166 #define E1000_DEV_ID_I211_COPPER                0x1539
 167 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 168 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 169 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 170 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 171 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 172 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 173 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 174
 175 #define E1000_REVISION_0        0
 176 #define E1000_REVISION_1        1
 177 #define E1000_REVISION_2        2
 178 #define E1000_REVISION_3        3
 179 #define E1000_REVISION_4        4
 180
 181 #define E1000_FUNC_0            0
 182 #define E1000_FUNC_1            1
 183 #define E1000_FUNC_2            2
 184 #define E1000_FUNC_3            3
 185
 186 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 187 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 188 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 189 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 190
 191 enum e1000_mac_type {
 192         e1000_undefined = 0,
 193         e1000_82542,
 194         e1000_82543,
 195         e1000_82544,
 196         e1000_82540,
 197         e1000_82545,
 198         e1000_82545_rev_3,
 199         e1000_82546,
 200         e1000_82546_rev_3,
 201         e1000_82541,
 202         e1000_82541_rev_2,
 203         e1000_82547,
 204         e1000_82547_rev_2,
 205         e1000_82571,
 206         e1000_82572,
 207         e1000_82573,
 208         e1000_82574,
 209         e1000_82583,
 210         e1000_80003es2lan,
 211         e1000_ich8lan,
 212         e1000_ich9lan,
 213         e1000_ich10lan,
 214         e1000_pchlan,
 215         e1000_pch2lan,
 216         e1000_pch_lpt,
 217         e1000_pch_spt,
 218         e1000_pch_cnp,
 219         e1000_pch_adp,
 220         e1000_82575,
 221         e1000_82576,
 222         e1000_82580,
 223         e1000_i350,
 224         e1000_i354,
 225         e1000_i210,
 226         e1000_i211,
 227         e1000_vfadapt,
 228         e1000_vfadapt_i350,
 229         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 230 };
 231
 232 enum e1000_media_type {
 233         e1000_media_type_unknown = 0,
 234         e1000_media_type_copper = 1,
 235         e1000_media_type_fiber = 2,
 236         e1000_media_type_internal_serdes = 3,
 237         e1000_num_media_types
 238 };
 239
 240 enum e1000_nvm_type {
 241         e1000_nvm_unknown = 0,
 242         e1000_nvm_none,
 243         e1000_nvm_eeprom_spi,
 244         e1000_nvm_eeprom_microwire,
 245         e1000_nvm_flash_hw,
 246         e1000_nvm_invm,
 247         e1000_nvm_flash_sw
 248 };
 249
 250 enum e1000_nvm_override {
 251         e1000_nvm_override_none = 0,
 252         e1000_nvm_override_spi_small,
 253         e1000_nvm_override_spi_large,
 254         e1000_nvm_override_microwire_small,
 255         e1000_nvm_override_microwire_large
 256 };
 257
 258 enum e1000_phy_type {
 259         e1000_phy_unknown = 0,
 260         e1000_phy_none,
 261         e1000_phy_m88,
 262         e1000_phy_igp,
 263         e1000_phy_igp_2,
 264         e1000_phy_gg82563,
 265         e1000_phy_igp_3,
 266         e1000_phy_ife,
 267         e1000_phy_bm,
 268         e1000_phy_82578,
 269         e1000_phy_82577,
 270         e1000_phy_82579,
 271         e1000_phy_i217,
 272         e1000_phy_82580,
 273         e1000_phy_vf,
 274         e1000_phy_i210,
 275 };
 276
 277 enum e1000_bus_type {
 278         e1000_bus_type_unknown = 0,
 279         e1000_bus_type_pci,
 280         e1000_bus_type_pcix,
 281         e1000_bus_type_pci_express,
 282         e1000_bus_type_reserved
 283 };
 284
 285 enum e1000_bus_speed {
 286         e1000_bus_speed_unknown = 0,
 287         e1000_bus_speed_33,
 288         e1000_bus_speed_66,
 289         e1000_bus_speed_100,
 290         e1000_bus_speed_120,
 291         e1000_bus_speed_133,
 292         e1000_bus_speed_2500,
 293         e1000_bus_speed_5000,
 294         e1000_bus_speed_reserved
 295 };
 296
 297 enum e1000_bus_width {
 298         e1000_bus_width_unknown = 0,
 299         e1000_bus_width_pcie_x1,
 300         e1000_bus_width_pcie_x2,
 301         e1000_bus_width_pcie_x4 = 4,
 302         e1000_bus_width_pcie_x8 = 8,
 303         e1000_bus_width_32,
 304         e1000_bus_width_64,
 305         e1000_bus_width_reserved
 306 };
 307
 308 enum e1000_1000t_rx_status {
 309         e1000_1000t_rx_status_not_ok = 0,
 310         e1000_1000t_rx_status_ok,
 311         e1000_1000t_rx_status_undefined = 0xFF
 312 };
 313
 314 enum e1000_rev_polarity {
 315         e1000_rev_polarity_normal = 0,
 316         e1000_rev_polarity_reversed,
 317         e1000_rev_polarity_undefined = 0xFF
 318 };
 319
 320 enum e1000_fc_mode {
 321         e1000_fc_none = 0,
 322         e1000_fc_rx_pause,
 323         e1000_fc_tx_pause,
 324         e1000_fc_full,
 325         e1000_fc_default = 0xFF
 326 };
 327
 328 enum e1000_ffe_config {
 329         e1000_ffe_config_enabled = 0,
 330         e1000_ffe_config_active,
 331         e1000_ffe_config_blocked
 332 };
 333
 334 enum e1000_dsp_config {
 335         e1000_dsp_config_disabled = 0,
 336         e1000_dsp_config_enabled,
 337         e1000_dsp_config_activated,
 338         e1000_dsp_config_undefined = 0xFF
 339 };
 340
 341 enum e1000_ms_type {
 342         e1000_ms_hw_default = 0,
 343         e1000_ms_force_master,
 344         e1000_ms_force_slave,
 345         e1000_ms_auto
 346 };
 347
 348 enum e1000_smart_speed {
 349         e1000_smart_speed_default = 0,
 350         e1000_smart_speed_on,
 351         e1000_smart_speed_off
 352 };
 353
 354 enum e1000_serdes_link_state {
 355         e1000_serdes_link_down = 0,
 356         e1000_serdes_link_autoneg_progress,
 357         e1000_serdes_link_autoneg_complete,
 358         e1000_serdes_link_forced_up
 359 };
 360
 361 #define __le16 u16
 362 #define __le32 u32
 363 #define __le64 u64
 364 /* Receive Descriptor */
 365 struct e1000_rx_desc {
 366         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 367         __le16 length;      /* Length of data DMAed into data buffer */
 368         __le16 csum; /* Packet checksum */
 369         u8  status;  /* Descriptor status */
 370         u8  errors;  /* Descriptor Errors */
 371         __le16 special;
 372 };
 373
 374 /* Receive Descriptor - Extended */
 375 union e1000_rx_desc_extended {
 376         struct {
 377                 __le64 buffer_addr;
 378                 __le64 reserved;
 379         } read;
 380         struct {
 381                 struct {
 382                         __le32 mrq; /* Multiple Rx Queues */
 383                         union {
 384                                 __le32 rss; /* RSS Hash */
 385                                 struct {
 386                                         __le16 ip_id;  /* IP id */
 387                                         __le16 csum;   /* Packet Checksum */
 388                                 } csum_ip;
 389                         } hi_dword;
 390                 } lower;
 391                 struct {
 392                         __le32 status_error;  /* ext status/error */
 393                         __le16 length;
 394                         __le16 vlan; /* VLAN tag */
 395                 } upper;
 396         } wb;  /* writeback */
 397 };
 398
 399 #define MAX_PS_BUFFERS 4
 400
 401 /* Number of packet split data buffers (not including the header buffer) */
 402 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 403
 404 /* Receive Descriptor - Packet Split */
 405 union e1000_rx_desc_packet_split {
 406         struct {
 407                 /* one buffer for protocol header(s), three data buffers */
 408                 __le64 buffer_addr[MAX_PS_BUFFERS];
 409         } read;
 410         struct {
 411                 struct {
 412                         __le32 mrq;  /* Multiple Rx Queues */
 413                         union {
 414                                 __le32 rss; /* RSS Hash */
 415                                 struct {
 416                                         __le16 ip_id;    /* IP id */
 417                                         __le16 csum;     /* Packet Checksum */
 418                                 } csum_ip;
 419                         } hi_dword;
 420                 } lower;
 421                 struct {
 422                         __le32 status_error;  /* ext status/error */
 423                         __le16 length0;  /* length of buffer 0 */
 424                         __le16 vlan;  /* VLAN tag */
 425                 } middle;
 426                 struct {
 427                         __le16 header_status;
 428                         /* length of buffers 1-3 */
 429                         __le16 length[PS_PAGE_BUFFERS];
 430                 } upper;
 431                 __le64 reserved;
 432         } wb; /* writeback */
 433 };
 434
 435 /* Transmit Descriptor */
 436 struct e1000_tx_desc {
 437         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 438         union {
 439                 __le32 data;
 440                 struct {
 441                         __le16 length;  /* Data buffer length */
 442                         u8 cso;  /* Checksum offset */
 443                         u8 cmd;  /* Descriptor control */
 444                 } flags;
 445         } lower;
 446         union {
 447                 __le32 data;
 448                 struct {
 449                         u8 status; /* Descriptor status */
 450                         u8 css;  /* Checksum start */
 451                         __le16 special;
 452                 } fields;
 453         } upper;
 454 };
 455
 456 /* Offload Context Descriptor */
 457 struct e1000_context_desc {
 458         union {
 459                 __le32 ip_config;
 460                 struct {
 461                         u8 ipcss;  /* IP checksum start */
 462                         u8 ipcso;  /* IP checksum offset */
 463                         __le16 ipcse;  /* IP checksum end */
 464                 } ip_fields;
 465         } lower_setup;
 466         union {
 467                 __le32 tcp_config;
 468                 struct {
 469                         u8 tucss;  /* TCP checksum start */
 470                         u8 tucso;  /* TCP checksum offset */
 471                         __le16 tucse;  /* TCP checksum end */
 472                 } tcp_fields;
 473         } upper_setup;
 474         __le32 cmd_and_length;
 475         union {
 476                 __le32 data;
 477                 struct {
 478                         u8 status;  /* Descriptor status */
 479                         u8 hdr_len;  /* Header length */
 480                         __le16 mss;  /* Maximum segment size */
 481                 } fields;
 482         } tcp_seg_setup;
 483 };
 484
 485 /* Offload data descriptor */
 486 struct e1000_data_desc {
 487         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 488         union {
 489                 __le32 data;
 490                 struct {
 491                         __le16 length;  /* Data buffer length */
 492                         u8 typ_len_ext;
 493                         u8 cmd;
 494                 } flags;
 495         } lower;
 496         union {
 497                 __le32 data;
 498                 struct {
 499                         u8 status;  /* Descriptor status */
 500                         u8 popts;  /* Packet Options */
 501                         __le16 special;
 502                 } fields;
 503         } upper;
 504 };
 505
 506 /* Statistics counters collected by the MAC */
 507 struct e1000_hw_stats {
 508         u64 crcerrs;
 509         u64 algnerrc;
 510         u64 symerrs;
 511         u64 rxerrc;
 512         u64 mpc;
 513         u64 scc;
 514         u64 ecol;
 515         u64 mcc;
 516         u64 latecol;
 517         u64 colc;
 518         u64 dc;
 519         u64 tncrs;
 520         u64 sec;
 521         u64 cexterr;
 522         u64 rlec;
 523         u64 xonrxc;
 524         u64 xontxc;
 525         u64 xoffrxc;
 526         u64 xofftxc;
 527         u64 fcruc;
 528         u64 prc64;
 529         u64 prc127;
 530         u64 prc255;
 531         u64 prc511;
 532         u64 prc1023;
 533         u64 prc1522;
 534         u64 gprc;
 535         u64 bprc;
 536         u64 mprc;
 537         u64 gptc;
 538         u64 gorc;
 539         u64 gotc;
 540         u64 rnbc;
 541         u64 ruc;
 542         u64 rfc;
 543         u64 roc;
 544         u64 rjc;
 545         u64 mgprc;
 546         u64 mgpdc;
 547         u64 mgptc;
 548         u64 tor;
 549         u64 tot;
 550         u64 tpr;
 551         u64 tpt;
 552         u64 ptc64;
 553         u64 ptc127;
 554         u64 ptc255;
 555         u64 ptc511;
 556         u64 ptc1023;
 557         u64 ptc1522;
 558         u64 mptc;
 559         u64 bptc;
 560         u64 tsctc;
 561         u64 tsctfc;
 562         u64 iac;
 563         u64 icrxptc;
 564         u64 icrxatc;
 565         u64 ictxptc;
 566         u64 ictxatc;
 567         u64 ictxqec;
 568         u64 ictxqmtc;
 569         u64 icrxdmtc;
 570         u64 icrxoc;
 571         u64 cbtmpc;
 572         u64 htdpmc;
 573         u64 cbrdpc;
 574         u64 cbrmpc;
 575         u64 rpthc;
 576         u64 hgptc;
 577         u64 htcbdpc;
 578         u64 hgorc;
 579         u64 hgotc;
 580         u64 lenerrs;
 581         u64 scvpc;
 582         u64 hrmpc;
 583         u64 doosync;
 584         u64 o2bgptc;
 585         u64 o2bspc;
 586         u64 b2ospc;
 587         u64 b2ogprc;
 588 };
 589
 590 struct e1000_vf_stats {
 591         u64 base_gprc;
 592         u64 base_gptc;
 593         u64 base_gorc;
 594         u64 base_gotc;
 595         u64 base_mprc;
 596         u64 base_gotlbc;
 597         u64 base_gptlbc;
 598         u64 base_gorlbc;
 599         u64 base_gprlbc;
 600
 601         u32 last_gprc;
 602         u32 last_gptc;
 603         u32 last_gorc;
 604         u32 last_gotc;
 605         u32 last_mprc;
 606         u32 last_gotlbc;
 607         u32 last_gptlbc;
 608         u32 last_gorlbc;
 609         u32 last_gprlbc;
 610
 611         u64 gprc;
 612         u64 gptc;
 613         u64 gorc;
 614         u64 gotc;
 615         u64 mprc;
 616         u64 gotlbc;
 617         u64 gptlbc;
 618         u64 gorlbc;
 619         u64 gprlbc;
 620 };
 621
 622 struct e1000_phy_stats {
 623         u32 idle_errors;
 624         u32 receive_errors;
 625 };
 626
 627 struct e1000_host_mng_dhcp_cookie {
 628         u32 signature;
 629         u8  status;
 630         u8  reserved0;
 631         u16 vlan_id;
 632         u32 reserved1;
 633         u16 reserved2;
 634         u8  reserved3;
 635         u8  checksum;
 636 };
 637
 638 /* Host Interface "Rev 1" */
 639 struct e1000_host_command_header {
 640         u8 command_id;
 641         u8 command_length;
 642         u8 command_options;
 643         u8 checksum;
 644 };
 645
 646 #define E1000_HI_MAX_DATA_LENGTH        252
 647 struct e1000_host_command_info {
 648         struct e1000_host_command_header command_header;
 649         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 650 };
 651
 652 /* Host Interface "Rev 2" */
 653 struct e1000_host_mng_command_header {
 654         u8  command_id;
 655         u8  checksum;
 656         u16 reserved1;
 657         u16 reserved2;
 658         u16 command_length;
 659 };
 660
 661 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 662 struct e1000_host_mng_command_info {
 663         struct e1000_host_mng_command_header command_header;
 664         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 665 };
 666
 667 #include "e1000_mac.h"
 668 #include "e1000_phy.h"
 669 #include "e1000_nvm.h"
 670 #include "e1000_manage.h"
 671 #include "e1000_mbx.h"
 672
 673 /* Function pointers for the MAC. */
 674 struct e1000_mac_operations {
 675         s32  (*init_params)(struct e1000_hw *);
 676         s32  (*id_led_init)(struct e1000_hw *);
 677         s32  (*blink_led)(struct e1000_hw *);
 678         bool (*check_mng_mode)(struct e1000_hw *);
 679         s32  (*check_for_link)(struct e1000_hw *);
 680         s32  (*cleanup_led)(struct e1000_hw *);
 681         void (*clear_hw_cntrs)(struct e1000_hw *);
 682         void (*clear_vfta)(struct e1000_hw *);
 683         s32  (*get_bus_info)(struct e1000_hw *);
 684         void (*set_lan_id)(struct e1000_hw *);
 685         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 686         s32  (*led_on)(struct e1000_hw *);
 687         s32  (*led_off)(struct e1000_hw *);
 688         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 689         s32  (*reset_hw)(struct e1000_hw *);
 690         s32  (*init_hw)(struct e1000_hw *);
 691         void (*shutdown_serdes)(struct e1000_hw *);
 692         void (*power_up_serdes)(struct e1000_hw *);
 693         s32  (*setup_link)(struct e1000_hw *);
 694         s32  (*setup_physical_interface)(struct e1000_hw *);
 695         s32  (*setup_led)(struct e1000_hw *);
 696         void (*write_vfta)(struct e1000_hw *, u32, u32);
 697         void (*config_collision_dist)(struct e1000_hw *);
 698         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 699         s32  (*read_mac_addr)(struct e1000_hw *);
 700         s32  (*validate_mdi_setting)(struct e1000_hw *);
 701         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 702         void (*release_swfw_sync)(struct e1000_hw *, u16);
 703 };
 704
 705 /* When to use various PHY register access functions:
 706  *
 707  *                 Func   Caller
 708  *   Function      Does   Does    When to use
 709  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 710  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 711  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 712  *                                on different pages
 713  *   X_reg_page    A      L,P     for multiple accesses of different regs
 714  *                                on the same page
 715  *
 716  * Where X=[read|write], L=locking, P=sets page, A=register access
 717  *
 718  */
 719 struct e1000_phy_operations {
 720         s32  (*init_params)(struct e1000_hw *);
 721         s32  (*acquire)(struct e1000_hw *);
 722         s32  (*cfg_on_link_up)(struct e1000_hw *);
 723         s32  (*check_polarity)(struct e1000_hw *);
 724         s32  (*check_reset_block)(struct e1000_hw *);
 725         s32  (*commit)(struct e1000_hw *);
 726         s32  (*force_speed_duplex)(struct e1000_hw *);
 727         s32  (*get_cfg_done)(struct e1000_hw *hw);
 728         s32  (*get_cable_length)(struct e1000_hw *);
 729         s32  (*get_info)(struct e1000_hw *);
 730         s32  (*set_page)(struct e1000_hw *, u16);
 731         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 732         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 733         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 734         void (*release)(struct e1000_hw *);
 735         s32  (*reset)(struct e1000_hw *);
 736         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 737         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 738         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 739         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 740         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 741         void (*power_up)(struct e1000_hw *);
 742         void (*power_down)(struct e1000_hw *);
 743         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 744         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 745 };
 746
 747 /* Function pointers for the NVM. */
 748 struct e1000_nvm_operations {
 749         s32  (*init_params)(struct e1000_hw *);
 750         s32  (*acquire)(struct e1000_hw *);
 751         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 752         void (*release)(struct e1000_hw *);
 753         void (*reload)(struct e1000_hw *);
 754         s32  (*update)(struct e1000_hw *);
 755         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 756         s32  (*validate)(struct e1000_hw *);
 757         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 758 };
 759
 760 struct e1000_mac_info {
 761         struct e1000_mac_operations ops;
 762         u8 addr[ETH_ADDR_LEN];
 763         u8 perm_addr[ETH_ADDR_LEN];
 764
 765         enum e1000_mac_type type;
 766
 767         u32 collision_delta;
 768         u32 ledctl_default;
 769         u32 ledctl_mode1;
 770         u32 ledctl_mode2;
 771         u32 mc_filter_type;
 772         u32 tx_packet_delta;
 773         u32 txcw;
 774
 775         u16 current_ifs_val;
 776         u16 ifs_max_val;
 777         u16 ifs_min_val;
 778         u16 ifs_ratio;
 779         u16 ifs_step_size;
 780         u16 mta_reg_count;
 781         u16 uta_reg_count;
 782
 783         /* Maximum size of the MTA register table in all supported adapters */
 784 #define MAX_MTA_REG 128
 785         u32 mta_shadow[MAX_MTA_REG];
 786         u16 rar_entry_count;
 787
 788         u8  forced_speed_duplex;
 789
 790         bool adaptive_ifs;
 791         bool has_fwsm;
 792         bool arc_subsystem_valid;
 793         bool asf_firmware_present;
 794         bool autoneg;
 795         bool autoneg_failed;
 796         bool get_link_status;
 797         bool in_ifs_mode;
 798         bool report_tx_early;
 799         enum e1000_serdes_link_state serdes_link_state;
 800         bool serdes_has_link;
 801         bool tx_pkt_filtering;
 802 };
 803
 804 struct e1000_phy_info {
 805         struct e1000_phy_operations ops;
 806         enum e1000_phy_type type;
 807
 808         enum e1000_1000t_rx_status local_rx;
 809         enum e1000_1000t_rx_status remote_rx;
 810         enum e1000_ms_type ms_type;
 811         enum e1000_ms_type original_ms_type;
 812         enum e1000_rev_polarity cable_polarity;
 813         enum e1000_smart_speed smart_speed;
 814
 815         u32 addr;
 816         u32 id;
 817         u32 reset_delay_us; /* in usec */
 818         u32 revision;
 819
 820         enum e1000_media_type media_type;
 821
 822         u16 autoneg_advertised;
 823         u16 autoneg_mask;
 824         u16 cable_length;
 825         u16 max_cable_length;
 826         u16 min_cable_length;
 827
 828         u8 mdix;
 829
 830         bool disable_polarity_correction;
 831         bool is_mdix;
 832         bool polarity_correction;
 833         bool speed_downgraded;
 834         bool autoneg_wait_to_complete;
 835 };
 836
 837 struct e1000_nvm_info {
 838         struct e1000_nvm_operations ops;
 839         enum e1000_nvm_type type;
 840         enum e1000_nvm_override override;
 841
 842         u32 flash_bank_size;
 843         u32 flash_base_addr;
 844
 845         u16 word_size;
 846         u16 delay_usec;
 847         u16 address_bits;
 848         u16 opcode_bits;
 849         u16 page_size;
 850 };
 851
 852 struct e1000_bus_info {
 853         enum e1000_bus_type type;
 854         enum e1000_bus_speed speed;
 855         enum e1000_bus_width width;
 856
 857         u16 func;
 858         u16 pci_cmd_word;
 859 };
 860
 861 struct e1000_fc_info {
 862         u32 high_water;  /* Flow control high-water mark */
 863         u32 low_water;  /* Flow control low-water mark */
 864         u16 pause_time;  /* Flow control pause timer */
 865         u16 refresh_time;  /* Flow control refresh timer */
 866         bool send_xon;  /* Flow control send XON */
 867         bool strict_ieee;  /* Strict IEEE mode */
 868         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 869         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 870 };
 871
 872 struct e1000_mbx_operations {
 873         s32 (*init_params)(struct e1000_hw *hw);
 874         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 875         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 876         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 877         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 878         s32 (*check_for_msg)(struct e1000_hw *, u16);
 879         s32 (*check_for_ack)(struct e1000_hw *, u16);
 880         s32 (*check_for_rst)(struct e1000_hw *, u16);
 881 };
 882
 883 struct e1000_mbx_stats {
 884         u32 msgs_tx;
 885         u32 msgs_rx;
 886
 887         u32 acks;
 888         u32 reqs;
 889         u32 rsts;
 890 };
 891
 892 struct e1000_mbx_info {
 893         struct e1000_mbx_operations ops;
 894         struct e1000_mbx_stats stats;
 895         u32 timeout;
 896         u32 usec_delay;
 897         u16 size;
 898 };
 899
 900 struct e1000_dev_spec_82541 {
 901         enum e1000_dsp_config dsp_config;
 902         enum e1000_ffe_config ffe_config;
 903         u16 spd_default;
 904         bool phy_init_script;
 905 };
 906
 907 struct e1000_dev_spec_82542 {
 908         bool dma_fairness;
 909 };
 910
 911 struct e1000_dev_spec_82543 {
 912         u32  tbi_compatibility;
 913         bool dma_fairness;
 914         bool init_phy_disabled;
 915 };
 916
 917 struct e1000_dev_spec_82571 {
 918         bool laa_is_present;
 919         u32 smb_counter;
 920         E1000_MUTEX swflag_mutex;
 921 };
 922
 923 struct e1000_dev_spec_80003es2lan {
 924         bool  mdic_wa_enable;
 925 };
 926
 927 struct e1000_shadow_ram {
 928         u16  value;
 929         bool modified;
 930 };
 931
 932 #define E1000_SHADOW_RAM_WORDS          2048
 933
 934 /* I218 PHY Ultra Low Power (ULP) states */
 935 enum e1000_ulp_state {
 936         e1000_ulp_state_unknown,
 937         e1000_ulp_state_off,
 938         e1000_ulp_state_on,
 939 };
 940
 941 struct e1000_dev_spec_ich8lan {
 942         bool kmrn_lock_loss_workaround_enabled;
 943         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 944         E1000_MUTEX nvm_mutex;
 945         E1000_MUTEX swflag_mutex;
 946         bool nvm_k1_enabled;
 947         bool disable_k1_off;
 948         bool eee_disable;
 949         u16 eee_lp_ability;
 950         enum e1000_ulp_state ulp_state;
 951         bool ulp_capability_disabled;
 952         bool during_suspend_flow;
 953         bool during_dpg_exit;
 954         u16 lat_enc;
 955         u16 max_ltr_enc;
 956         bool smbus_disable;
 957 };
 958
 959 struct e1000_dev_spec_82575 {
 960         bool sgmii_active;
 961         bool global_device_reset;
 962         bool eee_disable;
 963         bool module_plugged;
 964         bool clear_semaphore_once;
 965         u32 mtu;
 966         struct sfp_e1000_flags eth_flags;
 967         u8 media_port;
 968         bool media_changed;
 969 };
 970
 971 struct e1000_dev_spec_vf {
 972         u32 vf_number;
 973         u32 v2p_mailbox;
 974 };
 975
 976 struct e1000_hw {
 977         void *back;
 978
 979         u8 *hw_addr;
 980         u8 *flash_address;
 981         unsigned long io_base;
 982
 983         struct e1000_mac_info  mac;
 984         struct e1000_fc_info   fc;
 985         struct e1000_phy_info  phy;
 986         struct e1000_nvm_info  nvm;
 987         struct e1000_bus_info  bus;
 988         struct e1000_mbx_info mbx;
 989         struct e1000_host_mng_dhcp_cookie mng_cookie;
 990
 991         union {
 992                 struct e1000_dev_spec_82541 _82541;
 993                 struct e1000_dev_spec_82542 _82542;
 994                 struct e1000_dev_spec_82543 _82543;
 995                 struct e1000_dev_spec_82571 _82571;
 996                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 997                 struct e1000_dev_spec_ich8lan ich8lan;
 998                 struct e1000_dev_spec_82575 _82575;
 999                 struct e1000_dev_spec_vf vf;
1000         } dev_spec;
1001
1002         u16 device_id;
1003         u16 subsystem_vendor_id;
1004         u16 subsystem_device_id;
1005         u16 vendor_id;
1006
1007         u8  revision_id;
1008 };
1009
1010 #include "e1000_82541.h"
1011 #include "e1000_82543.h"
1012 #include "e1000_82571.h"
1013 #include "e1000_80003es2lan.h"
1014 #include "e1000_ich8lan.h"
1015 #include "e1000_82575.h"
1016 #include "e1000_i210.h"
1017 #include "e1000_base.h"
1018
1019 /* These functions must be implemented by drivers */
1020 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1021 void e1000_pci_set_mwi(struct e1000_hw *hw);
1022 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1023 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1024 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1025 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1026
1027 #endif