drivers/net/e1000/base/e1000_hw.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 #ifndef _E1000_HW_H_
   6 #define _E1000_HW_H_
   7
   8 #include "e1000_osdep.h"
   9 #include "e1000_regs.h"
  10 #include "e1000_defines.h"
  11
  12 struct e1000_hw;
  13
  14 #define E1000_DEV_ID_82542                      0x1000
  15 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  16 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  17 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  18 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  19 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  20 #define E1000_DEV_ID_82544GC_LOM                0x100D
  21 #define E1000_DEV_ID_82540EM                    0x100E
  22 #define E1000_DEV_ID_82540EM_LOM                0x1015
  23 #define E1000_DEV_ID_82540EP_LOM                0x1016
  24 #define E1000_DEV_ID_82540EP                    0x1017
  25 #define E1000_DEV_ID_82540EP_LP                 0x101E
  26 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  27 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  28 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  29 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  30 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  31 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  32 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  33 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  34 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  35 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  36 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  37 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  38 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  39 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  40 #define E1000_DEV_ID_82541EI                    0x1013
  41 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  42 #define E1000_DEV_ID_82541ER_LOM                0x1014
  43 #define E1000_DEV_ID_82541ER                    0x1078
  44 #define E1000_DEV_ID_82541GI                    0x1076
  45 #define E1000_DEV_ID_82541GI_LF                 0x107C
  46 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  47 #define E1000_DEV_ID_82547EI                    0x1019
  48 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  49 #define E1000_DEV_ID_82547GI                    0x1075
  50 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  51 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  52 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  53 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  54 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  55 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  56 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  57 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  58 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  59 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  60 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  61 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  62 #define E1000_DEV_ID_82572EI                    0x10B9
  63 #define E1000_DEV_ID_82573E                     0x108B
  64 #define E1000_DEV_ID_82573E_IAMT                0x108C
  65 #define E1000_DEV_ID_82573L                     0x109A
  66 #define E1000_DEV_ID_82574L                     0x10D3
  67 #define E1000_DEV_ID_82574LA                    0x10F6
  68 #define E1000_DEV_ID_82583V                     0x150C
  69 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
  70 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
  71 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
  72 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
  73 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
  74 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
  75 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
  76 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
  77 #define E1000_DEV_ID_ICH8_IFE                   0x104C
  78 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
  79 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
  80 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
  81 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
  82 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
  83 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
  84 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
  85 #define E1000_DEV_ID_ICH9_BM                    0x10E5
  86 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
  87 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
  88 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
  89 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
  90 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
  91 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
  92 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
  93 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
  94 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
  95 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
  96 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
  97 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
  98 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
  99 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 100 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 101 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 102 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 103 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 104 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 105 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 106 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 107 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 108 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 109 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 110 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F /* Sunrise Point PCH */
 111 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570 /* Sunrise Point PCH */
 112 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7 /* Sunrise Point-H PCH */
 113 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8 /* Sunrise Point-H PCH */
 114 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9 /* LEWISBURG PCH */
 115 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
 116 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
 117 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
 118 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
 119 #define E1000_DEV_ID_PCH_CNP_I219_LM6           0x15BD
 120 #define E1000_DEV_ID_PCH_CNP_I219_V6            0x15BE
 121 #define E1000_DEV_ID_PCH_CNP_I219_LM7           0x15BB
 122 #define E1000_DEV_ID_PCH_CNP_I219_V7            0x15BC
 123 #define E1000_DEV_ID_PCH_ICP_I219_LM8           0x15DF
 124 #define E1000_DEV_ID_PCH_ICP_I219_V8            0x15E0
 125 #define E1000_DEV_ID_PCH_ICP_I219_LM9           0x15E1
 126 #define E1000_DEV_ID_PCH_ICP_I219_V9            0x15E2
 127 #define E1000_DEV_ID_82576                      0x10C9
 128 #define E1000_DEV_ID_82576_FIBER                0x10E6
 129 #define E1000_DEV_ID_82576_SERDES               0x10E7
 130 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 131 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 132 #define E1000_DEV_ID_82576_NS                   0x150A
 133 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 134 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 135 #define E1000_DEV_ID_82576_VF                   0x10CA
 136 #define E1000_DEV_ID_82576_VF_HV                0x152D
 137 #define E1000_DEV_ID_I350_VF                    0x1520
 138 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 139 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 140 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 141 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 142 #define E1000_DEV_ID_82580_COPPER               0x150E
 143 #define E1000_DEV_ID_82580_FIBER                0x150F
 144 #define E1000_DEV_ID_82580_SERDES               0x1510
 145 #define E1000_DEV_ID_82580_SGMII                0x1511
 146 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 147 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 148 #define E1000_DEV_ID_I350_COPPER                0x1521
 149 #define E1000_DEV_ID_I350_FIBER                 0x1522
 150 #define E1000_DEV_ID_I350_SERDES                0x1523
 151 #define E1000_DEV_ID_I350_SGMII                 0x1524
 152 #define E1000_DEV_ID_I350_DA4                   0x1546
 153 #define E1000_DEV_ID_I210_COPPER                0x1533
 154 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 155 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 156 #define E1000_DEV_ID_I210_FIBER                 0x1536
 157 #define E1000_DEV_ID_I210_SERDES                0x1537
 158 #define E1000_DEV_ID_I210_SGMII                 0x1538
 159 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 160 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 161 #define E1000_DEV_ID_I210_SGMII_FLASHLESS       0x15F6
 162 #define E1000_DEV_ID_I211_COPPER                0x1539
 163 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 164 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 165 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 166 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 167 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 168 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 169 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 170
 171 #define E1000_REVISION_0        0
 172 #define E1000_REVISION_1        1
 173 #define E1000_REVISION_2        2
 174 #define E1000_REVISION_3        3
 175 #define E1000_REVISION_4        4
 176
 177 #define E1000_FUNC_0            0
 178 #define E1000_FUNC_1            1
 179 #define E1000_FUNC_2            2
 180 #define E1000_FUNC_3            3
 181
 182 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 183 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 184 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 185 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 186
 187 enum e1000_mac_type {
 188         e1000_undefined = 0,
 189         e1000_82542,
 190         e1000_82543,
 191         e1000_82544,
 192         e1000_82540,
 193         e1000_82545,
 194         e1000_82545_rev_3,
 195         e1000_82546,
 196         e1000_82546_rev_3,
 197         e1000_82541,
 198         e1000_82541_rev_2,
 199         e1000_82547,
 200         e1000_82547_rev_2,
 201         e1000_82571,
 202         e1000_82572,
 203         e1000_82573,
 204         e1000_82574,
 205         e1000_82583,
 206         e1000_80003es2lan,
 207         e1000_ich8lan,
 208         e1000_ich9lan,
 209         e1000_ich10lan,
 210         e1000_pchlan,
 211         e1000_pch2lan,
 212         e1000_pch_lpt,
 213         e1000_pch_spt,
 214         e1000_pch_cnp,
 215         e1000_82575,
 216         e1000_82576,
 217         e1000_82580,
 218         e1000_i350,
 219         e1000_i354,
 220         e1000_i210,
 221         e1000_i211,
 222         e1000_vfadapt,
 223         e1000_vfadapt_i350,
 224         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 225 };
 226
 227 enum e1000_media_type {
 228         e1000_media_type_unknown = 0,
 229         e1000_media_type_copper = 1,
 230         e1000_media_type_fiber = 2,
 231         e1000_media_type_internal_serdes = 3,
 232         e1000_num_media_types
 233 };
 234
 235 enum e1000_nvm_type {
 236         e1000_nvm_unknown = 0,
 237         e1000_nvm_none,
 238         e1000_nvm_eeprom_spi,
 239         e1000_nvm_eeprom_microwire,
 240         e1000_nvm_flash_hw,
 241         e1000_nvm_invm,
 242         e1000_nvm_flash_sw
 243 };
 244
 245 enum e1000_nvm_override {
 246         e1000_nvm_override_none = 0,
 247         e1000_nvm_override_spi_small,
 248         e1000_nvm_override_spi_large,
 249         e1000_nvm_override_microwire_small,
 250         e1000_nvm_override_microwire_large
 251 };
 252
 253 enum e1000_phy_type {
 254         e1000_phy_unknown = 0,
 255         e1000_phy_none,
 256         e1000_phy_m88,
 257         e1000_phy_igp,
 258         e1000_phy_igp_2,
 259         e1000_phy_gg82563,
 260         e1000_phy_igp_3,
 261         e1000_phy_ife,
 262         e1000_phy_bm,
 263         e1000_phy_82578,
 264         e1000_phy_82577,
 265         e1000_phy_82579,
 266         e1000_phy_i217,
 267         e1000_phy_82580,
 268         e1000_phy_vf,
 269         e1000_phy_i210,
 270 };
 271
 272 enum e1000_bus_type {
 273         e1000_bus_type_unknown = 0,
 274         e1000_bus_type_pci,
 275         e1000_bus_type_pcix,
 276         e1000_bus_type_pci_express,
 277         e1000_bus_type_reserved
 278 };
 279
 280 enum e1000_bus_speed {
 281         e1000_bus_speed_unknown = 0,
 282         e1000_bus_speed_33,
 283         e1000_bus_speed_66,
 284         e1000_bus_speed_100,
 285         e1000_bus_speed_120,
 286         e1000_bus_speed_133,
 287         e1000_bus_speed_2500,
 288         e1000_bus_speed_5000,
 289         e1000_bus_speed_reserved
 290 };
 291
 292 enum e1000_bus_width {
 293         e1000_bus_width_unknown = 0,
 294         e1000_bus_width_pcie_x1,
 295         e1000_bus_width_pcie_x2,
 296         e1000_bus_width_pcie_x4 = 4,
 297         e1000_bus_width_pcie_x8 = 8,
 298         e1000_bus_width_32,
 299         e1000_bus_width_64,
 300         e1000_bus_width_reserved
 301 };
 302
 303 enum e1000_1000t_rx_status {
 304         e1000_1000t_rx_status_not_ok = 0,
 305         e1000_1000t_rx_status_ok,
 306         e1000_1000t_rx_status_undefined = 0xFF
 307 };
 308
 309 enum e1000_rev_polarity {
 310         e1000_rev_polarity_normal = 0,
 311         e1000_rev_polarity_reversed,
 312         e1000_rev_polarity_undefined = 0xFF
 313 };
 314
 315 enum e1000_fc_mode {
 316         e1000_fc_none = 0,
 317         e1000_fc_rx_pause,
 318         e1000_fc_tx_pause,
 319         e1000_fc_full,
 320         e1000_fc_default = 0xFF
 321 };
 322
 323 enum e1000_ffe_config {
 324         e1000_ffe_config_enabled = 0,
 325         e1000_ffe_config_active,
 326         e1000_ffe_config_blocked
 327 };
 328
 329 enum e1000_dsp_config {
 330         e1000_dsp_config_disabled = 0,
 331         e1000_dsp_config_enabled,
 332         e1000_dsp_config_activated,
 333         e1000_dsp_config_undefined = 0xFF
 334 };
 335
 336 enum e1000_ms_type {
 337         e1000_ms_hw_default = 0,
 338         e1000_ms_force_master,
 339         e1000_ms_force_slave,
 340         e1000_ms_auto
 341 };
 342
 343 enum e1000_smart_speed {
 344         e1000_smart_speed_default = 0,
 345         e1000_smart_speed_on,
 346         e1000_smart_speed_off
 347 };
 348
 349 enum e1000_serdes_link_state {
 350         e1000_serdes_link_down = 0,
 351         e1000_serdes_link_autoneg_progress,
 352         e1000_serdes_link_autoneg_complete,
 353         e1000_serdes_link_forced_up
 354 };
 355
 356 #define __le16 u16
 357 #define __le32 u32
 358 #define __le64 u64
 359 /* Receive Descriptor */
 360 struct e1000_rx_desc {
 361         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 362         __le16 length;      /* Length of data DMAed into data buffer */
 363         __le16 csum; /* Packet checksum */
 364         u8  status;  /* Descriptor status */
 365         u8  errors;  /* Descriptor Errors */
 366         __le16 special;
 367 };
 368
 369 /* Receive Descriptor - Extended */
 370 union e1000_rx_desc_extended {
 371         struct {
 372                 __le64 buffer_addr;
 373                 __le64 reserved;
 374         } read;
 375         struct {
 376                 struct {
 377                         __le32 mrq; /* Multiple Rx Queues */
 378                         union {
 379                                 __le32 rss; /* RSS Hash */
 380                                 struct {
 381                                         __le16 ip_id;  /* IP id */
 382                                         __le16 csum;   /* Packet Checksum */
 383                                 } csum_ip;
 384                         } hi_dword;
 385                 } lower;
 386                 struct {
 387                         __le32 status_error;  /* ext status/error */
 388                         __le16 length;
 389                         __le16 vlan; /* VLAN tag */
 390                 } upper;
 391         } wb;  /* writeback */
 392 };
 393
 394 #define MAX_PS_BUFFERS 4
 395
 396 /* Number of packet split data buffers (not including the header buffer) */
 397 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 398
 399 /* Receive Descriptor - Packet Split */
 400 union e1000_rx_desc_packet_split {
 401         struct {
 402                 /* one buffer for protocol header(s), three data buffers */
 403                 __le64 buffer_addr[MAX_PS_BUFFERS];
 404         } read;
 405         struct {
 406                 struct {
 407                         __le32 mrq;  /* Multiple Rx Queues */
 408                         union {
 409                                 __le32 rss; /* RSS Hash */
 410                                 struct {
 411                                         __le16 ip_id;    /* IP id */
 412                                         __le16 csum;     /* Packet Checksum */
 413                                 } csum_ip;
 414                         } hi_dword;
 415                 } lower;
 416                 struct {
 417                         __le32 status_error;  /* ext status/error */
 418                         __le16 length0;  /* length of buffer 0 */
 419                         __le16 vlan;  /* VLAN tag */
 420                 } middle;
 421                 struct {
 422                         __le16 header_status;
 423                         /* length of buffers 1-3 */
 424                         __le16 length[PS_PAGE_BUFFERS];
 425                 } upper;
 426                 __le64 reserved;
 427         } wb; /* writeback */
 428 };
 429
 430 /* Transmit Descriptor */
 431 struct e1000_tx_desc {
 432         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 433         union {
 434                 __le32 data;
 435                 struct {
 436                         __le16 length;  /* Data buffer length */
 437                         u8 cso;  /* Checksum offset */
 438                         u8 cmd;  /* Descriptor control */
 439                 } flags;
 440         } lower;
 441         union {
 442                 __le32 data;
 443                 struct {
 444                         u8 status; /* Descriptor status */
 445                         u8 css;  /* Checksum start */
 446                         __le16 special;
 447                 } fields;
 448         } upper;
 449 };
 450
 451 /* Offload Context Descriptor */
 452 struct e1000_context_desc {
 453         union {
 454                 __le32 ip_config;
 455                 struct {
 456                         u8 ipcss;  /* IP checksum start */
 457                         u8 ipcso;  /* IP checksum offset */
 458                         __le16 ipcse;  /* IP checksum end */
 459                 } ip_fields;
 460         } lower_setup;
 461         union {
 462                 __le32 tcp_config;
 463                 struct {
 464                         u8 tucss;  /* TCP checksum start */
 465                         u8 tucso;  /* TCP checksum offset */
 466                         __le16 tucse;  /* TCP checksum end */
 467                 } tcp_fields;
 468         } upper_setup;
 469         __le32 cmd_and_length;
 470         union {
 471                 __le32 data;
 472                 struct {
 473                         u8 status;  /* Descriptor status */
 474                         u8 hdr_len;  /* Header length */
 475                         __le16 mss;  /* Maximum segment size */
 476                 } fields;
 477         } tcp_seg_setup;
 478 };
 479
 480 /* Offload data descriptor */
 481 struct e1000_data_desc {
 482         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 483         union {
 484                 __le32 data;
 485                 struct {
 486                         __le16 length;  /* Data buffer length */
 487                         u8 typ_len_ext;
 488                         u8 cmd;
 489                 } flags;
 490         } lower;
 491         union {
 492                 __le32 data;
 493                 struct {
 494                         u8 status;  /* Descriptor status */
 495                         u8 popts;  /* Packet Options */
 496                         __le16 special;
 497                 } fields;
 498         } upper;
 499 };
 500
 501 /* Statistics counters collected by the MAC */
 502 struct e1000_hw_stats {
 503         u64 crcerrs;
 504         u64 algnerrc;
 505         u64 symerrs;
 506         u64 rxerrc;
 507         u64 mpc;
 508         u64 scc;
 509         u64 ecol;
 510         u64 mcc;
 511         u64 latecol;
 512         u64 colc;
 513         u64 dc;
 514         u64 tncrs;
 515         u64 sec;
 516         u64 cexterr;
 517         u64 rlec;
 518         u64 xonrxc;
 519         u64 xontxc;
 520         u64 xoffrxc;
 521         u64 xofftxc;
 522         u64 fcruc;
 523         u64 prc64;
 524         u64 prc127;
 525         u64 prc255;
 526         u64 prc511;
 527         u64 prc1023;
 528         u64 prc1522;
 529         u64 gprc;
 530         u64 bprc;
 531         u64 mprc;
 532         u64 gptc;
 533         u64 gorc;
 534         u64 gotc;
 535         u64 rnbc;
 536         u64 ruc;
 537         u64 rfc;
 538         u64 roc;
 539         u64 rjc;
 540         u64 mgprc;
 541         u64 mgpdc;
 542         u64 mgptc;
 543         u64 tor;
 544         u64 tot;
 545         u64 tpr;
 546         u64 tpt;
 547         u64 ptc64;
 548         u64 ptc127;
 549         u64 ptc255;
 550         u64 ptc511;
 551         u64 ptc1023;
 552         u64 ptc1522;
 553         u64 mptc;
 554         u64 bptc;
 555         u64 tsctc;
 556         u64 tsctfc;
 557         u64 iac;
 558         u64 icrxptc;
 559         u64 icrxatc;
 560         u64 ictxptc;
 561         u64 ictxatc;
 562         u64 ictxqec;
 563         u64 ictxqmtc;
 564         u64 icrxdmtc;
 565         u64 icrxoc;
 566         u64 cbtmpc;
 567         u64 htdpmc;
 568         u64 cbrdpc;
 569         u64 cbrmpc;
 570         u64 rpthc;
 571         u64 hgptc;
 572         u64 htcbdpc;
 573         u64 hgorc;
 574         u64 hgotc;
 575         u64 lenerrs;
 576         u64 scvpc;
 577         u64 hrmpc;
 578         u64 doosync;
 579         u64 o2bgptc;
 580         u64 o2bspc;
 581         u64 b2ospc;
 582         u64 b2ogprc;
 583 };
 584
 585 struct e1000_vf_stats {
 586         u64 base_gprc;
 587         u64 base_gptc;
 588         u64 base_gorc;
 589         u64 base_gotc;
 590         u64 base_mprc;
 591         u64 base_gotlbc;
 592         u64 base_gptlbc;
 593         u64 base_gorlbc;
 594         u64 base_gprlbc;
 595
 596         u32 last_gprc;
 597         u32 last_gptc;
 598         u32 last_gorc;
 599         u32 last_gotc;
 600         u32 last_mprc;
 601         u32 last_gotlbc;
 602         u32 last_gptlbc;
 603         u32 last_gorlbc;
 604         u32 last_gprlbc;
 605
 606         u64 gprc;
 607         u64 gptc;
 608         u64 gorc;
 609         u64 gotc;
 610         u64 mprc;
 611         u64 gotlbc;
 612         u64 gptlbc;
 613         u64 gorlbc;
 614         u64 gprlbc;
 615 };
 616
 617 struct e1000_phy_stats {
 618         u32 idle_errors;
 619         u32 receive_errors;
 620 };
 621
 622 struct e1000_host_mng_dhcp_cookie {
 623         u32 signature;
 624         u8  status;
 625         u8  reserved0;
 626         u16 vlan_id;
 627         u32 reserved1;
 628         u16 reserved2;
 629         u8  reserved3;
 630         u8  checksum;
 631 };
 632
 633 /* Host Interface "Rev 1" */
 634 struct e1000_host_command_header {
 635         u8 command_id;
 636         u8 command_length;
 637         u8 command_options;
 638         u8 checksum;
 639 };
 640
 641 #define E1000_HI_MAX_DATA_LENGTH        252
 642 struct e1000_host_command_info {
 643         struct e1000_host_command_header command_header;
 644         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 645 };
 646
 647 /* Host Interface "Rev 2" */
 648 struct e1000_host_mng_command_header {
 649         u8  command_id;
 650         u8  checksum;
 651         u16 reserved1;
 652         u16 reserved2;
 653         u16 command_length;
 654 };
 655
 656 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 657 struct e1000_host_mng_command_info {
 658         struct e1000_host_mng_command_header command_header;
 659         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 660 };
 661
 662 #include "e1000_mac.h"
 663 #include "e1000_phy.h"
 664 #include "e1000_nvm.h"
 665 #include "e1000_manage.h"
 666 #include "e1000_mbx.h"
 667
 668 /* Function pointers for the MAC. */
 669 struct e1000_mac_operations {
 670         s32  (*init_params)(struct e1000_hw *);
 671         s32  (*id_led_init)(struct e1000_hw *);
 672         s32  (*blink_led)(struct e1000_hw *);
 673         bool (*check_mng_mode)(struct e1000_hw *);
 674         s32  (*check_for_link)(struct e1000_hw *);
 675         s32  (*cleanup_led)(struct e1000_hw *);
 676         void (*clear_hw_cntrs)(struct e1000_hw *);
 677         void (*clear_vfta)(struct e1000_hw *);
 678         s32  (*get_bus_info)(struct e1000_hw *);
 679         void (*set_lan_id)(struct e1000_hw *);
 680         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 681         s32  (*led_on)(struct e1000_hw *);
 682         s32  (*led_off)(struct e1000_hw *);
 683         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 684         s32  (*reset_hw)(struct e1000_hw *);
 685         s32  (*init_hw)(struct e1000_hw *);
 686         void (*shutdown_serdes)(struct e1000_hw *);
 687         void (*power_up_serdes)(struct e1000_hw *);
 688         s32  (*setup_link)(struct e1000_hw *);
 689         s32  (*setup_physical_interface)(struct e1000_hw *);
 690         s32  (*setup_led)(struct e1000_hw *);
 691         void (*write_vfta)(struct e1000_hw *, u32, u32);
 692         void (*config_collision_dist)(struct e1000_hw *);
 693         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 694         s32  (*read_mac_addr)(struct e1000_hw *);
 695         s32  (*validate_mdi_setting)(struct e1000_hw *);
 696         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 697         void (*release_swfw_sync)(struct e1000_hw *, u16);
 698 };
 699
 700 /* When to use various PHY register access functions:
 701  *
 702  *                 Func   Caller
 703  *   Function      Does   Does    When to use
 704  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 705  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 706  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 707  *                                on different pages
 708  *   X_reg_page    A      L,P     for multiple accesses of different regs
 709  *                                on the same page
 710  *
 711  * Where X=[read|write], L=locking, P=sets page, A=register access
 712  *
 713  */
 714 struct e1000_phy_operations {
 715         s32  (*init_params)(struct e1000_hw *);
 716         s32  (*acquire)(struct e1000_hw *);
 717         s32  (*cfg_on_link_up)(struct e1000_hw *);
 718         s32  (*check_polarity)(struct e1000_hw *);
 719         s32  (*check_reset_block)(struct e1000_hw *);
 720         s32  (*commit)(struct e1000_hw *);
 721         s32  (*force_speed_duplex)(struct e1000_hw *);
 722         s32  (*get_cfg_done)(struct e1000_hw *hw);
 723         s32  (*get_cable_length)(struct e1000_hw *);
 724         s32  (*get_info)(struct e1000_hw *);
 725         s32  (*set_page)(struct e1000_hw *, u16);
 726         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 727         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 728         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 729         void (*release)(struct e1000_hw *);
 730         s32  (*reset)(struct e1000_hw *);
 731         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 732         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 733         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 734         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 735         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 736         void (*power_up)(struct e1000_hw *);
 737         void (*power_down)(struct e1000_hw *);
 738         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 739         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 740 };
 741
 742 /* Function pointers for the NVM. */
 743 struct e1000_nvm_operations {
 744         s32  (*init_params)(struct e1000_hw *);
 745         s32  (*acquire)(struct e1000_hw *);
 746         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 747         void (*release)(struct e1000_hw *);
 748         void (*reload)(struct e1000_hw *);
 749         s32  (*update)(struct e1000_hw *);
 750         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 751         s32  (*validate)(struct e1000_hw *);
 752         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 753 };
 754
 755 struct e1000_mac_info {
 756         struct e1000_mac_operations ops;
 757         u8 addr[ETH_ADDR_LEN];
 758         u8 perm_addr[ETH_ADDR_LEN];
 759
 760         enum e1000_mac_type type;
 761
 762         u32 collision_delta;
 763         u32 ledctl_default;
 764         u32 ledctl_mode1;
 765         u32 ledctl_mode2;
 766         u32 mc_filter_type;
 767         u32 tx_packet_delta;
 768         u32 txcw;
 769
 770         u16 current_ifs_val;
 771         u16 ifs_max_val;
 772         u16 ifs_min_val;
 773         u16 ifs_ratio;
 774         u16 ifs_step_size;
 775         u16 mta_reg_count;
 776         u16 uta_reg_count;
 777
 778         /* Maximum size of the MTA register table in all supported adapters */
 779 #define MAX_MTA_REG 128
 780         u32 mta_shadow[MAX_MTA_REG];
 781         u16 rar_entry_count;
 782
 783         u8  forced_speed_duplex;
 784
 785         bool adaptive_ifs;
 786         bool has_fwsm;
 787         bool arc_subsystem_valid;
 788         bool asf_firmware_present;
 789         bool autoneg;
 790         bool autoneg_failed;
 791         bool get_link_status;
 792         bool in_ifs_mode;
 793         bool report_tx_early;
 794         enum e1000_serdes_link_state serdes_link_state;
 795         bool serdes_has_link;
 796         bool tx_pkt_filtering;
 797 };
 798
 799 struct e1000_phy_info {
 800         struct e1000_phy_operations ops;
 801         enum e1000_phy_type type;
 802
 803         enum e1000_1000t_rx_status local_rx;
 804         enum e1000_1000t_rx_status remote_rx;
 805         enum e1000_ms_type ms_type;
 806         enum e1000_ms_type original_ms_type;
 807         enum e1000_rev_polarity cable_polarity;
 808         enum e1000_smart_speed smart_speed;
 809
 810         u32 addr;
 811         u32 id;
 812         u32 reset_delay_us; /* in usec */
 813         u32 revision;
 814
 815         enum e1000_media_type media_type;
 816
 817         u16 autoneg_advertised;
 818         u16 autoneg_mask;
 819         u16 cable_length;
 820         u16 max_cable_length;
 821         u16 min_cable_length;
 822
 823         u8 mdix;
 824
 825         bool disable_polarity_correction;
 826         bool is_mdix;
 827         bool polarity_correction;
 828         bool speed_downgraded;
 829         bool autoneg_wait_to_complete;
 830 };
 831
 832 struct e1000_nvm_info {
 833         struct e1000_nvm_operations ops;
 834         enum e1000_nvm_type type;
 835         enum e1000_nvm_override override;
 836
 837         u32 flash_bank_size;
 838         u32 flash_base_addr;
 839
 840         u16 word_size;
 841         u16 delay_usec;
 842         u16 address_bits;
 843         u16 opcode_bits;
 844         u16 page_size;
 845 };
 846
 847 struct e1000_bus_info {
 848         enum e1000_bus_type type;
 849         enum e1000_bus_speed speed;
 850         enum e1000_bus_width width;
 851
 852         u16 func;
 853         u16 pci_cmd_word;
 854 };
 855
 856 struct e1000_fc_info {
 857         u32 high_water;  /* Flow control high-water mark */
 858         u32 low_water;  /* Flow control low-water mark */
 859         u16 pause_time;  /* Flow control pause timer */
 860         u16 refresh_time;  /* Flow control refresh timer */
 861         bool send_xon;  /* Flow control send XON */
 862         bool strict_ieee;  /* Strict IEEE mode */
 863         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 864         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 865 };
 866
 867 struct e1000_mbx_operations {
 868         s32 (*init_params)(struct e1000_hw *hw);
 869         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 870         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 871         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 872         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 873         s32 (*check_for_msg)(struct e1000_hw *, u16);
 874         s32 (*check_for_ack)(struct e1000_hw *, u16);
 875         s32 (*check_for_rst)(struct e1000_hw *, u16);
 876 };
 877
 878 struct e1000_mbx_stats {
 879         u32 msgs_tx;
 880         u32 msgs_rx;
 881
 882         u32 acks;
 883         u32 reqs;
 884         u32 rsts;
 885 };
 886
 887 struct e1000_mbx_info {
 888         struct e1000_mbx_operations ops;
 889         struct e1000_mbx_stats stats;
 890         u32 timeout;
 891         u32 usec_delay;
 892         u16 size;
 893 };
 894
 895 struct e1000_dev_spec_82541 {
 896         enum e1000_dsp_config dsp_config;
 897         enum e1000_ffe_config ffe_config;
 898         u16 spd_default;
 899         bool phy_init_script;
 900 };
 901
 902 struct e1000_dev_spec_82542 {
 903         bool dma_fairness;
 904 };
 905
 906 struct e1000_dev_spec_82543 {
 907         u32  tbi_compatibility;
 908         bool dma_fairness;
 909         bool init_phy_disabled;
 910 };
 911
 912 struct e1000_dev_spec_82571 {
 913         bool laa_is_present;
 914         u32 smb_counter;
 915         E1000_MUTEX swflag_mutex;
 916 };
 917
 918 struct e1000_dev_spec_80003es2lan {
 919         bool  mdic_wa_enable;
 920 };
 921
 922 struct e1000_shadow_ram {
 923         u16  value;
 924         bool modified;
 925 };
 926
 927 #define E1000_SHADOW_RAM_WORDS          2048
 928
 929 #ifdef ULP_SUPPORT
 930 /* I218 PHY Ultra Low Power (ULP) states */
 931 enum e1000_ulp_state {
 932         e1000_ulp_state_unknown,
 933         e1000_ulp_state_off,
 934         e1000_ulp_state_on,
 935 };
 936
 937 #endif /* ULP_SUPPORT */
 938 struct e1000_dev_spec_ich8lan {
 939         bool kmrn_lock_loss_workaround_enabled;
 940         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 941         E1000_MUTEX nvm_mutex;
 942         E1000_MUTEX swflag_mutex;
 943         bool nvm_k1_enabled;
 944         bool disable_k1_off;
 945         bool eee_disable;
 946         u16 eee_lp_ability;
 947 #ifdef ULP_SUPPORT
 948         enum e1000_ulp_state ulp_state;
 949         bool ulp_capability_disabled;
 950         bool during_suspend_flow;
 951         bool during_dpg_exit;
 952 #endif /* ULP_SUPPORT */
 953         u16 lat_enc;
 954         u16 max_ltr_enc;
 955         bool smbus_disable;
 956 };
 957
 958 struct e1000_dev_spec_82575 {
 959         bool sgmii_active;
 960         bool global_device_reset;
 961         bool eee_disable;
 962         bool module_plugged;
 963         bool clear_semaphore_once;
 964         u32 mtu;
 965         struct sfp_e1000_flags eth_flags;
 966         u8 media_port;
 967         bool media_changed;
 968 };
 969
 970 struct e1000_dev_spec_vf {
 971         u32 vf_number;
 972         u32 v2p_mailbox;
 973 };
 974
 975 struct e1000_hw {
 976         void *back;
 977
 978         u8 *hw_addr;
 979         u8 *flash_address;
 980         unsigned long io_base;
 981
 982         struct e1000_mac_info  mac;
 983         struct e1000_fc_info   fc;
 984         struct e1000_phy_info  phy;
 985         struct e1000_nvm_info  nvm;
 986         struct e1000_bus_info  bus;
 987         struct e1000_mbx_info mbx;
 988         struct e1000_host_mng_dhcp_cookie mng_cookie;
 989
 990         union {
 991                 struct e1000_dev_spec_82541 _82541;
 992                 struct e1000_dev_spec_82542 _82542;
 993                 struct e1000_dev_spec_82543 _82543;
 994                 struct e1000_dev_spec_82571 _82571;
 995                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 996                 struct e1000_dev_spec_ich8lan ich8lan;
 997                 struct e1000_dev_spec_82575 _82575;
 998                 struct e1000_dev_spec_vf vf;
 999         } dev_spec;
1000
1001         u16 device_id;
1002         u16 subsystem_vendor_id;
1003         u16 subsystem_device_id;
1004         u16 vendor_id;
1005
1006         u8  revision_id;
1007 };
1008
1009 #include "e1000_82541.h"
1010 #include "e1000_82543.h"
1011 #include "e1000_82571.h"
1012 #include "e1000_80003es2lan.h"
1013 #include "e1000_ich8lan.h"
1014 #include "e1000_82575.h"
1015 #include "e1000_i210.h"
1016 #include "e1000_base.h"
1017
1018 /* These functions must be implemented by drivers */
1019 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1020 void e1000_pci_set_mwi(struct e1000_hw *hw);
1021 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1022 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1023 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1024 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1025
1026 #endif