1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "e1000_osdep.h"
38 #include "e1000_regs.h"
39 #include "e1000_defines.h"
43 #define E1000_DEV_ID_82542 0x1000
44 #define E1000_DEV_ID_82543GC_FIBER 0x1001
45 #define E1000_DEV_ID_82543GC_COPPER 0x1004
46 #define E1000_DEV_ID_82544EI_COPPER 0x1008
47 #define E1000_DEV_ID_82544EI_FIBER 0x1009
48 #define E1000_DEV_ID_82544GC_COPPER 0x100C
49 #define E1000_DEV_ID_82544GC_LOM 0x100D
50 #define E1000_DEV_ID_82540EM 0x100E
51 #define E1000_DEV_ID_82540EM_LOM 0x1015
52 #define E1000_DEV_ID_82540EP_LOM 0x1016
53 #define E1000_DEV_ID_82540EP 0x1017
54 #define E1000_DEV_ID_82540EP_LP 0x101E
55 #define E1000_DEV_ID_82545EM_COPPER 0x100F
56 #define E1000_DEV_ID_82545EM_FIBER 0x1011
57 #define E1000_DEV_ID_82545GM_COPPER 0x1026
58 #define E1000_DEV_ID_82545GM_FIBER 0x1027
59 #define E1000_DEV_ID_82545GM_SERDES 0x1028
60 #define E1000_DEV_ID_82546EB_COPPER 0x1010
61 #define E1000_DEV_ID_82546EB_FIBER 0x1012
62 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
63 #define E1000_DEV_ID_82546GB_COPPER 0x1079
64 #define E1000_DEV_ID_82546GB_FIBER 0x107A
65 #define E1000_DEV_ID_82546GB_SERDES 0x107B
66 #define E1000_DEV_ID_82546GB_PCIE 0x108A
67 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
69 #define E1000_DEV_ID_82541EI 0x1013
70 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
71 #define E1000_DEV_ID_82541ER_LOM 0x1014
72 #define E1000_DEV_ID_82541ER 0x1078
73 #define E1000_DEV_ID_82541GI 0x1076
74 #define E1000_DEV_ID_82541GI_LF 0x107C
75 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
76 #define E1000_DEV_ID_82547EI 0x1019
77 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
78 #define E1000_DEV_ID_82547GI 0x1075
79 #define E1000_DEV_ID_82571EB_COPPER 0x105E
80 #define E1000_DEV_ID_82571EB_FIBER 0x105F
81 #define E1000_DEV_ID_82571EB_SERDES 0x1060
82 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
83 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
84 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
85 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
86 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
87 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
88 #define E1000_DEV_ID_82572EI_COPPER 0x107D
89 #define E1000_DEV_ID_82572EI_FIBER 0x107E
90 #define E1000_DEV_ID_82572EI_SERDES 0x107F
91 #define E1000_DEV_ID_82572EI 0x10B9
92 #define E1000_DEV_ID_82573E 0x108B
93 #define E1000_DEV_ID_82573E_IAMT 0x108C
94 #define E1000_DEV_ID_82573L 0x109A
95 #define E1000_DEV_ID_82574L 0x10D3
96 #define E1000_DEV_ID_82574LA 0x10F6
97 #define E1000_DEV_ID_82583V 0x150C
98 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
99 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
100 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
101 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
102 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
103 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
104 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
105 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
106 #define E1000_DEV_ID_ICH8_IFE 0x104C
107 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
108 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
109 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
110 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
111 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
112 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
113 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
114 #define E1000_DEV_ID_ICH9_BM 0x10E5
115 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
116 #define E1000_DEV_ID_ICH9_IFE 0x10C0
117 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
118 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
119 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
120 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
121 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
122 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
123 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
124 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
125 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
126 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
127 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
128 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
129 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
130 #define E1000_DEV_ID_PCH2_LV_V 0x1503
131 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
132 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
133 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
134 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
135 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
136 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
137 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
138 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
139 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */
140 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */
141 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */
142 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */
143 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */
144 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
145 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
146 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
147 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
148 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
149 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
150 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
151 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
152 #define E1000_DEV_ID_82576 0x10C9
153 #define E1000_DEV_ID_82576_FIBER 0x10E6
154 #define E1000_DEV_ID_82576_SERDES 0x10E7
155 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
156 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
157 #define E1000_DEV_ID_82576_NS 0x150A
158 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
159 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
160 #define E1000_DEV_ID_82576_VF 0x10CA
161 #define E1000_DEV_ID_82576_VF_HV 0x152D
162 #define E1000_DEV_ID_I350_VF 0x1520
163 #define E1000_DEV_ID_I350_VF_HV 0x152F
164 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
165 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
166 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
167 #define E1000_DEV_ID_82580_COPPER 0x150E
168 #define E1000_DEV_ID_82580_FIBER 0x150F
169 #define E1000_DEV_ID_82580_SERDES 0x1510
170 #define E1000_DEV_ID_82580_SGMII 0x1511
171 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
172 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
173 #define E1000_DEV_ID_I350_COPPER 0x1521
174 #define E1000_DEV_ID_I350_FIBER 0x1522
175 #define E1000_DEV_ID_I350_SERDES 0x1523
176 #define E1000_DEV_ID_I350_SGMII 0x1524
177 #define E1000_DEV_ID_I350_DA4 0x1546
178 #define E1000_DEV_ID_I210_COPPER 0x1533
179 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
180 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
181 #define E1000_DEV_ID_I210_FIBER 0x1536
182 #define E1000_DEV_ID_I210_SERDES 0x1537
183 #define E1000_DEV_ID_I210_SGMII 0x1538
184 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
185 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
186 #define E1000_DEV_ID_I211_COPPER 0x1539
187 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
188 #define E1000_DEV_ID_I354_SGMII 0x1F41
189 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
190 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
191 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
192 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
193 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
195 #define E1000_REVISION_0 0
196 #define E1000_REVISION_1 1
197 #define E1000_REVISION_2 2
198 #define E1000_REVISION_3 3
199 #define E1000_REVISION_4 4
201 #define E1000_FUNC_0 0
202 #define E1000_FUNC_1 1
203 #define E1000_FUNC_2 2
204 #define E1000_FUNC_3 3
206 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
207 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
208 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
209 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
211 enum e1000_mac_type {
248 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
251 enum e1000_media_type {
252 e1000_media_type_unknown = 0,
253 e1000_media_type_copper = 1,
254 e1000_media_type_fiber = 2,
255 e1000_media_type_internal_serdes = 3,
256 e1000_num_media_types
259 enum e1000_nvm_type {
260 e1000_nvm_unknown = 0,
262 e1000_nvm_eeprom_spi,
263 e1000_nvm_eeprom_microwire,
269 enum e1000_nvm_override {
270 e1000_nvm_override_none = 0,
271 e1000_nvm_override_spi_small,
272 e1000_nvm_override_spi_large,
273 e1000_nvm_override_microwire_small,
274 e1000_nvm_override_microwire_large
277 enum e1000_phy_type {
278 e1000_phy_unknown = 0,
296 enum e1000_bus_type {
297 e1000_bus_type_unknown = 0,
300 e1000_bus_type_pci_express,
301 e1000_bus_type_reserved
304 enum e1000_bus_speed {
305 e1000_bus_speed_unknown = 0,
311 e1000_bus_speed_2500,
312 e1000_bus_speed_5000,
313 e1000_bus_speed_reserved
316 enum e1000_bus_width {
317 e1000_bus_width_unknown = 0,
318 e1000_bus_width_pcie_x1,
319 e1000_bus_width_pcie_x2,
320 e1000_bus_width_pcie_x4 = 4,
321 e1000_bus_width_pcie_x8 = 8,
324 e1000_bus_width_reserved
327 enum e1000_1000t_rx_status {
328 e1000_1000t_rx_status_not_ok = 0,
329 e1000_1000t_rx_status_ok,
330 e1000_1000t_rx_status_undefined = 0xFF
333 enum e1000_rev_polarity {
334 e1000_rev_polarity_normal = 0,
335 e1000_rev_polarity_reversed,
336 e1000_rev_polarity_undefined = 0xFF
344 e1000_fc_default = 0xFF
347 enum e1000_ffe_config {
348 e1000_ffe_config_enabled = 0,
349 e1000_ffe_config_active,
350 e1000_ffe_config_blocked
353 enum e1000_dsp_config {
354 e1000_dsp_config_disabled = 0,
355 e1000_dsp_config_enabled,
356 e1000_dsp_config_activated,
357 e1000_dsp_config_undefined = 0xFF
361 e1000_ms_hw_default = 0,
362 e1000_ms_force_master,
363 e1000_ms_force_slave,
367 enum e1000_smart_speed {
368 e1000_smart_speed_default = 0,
369 e1000_smart_speed_on,
370 e1000_smart_speed_off
373 enum e1000_serdes_link_state {
374 e1000_serdes_link_down = 0,
375 e1000_serdes_link_autoneg_progress,
376 e1000_serdes_link_autoneg_complete,
377 e1000_serdes_link_forced_up
383 /* Receive Descriptor */
384 struct e1000_rx_desc {
385 __le64 buffer_addr; /* Address of the descriptor's data buffer */
386 __le16 length; /* Length of data DMAed into data buffer */
387 __le16 csum; /* Packet checksum */
388 u8 status; /* Descriptor status */
389 u8 errors; /* Descriptor Errors */
393 /* Receive Descriptor - Extended */
394 union e1000_rx_desc_extended {
401 __le32 mrq; /* Multiple Rx Queues */
403 __le32 rss; /* RSS Hash */
405 __le16 ip_id; /* IP id */
406 __le16 csum; /* Packet Checksum */
411 __le32 status_error; /* ext status/error */
413 __le16 vlan; /* VLAN tag */
415 } wb; /* writeback */
418 #define MAX_PS_BUFFERS 4
420 /* Number of packet split data buffers (not including the header buffer) */
421 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
423 /* Receive Descriptor - Packet Split */
424 union e1000_rx_desc_packet_split {
426 /* one buffer for protocol header(s), three data buffers */
427 __le64 buffer_addr[MAX_PS_BUFFERS];
431 __le32 mrq; /* Multiple Rx Queues */
433 __le32 rss; /* RSS Hash */
435 __le16 ip_id; /* IP id */
436 __le16 csum; /* Packet Checksum */
441 __le32 status_error; /* ext status/error */
442 __le16 length0; /* length of buffer 0 */
443 __le16 vlan; /* VLAN tag */
446 __le16 header_status;
447 /* length of buffers 1-3 */
448 __le16 length[PS_PAGE_BUFFERS];
451 } wb; /* writeback */
454 /* Transmit Descriptor */
455 struct e1000_tx_desc {
456 __le64 buffer_addr; /* Address of the descriptor's data buffer */
460 __le16 length; /* Data buffer length */
461 u8 cso; /* Checksum offset */
462 u8 cmd; /* Descriptor control */
468 u8 status; /* Descriptor status */
469 u8 css; /* Checksum start */
475 /* Offload Context Descriptor */
476 struct e1000_context_desc {
480 u8 ipcss; /* IP checksum start */
481 u8 ipcso; /* IP checksum offset */
482 __le16 ipcse; /* IP checksum end */
488 u8 tucss; /* TCP checksum start */
489 u8 tucso; /* TCP checksum offset */
490 __le16 tucse; /* TCP checksum end */
493 __le32 cmd_and_length;
497 u8 status; /* Descriptor status */
498 u8 hdr_len; /* Header length */
499 __le16 mss; /* Maximum segment size */
504 /* Offload data descriptor */
505 struct e1000_data_desc {
506 __le64 buffer_addr; /* Address of the descriptor's buffer address */
510 __le16 length; /* Data buffer length */
518 u8 status; /* Descriptor status */
519 u8 popts; /* Packet Options */
525 /* Statistics counters collected by the MAC */
526 struct e1000_hw_stats {
609 struct e1000_vf_stats {
641 struct e1000_phy_stats {
646 struct e1000_host_mng_dhcp_cookie {
657 /* Host Interface "Rev 1" */
658 struct e1000_host_command_header {
665 #define E1000_HI_MAX_DATA_LENGTH 252
666 struct e1000_host_command_info {
667 struct e1000_host_command_header command_header;
668 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
671 /* Host Interface "Rev 2" */
672 struct e1000_host_mng_command_header {
680 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
681 struct e1000_host_mng_command_info {
682 struct e1000_host_mng_command_header command_header;
683 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
686 #include "e1000_mac.h"
687 #include "e1000_phy.h"
688 #include "e1000_nvm.h"
689 #include "e1000_manage.h"
690 #include "e1000_mbx.h"
692 /* Function pointers for the MAC. */
693 struct e1000_mac_operations {
694 s32 (*init_params)(struct e1000_hw *);
695 s32 (*id_led_init)(struct e1000_hw *);
696 s32 (*blink_led)(struct e1000_hw *);
697 bool (*check_mng_mode)(struct e1000_hw *);
698 s32 (*check_for_link)(struct e1000_hw *);
699 s32 (*cleanup_led)(struct e1000_hw *);
700 void (*clear_hw_cntrs)(struct e1000_hw *);
701 void (*clear_vfta)(struct e1000_hw *);
702 s32 (*get_bus_info)(struct e1000_hw *);
703 void (*set_lan_id)(struct e1000_hw *);
704 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
705 s32 (*led_on)(struct e1000_hw *);
706 s32 (*led_off)(struct e1000_hw *);
707 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
708 s32 (*reset_hw)(struct e1000_hw *);
709 s32 (*init_hw)(struct e1000_hw *);
710 void (*shutdown_serdes)(struct e1000_hw *);
711 void (*power_up_serdes)(struct e1000_hw *);
712 s32 (*setup_link)(struct e1000_hw *);
713 s32 (*setup_physical_interface)(struct e1000_hw *);
714 s32 (*setup_led)(struct e1000_hw *);
715 void (*write_vfta)(struct e1000_hw *, u32, u32);
716 void (*config_collision_dist)(struct e1000_hw *);
717 int (*rar_set)(struct e1000_hw *, u8*, u32);
718 s32 (*read_mac_addr)(struct e1000_hw *);
719 s32 (*validate_mdi_setting)(struct e1000_hw *);
720 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
721 void (*release_swfw_sync)(struct e1000_hw *, u16);
724 /* When to use various PHY register access functions:
727 * Function Does Does When to use
728 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
729 * X_reg L,P,A n/a for simple PHY reg accesses
730 * X_reg_locked P,A L for multiple accesses of different regs
732 * X_reg_page A L,P for multiple accesses of different regs
735 * Where X=[read|write], L=locking, P=sets page, A=register access
738 struct e1000_phy_operations {
739 s32 (*init_params)(struct e1000_hw *);
740 s32 (*acquire)(struct e1000_hw *);
741 s32 (*cfg_on_link_up)(struct e1000_hw *);
742 s32 (*check_polarity)(struct e1000_hw *);
743 s32 (*check_reset_block)(struct e1000_hw *);
744 s32 (*commit)(struct e1000_hw *);
745 s32 (*force_speed_duplex)(struct e1000_hw *);
746 s32 (*get_cfg_done)(struct e1000_hw *hw);
747 s32 (*get_cable_length)(struct e1000_hw *);
748 s32 (*get_info)(struct e1000_hw *);
749 s32 (*set_page)(struct e1000_hw *, u16);
750 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
751 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
752 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
753 void (*release)(struct e1000_hw *);
754 s32 (*reset)(struct e1000_hw *);
755 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
756 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
757 s32 (*write_reg)(struct e1000_hw *, u32, u16);
758 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
759 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
760 void (*power_up)(struct e1000_hw *);
761 void (*power_down)(struct e1000_hw *);
762 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
763 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
766 /* Function pointers for the NVM. */
767 struct e1000_nvm_operations {
768 s32 (*init_params)(struct e1000_hw *);
769 s32 (*acquire)(struct e1000_hw *);
770 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
771 void (*release)(struct e1000_hw *);
772 void (*reload)(struct e1000_hw *);
773 s32 (*update)(struct e1000_hw *);
774 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
775 s32 (*validate)(struct e1000_hw *);
776 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
779 struct e1000_mac_info {
780 struct e1000_mac_operations ops;
781 u8 addr[ETH_ADDR_LEN];
782 u8 perm_addr[ETH_ADDR_LEN];
784 enum e1000_mac_type type;
802 /* Maximum size of the MTA register table in all supported adapters */
803 #define MAX_MTA_REG 128
804 u32 mta_shadow[MAX_MTA_REG];
807 u8 forced_speed_duplex;
811 bool arc_subsystem_valid;
812 bool asf_firmware_present;
815 bool get_link_status;
817 bool report_tx_early;
818 enum e1000_serdes_link_state serdes_link_state;
819 bool serdes_has_link;
820 bool tx_pkt_filtering;
823 struct e1000_phy_info {
824 struct e1000_phy_operations ops;
825 enum e1000_phy_type type;
827 enum e1000_1000t_rx_status local_rx;
828 enum e1000_1000t_rx_status remote_rx;
829 enum e1000_ms_type ms_type;
830 enum e1000_ms_type original_ms_type;
831 enum e1000_rev_polarity cable_polarity;
832 enum e1000_smart_speed smart_speed;
836 u32 reset_delay_us; /* in usec */
839 enum e1000_media_type media_type;
841 u16 autoneg_advertised;
844 u16 max_cable_length;
845 u16 min_cable_length;
849 bool disable_polarity_correction;
851 bool polarity_correction;
852 bool speed_downgraded;
853 bool autoneg_wait_to_complete;
856 struct e1000_nvm_info {
857 struct e1000_nvm_operations ops;
858 enum e1000_nvm_type type;
859 enum e1000_nvm_override override;
871 struct e1000_bus_info {
872 enum e1000_bus_type type;
873 enum e1000_bus_speed speed;
874 enum e1000_bus_width width;
880 struct e1000_fc_info {
881 u32 high_water; /* Flow control high-water mark */
882 u32 low_water; /* Flow control low-water mark */
883 u16 pause_time; /* Flow control pause timer */
884 u16 refresh_time; /* Flow control refresh timer */
885 bool send_xon; /* Flow control send XON */
886 bool strict_ieee; /* Strict IEEE mode */
887 enum e1000_fc_mode current_mode; /* FC mode in effect */
888 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
891 struct e1000_mbx_operations {
892 s32 (*init_params)(struct e1000_hw *hw);
893 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
894 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
895 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
896 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
897 s32 (*check_for_msg)(struct e1000_hw *, u16);
898 s32 (*check_for_ack)(struct e1000_hw *, u16);
899 s32 (*check_for_rst)(struct e1000_hw *, u16);
902 struct e1000_mbx_stats {
911 struct e1000_mbx_info {
912 struct e1000_mbx_operations ops;
913 struct e1000_mbx_stats stats;
919 struct e1000_dev_spec_82541 {
920 enum e1000_dsp_config dsp_config;
921 enum e1000_ffe_config ffe_config;
923 bool phy_init_script;
926 struct e1000_dev_spec_82542 {
930 struct e1000_dev_spec_82543 {
931 u32 tbi_compatibility;
933 bool init_phy_disabled;
936 struct e1000_dev_spec_82571 {
939 E1000_MUTEX swflag_mutex;
942 struct e1000_dev_spec_80003es2lan {
946 struct e1000_shadow_ram {
951 #define E1000_SHADOW_RAM_WORDS 2048
954 /* I218 PHY Ultra Low Power (ULP) states */
955 enum e1000_ulp_state {
956 e1000_ulp_state_unknown,
961 #endif /* ULP_SUPPORT */
962 struct e1000_dev_spec_ich8lan {
963 bool kmrn_lock_loss_workaround_enabled;
964 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
965 E1000_MUTEX nvm_mutex;
966 E1000_MUTEX swflag_mutex;
972 enum e1000_ulp_state ulp_state;
973 bool ulp_capability_disabled;
974 bool during_suspend_flow;
975 bool during_dpg_exit;
976 #endif /* ULP_SUPPORT */
982 struct e1000_dev_spec_82575 {
984 bool global_device_reset;
987 bool clear_semaphore_once;
989 struct sfp_e1000_flags eth_flags;
994 struct e1000_dev_spec_vf {
1004 unsigned long io_base;
1006 struct e1000_mac_info mac;
1007 struct e1000_fc_info fc;
1008 struct e1000_phy_info phy;
1009 struct e1000_nvm_info nvm;
1010 struct e1000_bus_info bus;
1011 struct e1000_mbx_info mbx;
1012 struct e1000_host_mng_dhcp_cookie mng_cookie;
1015 struct e1000_dev_spec_82541 _82541;
1016 struct e1000_dev_spec_82542 _82542;
1017 struct e1000_dev_spec_82543 _82543;
1018 struct e1000_dev_spec_82571 _82571;
1019 struct e1000_dev_spec_80003es2lan _80003es2lan;
1020 struct e1000_dev_spec_ich8lan ich8lan;
1021 struct e1000_dev_spec_82575 _82575;
1022 struct e1000_dev_spec_vf vf;
1026 u16 subsystem_vendor_id;
1027 u16 subsystem_device_id;
1033 #include "e1000_82541.h"
1034 #include "e1000_82543.h"
1035 #include "e1000_82571.h"
1036 #include "e1000_80003es2lan.h"
1037 #include "e1000_ich8lan.h"
1038 #include "e1000_82575.h"
1039 #include "e1000_i210.h"
1041 /* These functions must be implemented by drivers */
1042 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1043 void e1000_pci_set_mwi(struct e1000_hw *hw);
1044 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1045 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1046 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1047 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);