drivers/net/e1000/base/e1000_i210.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 #ifndef _E1000_I210_H_
   6 #define _E1000_I210_H_
   7
   8 bool e1000_get_flash_presence_i210(struct e1000_hw *hw);
   9 s32 e1000_update_flash_i210(struct e1000_hw *hw);
  10 s32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw);
  11 s32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw);
  12 s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,
  13                               u16 words, u16 *data);
  14 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
  15                              u16 words, u16 *data);
  16 s32 e1000_read_invm_version(struct e1000_hw *hw,
  17                             struct e1000_fw_version *invm_ver);
  18 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
  19 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
  20 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
  21                          u16 *data);
  22 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
  23                           u16 data);
  24 s32 e1000_init_hw_i210(struct e1000_hw *hw);
  25
  26 #define E1000_STM_OPCODE                0xDB00
  27 #define E1000_EEPROM_FLASH_SIZE_WORD    0x11
  28
  29 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
  30         (u8)((invm_dword) & 0x7)
  31 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
  32         (u8)(((invm_dword) & 0x0000FE00) >> 9)
  33 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \
  34         (u16)(((invm_dword) & 0xFFFF0000) >> 16)
  35
  36 enum E1000_INVM_STRUCTURE_TYPE {
  37         E1000_INVM_UNINITIALIZED_STRUCTURE              = 0x00,
  38         E1000_INVM_WORD_AUTOLOAD_STRUCTURE              = 0x01,
  39         E1000_INVM_CSR_AUTOLOAD_STRUCTURE               = 0x02,
  40         E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE      = 0x03,
  41         E1000_INVM_RSA_KEY_SHA256_STRUCTURE             = 0x04,
  42         E1000_INVM_INVALIDATED_STRUCTURE                = 0x0F,
  43 };
  44
  45 #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS   8
  46 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS     1
  47 #define E1000_INVM_ULT_BYTES_SIZE       8
  48 #define E1000_INVM_RECORD_SIZE_IN_BYTES 4
  49 #define E1000_INVM_VER_FIELD_ONE        0x1FF8
  50 #define E1000_INVM_VER_FIELD_TWO        0x7FE000
  51 #define E1000_INVM_IMGTYPE_FIELD        0x1F800000
  52
  53 #define E1000_INVM_MAJOR_MASK   0x3F0
  54 #define E1000_INVM_MINOR_MASK   0xF
  55 #define E1000_INVM_MAJOR_SHIFT  4
  56
  57 #define ID_LED_DEFAULT_I210             ((ID_LED_OFF1_ON2  << 8) | \
  58                                          (ID_LED_DEF1_DEF2 <<  4) | \
  59                                          (ID_LED_OFF1_OFF2))
  60 #define ID_LED_DEFAULT_I210_SERDES      ((ID_LED_DEF1_DEF2 << 8) | \
  61                                          (ID_LED_DEF1_DEF2 <<  4) | \
  62                                          (ID_LED_OFF1_ON2))
  63
  64 /* NVM offset defaults for I211 devices */
  65 #define NVM_INIT_CTRL_2_DEFAULT_I211    0X7243
  66 #define NVM_INIT_CTRL_4_DEFAULT_I211    0x00C1
  67 #define NVM_LED_1_CFG_DEFAULT_I211      0x0184
  68 #define NVM_LED_0_2_CFG_DEFAULT_I211    0x200C
  69
  70 /* PLL Defines */
  71 #define E1000_PCI_PMCSR                 0x44
  72 #define E1000_PCI_PMCSR_D3              0x03
  73 #define E1000_MAX_PLL_TRIES             5
  74 #define E1000_PHY_PLL_UNCONF            0xFF
  75 #define E1000_PHY_PLL_FREQ_PAGE         0xFC0000
  76 #define E1000_PHY_PLL_FREQ_REG          0x000E
  77 #define E1000_INVM_DEFAULT_AL           0x202F
  78 #define E1000_INVM_AUTOLOAD             0x0A
  79 #define E1000_INVM_PLL_WO_VAL           0x0010
  80
  81 #endif