drivers/net/e1000/base/e1000_ich8lan.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82562G 10/100 Network Connection
  35  * 82562G-2 10/100 Network Connection
  36  * 82562GT 10/100 Network Connection
  37  * 82562GT-2 10/100 Network Connection
  38  * 82562V 10/100 Network Connection
  39  * 82562V-2 10/100 Network Connection
  40  * 82566DC-2 Gigabit Network Connection
  41  * 82566DC Gigabit Network Connection
  42  * 82566DM-2 Gigabit Network Connection
  43  * 82566DM Gigabit Network Connection
  44  * 82566MC Gigabit Network Connection
  45  * 82566MM Gigabit Network Connection
  46  * 82567LM Gigabit Network Connection
  47  * 82567LF Gigabit Network Connection
  48  * 82567V Gigabit Network Connection
  49  * 82567LM-2 Gigabit Network Connection
  50  * 82567LF-2 Gigabit Network Connection
  51  * 82567V-2 Gigabit Network Connection
  52  * 82567LF-3 Gigabit Network Connection
  53  * 82567LM-3 Gigabit Network Connection
  54  * 82567LM-4 Gigabit Network Connection
  55  * 82577LM Gigabit Network Connection
  56  * 82577LC Gigabit Network Connection
  57  * 82578DM Gigabit Network Connection
  58  * 82578DC Gigabit Network Connection
  59  * 82579LM Gigabit Network Connection
  60  * 82579V Gigabit Network Connection
  61  * Ethernet Connection I217-LM
  62  * Ethernet Connection I217-V
  63  * Ethernet Connection I218-V
  64  * Ethernet Connection I218-LM
  65  * Ethernet Connection (2) I218-LM
  66  * Ethernet Connection (2) I218-V
  67  * Ethernet Connection (3) I218-LM
  68  * Ethernet Connection (3) I218-V
  69  */
  70
  71 #include "e1000_api.h"
  72
  73 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  74 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  75 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  76 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  77 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  78 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  79 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  80 STATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  81 STATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  82 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  83 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  84 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  85                                               u8 *mc_addr_list,
  86                                               u32 mc_addr_count);
  87 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  88 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  90 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  91 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  92                                             bool active);
  93 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  94                                             bool active);
  95 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  96                                    u16 words, u16 *data);
  97 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  98                                     u16 words, u16 *data);
  99 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 100 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
 101 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
 102                                             u16 *data);
 103 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 104 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 105 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 106 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 107 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 108 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 109 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 110 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 111                                            u16 *speed, u16 *duplex);
 112 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 113 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 114 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 115 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 116 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 117 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 118 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 119 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 120 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 121 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 122 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 123 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 124 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 125                                           u32 offset, u8 *data);
 126 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 127                                           u8 size, u16 *data);
 128 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 129                                           u32 offset, u16 *data);
 130 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 131                                                  u32 offset, u8 byte);
 132 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 133 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 134 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 135 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 136 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 137 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 138
 139 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 140 /* Offset 04h HSFSTS */
 141 union ich8_hws_flash_status {
 142         struct ich8_hsfsts {
 143                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 144                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 145                 u16 dael:1; /* bit 2 Direct Access error Log */
 146                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 147                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 148                 u16 reserved1:2; /* bit 13:6 Reserved */
 149                 u16 reserved2:6; /* bit 13:6 Reserved */
 150                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 151                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 152         } hsf_status;
 153         u16 regval;
 154 };
 155
 156 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 157 /* Offset 06h FLCTL */
 158 union ich8_hws_flash_ctrl {
 159         struct ich8_hsflctl {
 160                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 161                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 162                 u16 reserved:5;   /* 7:3 Reserved  */
 163                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 164                 u16 flockdn:6;   /* 15:10 Reserved */
 165         } hsf_ctrl;
 166         u16 regval;
 167 };
 168
 169 /* ICH Flash Region Access Permissions */
 170 union ich8_hws_flash_regacc {
 171         struct ich8_flracc {
 172                 u32 grra:8; /* 0:7 GbE region Read Access */
 173                 u32 grwa:8; /* 8:15 GbE region Write Access */
 174                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 175                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 176         } hsf_flregacc;
 177         u16 regval;
 178 };
 179
 180 /**
 181  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 182  *  @hw: pointer to the HW structure
 183  *
 184  *  Test access to the PHY registers by reading the PHY ID registers.  If
 185  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 186  *  otherwise assume the read PHY ID is correct if it is valid.
 187  *
 188  *  Assumes the sw/fw/hw semaphore is already acquired.
 189  **/
 190 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 191 {
 192         u16 phy_reg = 0;
 193         u32 phy_id = 0;
 194         s32 ret_val = 0;
 195         u16 retry_count;
 196         u32 mac_reg = 0;
 197
 198         for (retry_count = 0; retry_count < 2; retry_count++) {
 199                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 200                 if (ret_val || (phy_reg == 0xFFFF))
 201                         continue;
 202                 phy_id = (u32)(phy_reg << 16);
 203
 204                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 205                 if (ret_val || (phy_reg == 0xFFFF)) {
 206                         phy_id = 0;
 207                         continue;
 208                 }
 209                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 210                 break;
 211         }
 212
 213         if (hw->phy.id) {
 214                 if  (hw->phy.id == phy_id)
 215                         goto out;
 216         } else if (phy_id) {
 217                 hw->phy.id = phy_id;
 218                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 219                 goto out;
 220         }
 221
 222         /* In case the PHY needs to be in mdio slow mode,
 223          * set slow mode and try to get the PHY id again.
 224          */
 225         if (hw->mac.type < e1000_pch_lpt) {
 226                 hw->phy.ops.release(hw);
 227                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 228                 if (!ret_val)
 229                         ret_val = e1000_get_phy_id(hw);
 230                 hw->phy.ops.acquire(hw);
 231         }
 232
 233         if (ret_val)
 234                 return false;
 235 out:
 236         if (hw->mac.type == e1000_pch_lpt) {
 237                 /* Only unforce SMBus if ME is not active */
 238                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
 239                     E1000_ICH_FWSM_FW_VALID)) {
 240                         /* Unforce SMBus mode in PHY */
 241                         hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 242                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 243                         hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 244
 245                         /* Unforce SMBus mode in MAC */
 246                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 247                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 248                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 249                 }
 250         }
 251
 252         return true;
 253 }
 254
 255 /**
 256  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 257  *  @hw: pointer to the HW structure
 258  *
 259  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 260  *  used to reset the PHY to a quiescent state when necessary.
 261  **/
 262 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 263 {
 264         u32 mac_reg;
 265
 266         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 267
 268         /* Set Phy Config Counter to 50msec */
 269         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 270         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 271         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 272         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 273
 274         /* Toggle LANPHYPC Value bit */
 275         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 276         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 277         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 278         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 279         E1000_WRITE_FLUSH(hw);
 280         msec_delay(1);
 281         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 282         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 283         E1000_WRITE_FLUSH(hw);
 284
 285         if (hw->mac.type < e1000_pch_lpt) {
 286                 msec_delay(50);
 287         } else {
 288                 u16 count = 20;
 289
 290                 do {
 291                         msec_delay(5);
 292                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 293                            E1000_CTRL_EXT_LPCD) && count--);
 294
 295                 msec_delay(30);
 296         }
 297 }
 298
 299 /**
 300  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 301  *  @hw: pointer to the HW structure
 302  *
 303  *  Workarounds/flow necessary for PHY initialization during driver load
 304  *  and resume paths.
 305  **/
 306 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 307 {
 308         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 309         s32 ret_val;
 310
 311         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 312
 313         /* Gate automatic PHY configuration by hardware on managed and
 314          * non-managed 82579 and newer adapters.
 315          */
 316         e1000_gate_hw_phy_config_ich8lan(hw, true);
 317
 318 #ifdef ULP_SUPPORT
 319         /* It is not possible to be certain of the current state of ULP
 320          * so forcibly disable it.
 321          */
 322         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 323
 324 #endif /* ULP_SUPPORT */
 325         ret_val = hw->phy.ops.acquire(hw);
 326         if (ret_val) {
 327                 DEBUGOUT("Failed to initialize PHY flow\n");
 328                 goto out;
 329         }
 330
 331         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 332          * inaccessible and resetting the PHY is not blocked, toggle the
 333          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 334          */
 335         switch (hw->mac.type) {
 336         case e1000_pch_lpt:
 337                 if (e1000_phy_is_accessible_pchlan(hw))
 338                         break;
 339
 340                 /* Before toggling LANPHYPC, see if PHY is accessible by
 341                  * forcing MAC to SMBus mode first.
 342                  */
 343                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 344                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 345                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 346
 347                 /* Wait 50 milliseconds for MAC to finish any retries
 348                  * that it might be trying to perform from previous
 349                  * attempts to acknowledge any phy read requests.
 350                  */
 351                  msec_delay(50);
 352
 353                 /* fall-through */
 354         case e1000_pch2lan:
 355                 if (e1000_phy_is_accessible_pchlan(hw))
 356                         break;
 357
 358                 /* fall-through */
 359         case e1000_pchlan:
 360                 if ((hw->mac.type == e1000_pchlan) &&
 361                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 362                         break;
 363
 364                 if (hw->phy.ops.check_reset_block(hw)) {
 365                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 366                         ret_val = -E1000_ERR_PHY;
 367                         break;
 368                 }
 369
 370                 /* Toggle LANPHYPC Value bit */
 371                 e1000_toggle_lanphypc_pch_lpt(hw);
 372                 if (hw->mac.type >= e1000_pch_lpt) {
 373                         if (e1000_phy_is_accessible_pchlan(hw))
 374                                 break;
 375
 376                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 377                          * so ensure that the MAC is also out of SMBus mode
 378                          */
 379                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 380                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 381                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 382
 383                         if (e1000_phy_is_accessible_pchlan(hw))
 384                                 break;
 385
 386                         ret_val = -E1000_ERR_PHY;
 387                 }
 388                 break;
 389         default:
 390                 break;
 391         }
 392
 393         hw->phy.ops.release(hw);
 394         if (!ret_val) {
 395
 396                 /* Check to see if able to reset PHY.  Print error if not */
 397                 if (hw->phy.ops.check_reset_block(hw)) {
 398                         ERROR_REPORT("Reset blocked by ME\n");
 399                         goto out;
 400                 }
 401
 402                 /* Reset the PHY before any access to it.  Doing so, ensures
 403                  * that the PHY is in a known good state before we read/write
 404                  * PHY registers.  The generic reset is sufficient here,
 405                  * because we haven't determined the PHY type yet.
 406                  */
 407                 ret_val = e1000_phy_hw_reset_generic(hw);
 408                 if (ret_val)
 409                         goto out;
 410
 411                 /* On a successful reset, possibly need to wait for the PHY
 412                  * to quiesce to an accessible state before returning control
 413                  * to the calling function.  If the PHY does not quiesce, then
 414                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 415                  *  the PHY is in.
 416                  */
 417                 ret_val = hw->phy.ops.check_reset_block(hw);
 418                 if (ret_val)
 419                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 420         }
 421
 422 out:
 423         /* Ungate automatic PHY configuration on non-managed 82579 */
 424         if ((hw->mac.type == e1000_pch2lan) &&
 425             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 426                 msec_delay(10);
 427                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 428         }
 429
 430         return ret_val;
 431 }
 432
 433 /**
 434  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 435  *  @hw: pointer to the HW structure
 436  *
 437  *  Initialize family-specific PHY parameters and function pointers.
 438  **/
 439 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 440 {
 441         struct e1000_phy_info *phy = &hw->phy;
 442         s32 ret_val;
 443
 444         DEBUGFUNC("e1000_init_phy_params_pchlan");
 445
 446         phy->addr               = 1;
 447         phy->reset_delay_us     = 100;
 448
 449         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 450         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 451         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 452         phy->ops.set_page       = e1000_set_page_igp;
 453         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 454         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 455         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 456         phy->ops.release        = e1000_release_swflag_ich8lan;
 457         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 458         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 459         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 460         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 461         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 462         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 463         phy->ops.power_up       = e1000_power_up_phy_copper;
 464         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 465         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 466
 467         phy->id = e1000_phy_unknown;
 468
 469         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 470         if (ret_val)
 471                 return ret_val;
 472
 473         if (phy->id == e1000_phy_unknown)
 474                 switch (hw->mac.type) {
 475                 default:
 476                         ret_val = e1000_get_phy_id(hw);
 477                         if (ret_val)
 478                                 return ret_val;
 479                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 480                                 break;
 481                         /* fall-through */
 482                 case e1000_pch2lan:
 483                 case e1000_pch_lpt:
 484                         /* In case the PHY needs to be in mdio slow mode,
 485                          * set slow mode and try to get the PHY id again.
 486                          */
 487                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 488                         if (ret_val)
 489                                 return ret_val;
 490                         ret_val = e1000_get_phy_id(hw);
 491                         if (ret_val)
 492                                 return ret_val;
 493                         break;
 494                 }
 495         phy->type = e1000_get_phy_type_from_id(phy->id);
 496
 497         switch (phy->type) {
 498         case e1000_phy_82577:
 499         case e1000_phy_82579:
 500         case e1000_phy_i217:
 501                 phy->ops.check_polarity = e1000_check_polarity_82577;
 502                 phy->ops.force_speed_duplex =
 503                         e1000_phy_force_speed_duplex_82577;
 504                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 505                 phy->ops.get_info = e1000_get_phy_info_82577;
 506                 phy->ops.commit = e1000_phy_sw_reset_generic;
 507                 break;
 508         case e1000_phy_82578:
 509                 phy->ops.check_polarity = e1000_check_polarity_m88;
 510                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 511                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 512                 phy->ops.get_info = e1000_get_phy_info_m88;
 513                 break;
 514         default:
 515                 ret_val = -E1000_ERR_PHY;
 516                 break;
 517         }
 518
 519         return ret_val;
 520 }
 521
 522 /**
 523  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 524  *  @hw: pointer to the HW structure
 525  *
 526  *  Initialize family-specific PHY parameters and function pointers.
 527  **/
 528 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 529 {
 530         struct e1000_phy_info *phy = &hw->phy;
 531         s32 ret_val;
 532         u16 i = 0;
 533
 534         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 535
 536         phy->addr               = 1;
 537         phy->reset_delay_us     = 100;
 538
 539         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 540         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 541         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 542         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 543         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 544         phy->ops.release        = e1000_release_swflag_ich8lan;
 545         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 546         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 547         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 548         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 549         phy->ops.power_up       = e1000_power_up_phy_copper;
 550         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 551
 552         /* We may need to do this twice - once for IGP and if that fails,
 553          * we'll set BM func pointers and try again
 554          */
 555         ret_val = e1000_determine_phy_address(hw);
 556         if (ret_val) {
 557                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 558                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 559                 ret_val = e1000_determine_phy_address(hw);
 560                 if (ret_val) {
 561                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 562                         return ret_val;
 563                 }
 564         }
 565
 566         phy->id = 0;
 567         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 568                (i++ < 100)) {
 569                 msec_delay(1);
 570                 ret_val = e1000_get_phy_id(hw);
 571                 if (ret_val)
 572                         return ret_val;
 573         }
 574
 575         /* Verify phy id */
 576         switch (phy->id) {
 577         case IGP03E1000_E_PHY_ID:
 578                 phy->type = e1000_phy_igp_3;
 579                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 580                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 581                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 582                 phy->ops.get_info = e1000_get_phy_info_igp;
 583                 phy->ops.check_polarity = e1000_check_polarity_igp;
 584                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 585                 break;
 586         case IFE_E_PHY_ID:
 587         case IFE_PLUS_E_PHY_ID:
 588         case IFE_C_E_PHY_ID:
 589                 phy->type = e1000_phy_ife;
 590                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 591                 phy->ops.get_info = e1000_get_phy_info_ife;
 592                 phy->ops.check_polarity = e1000_check_polarity_ife;
 593                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 594                 break;
 595         case BME1000_E_PHY_ID:
 596                 phy->type = e1000_phy_bm;
 597                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 598                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 599                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 600                 phy->ops.commit = e1000_phy_sw_reset_generic;
 601                 phy->ops.get_info = e1000_get_phy_info_m88;
 602                 phy->ops.check_polarity = e1000_check_polarity_m88;
 603                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 604                 break;
 605         default:
 606                 return -E1000_ERR_PHY;
 607                 break;
 608         }
 609
 610         return E1000_SUCCESS;
 611 }
 612
 613 /**
 614  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 615  *  @hw: pointer to the HW structure
 616  *
 617  *  Initialize family-specific NVM parameters and function
 618  *  pointers.
 619  **/
 620 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 621 {
 622         struct e1000_nvm_info *nvm = &hw->nvm;
 623         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 624         u32 gfpreg, sector_base_addr, sector_end_addr;
 625         u16 i;
 626
 627         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 628
 629         /* Can't read flash registers if the register set isn't mapped. */
 630         nvm->type = e1000_nvm_flash_sw;
 631         if (!hw->flash_address) {
 632                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 633                 return -E1000_ERR_CONFIG;
 634         }
 635
 636         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 637
 638         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 639          * Add 1 to sector_end_addr since this sector is included in
 640          * the overall size.
 641          */
 642         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 643         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 644
 645         /* flash_base_addr is byte-aligned */
 646         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 647
 648         /* find total size of the NVM, then cut in half since the total
 649          * size represents two separate NVM banks.
 650          */
 651         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 652                                 << FLASH_SECTOR_ADDR_SHIFT);
 653         nvm->flash_bank_size /= 2;
 654         /* Adjust to word count */
 655         nvm->flash_bank_size /= sizeof(u16);
 656
 657         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 658
 659         /* Clear shadow ram */
 660         for (i = 0; i < nvm->word_size; i++) {
 661                 dev_spec->shadow_ram[i].modified = false;
 662                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 663         }
 664
 665         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 666         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 667
 668         /* Function Pointers */
 669         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 670         nvm->ops.release        = e1000_release_nvm_ich8lan;
 671         nvm->ops.read           = e1000_read_nvm_ich8lan;
 672         nvm->ops.update         = e1000_update_nvm_checksum_ich8lan;
 673         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 674         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 675         nvm->ops.write          = e1000_write_nvm_ich8lan;
 676
 677         return E1000_SUCCESS;
 678 }
 679
 680 /**
 681  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 682  *  @hw: pointer to the HW structure
 683  *
 684  *  Initialize family-specific MAC parameters and function
 685  *  pointers.
 686  **/
 687 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 688 {
 689         struct e1000_mac_info *mac = &hw->mac;
 690 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 691         u16 pci_cfg;
 692 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 693
 694         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 695
 696         /* Set media type function pointer */
 697         hw->phy.media_type = e1000_media_type_copper;
 698
 699         /* Set mta register count */
 700         mac->mta_reg_count = 32;
 701         /* Set rar entry count */
 702         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 703         if (mac->type == e1000_ich8lan)
 704                 mac->rar_entry_count--;
 705         /* Set if part includes ASF firmware */
 706         mac->asf_firmware_present = true;
 707         /* FWSM register */
 708         mac->has_fwsm = true;
 709         /* ARC subsystem not supported */
 710         mac->arc_subsystem_valid = false;
 711         /* Adaptive IFS supported */
 712         mac->adaptive_ifs = true;
 713
 714         /* Function pointers */
 715
 716         /* bus type/speed/width */
 717         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 718         /* function id */
 719         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 720         /* reset */
 721         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 722         /* hw initialization */
 723         mac->ops.init_hw = e1000_init_hw_ich8lan;
 724         /* link setup */
 725         mac->ops.setup_link = e1000_setup_link_ich8lan;
 726         /* physical interface setup */
 727         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 728         /* check for link */
 729         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 730         /* link info */
 731         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 732         /* multicast address update */
 733         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 734         /* clear hardware counters */
 735         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 736
 737         /* LED and other operations */
 738         switch (mac->type) {
 739         case e1000_ich8lan:
 740         case e1000_ich9lan:
 741         case e1000_ich10lan:
 742                 /* check management mode */
 743                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 744                 /* ID LED init */
 745                 mac->ops.id_led_init = e1000_id_led_init_generic;
 746                 /* blink LED */
 747                 mac->ops.blink_led = e1000_blink_led_generic;
 748                 /* setup LED */
 749                 mac->ops.setup_led = e1000_setup_led_generic;
 750                 /* cleanup LED */
 751                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 752                 /* turn on/off LED */
 753                 mac->ops.led_on = e1000_led_on_ich8lan;
 754                 mac->ops.led_off = e1000_led_off_ich8lan;
 755                 break;
 756         case e1000_pch2lan:
 757                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 758                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 759                 /* fall-through */
 760         case e1000_pch_lpt:
 761 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 762                 /* multicast address update for pch2 */
 763                 mac->ops.update_mc_addr_list =
 764                         e1000_update_mc_addr_list_pch2lan;
 765                 /* fall-through */
 766 #endif
 767         case e1000_pchlan:
 768 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 769                 /* save PCH revision_id */
 770                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 771                 hw->revision_id = (u8)(pci_cfg &= 0x000F);
 772 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 773                 /* check management mode */
 774                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 775                 /* ID LED init */
 776                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 777                 /* setup LED */
 778                 mac->ops.setup_led = e1000_setup_led_pchlan;
 779                 /* cleanup LED */
 780                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 781                 /* turn on/off LED */
 782                 mac->ops.led_on = e1000_led_on_pchlan;
 783                 mac->ops.led_off = e1000_led_off_pchlan;
 784                 break;
 785         default:
 786                 break;
 787         }
 788
 789         if (mac->type == e1000_pch_lpt) {
 790                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 791                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 792                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 793         }
 794
 795         /* Enable PCS Lock-loss workaround for ICH8 */
 796         if (mac->type == e1000_ich8lan)
 797                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 798
 799         return E1000_SUCCESS;
 800 }
 801
 802 /**
 803  *  __e1000_access_emi_reg_locked - Read/write EMI register
 804  *  @hw: pointer to the HW structure
 805  *  @addr: EMI address to program
 806  *  @data: pointer to value to read/write from/to the EMI address
 807  *  @read: boolean flag to indicate read or write
 808  *
 809  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 810  **/
 811 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 812                                          u16 *data, bool read)
 813 {
 814         s32 ret_val;
 815
 816         DEBUGFUNC("__e1000_access_emi_reg_locked");
 817
 818         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 819         if (ret_val)
 820                 return ret_val;
 821
 822         if (read)
 823                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 824                                                       data);
 825         else
 826                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 827                                                        *data);
 828
 829         return ret_val;
 830 }
 831
 832 /**
 833  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 834  *  @hw: pointer to the HW structure
 835  *  @addr: EMI address to program
 836  *  @data: value to be read from the EMI address
 837  *
 838  *  Assumes the SW/FW/HW Semaphore is already acquired.
 839  **/
 840 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 841 {
 842         DEBUGFUNC("e1000_read_emi_reg_locked");
 843
 844         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 845 }
 846
 847 /**
 848  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 849  *  @hw: pointer to the HW structure
 850  *  @addr: EMI address to program
 851  *  @data: value to be written to the EMI address
 852  *
 853  *  Assumes the SW/FW/HW Semaphore is already acquired.
 854  **/
 855 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 856 {
 857         DEBUGFUNC("e1000_read_emi_reg_locked");
 858
 859         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 860 }
 861
 862 /**
 863  *  e1000_set_eee_pchlan - Enable/disable EEE support
 864  *  @hw: pointer to the HW structure
 865  *
 866  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 867  *  the link and the EEE capabilities of the link partner.  The LPI Control
 868  *  register bits will remain set only if/when link is up.
 869  *
 870  *  EEE LPI must not be asserted earlier than one second after link is up.
 871  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 872  *  can be link issues with some switches.  Other devices can have EEE LPI
 873  *  enabled immediately upon link up since they have a timer in hardware which
 874  *  prevents LPI from being asserted too early.
 875  **/
 876 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 877 {
 878         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 879         s32 ret_val;
 880         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 881
 882         DEBUGFUNC("e1000_set_eee_pchlan");
 883
 884         switch (hw->phy.type) {
 885         case e1000_phy_82579:
 886                 lpa = I82579_EEE_LP_ABILITY;
 887                 pcs_status = I82579_EEE_PCS_STATUS;
 888                 adv_addr = I82579_EEE_ADVERTISEMENT;
 889                 break;
 890         case e1000_phy_i217:
 891                 lpa = I217_EEE_LP_ABILITY;
 892                 pcs_status = I217_EEE_PCS_STATUS;
 893                 adv_addr = I217_EEE_ADVERTISEMENT;
 894                 break;
 895         default:
 896                 return E1000_SUCCESS;
 897         }
 898
 899         ret_val = hw->phy.ops.acquire(hw);
 900         if (ret_val)
 901                 return ret_val;
 902
 903         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 904         if (ret_val)
 905                 goto release;
 906
 907         /* Clear bits that enable EEE in various speeds */
 908         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 909
 910         /* Enable EEE if not disabled by user */
 911         if (!dev_spec->eee_disable) {
 912                 /* Save off link partner's EEE ability */
 913                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 914                                                     &dev_spec->eee_lp_ability);
 915                 if (ret_val)
 916                         goto release;
 917
 918                 /* Read EEE advertisement */
 919                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 920                 if (ret_val)
 921                         goto release;
 922
 923                 /* Enable EEE only for speeds in which the link partner is
 924                  * EEE capable and for which we advertise EEE.
 925                  */
 926                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 927                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 928
 929                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 930                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 931                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 932                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 933                         else
 934                                 /* EEE is not supported in 100Half, so ignore
 935                                  * partner's EEE in 100 ability if full-duplex
 936                                  * is not advertised.
 937                                  */
 938                                 dev_spec->eee_lp_ability &=
 939                                     ~I82579_EEE_100_SUPPORTED;
 940                 }
 941         }
 942
 943         if (hw->phy.type == e1000_phy_82579) {
 944                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 945                                                     &data);
 946                 if (ret_val)
 947                         goto release;
 948
 949                 data &= ~I82579_LPI_100_PLL_SHUT;
 950                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 951                                                      data);
 952         }
 953
 954         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 955         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 956         if (ret_val)
 957                 goto release;
 958
 959         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 960 release:
 961         hw->phy.ops.release(hw);
 962
 963         return ret_val;
 964 }
 965
 966 /**
 967  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 968  *  @hw:   pointer to the HW structure
 969  *  @link: link up bool flag
 970  *
 971  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 972  *  preventing further DMA write requests.  Workaround the issue by disabling
 973  *  the de-assertion of the clock request when in 1Gpbs mode.
 974  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 975  *  speeds in order to avoid Tx hangs.
 976  **/
 977 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 978 {
 979         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
 980         u32 status = E1000_READ_REG(hw, E1000_STATUS);
 981         s32 ret_val = E1000_SUCCESS;
 982         u16 reg;
 983
 984         if (link && (status & E1000_STATUS_SPEED_1000)) {
 985                 ret_val = hw->phy.ops.acquire(hw);
 986                 if (ret_val)
 987                         return ret_val;
 988
 989                 ret_val =
 990                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 991                                                &reg);
 992                 if (ret_val)
 993                         goto release;
 994
 995                 ret_val =
 996                     e1000_write_kmrn_reg_locked(hw,
 997                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 998                                                 reg &
 999                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1000                 if (ret_val)
1001                         goto release;
1002
1003                 usec_delay(10);
1004
1005                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1006                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1007
1008                 ret_val =
1009                     e1000_write_kmrn_reg_locked(hw,
1010                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1011                                                 reg);
1012 release:
1013                 hw->phy.ops.release(hw);
1014         } else {
1015                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1016                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1017
1018                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1019                               (status & E1000_STATUS_FD)))
1020                         goto update_fextnvm6;
1021
1022                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1023                 if (ret_val)
1024                         return ret_val;
1025
1026                 /* Clear link status transmit timeout */
1027                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1028
1029                 if (status & E1000_STATUS_SPEED_100) {
1030                         /* Set inband Tx timeout to 5x10us for 100Half */
1031                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1032
1033                         /* Do not extend the K1 entry latency for 100Half */
1034                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1035                 } else {
1036                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1037                         reg |= 50 <<
1038                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1039
1040                         /* Extend the K1 entry latency for 10 Mbps */
1041                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1042                 }
1043
1044                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1045                 if (ret_val)
1046                         return ret_val;
1047
1048 update_fextnvm6:
1049                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1050         }
1051
1052         return ret_val;
1053 }
1054
1055 #ifdef ULP_SUPPORT
1056 /**
1057  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1058  *  @hw: pointer to the HW structure
1059  *  @to_sx: boolean indicating a system power state transition to Sx
1060  *
1061  *  When link is down, configure ULP mode to significantly reduce the power
1062  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1063  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1064  *  system, configure the ULP mode by software.
1065  */
1066 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1067 {
1068         u32 mac_reg;
1069         s32 ret_val = E1000_SUCCESS;
1070         u16 phy_reg;
1071
1072         if ((hw->mac.type < e1000_pch_lpt) ||
1073             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1074             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1075             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1076             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1077             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1078                 return 0;
1079
1080         if (!to_sx) {
1081                 int i = 0;
1082                 /* Poll up to 5 seconds for Cable Disconnected indication */
1083                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1084                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1085                         /* Bail if link is re-acquired */
1086                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1087                                 return -E1000_ERR_PHY;
1088                         if (i++ == 100)
1089                                 break;
1090
1091                         msec_delay(50);
1092                 }
1093                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1094                           (E1000_READ_REG(hw, E1000_FEXT) &
1095                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1096                           i * 50);
1097                 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1098                     E1000_FEXT_PHY_CABLE_DISCONNECTED))
1099                         return 0;
1100         }
1101
1102         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103                 /* Request ME configure ULP mode in the PHY */
1104                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1105                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1107
1108                 goto out;
1109         }
1110
1111         ret_val = hw->phy.ops.acquire(hw);
1112         if (ret_val)
1113                 goto out;
1114
1115         /* During S0 Idle keep the phy in PCI-E mode */
1116         if (hw->dev_spec.ich8lan.smbus_disable)
1117                 goto skip_smbus;
1118
1119         /* Force SMBus mode in PHY */
1120         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1121         if (ret_val)
1122                 goto release;
1123         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1124         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1125
1126         /* Force SMBus mode in MAC */
1127         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1128         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1129         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1130
1131 skip_smbus:
1132         if (!to_sx) {
1133                 /* Change the 'Link Status Change' interrupt to trigger
1134                  * on 'Cable Status Change'
1135                  */
1136                 ret_val = e1000_read_kmrn_reg_locked(hw,
1137                                                      E1000_KMRNCTRLSTA_OP_MODES,
1138                                                      &phy_reg);
1139                 if (ret_val)
1140                         goto release;
1141                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1142                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1143                                             phy_reg);
1144         }
1145
1146         /* Set Inband ULP Exit, Reset to SMBus mode and
1147          * Disable SMBus Release on PERST# in PHY
1148          */
1149         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1150         if (ret_val)
1151                 goto release;
1152         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1153                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1154         if (to_sx) {
1155                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1156                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1157                 else
1158                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1159
1160                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1161                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1162         } else {
1163                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1164                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1165                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1166         }
1167         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1168
1169         /* Set Disable SMBus Release on PERST# in MAC */
1170         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1171         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1172         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1173
1174         /* Commit ULP changes in PHY by starting auto ULP configuration */
1175         phy_reg |= I218_ULP_CONFIG1_START;
1176         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1177
1178         if (!to_sx) {
1179                 /* Disable Tx so that the MAC doesn't send any (buffered)
1180                  * packets to the PHY.
1181                  */
1182                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1183                 mac_reg &= ~E1000_TCTL_EN;
1184                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1185         }
1186
1187 release:
1188         hw->phy.ops.release(hw);
1189 out:
1190         if (ret_val)
1191                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1192         else
1193                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1194
1195         return ret_val;
1196 }
1197
1198 /**
1199  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1200  *  @hw: pointer to the HW structure
1201  *  @force: boolean indicating whether or not to force disabling ULP
1202  *
1203  *  Un-configure ULP mode when link is up, the system is transitioned from
1204  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1205  *  system, poll for an indication from ME that ULP has been un-configured.
1206  *  If not on an ME enabled system, un-configure the ULP mode by software.
1207  *
1208  *  During nominal operation, this function is called when link is acquired
1209  *  to disable ULP mode (force=false); otherwise, for example when unloading
1210  *  the driver or during Sx->S0 transitions, this is called with force=true
1211  *  to forcibly disable ULP.
1212
1213  *  When the cable is plugged in while the device is in D0, a Cable Status
1214  *  Change interrupt is generated which causes this function to be called
1215  *  to partially disable ULP mode and restart autonegotiation.  This function
1216  *  is then called again due to the resulting Link Status Change interrupt
1217  *  to finish cleaning up after the ULP flow.
1218  */
1219 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1220 {
1221         s32 ret_val = E1000_SUCCESS;
1222         u32 mac_reg;
1223         u16 phy_reg;
1224         int i = 0;
1225
1226         if ((hw->mac.type < e1000_pch_lpt) ||
1227             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1228             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1229             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1230             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1231             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1232                 return 0;
1233
1234         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1235                 if (force) {
1236                         /* Request ME un-configure ULP mode in the PHY */
1237                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1238                         mac_reg &= ~E1000_H2ME_ULP;
1239                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1240                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1241                 }
1242
1243                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1244                 while (E1000_READ_REG(hw, E1000_FWSM) &
1245                        E1000_FWSM_ULP_CFG_DONE) {
1246                         if (i++ == 30) {
1247                                 ret_val = -E1000_ERR_PHY;
1248                                 goto out;
1249                         }
1250
1251                         msec_delay(10);
1252                 }
1253                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1254
1255                 if (force) {
1256                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1257                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1258                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1259                 } else {
1260                         /* Clear H2ME.ULP after ME ULP configuration */
1261                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1262                         mac_reg &= ~E1000_H2ME_ULP;
1263                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1264
1265                         /* Restore link speed advertisements and restart
1266                          * Auto-negotiation
1267                          */
1268                         if (hw->mac.autoneg) {
1269                                 ret_val = e1000_phy_setup_autoneg(hw);
1270                                 if (ret_val)
1271                                         goto out;
1272                         } else {
1273                                 ret_val = e1000_setup_copper_link_generic(hw);
1274                                 if (ret_val)
1275                                         goto out;
1276                         }
1277                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1278                 }
1279
1280                 goto out;
1281         }
1282
1283         ret_val = hw->phy.ops.acquire(hw);
1284         if (ret_val)
1285                 goto out;
1286
1287         /* Revert the change to the 'Link Status Change'
1288          * interrupt to trigger on 'Cable Status Change'
1289          */
1290         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1291                                              &phy_reg);
1292         if (ret_val)
1293                 goto release;
1294         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1295         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1296
1297         if (force)
1298                 /* Toggle LANPHYPC Value bit */
1299                 e1000_toggle_lanphypc_pch_lpt(hw);
1300
1301         /* Unforce SMBus mode in PHY */
1302         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1303         if (ret_val) {
1304                 /* The MAC might be in PCIe mode, so temporarily force to
1305                  * SMBus mode in order to access the PHY.
1306                  */
1307                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1308                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1309                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1310
1311                 msec_delay(50);
1312
1313                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1314                                                        &phy_reg);
1315                 if (ret_val)
1316                         goto release;
1317         }
1318         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1319         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1320
1321         /* Unforce SMBus mode in MAC */
1322         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1323         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1324         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1325
1326         /* When ULP mode was previously entered, K1 was disabled by the
1327          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1328          */
1329         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1330         if (ret_val)
1331                 goto release;
1332         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1333         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1334
1335         /* Clear ULP enabled configuration */
1336         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1337         if (ret_val)
1338                 goto release;
1339         /* CSC interrupt received due to ULP Indication */
1340         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1341                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1342                              I218_ULP_CONFIG1_STICKY_ULP |
1343                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1344                              I218_ULP_CONFIG1_WOL_HOST |
1345                              I218_ULP_CONFIG1_INBAND_EXIT |
1346                              I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1347                              I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1348                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1349                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1350
1351                 /* Commit ULP changes by starting auto ULP configuration */
1352                 phy_reg |= I218_ULP_CONFIG1_START;
1353                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1354
1355                 /* Clear Disable SMBus Release on PERST# in MAC */
1356                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1357                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1358                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1359
1360                 if (!force) {
1361                         hw->phy.ops.release(hw);
1362
1363                         if (hw->mac.autoneg)
1364                                 e1000_phy_setup_autoneg(hw);
1365                         else
1366                                 e1000_setup_copper_link_generic(hw);
1367
1368                         e1000_sw_lcd_config_ich8lan(hw);
1369
1370                         e1000_oem_bits_config_ich8lan(hw, true);
1371
1372                         /* Set ULP state to unknown and return non-zero to
1373                          * indicate no link (yet) and re-enter on the next LSC
1374                          * to finish disabling ULP flow.
1375                          */
1376                         hw->dev_spec.ich8lan.ulp_state =
1377                             e1000_ulp_state_unknown;
1378
1379                         return 1;
1380                 }
1381         }
1382
1383         /* Re-enable Tx */
1384         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1385         mac_reg |= E1000_TCTL_EN;
1386         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1387
1388 release:
1389         hw->phy.ops.release(hw);
1390         if (force) {
1391                 hw->phy.ops.reset(hw);
1392                 msec_delay(50);
1393         }
1394 out:
1395         if (ret_val)
1396                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1397         else
1398                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1399
1400         return ret_val;
1401 }
1402
1403 #endif /* ULP_SUPPORT */
1404 /**
1405  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1406  *  @hw: pointer to the HW structure
1407  *
1408  *  Checks to see of the link status of the hardware has changed.  If a
1409  *  change in link status has been detected, then we read the PHY registers
1410  *  to get the current speed/duplex if link exists.
1411  **/
1412 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1413 {
1414         struct e1000_mac_info *mac = &hw->mac;
1415         s32 ret_val, tipg_reg = 0;
1416         u16 emi_addr, emi_val = 0;
1417         bool link = false;
1418         u16 phy_reg;
1419
1420         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1421
1422         /* We only want to go out to the PHY registers to see if Auto-Neg
1423          * has completed and/or if our link status has changed.  The
1424          * get_link_status flag is set upon receiving a Link Status
1425          * Change or Rx Sequence Error interrupt.
1426          */
1427         if (!mac->get_link_status)
1428                 return E1000_SUCCESS;
1429
1430         if ((hw->mac.type < e1000_pch_lpt) ||
1431             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1432             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1433                 /* First we want to see if the MII Status Register reports
1434                  * link.  If so, then we want to get the current speed/duplex
1435                  * of the PHY.
1436                  */
1437                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1438                 if (ret_val)
1439                         return ret_val;
1440         } else {
1441                 /* Check the MAC's STATUS register to determine link state
1442                  * since the PHY could be inaccessible while in ULP mode.
1443                  */
1444                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1445                 if (link)
1446                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1447                 else
1448                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1449                 if (ret_val)
1450                         return ret_val;
1451         }
1452
1453         if (hw->mac.type == e1000_pchlan) {
1454                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1455                 if (ret_val)
1456                         return ret_val;
1457         }
1458
1459         /* When connected at 10Mbps half-duplex, some parts are excessively
1460          * aggressive resulting in many collisions. To avoid this, increase
1461          * the IPG and reduce Rx latency in the PHY.
1462          */
1463         if (((hw->mac.type == e1000_pch2lan) ||
1464              (hw->mac.type == e1000_pch_lpt)) && link) {
1465                 u16 speed, duplex;
1466
1467                 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1468                 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1469                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1470
1471                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1472                         tipg_reg |= 0xFF;
1473                         /* Reduce Rx latency in analog PHY */
1474                         emi_val = 0;
1475                 } else {
1476                         /* Roll back the default values */
1477                         tipg_reg |= 0x08;
1478                         emi_val = 1;
1479                 }
1480
1481                 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1482
1483                 ret_val = hw->phy.ops.acquire(hw);
1484                 if (ret_val)
1485                         return ret_val;
1486
1487                 if (hw->mac.type == e1000_pch2lan)
1488                         emi_addr = I82579_RX_CONFIG;
1489                 else
1490                         emi_addr = I217_RX_CONFIG;
1491                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1492
1493
1494                 if (hw->mac.type >= e1000_pch_lpt) {
1495                         u16 phy_reg;
1496
1497                         hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1498                                                     &phy_reg);
1499                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1500                         if (speed == SPEED_100 || speed == SPEED_10)
1501                                 phy_reg |= 0x3E8;
1502                         else
1503                                 phy_reg |= 0xFA;
1504                         hw->phy.ops.write_reg_locked(hw,
1505                                                      I217_PLL_CLOCK_GATE_REG,
1506                                                      phy_reg);
1507                  }
1508                 hw->phy.ops.release(hw);
1509
1510                 if (ret_val)
1511                         return ret_val;
1512         }
1513
1514         /* I217 Packet Loss issue:
1515          * ensure that FEXTNVM4 Beacon Duration is set correctly
1516          * on power up.
1517          * Set the Beacon Duration for I217 to 8 usec
1518          */
1519         if (hw->mac.type == e1000_pch_lpt) {
1520                 u32 mac_reg;
1521
1522                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1523                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1524                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1525                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1526         }
1527
1528         /* Work-around I218 hang issue */
1529         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1530             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1531             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1532             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1533                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1534                 if (ret_val)
1535                         return ret_val;
1536         }
1537         /* Clear link partner's EEE ability */
1538         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1539
1540         /* Configure K0s minimum time */
1541         if (hw->mac.type == e1000_pch_lpt) {
1542                 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1543         }
1544
1545         if (!link)
1546                 return E1000_SUCCESS; /* No link detected */
1547
1548         mac->get_link_status = false;
1549
1550         switch (hw->mac.type) {
1551         case e1000_pch2lan:
1552                 ret_val = e1000_k1_workaround_lv(hw);
1553                 if (ret_val)
1554                         return ret_val;
1555                 /* fall-thru */
1556         case e1000_pchlan:
1557                 if (hw->phy.type == e1000_phy_82578) {
1558                         ret_val = e1000_link_stall_workaround_hv(hw);
1559                         if (ret_val)
1560                                 return ret_val;
1561                 }
1562
1563                 /* Workaround for PCHx parts in half-duplex:
1564                  * Set the number of preambles removed from the packet
1565                  * when it is passed from the PHY to the MAC to prevent
1566                  * the MAC from misinterpreting the packet type.
1567                  */
1568                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1569                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1570
1571                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1572                     E1000_STATUS_FD)
1573                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1574
1575                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1576                 break;
1577         default:
1578                 break;
1579         }
1580
1581         /* Check if there was DownShift, must be checked
1582          * immediately after link-up
1583          */
1584         e1000_check_downshift_generic(hw);
1585
1586         /* Enable/Disable EEE after link up */
1587         if (hw->phy.type > e1000_phy_82579) {
1588                 ret_val = e1000_set_eee_pchlan(hw);
1589                 if (ret_val)
1590                         return ret_val;
1591         }
1592
1593         /* If we are forcing speed/duplex, then we simply return since
1594          * we have already determined whether we have link or not.
1595          */
1596         if (!mac->autoneg)
1597                 return -E1000_ERR_CONFIG;
1598
1599         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1600          * of MAC speed/duplex configuration.  So we only need to
1601          * configure Collision Distance in the MAC.
1602          */
1603         mac->ops.config_collision_dist(hw);
1604
1605         /* Configure Flow Control now that Auto-Neg has completed.
1606          * First, we need to restore the desired flow control
1607          * settings because we may have had to re-autoneg with a
1608          * different link partner.
1609          */
1610         ret_val = e1000_config_fc_after_link_up_generic(hw);
1611         if (ret_val)
1612                 DEBUGOUT("Error configuring flow control\n");
1613
1614         return ret_val;
1615 }
1616
1617 /**
1618  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1619  *  @hw: pointer to the HW structure
1620  *
1621  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1622  **/
1623 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1624 {
1625         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1626
1627         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1628         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1629         switch (hw->mac.type) {
1630         case e1000_ich8lan:
1631         case e1000_ich9lan:
1632         case e1000_ich10lan:
1633                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1634                 break;
1635         case e1000_pchlan:
1636         case e1000_pch2lan:
1637         case e1000_pch_lpt:
1638                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1639                 break;
1640         default:
1641                 break;
1642         }
1643 }
1644
1645 /**
1646  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1647  *  @hw: pointer to the HW structure
1648  *
1649  *  Acquires the mutex for performing NVM operations.
1650  **/
1651 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1652 {
1653         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1654
1655         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1656
1657         return E1000_SUCCESS;
1658 }
1659
1660 /**
1661  *  e1000_release_nvm_ich8lan - Release NVM mutex
1662  *  @hw: pointer to the HW structure
1663  *
1664  *  Releases the mutex used while performing NVM operations.
1665  **/
1666 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1667 {
1668         DEBUGFUNC("e1000_release_nvm_ich8lan");
1669
1670         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1671
1672         return;
1673 }
1674
1675 /**
1676  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1677  *  @hw: pointer to the HW structure
1678  *
1679  *  Acquires the software control flag for performing PHY and select
1680  *  MAC CSR accesses.
1681  **/
1682 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1683 {
1684         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1685         s32 ret_val = E1000_SUCCESS;
1686
1687         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1688
1689         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1690
1691         while (timeout) {
1692                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1693                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1694                         break;
1695
1696                 msec_delay_irq(1);
1697                 timeout--;
1698         }
1699
1700         if (!timeout) {
1701                 DEBUGOUT("SW has already locked the resource.\n");
1702                 ret_val = -E1000_ERR_CONFIG;
1703                 goto out;
1704         }
1705
1706         timeout = SW_FLAG_TIMEOUT;
1707
1708         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1709         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1710
1711         while (timeout) {
1712                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1713                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1714                         break;
1715
1716                 msec_delay_irq(1);
1717                 timeout--;
1718         }
1719
1720         if (!timeout) {
1721                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1722                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1723                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1724                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1725                 ret_val = -E1000_ERR_CONFIG;
1726                 goto out;
1727         }
1728
1729 out:
1730         if (ret_val)
1731                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1732
1733         return ret_val;
1734 }
1735
1736 /**
1737  *  e1000_release_swflag_ich8lan - Release software control flag
1738  *  @hw: pointer to the HW structure
1739  *
1740  *  Releases the software control flag for performing PHY and select
1741  *  MAC CSR accesses.
1742  **/
1743 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1744 {
1745         u32 extcnf_ctrl;
1746
1747         DEBUGFUNC("e1000_release_swflag_ich8lan");
1748
1749         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1750
1751         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1752                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1753                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1754         } else {
1755                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1756         }
1757
1758         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1759
1760         return;
1761 }
1762
1763 /**
1764  *  e1000_check_mng_mode_ich8lan - Checks management mode
1765  *  @hw: pointer to the HW structure
1766  *
1767  *  This checks if the adapter has any manageability enabled.
1768  *  This is a function pointer entry point only called by read/write
1769  *  routines for the PHY and NVM parts.
1770  **/
1771 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1772 {
1773         u32 fwsm;
1774
1775         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1776
1777         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1778
1779         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1780                ((fwsm & E1000_FWSM_MODE_MASK) ==
1781                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1782 }
1783
1784 /**
1785  *  e1000_check_mng_mode_pchlan - Checks management mode
1786  *  @hw: pointer to the HW structure
1787  *
1788  *  This checks if the adapter has iAMT enabled.
1789  *  This is a function pointer entry point only called by read/write
1790  *  routines for the PHY and NVM parts.
1791  **/
1792 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1793 {
1794         u32 fwsm;
1795
1796         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1797
1798         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1799
1800         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1801                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1802 }
1803
1804 /**
1805  *  e1000_rar_set_pch2lan - Set receive address register
1806  *  @hw: pointer to the HW structure
1807  *  @addr: pointer to the receive address
1808  *  @index: receive address array register
1809  *
1810  *  Sets the receive address array register at index to the address passed
1811  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1812  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1813  *  Use SHRA[0-3] in place of those reserved for ME.
1814  **/
1815 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1816 {
1817         u32 rar_low, rar_high;
1818
1819         DEBUGFUNC("e1000_rar_set_pch2lan");
1820
1821         /* HW expects these in little endian so we reverse the byte order
1822          * from network order (big endian) to little endian
1823          */
1824         rar_low = ((u32) addr[0] |
1825                    ((u32) addr[1] << 8) |
1826                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1827
1828         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1829
1830         /* If MAC address zero, no need to set the AV bit */
1831         if (rar_low || rar_high)
1832                 rar_high |= E1000_RAH_AV;
1833
1834         if (index == 0) {
1835                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1836                 E1000_WRITE_FLUSH(hw);
1837                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1838                 E1000_WRITE_FLUSH(hw);
1839                 return E1000_SUCCESS;
1840         }
1841
1842         /* RAR[1-6] are owned by manageability.  Skip those and program the
1843          * next address into the SHRA register array.
1844          */
1845         if (index < (u32) (hw->mac.rar_entry_count)) {
1846                 s32 ret_val;
1847
1848                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1849                 if (ret_val)
1850                         goto out;
1851
1852                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1853                 E1000_WRITE_FLUSH(hw);
1854                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1855                 E1000_WRITE_FLUSH(hw);
1856
1857                 e1000_release_swflag_ich8lan(hw);
1858
1859                 /* verify the register updates */
1860                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1861                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1862                         return E1000_SUCCESS;
1863
1864                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1865                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1866         }
1867
1868 out:
1869         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1870         return -E1000_ERR_CONFIG;
1871 }
1872
1873 /**
1874  *  e1000_rar_set_pch_lpt - Set receive address registers
1875  *  @hw: pointer to the HW structure
1876  *  @addr: pointer to the receive address
1877  *  @index: receive address array register
1878  *
1879  *  Sets the receive address register array at index to the address passed
1880  *  in by addr. For LPT, RAR[0] is the base address register that is to
1881  *  contain the MAC address. SHRA[0-10] are the shared receive address
1882  *  registers that are shared between the Host and manageability engine (ME).
1883  **/
1884 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1885 {
1886         u32 rar_low, rar_high;
1887         u32 wlock_mac;
1888
1889         DEBUGFUNC("e1000_rar_set_pch_lpt");
1890
1891         /* HW expects these in little endian so we reverse the byte order
1892          * from network order (big endian) to little endian
1893          */
1894         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1895                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1896
1897         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1898
1899         /* If MAC address zero, no need to set the AV bit */
1900         if (rar_low || rar_high)
1901                 rar_high |= E1000_RAH_AV;
1902
1903         if (index == 0) {
1904                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1905                 E1000_WRITE_FLUSH(hw);
1906                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1907                 E1000_WRITE_FLUSH(hw);
1908                 return E1000_SUCCESS;
1909         }
1910
1911         /* The manageability engine (ME) can lock certain SHRAR registers that
1912          * it is using - those registers are unavailable for use.
1913          */
1914         if (index < hw->mac.rar_entry_count) {
1915                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1916                             E1000_FWSM_WLOCK_MAC_MASK;
1917                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1918
1919                 /* Check if all SHRAR registers are locked */
1920                 if (wlock_mac == 1)
1921                         goto out;
1922
1923                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1924                         s32 ret_val;
1925
1926                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1927
1928                         if (ret_val)
1929                                 goto out;
1930
1931                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1932                                         rar_low);
1933                         E1000_WRITE_FLUSH(hw);
1934                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1935                                         rar_high);
1936                         E1000_WRITE_FLUSH(hw);
1937
1938                         e1000_release_swflag_ich8lan(hw);
1939
1940                         /* verify the register updates */
1941                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1942                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1943                                 return E1000_SUCCESS;
1944                 }
1945         }
1946
1947 out:
1948         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1949         return -E1000_ERR_CONFIG;
1950 }
1951
1952 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1953 /**
1954  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1955  *  @hw: pointer to the HW structure
1956  *  @mc_addr_list: array of multicast addresses to program
1957  *  @mc_addr_count: number of multicast addresses to program
1958  *
1959  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1960  *  The caller must have a packed mc_addr_list of multicast addresses.
1961  **/
1962 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1963                                               u8 *mc_addr_list,
1964                                               u32 mc_addr_count)
1965 {
1966         u16 phy_reg = 0;
1967         int i;
1968         s32 ret_val;
1969
1970         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1971
1972         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1973
1974         ret_val = hw->phy.ops.acquire(hw);
1975         if (ret_val)
1976                 return;
1977
1978         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1979         if (ret_val)
1980                 goto release;
1981
1982         for (i = 0; i < hw->mac.mta_reg_count; i++) {
1983                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1984                                            (u16)(hw->mac.mta_shadow[i] &
1985                                                  0xFFFF));
1986                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1987                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
1988                                                  0xFFFF));
1989         }
1990
1991         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1992
1993 release:
1994         hw->phy.ops.release(hw);
1995 }
1996
1997 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1998 /**
1999  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2000  *  @hw: pointer to the HW structure
2001  *
2002  *  Checks if firmware is blocking the reset of the PHY.
2003  *  This is a function pointer entry point only called by
2004  *  reset routines.
2005  **/
2006 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2007 {
2008         u32 fwsm;
2009         bool blocked = false;
2010         int i = 0;
2011
2012         DEBUGFUNC("e1000_check_reset_block_ich8lan");
2013
2014         do {
2015                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2016                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2017                         blocked = true;
2018                         msec_delay(10);
2019                         continue;
2020                 }
2021                 blocked = false;
2022         } while (blocked && (i++ < 30));
2023         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2024 }
2025
2026 /**
2027  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2028  *  @hw: pointer to the HW structure
2029  *
2030  *  Assumes semaphore already acquired.
2031  *
2032  **/
2033 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2034 {
2035         u16 phy_data;
2036         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2037         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2038                 E1000_STRAP_SMT_FREQ_SHIFT;
2039         s32 ret_val;
2040
2041         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2042
2043         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2044         if (ret_val)
2045                 return ret_val;
2046
2047         phy_data &= ~HV_SMB_ADDR_MASK;
2048         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2049         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2050
2051         if (hw->phy.type == e1000_phy_i217) {
2052                 /* Restore SMBus frequency */
2053                 if (freq--) {
2054                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2055                         phy_data |= (freq & (1 << 0)) <<
2056                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2057                         phy_data |= (freq & (1 << 1)) <<
2058                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2059                 } else {
2060                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2061                 }
2062         }
2063
2064         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2065 }
2066
2067 /**
2068  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2069  *  @hw:   pointer to the HW structure
2070  *
2071  *  SW should configure the LCD from the NVM extended configuration region
2072  *  as a workaround for certain parts.
2073  **/
2074 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2075 {
2076         struct e1000_phy_info *phy = &hw->phy;
2077         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2078         s32 ret_val = E1000_SUCCESS;
2079         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2080
2081         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2082
2083         /* Initialize the PHY from the NVM on ICH platforms.  This
2084          * is needed due to an issue where the NVM configuration is
2085          * not properly autoloaded after power transitions.
2086          * Therefore, after each PHY reset, we will load the
2087          * configuration data out of the NVM manually.
2088          */
2089         switch (hw->mac.type) {
2090         case e1000_ich8lan:
2091                 if (phy->type != e1000_phy_igp_3)
2092                         return ret_val;
2093
2094                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2095                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2096                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2097                         break;
2098                 }
2099                 /* Fall-thru */
2100         case e1000_pchlan:
2101         case e1000_pch2lan:
2102         case e1000_pch_lpt:
2103                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2104                 break;
2105         default:
2106                 return ret_val;
2107         }
2108
2109         ret_val = hw->phy.ops.acquire(hw);
2110         if (ret_val)
2111                 return ret_val;
2112
2113         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2114         if (!(data & sw_cfg_mask))
2115                 goto release;
2116
2117         /* Make sure HW does not configure LCD from PHY
2118          * extended configuration before SW configuration
2119          */
2120         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2121         if ((hw->mac.type < e1000_pch2lan) &&
2122             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2123                         goto release;
2124
2125         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2126         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2127         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2128         if (!cnf_size)
2129                 goto release;
2130
2131         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2132         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2133
2134         if (((hw->mac.type == e1000_pchlan) &&
2135              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2136             (hw->mac.type > e1000_pchlan)) {
2137                 /* HW configures the SMBus address and LEDs when the
2138                  * OEM and LCD Write Enable bits are set in the NVM.
2139                  * When both NVM bits are cleared, SW will configure
2140                  * them instead.
2141                  */
2142                 ret_val = e1000_write_smbus_addr(hw);
2143                 if (ret_val)
2144                         goto release;
2145
2146                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2147                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2148                                                         (u16)data);
2149                 if (ret_val)
2150                         goto release;
2151         }
2152
2153         /* Configure LCD from extended configuration region. */
2154
2155         /* cnf_base_addr is in DWORD */
2156         word_addr = (u16)(cnf_base_addr << 1);
2157
2158         for (i = 0; i < cnf_size; i++) {
2159                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2160                                            &reg_data);
2161                 if (ret_val)
2162                         goto release;
2163
2164                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2165                                            1, &reg_addr);
2166                 if (ret_val)
2167                         goto release;
2168
2169                 /* Save off the PHY page for future writes. */
2170                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2171                         phy_page = reg_data;
2172                         continue;
2173                 }
2174
2175                 reg_addr &= PHY_REG_MASK;
2176                 reg_addr |= phy_page;
2177
2178                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2179                                                     reg_data);
2180                 if (ret_val)
2181                         goto release;
2182         }
2183
2184 release:
2185         hw->phy.ops.release(hw);
2186         return ret_val;
2187 }
2188
2189 /**
2190  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2191  *  @hw:   pointer to the HW structure
2192  *  @link: link up bool flag
2193  *
2194  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2195  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2196  *  If link is down, the function will restore the default K1 setting located
2197  *  in the NVM.
2198  **/
2199 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2200 {
2201         s32 ret_val = E1000_SUCCESS;
2202         u16 status_reg = 0;
2203         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2204
2205         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2206
2207         if (hw->mac.type != e1000_pchlan)
2208                 return E1000_SUCCESS;
2209
2210         /* Wrap the whole flow with the sw flag */
2211         ret_val = hw->phy.ops.acquire(hw);
2212         if (ret_val)
2213                 return ret_val;
2214
2215         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2216         if (link) {
2217                 if (hw->phy.type == e1000_phy_82578) {
2218                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2219                                                               &status_reg);
2220                         if (ret_val)
2221                                 goto release;
2222
2223                         status_reg &= (BM_CS_STATUS_LINK_UP |
2224                                        BM_CS_STATUS_RESOLVED |
2225                                        BM_CS_STATUS_SPEED_MASK);
2226
2227                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2228                                            BM_CS_STATUS_RESOLVED |
2229                                            BM_CS_STATUS_SPEED_1000))
2230                                 k1_enable = false;
2231                 }
2232
2233                 if (hw->phy.type == e1000_phy_82577) {
2234                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2235                                                               &status_reg);
2236                         if (ret_val)
2237                                 goto release;
2238
2239                         status_reg &= (HV_M_STATUS_LINK_UP |
2240                                        HV_M_STATUS_AUTONEG_COMPLETE |
2241                                        HV_M_STATUS_SPEED_MASK);
2242
2243                         if (status_reg == (HV_M_STATUS_LINK_UP |
2244                                            HV_M_STATUS_AUTONEG_COMPLETE |
2245                                            HV_M_STATUS_SPEED_1000))
2246                                 k1_enable = false;
2247                 }
2248
2249                 /* Link stall fix for link up */
2250                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2251                                                        0x0100);
2252                 if (ret_val)
2253                         goto release;
2254
2255         } else {
2256                 /* Link stall fix for link down */
2257                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2258                                                        0x4100);
2259                 if (ret_val)
2260                         goto release;
2261         }
2262
2263         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2264
2265 release:
2266         hw->phy.ops.release(hw);
2267
2268         return ret_val;
2269 }
2270
2271 /**
2272  *  e1000_configure_k1_ich8lan - Configure K1 power state
2273  *  @hw: pointer to the HW structure
2274  *  @enable: K1 state to configure
2275  *
2276  *  Configure the K1 power state based on the provided parameter.
2277  *  Assumes semaphore already acquired.
2278  *
2279  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2280  **/
2281 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2282 {
2283         s32 ret_val;
2284         u32 ctrl_reg = 0;
2285         u32 ctrl_ext = 0;
2286         u32 reg = 0;
2287         u16 kmrn_reg = 0;
2288
2289         DEBUGFUNC("e1000_configure_k1_ich8lan");
2290
2291         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2292                                              &kmrn_reg);
2293         if (ret_val)
2294                 return ret_val;
2295
2296         if (k1_enable)
2297                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2298         else
2299                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2300
2301         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2302                                               kmrn_reg);
2303         if (ret_val)
2304                 return ret_val;
2305
2306         usec_delay(20);
2307         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2308         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2309
2310         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2311         reg |= E1000_CTRL_FRCSPD;
2312         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2313
2314         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2315         E1000_WRITE_FLUSH(hw);
2316         usec_delay(20);
2317         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2318         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2319         E1000_WRITE_FLUSH(hw);
2320         usec_delay(20);
2321
2322         return E1000_SUCCESS;
2323 }
2324
2325 /**
2326  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2327  *  @hw:       pointer to the HW structure
2328  *  @d0_state: boolean if entering d0 or d3 device state
2329  *
2330  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2331  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2332  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2333  **/
2334 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2335 {
2336         s32 ret_val = 0;
2337         u32 mac_reg;
2338         u16 oem_reg;
2339
2340         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2341
2342         if (hw->mac.type < e1000_pchlan)
2343                 return ret_val;
2344
2345         ret_val = hw->phy.ops.acquire(hw);
2346         if (ret_val)
2347                 return ret_val;
2348
2349         if (hw->mac.type == e1000_pchlan) {
2350                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2351                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2352                         goto release;
2353         }
2354
2355         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2356         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2357                 goto release;
2358
2359         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2360
2361         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2362         if (ret_val)
2363                 goto release;
2364
2365         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2366
2367         if (d0_state) {
2368                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2369                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2370
2371                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2372                         oem_reg |= HV_OEM_BITS_LPLU;
2373         } else {
2374                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2375                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2376                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2377
2378                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2379                     E1000_PHY_CTRL_NOND0A_LPLU))
2380                         oem_reg |= HV_OEM_BITS_LPLU;
2381         }
2382
2383         /* Set Restart auto-neg to activate the bits */
2384         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2385             !hw->phy.ops.check_reset_block(hw))
2386                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2387
2388         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2389
2390 release:
2391         hw->phy.ops.release(hw);
2392
2393         return ret_val;
2394 }
2395
2396
2397 /**
2398  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2399  *  @hw:   pointer to the HW structure
2400  **/
2401 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2402 {
2403         s32 ret_val;
2404         u16 data;
2405
2406         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2407
2408         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2409         if (ret_val)
2410                 return ret_val;
2411
2412         data |= HV_KMRN_MDIO_SLOW;
2413
2414         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2415
2416         return ret_val;
2417 }
2418
2419 /**
2420  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2421  *  done after every PHY reset.
2422  **/
2423 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2424 {
2425         s32 ret_val = E1000_SUCCESS;
2426         u16 phy_data;
2427
2428         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2429
2430         if (hw->mac.type != e1000_pchlan)
2431                 return E1000_SUCCESS;
2432
2433         /* Set MDIO slow mode before any other MDIO access */
2434         if (hw->phy.type == e1000_phy_82577) {
2435                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2436                 if (ret_val)
2437                         return ret_val;
2438         }
2439
2440         if (((hw->phy.type == e1000_phy_82577) &&
2441              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2442             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2443                 /* Disable generation of early preamble */
2444                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2445                 if (ret_val)
2446                         return ret_val;
2447
2448                 /* Preamble tuning for SSC */
2449                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2450                                                 0xA204);
2451                 if (ret_val)
2452                         return ret_val;
2453         }
2454
2455         if (hw->phy.type == e1000_phy_82578) {
2456                 /* Return registers to default by doing a soft reset then
2457                  * writing 0x3140 to the control register.
2458                  */
2459                 if (hw->phy.revision < 2) {
2460                         e1000_phy_sw_reset_generic(hw);
2461                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2462                                                         0x3140);
2463                 }
2464         }
2465
2466         /* Select page 0 */
2467         ret_val = hw->phy.ops.acquire(hw);
2468         if (ret_val)
2469                 return ret_val;
2470
2471         hw->phy.addr = 1;
2472         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2473         hw->phy.ops.release(hw);
2474         if (ret_val)
2475                 return ret_val;
2476
2477         /* Configure the K1 Si workaround during phy reset assuming there is
2478          * link so that it disables K1 if link is in 1Gbps.
2479          */
2480         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2481         if (ret_val)
2482                 return ret_val;
2483
2484         /* Workaround for link disconnects on a busy hub in half duplex */
2485         ret_val = hw->phy.ops.acquire(hw);
2486         if (ret_val)
2487                 return ret_val;
2488         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2489         if (ret_val)
2490                 goto release;
2491         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2492                                                phy_data & 0x00FF);
2493         if (ret_val)
2494                 goto release;
2495
2496         /* set MSE higher to enable link to stay up when noise is high */
2497         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2498 release:
2499         hw->phy.ops.release(hw);
2500
2501         return ret_val;
2502 }
2503
2504 /**
2505  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2506  *  @hw:   pointer to the HW structure
2507  **/
2508 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2509 {
2510         u32 mac_reg;
2511         u16 i, phy_reg = 0;
2512         s32 ret_val;
2513
2514         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2515
2516         ret_val = hw->phy.ops.acquire(hw);
2517         if (ret_val)
2518                 return;
2519         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2520         if (ret_val)
2521                 goto release;
2522
2523         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2524         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2525                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2526                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2527                                            (u16)(mac_reg & 0xFFFF));
2528                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2529                                            (u16)((mac_reg >> 16) & 0xFFFF));
2530
2531                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2532                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2533                                            (u16)(mac_reg & 0xFFFF));
2534                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2535                                            (u16)((mac_reg & E1000_RAH_AV)
2536                                                  >> 16));
2537         }
2538
2539         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2540
2541 release:
2542         hw->phy.ops.release(hw);
2543 }
2544
2545 #ifndef CRC32_OS_SUPPORT
2546 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2547 {
2548         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2549         u32 i, j, mask, crc;
2550
2551         DEBUGFUNC("e1000_calc_rx_da_crc");
2552
2553         crc = 0xffffffff;
2554         for (i = 0; i < 6; i++) {
2555                 crc = crc ^ mac[i];
2556                 for (j = 8; j > 0; j--) {
2557                         mask = (crc & 1) * (-1);
2558                         crc = (crc >> 1) ^ (poly & mask);
2559                 }
2560         }
2561         return ~crc;
2562 }
2563
2564 #endif /* CRC32_OS_SUPPORT */
2565 /**
2566  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2567  *  with 82579 PHY
2568  *  @hw: pointer to the HW structure
2569  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2570  **/
2571 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2572 {
2573         s32 ret_val = E1000_SUCCESS;
2574         u16 phy_reg, data;
2575         u32 mac_reg;
2576         u16 i;
2577
2578         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2579
2580         if (hw->mac.type < e1000_pch2lan)
2581                 return E1000_SUCCESS;
2582
2583         /* disable Rx path while enabling/disabling workaround */
2584         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2585         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2586                                         phy_reg | (1 << 14));
2587         if (ret_val)
2588                 return ret_val;
2589
2590         if (enable) {
2591                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2592                  * SHRAL/H) and initial CRC values to the MAC
2593                  */
2594                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2595                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2596                         u32 addr_high, addr_low;
2597
2598                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2599                         if (!(addr_high & E1000_RAH_AV))
2600                                 continue;
2601                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2602                         mac_addr[0] = (addr_low & 0xFF);
2603                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2604                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2605                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2606                         mac_addr[4] = (addr_high & 0xFF);
2607                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2608
2609 #ifndef CRC32_OS_SUPPORT
2610                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2611                                         e1000_calc_rx_da_crc(mac_addr));
2612 #else /* CRC32_OS_SUPPORT */
2613                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2614                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2615 #endif /* CRC32_OS_SUPPORT */
2616                 }
2617
2618                 /* Write Rx addresses to the PHY */
2619                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2620
2621                 /* Enable jumbo frame workaround in the MAC */
2622                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2623                 mac_reg &= ~(1 << 14);
2624                 mac_reg |= (7 << 15);
2625                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2626
2627                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2628                 mac_reg |= E1000_RCTL_SECRC;
2629                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2630
2631                 ret_val = e1000_read_kmrn_reg_generic(hw,
2632                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2633                                                 &data);
2634                 if (ret_val)
2635                         return ret_val;
2636                 ret_val = e1000_write_kmrn_reg_generic(hw,
2637                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2638                                                 data | (1 << 0));
2639                 if (ret_val)
2640                         return ret_val;
2641                 ret_val = e1000_read_kmrn_reg_generic(hw,
2642                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2643                                                 &data);
2644                 if (ret_val)
2645                         return ret_val;
2646                 data &= ~(0xF << 8);
2647                 data |= (0xB << 8);
2648                 ret_val = e1000_write_kmrn_reg_generic(hw,
2649                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2650                                                 data);
2651                 if (ret_val)
2652                         return ret_val;
2653
2654                 /* Enable jumbo frame workaround in the PHY */
2655                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2656                 data &= ~(0x7F << 5);
2657                 data |= (0x37 << 5);
2658                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2659                 if (ret_val)
2660                         return ret_val;
2661                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2662                 data &= ~(1 << 13);
2663                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2664                 if (ret_val)
2665                         return ret_val;
2666                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2667                 data &= ~(0x3FF << 2);
2668                 data |= (E1000_TX_PTR_GAP << 2);
2669                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2670                 if (ret_val)
2671                         return ret_val;
2672                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2673                 if (ret_val)
2674                         return ret_val;
2675                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2676                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2677                                                 (1 << 10));
2678                 if (ret_val)
2679                         return ret_val;
2680         } else {
2681                 /* Write MAC register values back to h/w defaults */
2682                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2683                 mac_reg &= ~(0xF << 14);
2684                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2685
2686                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2687                 mac_reg &= ~E1000_RCTL_SECRC;
2688                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2689
2690                 ret_val = e1000_read_kmrn_reg_generic(hw,
2691                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2692                                                 &data);
2693                 if (ret_val)
2694                         return ret_val;
2695                 ret_val = e1000_write_kmrn_reg_generic(hw,
2696                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2697                                                 data & ~(1 << 0));
2698                 if (ret_val)
2699                         return ret_val;
2700                 ret_val = e1000_read_kmrn_reg_generic(hw,
2701                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2702                                                 &data);
2703                 if (ret_val)
2704                         return ret_val;
2705                 data &= ~(0xF << 8);
2706                 data |= (0xB << 8);
2707                 ret_val = e1000_write_kmrn_reg_generic(hw,
2708                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2709                                                 data);
2710                 if (ret_val)
2711                         return ret_val;
2712
2713                 /* Write PHY register values back to h/w defaults */
2714                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2715                 data &= ~(0x7F << 5);
2716                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2717                 if (ret_val)
2718                         return ret_val;
2719                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2720                 data |= (1 << 13);
2721                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2722                 if (ret_val)
2723                         return ret_val;
2724                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2725                 data &= ~(0x3FF << 2);
2726                 data |= (0x8 << 2);
2727                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2728                 if (ret_val)
2729                         return ret_val;
2730                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2731                 if (ret_val)
2732                         return ret_val;
2733                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2734                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2735                                                 ~(1 << 10));
2736                 if (ret_val)
2737                         return ret_val;
2738         }
2739
2740         /* re-enable Rx path after enabling/disabling workaround */
2741         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2742                                      ~(1 << 14));
2743 }
2744
2745 /**
2746  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2747  *  done after every PHY reset.
2748  **/
2749 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2750 {
2751         s32 ret_val = E1000_SUCCESS;
2752
2753         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2754
2755         if (hw->mac.type != e1000_pch2lan)
2756                 return E1000_SUCCESS;
2757
2758         /* Set MDIO slow mode before any other MDIO access */
2759         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2760         if (ret_val)
2761                 return ret_val;
2762
2763         ret_val = hw->phy.ops.acquire(hw);
2764         if (ret_val)
2765                 return ret_val;
2766         /* set MSE higher to enable link to stay up when noise is high */
2767         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2768         if (ret_val)
2769                 goto release;
2770         /* drop link after 5 times MSE threshold was reached */
2771         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2772 release:
2773         hw->phy.ops.release(hw);
2774
2775         return ret_val;
2776 }
2777
2778 /**
2779  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2780  *  @hw:   pointer to the HW structure
2781  *
2782  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2783  *  Disable K1 for 1000 and 100 speeds
2784  **/
2785 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2786 {
2787         s32 ret_val = E1000_SUCCESS;
2788         u16 status_reg = 0;
2789
2790         DEBUGFUNC("e1000_k1_workaround_lv");
2791
2792         if (hw->mac.type != e1000_pch2lan)
2793                 return E1000_SUCCESS;
2794
2795         /* Set K1 beacon duration based on 10Mbs speed */
2796         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2797         if (ret_val)
2798                 return ret_val;
2799
2800         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2801             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2802                 if (status_reg &
2803                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2804                         u16 pm_phy_reg;
2805
2806                         /* LV 1G/100 Packet drop issue wa  */
2807                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2808                                                        &pm_phy_reg);
2809                         if (ret_val)
2810                                 return ret_val;
2811                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2812                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2813                                                         pm_phy_reg);
2814                         if (ret_val)
2815                                 return ret_val;
2816                 } else {
2817                         u32 mac_reg;
2818                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2819                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2820                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2821                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2822                 }
2823         }
2824
2825         return ret_val;
2826 }
2827
2828 /**
2829  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2830  *  @hw:   pointer to the HW structure
2831  *  @gate: boolean set to true to gate, false to ungate
2832  *
2833  *  Gate/ungate the automatic PHY configuration via hardware; perform
2834  *  the configuration via software instead.
2835  **/
2836 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2837 {
2838         u32 extcnf_ctrl;
2839
2840         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2841
2842         if (hw->mac.type < e1000_pch2lan)
2843                 return;
2844
2845         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2846
2847         if (gate)
2848                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2849         else
2850                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2851
2852         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2853 }
2854
2855 /**
2856  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2857  *  @hw: pointer to the HW structure
2858  *
2859  *  Check the appropriate indication the MAC has finished configuring the
2860  *  PHY after a software reset.
2861  **/
2862 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2863 {
2864         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2865
2866         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2867
2868         /* Wait for basic configuration completes before proceeding */
2869         do {
2870                 data = E1000_READ_REG(hw, E1000_STATUS);
2871                 data &= E1000_STATUS_LAN_INIT_DONE;
2872                 usec_delay(100);
2873         } while ((!data) && --loop);
2874
2875         /* If basic configuration is incomplete before the above loop
2876          * count reaches 0, loading the configuration from NVM will
2877          * leave the PHY in a bad state possibly resulting in no link.
2878          */
2879         if (loop == 0)
2880                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2881
2882         /* Clear the Init Done bit for the next init event */
2883         data = E1000_READ_REG(hw, E1000_STATUS);
2884         data &= ~E1000_STATUS_LAN_INIT_DONE;
2885         E1000_WRITE_REG(hw, E1000_STATUS, data);
2886 }
2887
2888 /**
2889  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2890  *  @hw: pointer to the HW structure
2891  **/
2892 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2893 {
2894         s32 ret_val = E1000_SUCCESS;
2895         u16 reg;
2896
2897         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2898
2899         if (hw->phy.ops.check_reset_block(hw))
2900                 return E1000_SUCCESS;
2901
2902         /* Allow time for h/w to get to quiescent state after reset */
2903         msec_delay(10);
2904
2905         /* Perform any necessary post-reset workarounds */
2906         switch (hw->mac.type) {
2907         case e1000_pchlan:
2908                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2909                 if (ret_val)
2910                         return ret_val;
2911                 break;
2912         case e1000_pch2lan:
2913                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2914                 if (ret_val)
2915                         return ret_val;
2916                 break;
2917         default:
2918                 break;
2919         }
2920
2921         /* Clear the host wakeup bit after lcd reset */
2922         if (hw->mac.type >= e1000_pchlan) {
2923                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2924                 reg &= ~BM_WUC_HOST_WU_BIT;
2925                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2926         }
2927
2928         /* Configure the LCD with the extended configuration region in NVM */
2929         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2930         if (ret_val)
2931                 return ret_val;
2932
2933         /* Configure the LCD with the OEM bits in NVM */
2934         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2935
2936         if (hw->mac.type == e1000_pch2lan) {
2937                 /* Ungate automatic PHY configuration on non-managed 82579 */
2938                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2939                     E1000_ICH_FWSM_FW_VALID)) {
2940                         msec_delay(10);
2941                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2942                 }
2943
2944                 /* Set EEE LPI Update Timer to 200usec */
2945                 ret_val = hw->phy.ops.acquire(hw);
2946                 if (ret_val)
2947                         return ret_val;
2948                 ret_val = e1000_write_emi_reg_locked(hw,
2949                                                      I82579_LPI_UPDATE_TIMER,
2950                                                      0x1387);
2951                 hw->phy.ops.release(hw);
2952         }
2953
2954         return ret_val;
2955 }
2956
2957 /**
2958  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2959  *  @hw: pointer to the HW structure
2960  *
2961  *  Resets the PHY
2962  *  This is a function pointer entry point called by drivers
2963  *  or other shared routines.
2964  **/
2965 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2966 {
2967         s32 ret_val = E1000_SUCCESS;
2968
2969         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2970
2971         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2972         if ((hw->mac.type == e1000_pch2lan) &&
2973             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2974                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2975
2976         ret_val = e1000_phy_hw_reset_generic(hw);
2977         if (ret_val)
2978                 return ret_val;
2979
2980         return e1000_post_phy_reset_ich8lan(hw);
2981 }
2982
2983 /**
2984  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2985  *  @hw: pointer to the HW structure
2986  *  @active: true to enable LPLU, false to disable
2987  *
2988  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2989  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2990  *  the phy speed. This function will manually set the LPLU bit and restart
2991  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2992  *  since it configures the same bit.
2993  **/
2994 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2995 {
2996         s32 ret_val;
2997         u16 oem_reg;
2998
2999         DEBUGFUNC("e1000_set_lplu_state_pchlan");
3000         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3001         if (ret_val)
3002                 return ret_val;
3003
3004         if (active)
3005                 oem_reg |= HV_OEM_BITS_LPLU;
3006         else
3007                 oem_reg &= ~HV_OEM_BITS_LPLU;
3008
3009         if (!hw->phy.ops.check_reset_block(hw))
3010                 oem_reg |= HV_OEM_BITS_RESTART_AN;
3011
3012         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3013 }
3014
3015 /**
3016  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3017  *  @hw: pointer to the HW structure
3018  *  @active: true to enable LPLU, false to disable
3019  *
3020  *  Sets the LPLU D0 state according to the active flag.  When
3021  *  activating LPLU this function also disables smart speed
3022  *  and vice versa.  LPLU will not be activated unless the
3023  *  device autonegotiation advertisement meets standards of
3024  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3025  *  This is a function pointer entry point only called by
3026  *  PHY setup routines.
3027  **/
3028 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3029 {
3030         struct e1000_phy_info *phy = &hw->phy;
3031         u32 phy_ctrl;
3032         s32 ret_val = E1000_SUCCESS;
3033         u16 data;
3034
3035         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3036
3037         if (phy->type == e1000_phy_ife)
3038                 return E1000_SUCCESS;
3039
3040         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3041
3042         if (active) {
3043                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3044                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3045
3046                 if (phy->type != e1000_phy_igp_3)
3047                         return E1000_SUCCESS;
3048
3049                 /* Call gig speed drop workaround on LPLU before accessing
3050                  * any PHY registers
3051                  */
3052                 if (hw->mac.type == e1000_ich8lan)
3053                         e1000_gig_downshift_workaround_ich8lan(hw);
3054
3055                 /* When LPLU is enabled, we should disable SmartSpeed */
3056                 ret_val = phy->ops.read_reg(hw,
3057                                             IGP01E1000_PHY_PORT_CONFIG,
3058                                             &data);
3059                 if (ret_val)
3060                         return ret_val;
3061                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3062                 ret_val = phy->ops.write_reg(hw,
3063                                              IGP01E1000_PHY_PORT_CONFIG,
3064                                              data);
3065                 if (ret_val)
3066                         return ret_val;
3067         } else {
3068                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3069                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3070
3071                 if (phy->type != e1000_phy_igp_3)
3072                         return E1000_SUCCESS;
3073
3074                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3075                  * during Dx states where the power conservation is most
3076                  * important.  During driver activity we should enable
3077                  * SmartSpeed, so performance is maintained.
3078                  */
3079                 if (phy->smart_speed == e1000_smart_speed_on) {
3080                         ret_val = phy->ops.read_reg(hw,
3081                                                     IGP01E1000_PHY_PORT_CONFIG,
3082                                                     &data);
3083                         if (ret_val)
3084                                 return ret_val;
3085
3086                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3087                         ret_val = phy->ops.write_reg(hw,
3088                                                      IGP01E1000_PHY_PORT_CONFIG,
3089                                                      data);
3090                         if (ret_val)
3091                                 return ret_val;
3092                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3093                         ret_val = phy->ops.read_reg(hw,
3094                                                     IGP01E1000_PHY_PORT_CONFIG,
3095                                                     &data);
3096                         if (ret_val)
3097                                 return ret_val;
3098
3099                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3100                         ret_val = phy->ops.write_reg(hw,
3101                                                      IGP01E1000_PHY_PORT_CONFIG,
3102                                                      data);
3103                         if (ret_val)
3104                                 return ret_val;
3105                 }
3106         }
3107
3108         return E1000_SUCCESS;
3109 }
3110
3111 /**
3112  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3113  *  @hw: pointer to the HW structure
3114  *  @active: true to enable LPLU, false to disable
3115  *
3116  *  Sets the LPLU D3 state according to the active flag.  When
3117  *  activating LPLU this function also disables smart speed
3118  *  and vice versa.  LPLU will not be activated unless the
3119  *  device autonegotiation advertisement meets standards of
3120  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3121  *  This is a function pointer entry point only called by
3122  *  PHY setup routines.
3123  **/
3124 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3125 {
3126         struct e1000_phy_info *phy = &hw->phy;
3127         u32 phy_ctrl;
3128         s32 ret_val = E1000_SUCCESS;
3129         u16 data;
3130
3131         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3132
3133         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3134
3135         if (!active) {
3136                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3137                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3138
3139                 if (phy->type != e1000_phy_igp_3)
3140                         return E1000_SUCCESS;
3141
3142                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3143                  * during Dx states where the power conservation is most
3144                  * important.  During driver activity we should enable
3145                  * SmartSpeed, so performance is maintained.
3146                  */
3147                 if (phy->smart_speed == e1000_smart_speed_on) {
3148                         ret_val = phy->ops.read_reg(hw,
3149                                                     IGP01E1000_PHY_PORT_CONFIG,
3150                                                     &data);
3151                         if (ret_val)
3152                                 return ret_val;
3153
3154                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3155                         ret_val = phy->ops.write_reg(hw,
3156                                                      IGP01E1000_PHY_PORT_CONFIG,
3157                                                      data);
3158                         if (ret_val)
3159                                 return ret_val;
3160                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3161                         ret_val = phy->ops.read_reg(hw,
3162                                                     IGP01E1000_PHY_PORT_CONFIG,
3163                                                     &data);
3164                         if (ret_val)
3165                                 return ret_val;
3166
3167                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3168                         ret_val = phy->ops.write_reg(hw,
3169                                                      IGP01E1000_PHY_PORT_CONFIG,
3170                                                      data);
3171                         if (ret_val)
3172                                 return ret_val;
3173                 }
3174         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3175                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3176                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3177                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3178                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3179
3180                 if (phy->type != e1000_phy_igp_3)
3181                         return E1000_SUCCESS;
3182
3183                 /* Call gig speed drop workaround on LPLU before accessing
3184                  * any PHY registers
3185                  */
3186                 if (hw->mac.type == e1000_ich8lan)
3187                         e1000_gig_downshift_workaround_ich8lan(hw);
3188
3189                 /* When LPLU is enabled, we should disable SmartSpeed */
3190                 ret_val = phy->ops.read_reg(hw,
3191                                             IGP01E1000_PHY_PORT_CONFIG,
3192                                             &data);
3193                 if (ret_val)
3194                         return ret_val;
3195
3196                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3197                 ret_val = phy->ops.write_reg(hw,
3198                                              IGP01E1000_PHY_PORT_CONFIG,
3199                                              data);
3200         }
3201
3202         return ret_val;
3203 }
3204
3205 /**
3206  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3207  *  @hw: pointer to the HW structure
3208  *  @bank:  pointer to the variable that returns the active bank
3209  *
3210  *  Reads signature byte from the NVM using the flash access registers.
3211  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3212  **/
3213 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3214 {
3215         u32 eecd;
3216         struct e1000_nvm_info *nvm = &hw->nvm;
3217         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3218         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3219         u32 nvm_dword = 0;
3220         u8 sig_byte = 0;
3221         s32 ret_val;
3222
3223         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3224
3225         switch (hw->mac.type) {
3226         case e1000_ich8lan:
3227         case e1000_ich9lan:
3228                 eecd = E1000_READ_REG(hw, E1000_EECD);
3229                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3230                     E1000_EECD_SEC1VAL_VALID_MASK) {
3231                         if (eecd & E1000_EECD_SEC1VAL)
3232                                 *bank = 1;
3233                         else
3234                                 *bank = 0;
3235
3236                         return E1000_SUCCESS;
3237                 }
3238                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3239                 /* fall-thru */
3240         default:
3241                 /* set bank to 0 in case flash read fails */
3242                 *bank = 0;
3243
3244                 /* Check bank 0 */
3245                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3246                                                         &sig_byte);
3247                 if (ret_val)
3248                         return ret_val;
3249                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3250                     E1000_ICH_NVM_SIG_VALUE) {
3251                         *bank = 0;
3252                         return E1000_SUCCESS;
3253                 }
3254
3255                 /* Check bank 1 */
3256                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3257                                                         bank1_offset,
3258                                                         &sig_byte);
3259                 if (ret_val)
3260                         return ret_val;
3261                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3262                     E1000_ICH_NVM_SIG_VALUE) {
3263                         *bank = 1;
3264                         return E1000_SUCCESS;
3265                 }
3266
3267                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3268                 return -E1000_ERR_NVM;
3269         }
3270 }
3271
3272 /**
3273  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3274  *  @hw: pointer to the HW structure
3275  *  @offset: The offset (in bytes) of the word(s) to read.
3276  *  @words: Size of data to read in words
3277  *  @data: Pointer to the word(s) to read at offset.
3278  *
3279  *  Reads a word(s) from the NVM using the flash access registers.
3280  **/
3281 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3282                                   u16 *data)
3283 {
3284         struct e1000_nvm_info *nvm = &hw->nvm;
3285         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3286         u32 act_offset;
3287         s32 ret_val = E1000_SUCCESS;
3288         u32 bank = 0;
3289         u16 i, word;
3290
3291         DEBUGFUNC("e1000_read_nvm_ich8lan");
3292
3293         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3294             (words == 0)) {
3295                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3296                 ret_val = -E1000_ERR_NVM;
3297                 goto out;
3298         }
3299
3300         nvm->ops.acquire(hw);
3301
3302         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3303         if (ret_val != E1000_SUCCESS) {
3304                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3305                 bank = 0;
3306         }
3307
3308         act_offset = (bank) ? nvm->flash_bank_size : 0;
3309         act_offset += offset;
3310
3311         ret_val = E1000_SUCCESS;
3312         for (i = 0; i < words; i++) {
3313                 if (dev_spec->shadow_ram[offset+i].modified) {
3314                         data[i] = dev_spec->shadow_ram[offset+i].value;
3315                 } else {
3316                         ret_val = e1000_read_flash_word_ich8lan(hw,
3317                                                                 act_offset + i,
3318                                                                 &word);
3319                         if (ret_val)
3320                                 break;
3321                         data[i] = word;
3322                 }
3323         }
3324
3325         nvm->ops.release(hw);
3326
3327 out:
3328         if (ret_val)
3329                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3330
3331         return ret_val;
3332 }
3333
3334 /**
3335  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3336  *  @hw: pointer to the HW structure
3337  *
3338  *  This function does initial flash setup so that a new read/write/erase cycle
3339  *  can be started.
3340  **/
3341 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3342 {
3343         union ich8_hws_flash_status hsfsts;
3344         s32 ret_val = -E1000_ERR_NVM;
3345
3346         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3347
3348         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3349
3350         /* Check if the flash descriptor is valid */
3351         if (!hsfsts.hsf_status.fldesvalid) {
3352                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3353                 return -E1000_ERR_NVM;
3354         }
3355
3356         /* Clear FCERR and DAEL in hw status by writing 1 */
3357         hsfsts.hsf_status.flcerr = 1;
3358         hsfsts.hsf_status.dael = 1;
3359         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3360
3361         /* Either we should have a hardware SPI cycle in progress
3362          * bit to check against, in order to start a new cycle or
3363          * FDONE bit should be changed in the hardware so that it
3364          * is 1 after hardware reset, which can then be used as an
3365          * indication whether a cycle is in progress or has been
3366          * completed.
3367          */
3368
3369         if (!hsfsts.hsf_status.flcinprog) {
3370                 /* There is no cycle running at present,
3371                  * so we can start a cycle.
3372                  * Begin by setting Flash Cycle Done.
3373                  */
3374                 hsfsts.hsf_status.flcdone = 1;
3375                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3376                 ret_val = E1000_SUCCESS;
3377         } else {
3378                 s32 i;
3379
3380                 /* Otherwise poll for sometime so the current
3381                  * cycle has a chance to end before giving up.
3382                  */
3383                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3384                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3385                                                               ICH_FLASH_HSFSTS);
3386                         if (!hsfsts.hsf_status.flcinprog) {
3387                                 ret_val = E1000_SUCCESS;
3388                                 break;
3389                         }
3390                         usec_delay(1);
3391                 }
3392                 if (ret_val == E1000_SUCCESS) {
3393                         /* Successful in waiting for previous cycle to timeout,
3394                          * now set the Flash Cycle Done.
3395                          */
3396                         hsfsts.hsf_status.flcdone = 1;
3397                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3398                                                 hsfsts.regval);
3399                 } else {
3400                         DEBUGOUT("Flash controller busy, cannot get access\n");
3401                 }
3402         }
3403
3404         return ret_val;
3405 }
3406
3407 /**
3408  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3409  *  @hw: pointer to the HW structure
3410  *  @timeout: maximum time to wait for completion
3411  *
3412  *  This function starts a flash cycle and waits for its completion.
3413  **/
3414 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3415 {
3416         union ich8_hws_flash_ctrl hsflctl;
3417         union ich8_hws_flash_status hsfsts;
3418         u32 i = 0;
3419
3420         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3421
3422         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3423         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3424         hsflctl.hsf_ctrl.flcgo = 1;
3425
3426         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3427
3428         /* wait till FDONE bit is set to 1 */
3429         do {
3430                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3431                 if (hsfsts.hsf_status.flcdone)
3432                         break;
3433                 usec_delay(1);
3434         } while (i++ < timeout);
3435
3436         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3437                 return E1000_SUCCESS;
3438
3439         return -E1000_ERR_NVM;
3440 }
3441
3442 /**
3443  *  e1000_read_flash_word_ich8lan - Read word from flash
3444  *  @hw: pointer to the HW structure
3445  *  @offset: offset to data location
3446  *  @data: pointer to the location for storing the data
3447  *
3448  *  Reads the flash word at offset into data.  Offset is converted
3449  *  to bytes before read.
3450  **/
3451 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3452                                          u16 *data)
3453 {
3454         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3455
3456         if (!data)
3457                 return -E1000_ERR_NVM;
3458
3459         /* Must convert offset into bytes. */
3460         offset <<= 1;
3461
3462         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3463 }
3464
3465 /**
3466  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3467  *  @hw: pointer to the HW structure
3468  *  @offset: The offset of the byte to read.
3469  *  @data: Pointer to a byte to store the value read.
3470  *
3471  *  Reads a single byte from the NVM using the flash access registers.
3472  **/
3473 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3474                                          u8 *data)
3475 {
3476         s32 ret_val;
3477         u16 word = 0;
3478
3479         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3480
3481         if (ret_val)
3482                 return ret_val;
3483
3484         *data = (u8)word;
3485
3486         return E1000_SUCCESS;
3487 }
3488
3489 /**
3490  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3491  *  @hw: pointer to the HW structure
3492  *  @offset: The offset (in bytes) of the byte or word to read.
3493  *  @size: Size of data to read, 1=byte 2=word
3494  *  @data: Pointer to the word to store the value read.
3495  *
3496  *  Reads a byte or word from the NVM using the flash access registers.
3497  **/
3498 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3499                                          u8 size, u16 *data)
3500 {
3501         union ich8_hws_flash_status hsfsts;
3502         union ich8_hws_flash_ctrl hsflctl;
3503         u32 flash_linear_addr;
3504         u32 flash_data = 0;
3505         s32 ret_val = -E1000_ERR_NVM;
3506         u8 count = 0;
3507
3508         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3509
3510         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3511                 return -E1000_ERR_NVM;
3512         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3513                              hw->nvm.flash_base_addr);
3514
3515         do {
3516                 usec_delay(1);
3517                 /* Steps */
3518                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3519                 if (ret_val != E1000_SUCCESS)
3520                         break;
3521                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3522
3523                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3524                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3525                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3526                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3527                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3528
3529                 ret_val = e1000_flash_cycle_ich8lan(hw,
3530                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3531
3532                 /* Check if FCERR is set to 1, if set to 1, clear it
3533                  * and try the whole sequence a few more times, else
3534                  * read in (shift in) the Flash Data0, the order is
3535                  * least significant byte first msb to lsb
3536                  */
3537                 if (ret_val == E1000_SUCCESS) {
3538                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3539                         if (size == 1)
3540                                 *data = (u8)(flash_data & 0x000000FF);
3541                         else if (size == 2)
3542                                 *data = (u16)(flash_data & 0x0000FFFF);
3543                         break;
3544                 } else {
3545                         /* If we've gotten here, then things are probably
3546                          * completely hosed, but if the error condition is
3547                          * detected, it won't hurt to give it another try...
3548                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3549                          */
3550                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3551                                                               ICH_FLASH_HSFSTS);
3552                         if (hsfsts.hsf_status.flcerr) {
3553                                 /* Repeat for some time before giving up. */
3554                                 continue;
3555                         } else if (!hsfsts.hsf_status.flcdone) {
3556                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3557                                 break;
3558                         }
3559                 }
3560         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3561
3562         return ret_val;
3563 }
3564
3565
3566 /**
3567  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3568  *  @hw: pointer to the HW structure
3569  *  @offset: The offset (in bytes) of the word(s) to write.
3570  *  @words: Size of data to write in words
3571  *  @data: Pointer to the word(s) to write at offset.
3572  *
3573  *  Writes a byte or word to the NVM using the flash access registers.
3574  **/
3575 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3576                                    u16 *data)
3577 {
3578         struct e1000_nvm_info *nvm = &hw->nvm;
3579         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3580         u16 i;
3581
3582         DEBUGFUNC("e1000_write_nvm_ich8lan");
3583
3584         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3585             (words == 0)) {
3586                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3587                 return -E1000_ERR_NVM;
3588         }
3589
3590         nvm->ops.acquire(hw);
3591
3592         for (i = 0; i < words; i++) {
3593                 dev_spec->shadow_ram[offset+i].modified = true;
3594                 dev_spec->shadow_ram[offset+i].value = data[i];
3595         }
3596
3597         nvm->ops.release(hw);
3598
3599         return E1000_SUCCESS;
3600 }
3601
3602 /**
3603  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3604  *  @hw: pointer to the HW structure
3605  *
3606  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3607  *  which writes the checksum to the shadow ram.  The changes in the shadow
3608  *  ram are then committed to the EEPROM by processing each bank at a time
3609  *  checking for the modified bit and writing only the pending changes.
3610  *  After a successful commit, the shadow ram is cleared and is ready for
3611  *  future writes.
3612  **/
3613 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3614 {
3615         struct e1000_nvm_info *nvm = &hw->nvm;
3616         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3617         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3618         s32 ret_val;
3619         u16 data = 0;
3620
3621         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3622
3623         ret_val = e1000_update_nvm_checksum_generic(hw);
3624         if (ret_val)
3625                 goto out;
3626
3627         if (nvm->type != e1000_nvm_flash_sw)
3628                 goto out;
3629
3630         nvm->ops.acquire(hw);
3631
3632         /* We're writing to the opposite bank so if we're on bank 1,
3633          * write to bank 0 etc.  We also need to erase the segment that
3634          * is going to be written
3635          */
3636         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3637         if (ret_val != E1000_SUCCESS) {
3638                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3639                 bank = 0;
3640         }
3641
3642         if (bank == 0) {
3643                 new_bank_offset = nvm->flash_bank_size;
3644                 old_bank_offset = 0;
3645                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3646                 if (ret_val)
3647                         goto release;
3648         } else {
3649                 old_bank_offset = nvm->flash_bank_size;
3650                 new_bank_offset = 0;
3651                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3652                 if (ret_val)
3653                         goto release;
3654         }
3655         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3656                 if (dev_spec->shadow_ram[i].modified) {
3657                         data = dev_spec->shadow_ram[i].value;
3658                 } else {
3659                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3660                                                                 old_bank_offset,
3661                                                                 &data);
3662                         if (ret_val)
3663                                 break;
3664                 }
3665                 /* If the word is 0x13, then make sure the signature bits
3666                  * (15:14) are 11b until the commit has completed.
3667                  * This will allow us to write 10b which indicates the
3668                  * signature is valid.  We want to do this after the write
3669                  * has completed so that we don't mark the segment valid
3670                  * while the write is still in progress
3671                  */
3672                 if (i == E1000_ICH_NVM_SIG_WORD)
3673                         data |= E1000_ICH_NVM_SIG_MASK;
3674
3675                 /* Convert offset to bytes. */
3676                 act_offset = (i + new_bank_offset) << 1;
3677
3678                 usec_delay(100);
3679
3680                 /* Write the bytes to the new bank. */
3681                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3682                                                                act_offset,
3683                                                                (u8)data);
3684                 if (ret_val)
3685                         break;
3686
3687                 usec_delay(100);
3688                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3689                                                           act_offset + 1,
3690                                                           (u8)(data >> 8));
3691                 if (ret_val)
3692                         break;
3693         }
3694
3695         /* Don't bother writing the segment valid bits if sector
3696          * programming failed.
3697          */
3698         if (ret_val) {
3699                 DEBUGOUT("Flash commit failed.\n");
3700                 goto release;
3701         }
3702
3703         /* Finally validate the new segment by setting bit 15:14
3704          * to 10b in word 0x13 , this can be done without an
3705          * erase as well since these bits are 11 to start with
3706          * and we need to change bit 14 to 0b
3707          */
3708         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3709         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3710         if (ret_val)
3711                 goto release;
3712
3713         data &= 0xBFFF;
3714         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
3715                                                        (u8)(data >> 8));
3716         if (ret_val)
3717                 goto release;
3718
3719         /* And invalidate the previously valid segment by setting
3720          * its signature word (0x13) high_byte to 0b. This can be
3721          * done without an erase because flash erase sets all bits
3722          * to 1's. We can write 1's to 0's without an erase
3723          */
3724         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3725
3726         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3727
3728         if (ret_val)
3729                 goto release;
3730
3731         /* Great!  Everything worked, we can now clear the cached entries. */
3732         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3733                 dev_spec->shadow_ram[i].modified = false;
3734                 dev_spec->shadow_ram[i].value = 0xFFFF;
3735         }
3736
3737 release:
3738         nvm->ops.release(hw);
3739
3740         /* Reload the EEPROM, or else modifications will not appear
3741          * until after the next adapter reset.
3742          */
3743         if (!ret_val) {
3744                 nvm->ops.reload(hw);
3745                 msec_delay(10);
3746         }
3747
3748 out:
3749         if (ret_val)
3750                 DEBUGOUT1("NVM update error: %d\n", ret_val);
3751
3752         return ret_val;
3753 }
3754
3755 /**
3756  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3757  *  @hw: pointer to the HW structure
3758  *
3759  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3760  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3761  *  calculated, in which case we need to calculate the checksum and set bit 6.
3762  **/
3763 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3764 {
3765         s32 ret_val;
3766         u16 data;
3767         u16 word;
3768         u16 valid_csum_mask;
3769
3770         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3771
3772         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3773          * the checksum needs to be fixed.  This bit is an indication that
3774          * the NVM was prepared by OEM software and did not calculate
3775          * the checksum...a likely scenario.
3776          */
3777         switch (hw->mac.type) {
3778         case e1000_pch_lpt:
3779                 word = NVM_COMPAT;
3780                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3781                 break;
3782         default:
3783                 word = NVM_FUTURE_INIT_WORD1;
3784                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3785                 break;
3786         }
3787
3788         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3789         if (ret_val)
3790                 return ret_val;
3791
3792         if (!(data & valid_csum_mask)) {
3793                 data |= valid_csum_mask;
3794                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3795                 if (ret_val)
3796                         return ret_val;
3797                 ret_val = hw->nvm.ops.update(hw);
3798                 if (ret_val)
3799                         return ret_val;
3800         }
3801
3802         return e1000_validate_nvm_checksum_generic(hw);
3803 }
3804
3805 /**
3806  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3807  *  @hw: pointer to the HW structure
3808  *  @offset: The offset (in bytes) of the byte/word to read.
3809  *  @size: Size of data to read, 1=byte 2=word
3810  *  @data: The byte(s) to write to the NVM.
3811  *
3812  *  Writes one/two bytes to the NVM using the flash access registers.
3813  **/
3814 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3815                                           u8 size, u16 data)
3816 {
3817         union ich8_hws_flash_status hsfsts;
3818         union ich8_hws_flash_ctrl hsflctl;
3819         u32 flash_linear_addr;
3820         u32 flash_data = 0;
3821         s32 ret_val;
3822         u8 count = 0;
3823
3824         DEBUGFUNC("e1000_write_ich8_data");
3825
3826         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3827                 return -E1000_ERR_NVM;
3828
3829         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3830                              hw->nvm.flash_base_addr);
3831
3832         do {
3833                 usec_delay(1);
3834                 /* Steps */
3835                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3836                 if (ret_val != E1000_SUCCESS)
3837                         break;
3838                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3839
3840                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3841                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3842                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3843                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3844
3845                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3846
3847                 if (size == 1)
3848                         flash_data = (u32)data & 0x00FF;
3849                 else
3850                         flash_data = (u32)data;
3851
3852                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3853
3854                 /* check if FCERR is set to 1 , if set to 1, clear it
3855                  * and try the whole sequence a few more times else done
3856                  */
3857                 ret_val =
3858                     e1000_flash_cycle_ich8lan(hw,
3859                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3860                 if (ret_val == E1000_SUCCESS)
3861                         break;
3862
3863                 /* If we're here, then things are most likely
3864                  * completely hosed, but if the error condition
3865                  * is detected, it won't hurt to give it another
3866                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3867                  */
3868                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3869                 if (hsfsts.hsf_status.flcerr)
3870                         /* Repeat for some time before giving up. */
3871                         continue;
3872                 if (!hsfsts.hsf_status.flcdone) {
3873                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3874                         break;
3875                 }
3876         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3877
3878         return ret_val;
3879 }
3880
3881
3882 /**
3883  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3884  *  @hw: pointer to the HW structure
3885  *  @offset: The index of the byte to read.
3886  *  @data: The byte to write to the NVM.
3887  *
3888  *  Writes a single byte to the NVM using the flash access registers.
3889  **/
3890 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3891                                           u8 data)
3892 {
3893         u16 word = (u16)data;
3894
3895         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3896
3897         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3898 }
3899
3900
3901
3902 /**
3903  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3904  *  @hw: pointer to the HW structure
3905  *  @offset: The offset of the byte to write.
3906  *  @byte: The byte to write to the NVM.
3907  *
3908  *  Writes a single byte to the NVM using the flash access registers.
3909  *  Goes through a retry algorithm before giving up.
3910  **/
3911 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3912                                                 u32 offset, u8 byte)
3913 {
3914         s32 ret_val;
3915         u16 program_retries;
3916
3917         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3918
3919         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3920         if (!ret_val)
3921                 return ret_val;
3922
3923         for (program_retries = 0; program_retries < 100; program_retries++) {
3924                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3925                 usec_delay(100);
3926                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3927                 if (ret_val == E1000_SUCCESS)
3928                         break;
3929         }
3930         if (program_retries == 100)
3931                 return -E1000_ERR_NVM;
3932
3933         return E1000_SUCCESS;
3934 }
3935
3936 /**
3937  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3938  *  @hw: pointer to the HW structure
3939  *  @bank: 0 for first bank, 1 for second bank, etc.
3940  *
3941  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3942  *  bank N is 4096 * N + flash_reg_addr.
3943  **/
3944 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3945 {
3946         struct e1000_nvm_info *nvm = &hw->nvm;
3947         union ich8_hws_flash_status hsfsts;
3948         union ich8_hws_flash_ctrl hsflctl;
3949         u32 flash_linear_addr;
3950         /* bank size is in 16bit words - adjust to bytes */
3951         u32 flash_bank_size = nvm->flash_bank_size * 2;
3952         s32 ret_val;
3953         s32 count = 0;
3954         s32 j, iteration, sector_size;
3955
3956         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3957
3958         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3959
3960         /* Determine HW Sector size: Read BERASE bits of hw flash status
3961          * register
3962          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3963          *     consecutive sectors.  The start index for the nth Hw sector
3964          *     can be calculated as = bank * 4096 + n * 256
3965          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3966          *     The start index for the nth Hw sector can be calculated
3967          *     as = bank * 4096
3968          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3969          *     (ich9 only, otherwise error condition)
3970          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3971          */
3972         switch (hsfsts.hsf_status.berasesz) {
3973         case 0:
3974                 /* Hw sector size 256 */
3975                 sector_size = ICH_FLASH_SEG_SIZE_256;
3976                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3977                 break;
3978         case 1:
3979                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3980                 iteration = 1;
3981                 break;
3982         case 2:
3983                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3984                 iteration = 1;
3985                 break;
3986         case 3:
3987                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3988                 iteration = 1;
3989                 break;
3990         default:
3991                 return -E1000_ERR_NVM;
3992         }
3993
3994         /* Start with the base address, then add the sector offset. */
3995         flash_linear_addr = hw->nvm.flash_base_addr;
3996         flash_linear_addr += (bank) ? flash_bank_size : 0;
3997
3998         for (j = 0; j < iteration; j++) {
3999                 do {
4000                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4001
4002                         /* Steps */
4003                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4004                         if (ret_val)
4005                                 return ret_val;
4006
4007                         /* Write a value 11 (block Erase) in Flash
4008                          * Cycle field in hw flash control
4009                          */
4010                         hsflctl.regval =
4011                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4012
4013                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4014                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4015                                                 hsflctl.regval);
4016
4017                         /* Write the last 24 bits of an index within the
4018                          * block into Flash Linear address field in Flash
4019                          * Address.
4020                          */
4021                         flash_linear_addr += (j * sector_size);
4022                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4023                                               flash_linear_addr);
4024
4025                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4026                         if (ret_val == E1000_SUCCESS)
4027                                 break;
4028
4029                         /* Check if FCERR is set to 1.  If 1,
4030                          * clear it and try the whole sequence
4031                          * a few more times else Done
4032                          */
4033                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4034                                                       ICH_FLASH_HSFSTS);
4035                         if (hsfsts.hsf_status.flcerr)
4036                                 /* repeat for some time before giving up */
4037                                 continue;
4038                         else if (!hsfsts.hsf_status.flcdone)
4039                                 return ret_val;
4040                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4041         }
4042
4043         return E1000_SUCCESS;
4044 }
4045
4046 /**
4047  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4048  *  @hw: pointer to the HW structure
4049  *  @data: Pointer to the LED settings
4050  *
4051  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4052  *  settings is all 0's or F's, set the LED default to a valid LED default
4053  *  setting.
4054  **/
4055 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4056 {
4057         s32 ret_val;
4058
4059         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4060
4061         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4062         if (ret_val) {
4063                 DEBUGOUT("NVM Read Error\n");
4064                 return ret_val;
4065         }
4066
4067         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4068                 *data = ID_LED_DEFAULT_ICH8LAN;
4069
4070         return E1000_SUCCESS;
4071 }
4072
4073 /**
4074  *  e1000_id_led_init_pchlan - store LED configurations
4075  *  @hw: pointer to the HW structure
4076  *
4077  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4078  *  the PHY LED configuration register.
4079  *
4080  *  PCH also does not have an "always on" or "always off" mode which
4081  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4082  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4083  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4084  *  link based on logic in e1000_led_[on|off]_pchlan().
4085  **/
4086 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4087 {
4088         struct e1000_mac_info *mac = &hw->mac;
4089         s32 ret_val;
4090         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4091         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4092         u16 data, i, temp, shift;
4093
4094         DEBUGFUNC("e1000_id_led_init_pchlan");
4095
4096         /* Get default ID LED modes */
4097         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4098         if (ret_val)
4099                 return ret_val;
4100
4101         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4102         mac->ledctl_mode1 = mac->ledctl_default;
4103         mac->ledctl_mode2 = mac->ledctl_default;
4104
4105         for (i = 0; i < 4; i++) {
4106                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4107                 shift = (i * 5);
4108                 switch (temp) {
4109                 case ID_LED_ON1_DEF2:
4110                 case ID_LED_ON1_ON2:
4111                 case ID_LED_ON1_OFF2:
4112                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4113                         mac->ledctl_mode1 |= (ledctl_on << shift);
4114                         break;
4115                 case ID_LED_OFF1_DEF2:
4116                 case ID_LED_OFF1_ON2:
4117                 case ID_LED_OFF1_OFF2:
4118                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4119                         mac->ledctl_mode1 |= (ledctl_off << shift);
4120                         break;
4121                 default:
4122                         /* Do nothing */
4123                         break;
4124                 }
4125                 switch (temp) {
4126                 case ID_LED_DEF1_ON2:
4127                 case ID_LED_ON1_ON2:
4128                 case ID_LED_OFF1_ON2:
4129                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4130                         mac->ledctl_mode2 |= (ledctl_on << shift);
4131                         break;
4132                 case ID_LED_DEF1_OFF2:
4133                 case ID_LED_ON1_OFF2:
4134                 case ID_LED_OFF1_OFF2:
4135                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4136                         mac->ledctl_mode2 |= (ledctl_off << shift);
4137                         break;
4138                 default:
4139                         /* Do nothing */
4140                         break;
4141                 }
4142         }
4143
4144         return E1000_SUCCESS;
4145 }
4146
4147 /**
4148  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4149  *  @hw: pointer to the HW structure
4150  *
4151  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4152  *  register, so the the bus width is hard coded.
4153  **/
4154 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4155 {
4156         struct e1000_bus_info *bus = &hw->bus;
4157         s32 ret_val;
4158
4159         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4160
4161         ret_val = e1000_get_bus_info_pcie_generic(hw);
4162
4163         /* ICH devices are "PCI Express"-ish.  They have
4164          * a configuration space, but do not contain
4165          * PCI Express Capability registers, so bus width
4166          * must be hardcoded.
4167          */
4168         if (bus->width == e1000_bus_width_unknown)
4169                 bus->width = e1000_bus_width_pcie_x1;
4170
4171         return ret_val;
4172 }
4173
4174 /**
4175  *  e1000_reset_hw_ich8lan - Reset the hardware
4176  *  @hw: pointer to the HW structure
4177  *
4178  *  Does a full reset of the hardware which includes a reset of the PHY and
4179  *  MAC.
4180  **/
4181 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4182 {
4183         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4184         u16 kum_cfg;
4185         u32 ctrl, reg;
4186         s32 ret_val;
4187
4188         DEBUGFUNC("e1000_reset_hw_ich8lan");
4189
4190         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4191          * on the last TLP read/write transaction when MAC is reset.
4192          */
4193         ret_val = e1000_disable_pcie_master_generic(hw);
4194         if (ret_val)
4195                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4196
4197         DEBUGOUT("Masking off all interrupts\n");
4198         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4199
4200         /* Disable the Transmit and Receive units.  Then delay to allow
4201          * any pending transactions to complete before we hit the MAC
4202          * with the global reset.
4203          */
4204         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4205         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4206         E1000_WRITE_FLUSH(hw);
4207
4208         msec_delay(10);
4209
4210         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4211         if (hw->mac.type == e1000_ich8lan) {
4212                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4213                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4214                 /* Set Packet Buffer Size to 16k. */
4215                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4216         }
4217
4218         if (hw->mac.type == e1000_pchlan) {
4219                 /* Save the NVM K1 bit setting*/
4220                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4221                 if (ret_val)
4222                         return ret_val;
4223
4224                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4225                         dev_spec->nvm_k1_enabled = true;
4226                 else
4227                         dev_spec->nvm_k1_enabled = false;
4228         }
4229
4230         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4231
4232         if (!hw->phy.ops.check_reset_block(hw)) {
4233                 /* Full-chip reset requires MAC and PHY reset at the same
4234                  * time to make sure the interface between MAC and the
4235                  * external PHY is reset.
4236                  */
4237                 ctrl |= E1000_CTRL_PHY_RST;
4238
4239                 /* Gate automatic PHY configuration by hardware on
4240                  * non-managed 82579
4241                  */
4242                 if ((hw->mac.type == e1000_pch2lan) &&
4243                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4244                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4245         }
4246         ret_val = e1000_acquire_swflag_ich8lan(hw);
4247         DEBUGOUT("Issuing a global reset to ich8lan\n");
4248         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4249         /* cannot issue a flush here because it hangs the hardware */
4250         msec_delay(20);
4251
4252         /* Set Phy Config Counter to 50msec */
4253         if (hw->mac.type == e1000_pch2lan) {
4254                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4255                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4256                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4257                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4258         }
4259
4260         if (!ret_val)
4261                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4262
4263         if (ctrl & E1000_CTRL_PHY_RST) {
4264                 ret_val = hw->phy.ops.get_cfg_done(hw);
4265                 if (ret_val)
4266                         return ret_val;
4267
4268                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4269                 if (ret_val)
4270                         return ret_val;
4271         }
4272
4273         /* For PCH, this write will make sure that any noise
4274          * will be detected as a CRC error and be dropped rather than show up
4275          * as a bad packet to the DMA engine.
4276          */
4277         if (hw->mac.type == e1000_pchlan)
4278                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4279
4280         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4281         E1000_READ_REG(hw, E1000_ICR);
4282
4283         reg = E1000_READ_REG(hw, E1000_KABGTXD);
4284         reg |= E1000_KABGTXD_BGSQLBIAS;
4285         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4286
4287         return E1000_SUCCESS;
4288 }
4289
4290 /**
4291  *  e1000_init_hw_ich8lan - Initialize the hardware
4292  *  @hw: pointer to the HW structure
4293  *
4294  *  Prepares the hardware for transmit and receive by doing the following:
4295  *   - initialize hardware bits
4296  *   - initialize LED identification
4297  *   - setup receive address registers
4298  *   - setup flow control
4299  *   - setup transmit descriptors
4300  *   - clear statistics
4301  **/
4302 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4303 {
4304         struct e1000_mac_info *mac = &hw->mac;
4305         u32 ctrl_ext, txdctl, snoop;
4306         s32 ret_val;
4307         u16 i;
4308
4309         DEBUGFUNC("e1000_init_hw_ich8lan");
4310
4311         e1000_initialize_hw_bits_ich8lan(hw);
4312
4313         /* Initialize identification LED */
4314         ret_val = mac->ops.id_led_init(hw);
4315         /* An error is not fatal and we should not stop init due to this */
4316         if (ret_val)
4317                 DEBUGOUT("Error initializing identification LED\n");
4318
4319         /* Setup the receive address. */
4320         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4321
4322         /* Zero out the Multicast HASH table */
4323         DEBUGOUT("Zeroing the MTA\n");
4324         for (i = 0; i < mac->mta_reg_count; i++)
4325                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4326
4327         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4328          * the ME.  Disable wakeup by clearing the host wakeup bit.
4329          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4330          */
4331         if (hw->phy.type == e1000_phy_82578) {
4332                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4333                 i &= ~BM_WUC_HOST_WU_BIT;
4334                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4335                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4336                 if (ret_val)
4337                         return ret_val;
4338         }
4339
4340         /* Setup link and flow control */
4341         ret_val = mac->ops.setup_link(hw);
4342
4343         /* Set the transmit descriptor write-back policy for both queues */
4344         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4345         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4346                   E1000_TXDCTL_FULL_TX_DESC_WB);
4347         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4348                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4349         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4350         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4351         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4352                   E1000_TXDCTL_FULL_TX_DESC_WB);
4353         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4354                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4355         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4356
4357         /* ICH8 has opposite polarity of no_snoop bits.
4358          * By default, we should use snoop behavior.
4359          */
4360         if (mac->type == e1000_ich8lan)
4361                 snoop = PCIE_ICH8_SNOOP_ALL;
4362         else
4363                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4364         e1000_set_pcie_no_snoop_generic(hw, snoop);
4365
4366         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4367         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4368         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4369
4370         /* Clear all of the statistics registers (clear on read).  It is
4371          * important that we do this after we have tried to establish link
4372          * because the symbol error count will increment wildly if there
4373          * is no link.
4374          */
4375         e1000_clear_hw_cntrs_ich8lan(hw);
4376
4377         return ret_val;
4378 }
4379
4380 /**
4381  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4382  *  @hw: pointer to the HW structure
4383  *
4384  *  Sets/Clears required hardware bits necessary for correctly setting up the
4385  *  hardware for transmit and receive.
4386  **/
4387 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4388 {
4389         u32 reg;
4390
4391         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4392
4393         /* Extended Device Control */
4394         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4395         reg |= (1 << 22);
4396         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4397         if (hw->mac.type >= e1000_pchlan)
4398                 reg |= E1000_CTRL_EXT_PHYPDEN;
4399         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4400
4401         /* Transmit Descriptor Control 0 */
4402         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4403         reg |= (1 << 22);
4404         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4405
4406         /* Transmit Descriptor Control 1 */
4407         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4408         reg |= (1 << 22);
4409         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4410
4411         /* Transmit Arbitration Control 0 */
4412         reg = E1000_READ_REG(hw, E1000_TARC(0));
4413         if (hw->mac.type == e1000_ich8lan)
4414                 reg |= (1 << 28) | (1 << 29);
4415         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4416         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4417
4418         /* Transmit Arbitration Control 1 */
4419         reg = E1000_READ_REG(hw, E1000_TARC(1));
4420         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4421                 reg &= ~(1 << 28);
4422         else
4423                 reg |= (1 << 28);
4424         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4425         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4426
4427         /* Device Status */
4428         if (hw->mac.type == e1000_ich8lan) {
4429                 reg = E1000_READ_REG(hw, E1000_STATUS);
4430                 reg &= ~(1 << 31);
4431                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4432         }
4433
4434         /* work-around descriptor data corruption issue during nfs v2 udp
4435          * traffic, just disable the nfs filtering capability
4436          */
4437         reg = E1000_READ_REG(hw, E1000_RFCTL);
4438         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4439
4440         /* Disable IPv6 extension header parsing because some malformed
4441          * IPv6 headers can hang the Rx.
4442          */
4443         if (hw->mac.type == e1000_ich8lan)
4444                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4445         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4446
4447         /* Enable ECC on Lynxpoint */
4448         if (hw->mac.type == e1000_pch_lpt) {
4449                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4450                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4451                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4452
4453                 reg = E1000_READ_REG(hw, E1000_CTRL);
4454                 reg |= E1000_CTRL_MEHE;
4455                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4456         }
4457
4458         return;
4459 }
4460
4461 /**
4462  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4463  *  @hw: pointer to the HW structure
4464  *
4465  *  Determines which flow control settings to use, then configures flow
4466  *  control.  Calls the appropriate media-specific link configuration
4467  *  function.  Assuming the adapter has a valid link partner, a valid link
4468  *  should be established.  Assumes the hardware has previously been reset
4469  *  and the transmitter and receiver are not enabled.
4470  **/
4471 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4472 {
4473         s32 ret_val;
4474
4475         DEBUGFUNC("e1000_setup_link_ich8lan");
4476
4477         if (hw->phy.ops.check_reset_block(hw))
4478                 return E1000_SUCCESS;
4479
4480         /* ICH parts do not have a word in the NVM to determine
4481          * the default flow control setting, so we explicitly
4482          * set it to full.
4483          */
4484         if (hw->fc.requested_mode == e1000_fc_default)
4485                 hw->fc.requested_mode = e1000_fc_full;
4486
4487         /* Save off the requested flow control mode for use later.  Depending
4488          * on the link partner's capabilities, we may or may not use this mode.
4489          */
4490         hw->fc.current_mode = hw->fc.requested_mode;
4491
4492         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4493                 hw->fc.current_mode);
4494
4495         /* Continue to configure the copper link. */
4496         ret_val = hw->mac.ops.setup_physical_interface(hw);
4497         if (ret_val)
4498                 return ret_val;
4499
4500         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4501         if ((hw->phy.type == e1000_phy_82578) ||
4502             (hw->phy.type == e1000_phy_82579) ||
4503             (hw->phy.type == e1000_phy_i217) ||
4504             (hw->phy.type == e1000_phy_82577)) {
4505                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4506
4507                 ret_val = hw->phy.ops.write_reg(hw,
4508                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
4509                                              hw->fc.pause_time);
4510                 if (ret_val)
4511                         return ret_val;
4512         }
4513
4514         return e1000_set_fc_watermarks_generic(hw);
4515 }
4516
4517 /**
4518  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4519  *  @hw: pointer to the HW structure
4520  *
4521  *  Configures the kumeran interface to the PHY to wait the appropriate time
4522  *  when polling the PHY, then call the generic setup_copper_link to finish
4523  *  configuring the copper link.
4524  **/
4525 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4526 {
4527         u32 ctrl;
4528         s32 ret_val;
4529         u16 reg_data;
4530
4531         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4532
4533         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4534         ctrl |= E1000_CTRL_SLU;
4535         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4536         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4537
4538         /* Set the mac to wait the maximum time between each iteration
4539          * and increase the max iterations when polling the phy;
4540          * this fixes erroneous timeouts at 10Mbps.
4541          */
4542         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4543                                                0xFFFF);
4544         if (ret_val)
4545                 return ret_val;
4546         ret_val = e1000_read_kmrn_reg_generic(hw,
4547                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
4548                                               &reg_data);
4549         if (ret_val)
4550                 return ret_val;
4551         reg_data |= 0x3F;
4552         ret_val = e1000_write_kmrn_reg_generic(hw,
4553                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
4554                                                reg_data);
4555         if (ret_val)
4556                 return ret_val;
4557
4558         switch (hw->phy.type) {
4559         case e1000_phy_igp_3:
4560                 ret_val = e1000_copper_link_setup_igp(hw);
4561                 if (ret_val)
4562                         return ret_val;
4563                 break;
4564         case e1000_phy_bm:
4565         case e1000_phy_82578:
4566                 ret_val = e1000_copper_link_setup_m88(hw);
4567                 if (ret_val)
4568                         return ret_val;
4569                 break;
4570         case e1000_phy_82577:
4571         case e1000_phy_82579:
4572                 ret_val = e1000_copper_link_setup_82577(hw);
4573                 if (ret_val)
4574                         return ret_val;
4575                 break;
4576         case e1000_phy_ife:
4577                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4578                                                &reg_data);
4579                 if (ret_val)
4580                         return ret_val;
4581
4582                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4583
4584                 switch (hw->phy.mdix) {
4585                 case 1:
4586                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4587                         break;
4588                 case 2:
4589                         reg_data |= IFE_PMC_FORCE_MDIX;
4590                         break;
4591                 case 0:
4592                 default:
4593                         reg_data |= IFE_PMC_AUTO_MDIX;
4594                         break;
4595                 }
4596                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4597                                                 reg_data);
4598                 if (ret_val)
4599                         return ret_val;
4600                 break;
4601         default:
4602                 break;
4603         }
4604
4605         return e1000_setup_copper_link_generic(hw);
4606 }
4607
4608 /**
4609  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4610  *  @hw: pointer to the HW structure
4611  *
4612  *  Calls the PHY specific link setup function and then calls the
4613  *  generic setup_copper_link to finish configuring the link for
4614  *  Lynxpoint PCH devices
4615  **/
4616 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4617 {
4618         u32 ctrl;
4619         s32 ret_val;
4620
4621         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4622
4623         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4624         ctrl |= E1000_CTRL_SLU;
4625         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4626         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4627
4628         ret_val = e1000_copper_link_setup_82577(hw);
4629         if (ret_val)
4630                 return ret_val;
4631
4632         return e1000_setup_copper_link_generic(hw);
4633 }
4634
4635 /**
4636  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4637  *  @hw: pointer to the HW structure
4638  *  @speed: pointer to store current link speed
4639  *  @duplex: pointer to store the current link duplex
4640  *
4641  *  Calls the generic get_speed_and_duplex to retrieve the current link
4642  *  information and then calls the Kumeran lock loss workaround for links at
4643  *  gigabit speeds.
4644  **/
4645 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4646                                           u16 *duplex)
4647 {
4648         s32 ret_val;
4649
4650         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4651
4652         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4653         if (ret_val)
4654                 return ret_val;
4655
4656         if ((hw->mac.type == e1000_ich8lan) &&
4657             (hw->phy.type == e1000_phy_igp_3) &&
4658             (*speed == SPEED_1000)) {
4659                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4660         }
4661
4662         return ret_val;
4663 }
4664
4665 /**
4666  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4667  *  @hw: pointer to the HW structure
4668  *
4669  *  Work-around for 82566 Kumeran PCS lock loss:
4670  *  On link status change (i.e. PCI reset, speed change) and link is up and
4671  *  speed is gigabit-
4672  *    0) if workaround is optionally disabled do nothing
4673  *    1) wait 1ms for Kumeran link to come up
4674  *    2) check Kumeran Diagnostic register PCS lock loss bit
4675  *    3) if not set the link is locked (all is good), otherwise...
4676  *    4) reset the PHY
4677  *    5) repeat up to 10 times
4678  *  Note: this is only called for IGP3 copper when speed is 1gb.
4679  **/
4680 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4681 {
4682         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4683         u32 phy_ctrl;
4684         s32 ret_val;
4685         u16 i, data;
4686         bool link;
4687
4688         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4689
4690         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4691                 return E1000_SUCCESS;
4692
4693         /* Make sure link is up before proceeding.  If not just return.
4694          * Attempting this while link is negotiating fouled up link
4695          * stability
4696          */
4697         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4698         if (!link)
4699                 return E1000_SUCCESS;
4700
4701         for (i = 0; i < 10; i++) {
4702                 /* read once to clear */
4703                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4704                 if (ret_val)
4705                         return ret_val;
4706                 /* and again to get new status */
4707                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4708                 if (ret_val)
4709                         return ret_val;
4710
4711                 /* check for PCS lock */
4712                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4713                         return E1000_SUCCESS;
4714
4715                 /* Issue PHY reset */
4716                 hw->phy.ops.reset(hw);
4717                 msec_delay_irq(5);
4718         }
4719         /* Disable GigE link negotiation */
4720         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4721         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4722                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4723         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4724
4725         /* Call gig speed drop workaround on Gig disable before accessing
4726          * any PHY registers
4727          */
4728         e1000_gig_downshift_workaround_ich8lan(hw);
4729
4730         /* unable to acquire PCS lock */
4731         return -E1000_ERR_PHY;
4732 }
4733
4734 /**
4735  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4736  *  @hw: pointer to the HW structure
4737  *  @state: boolean value used to set the current Kumeran workaround state
4738  *
4739  *  If ICH8, set the current Kumeran workaround state (enabled - true
4740  *  /disabled - false).
4741  **/
4742 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4743                                                  bool state)
4744 {
4745         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4746
4747         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4748
4749         if (hw->mac.type != e1000_ich8lan) {
4750                 DEBUGOUT("Workaround applies to ICH8 only.\n");
4751                 return;
4752         }
4753
4754         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4755
4756         return;
4757 }
4758
4759 /**
4760  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4761  *  @hw: pointer to the HW structure
4762  *
4763  *  Workaround for 82566 power-down on D3 entry:
4764  *    1) disable gigabit link
4765  *    2) write VR power-down enable
4766  *    3) read it back
4767  *  Continue if successful, else issue LCD reset and repeat
4768  **/
4769 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4770 {
4771         u32 reg;
4772         u16 data;
4773         u8  retry = 0;
4774
4775         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4776
4777         if (hw->phy.type != e1000_phy_igp_3)
4778                 return;
4779
4780         /* Try the workaround twice (if needed) */
4781         do {
4782                 /* Disable link */
4783                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4784                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4785                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4786                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4787
4788                 /* Call gig speed drop workaround on Gig disable before
4789                  * accessing any PHY registers
4790                  */
4791                 if (hw->mac.type == e1000_ich8lan)
4792                         e1000_gig_downshift_workaround_ich8lan(hw);
4793
4794                 /* Write VR power-down enable */
4795                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4796                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4797                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4798                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4799
4800                 /* Read it back and test */
4801                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4802                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4803                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4804                         break;
4805
4806                 /* Issue PHY reset and repeat at most one more time */
4807                 reg = E1000_READ_REG(hw, E1000_CTRL);
4808                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4809                 retry++;
4810         } while (retry);
4811 }
4812
4813 /**
4814  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4815  *  @hw: pointer to the HW structure
4816  *
4817  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4818  *  LPLU, Gig disable, MDIC PHY reset):
4819  *    1) Set Kumeran Near-end loopback
4820  *    2) Clear Kumeran Near-end loopback
4821  *  Should only be called for ICH8[m] devices with any 1G Phy.
4822  **/
4823 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4824 {
4825         s32 ret_val;
4826         u16 reg_data;
4827
4828         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4829
4830         if ((hw->mac.type != e1000_ich8lan) ||
4831             (hw->phy.type == e1000_phy_ife))
4832                 return;
4833
4834         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4835                                               &reg_data);
4836         if (ret_val)
4837                 return;
4838         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4839         ret_val = e1000_write_kmrn_reg_generic(hw,
4840                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
4841                                                reg_data);
4842         if (ret_val)
4843                 return;
4844         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4845         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4846                                      reg_data);
4847 }
4848
4849 /**
4850  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4851  *  @hw: pointer to the HW structure
4852  *
4853  *  During S0 to Sx transition, it is possible the link remains at gig
4854  *  instead of negotiating to a lower speed.  Before going to Sx, set
4855  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4856  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4857  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4858  *  needs to be written.
4859  *  Parts that support (and are linked to a partner which support) EEE in
4860  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4861  *  than 10Mbps w/o EEE.
4862  **/
4863 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4864 {
4865         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4866         u32 phy_ctrl;
4867         s32 ret_val;
4868
4869         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4870
4871         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4872         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4873
4874         if (hw->phy.type == e1000_phy_i217) {
4875                 u16 phy_reg, device_id = hw->device_id;
4876
4877                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4878                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4879                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4880                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4881                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4882
4883                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4884                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4885                 }
4886
4887                 ret_val = hw->phy.ops.acquire(hw);
4888                 if (ret_val)
4889                         goto out;
4890
4891                 if (!dev_spec->eee_disable) {
4892                         u16 eee_advert;
4893
4894                         ret_val =
4895                             e1000_read_emi_reg_locked(hw,
4896                                                       I217_EEE_ADVERTISEMENT,
4897                                                       &eee_advert);
4898                         if (ret_val)
4899                                 goto release;
4900
4901                         /* Disable LPLU if both link partners support 100BaseT
4902                          * EEE and 100Full is advertised on both ends of the
4903                          * link, and enable Auto Enable LPI since there will
4904                          * be no driver to enable LPI while in Sx.
4905                          */
4906                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4907                             (dev_spec->eee_lp_ability &
4908                              I82579_EEE_100_SUPPORTED) &&
4909                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4910                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4911                                               E1000_PHY_CTRL_NOND0A_LPLU);
4912
4913                                 /* Set Auto Enable LPI after link up */
4914                                 hw->phy.ops.read_reg_locked(hw,
4915                                                             I217_LPI_GPIO_CTRL,
4916                                                             &phy_reg);
4917                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4918                                 hw->phy.ops.write_reg_locked(hw,
4919                                                              I217_LPI_GPIO_CTRL,
4920                                                              phy_reg);
4921                         }
4922                 }
4923
4924                 /* For i217 Intel Rapid Start Technology support,
4925                  * when the system is going into Sx and no manageability engine
4926                  * is present, the driver must configure proxy to reset only on
4927                  * power good.  LPI (Low Power Idle) state must also reset only
4928                  * on power good, as well as the MTA (Multicast table array).
4929                  * The SMBus release must also be disabled on LCD reset.
4930                  */
4931                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4932                       E1000_ICH_FWSM_FW_VALID)) {
4933                         /* Enable proxy to reset only on power good. */
4934                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4935                                                     &phy_reg);
4936                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4937                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4938                                                      phy_reg);
4939
4940                         /* Set bit enable LPI (EEE) to reset only on
4941                          * power good.
4942                         */
4943                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4944                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4945                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4946
4947                         /* Disable the SMB release on LCD reset. */
4948                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4949                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4950                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4951                 }
4952
4953                 /* Enable MTA to reset for Intel Rapid Start Technology
4954                  * Support
4955                  */
4956                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4957                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4958                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4959
4960 release:
4961                 hw->phy.ops.release(hw);
4962         }
4963 out:
4964         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4965
4966         if (hw->mac.type == e1000_ich8lan)
4967                 e1000_gig_downshift_workaround_ich8lan(hw);
4968
4969         if (hw->mac.type >= e1000_pchlan) {
4970                 e1000_oem_bits_config_ich8lan(hw, false);
4971
4972                 /* Reset PHY to activate OEM bits on 82577/8 */
4973                 if (hw->mac.type == e1000_pchlan)
4974                         e1000_phy_hw_reset_generic(hw);
4975
4976                 ret_val = hw->phy.ops.acquire(hw);
4977                 if (ret_val)
4978                         return;
4979                 e1000_write_smbus_addr(hw);
4980                 hw->phy.ops.release(hw);
4981         }
4982
4983         return;
4984 }
4985
4986 /**
4987  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4988  *  @hw: pointer to the HW structure
4989  *
4990  *  During Sx to S0 transitions on non-managed devices or managed devices
4991  *  on which PHY resets are not blocked, if the PHY registers cannot be
4992  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4993  *  the PHY.
4994  *  On i217, setup Intel Rapid Start Technology.
4995  **/
4996 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4997 {
4998         s32 ret_val;
4999
5000         DEBUGFUNC("e1000_resume_workarounds_pchlan");
5001         if (hw->mac.type < e1000_pch2lan)
5002                 return E1000_SUCCESS;
5003
5004         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5005         if (ret_val) {
5006                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5007                 return ret_val;
5008         }
5009
5010         /* For i217 Intel Rapid Start Technology support when the system
5011          * is transitioning from Sx and no manageability engine is present
5012          * configure SMBus to restore on reset, disable proxy, and enable
5013          * the reset on MTA (Multicast table array).
5014          */
5015         if (hw->phy.type == e1000_phy_i217) {
5016                 u16 phy_reg;
5017
5018                 ret_val = hw->phy.ops.acquire(hw);
5019                 if (ret_val) {
5020                         DEBUGOUT("Failed to setup iRST\n");
5021                         return ret_val;
5022                 }
5023
5024                 /* Clear Auto Enable LPI after link up */
5025                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5026                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5027                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5028
5029                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5030                     E1000_ICH_FWSM_FW_VALID)) {
5031                         /* Restore clear on SMB if no manageability engine
5032                          * is present
5033                          */
5034                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5035                                                               &phy_reg);
5036                         if (ret_val)
5037                                 goto release;
5038                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5039                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5040
5041                         /* Disable Proxy */
5042                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5043                 }
5044                 /* Enable reset on MTA */
5045                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5046                                                       &phy_reg);
5047                 if (ret_val)
5048                         goto release;
5049                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5050                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5051 release:
5052                 if (ret_val)
5053                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5054                 hw->phy.ops.release(hw);
5055                 return ret_val;
5056         }
5057         return E1000_SUCCESS;
5058 }
5059
5060 /**
5061  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5062  *  @hw: pointer to the HW structure
5063  *
5064  *  Return the LED back to the default configuration.
5065  **/
5066 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5067 {
5068         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5069
5070         if (hw->phy.type == e1000_phy_ife)
5071                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5072                                              0);
5073
5074         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5075         return E1000_SUCCESS;
5076 }
5077
5078 /**
5079  *  e1000_led_on_ich8lan - Turn LEDs on
5080  *  @hw: pointer to the HW structure
5081  *
5082  *  Turn on the LEDs.
5083  **/
5084 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5085 {
5086         DEBUGFUNC("e1000_led_on_ich8lan");
5087
5088         if (hw->phy.type == e1000_phy_ife)
5089                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5090                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5091
5092         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5093         return E1000_SUCCESS;
5094 }
5095
5096 /**
5097  *  e1000_led_off_ich8lan - Turn LEDs off
5098  *  @hw: pointer to the HW structure
5099  *
5100  *  Turn off the LEDs.
5101  **/
5102 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5103 {
5104         DEBUGFUNC("e1000_led_off_ich8lan");
5105
5106         if (hw->phy.type == e1000_phy_ife)
5107                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5108                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5109
5110         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5111         return E1000_SUCCESS;
5112 }
5113
5114 /**
5115  *  e1000_setup_led_pchlan - Configures SW controllable LED
5116  *  @hw: pointer to the HW structure
5117  *
5118  *  This prepares the SW controllable LED for use.
5119  **/
5120 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5121 {
5122         DEBUGFUNC("e1000_setup_led_pchlan");
5123
5124         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5125                                      (u16)hw->mac.ledctl_mode1);
5126 }
5127
5128 /**
5129  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5130  *  @hw: pointer to the HW structure
5131  *
5132  *  Return the LED back to the default configuration.
5133  **/
5134 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5135 {
5136         DEBUGFUNC("e1000_cleanup_led_pchlan");
5137
5138         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5139                                      (u16)hw->mac.ledctl_default);
5140 }
5141
5142 /**
5143  *  e1000_led_on_pchlan - Turn LEDs on
5144  *  @hw: pointer to the HW structure
5145  *
5146  *  Turn on the LEDs.
5147  **/
5148 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5149 {
5150         u16 data = (u16)hw->mac.ledctl_mode2;
5151         u32 i, led;
5152
5153         DEBUGFUNC("e1000_led_on_pchlan");
5154
5155         /* If no link, then turn LED on by setting the invert bit
5156          * for each LED that's mode is "link_up" in ledctl_mode2.
5157          */
5158         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5159                 for (i = 0; i < 3; i++) {
5160                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5161                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5162                             E1000_LEDCTL_MODE_LINK_UP)
5163                                 continue;
5164                         if (led & E1000_PHY_LED0_IVRT)
5165                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5166                         else
5167                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5168                 }
5169         }
5170
5171         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5172 }
5173
5174 /**
5175  *  e1000_led_off_pchlan - Turn LEDs off
5176  *  @hw: pointer to the HW structure
5177  *
5178  *  Turn off the LEDs.
5179  **/
5180 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5181 {
5182         u16 data = (u16)hw->mac.ledctl_mode1;
5183         u32 i, led;
5184
5185         DEBUGFUNC("e1000_led_off_pchlan");
5186
5187         /* If no link, then turn LED off by clearing the invert bit
5188          * for each LED that's mode is "link_up" in ledctl_mode1.
5189          */
5190         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5191                 for (i = 0; i < 3; i++) {
5192                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5193                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5194                             E1000_LEDCTL_MODE_LINK_UP)
5195                                 continue;
5196                         if (led & E1000_PHY_LED0_IVRT)
5197                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5198                         else
5199                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5200                 }
5201         }
5202
5203         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5204 }
5205
5206 /**
5207  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5208  *  @hw: pointer to the HW structure
5209  *
5210  *  Read appropriate register for the config done bit for completion status
5211  *  and configure the PHY through s/w for EEPROM-less parts.
5212  *
5213  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5214  *  config done bit, so only an error is logged and continues.  If we were
5215  *  to return with error, EEPROM-less silicon would not be able to be reset
5216  *  or change link.
5217  **/
5218 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5219 {
5220         s32 ret_val = E1000_SUCCESS;
5221         u32 bank = 0;
5222         u32 status;
5223
5224         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5225
5226         e1000_get_cfg_done_generic(hw);
5227
5228         /* Wait for indication from h/w that it has completed basic config */
5229         if (hw->mac.type >= e1000_ich10lan) {
5230                 e1000_lan_init_done_ich8lan(hw);
5231         } else {
5232                 ret_val = e1000_get_auto_rd_done_generic(hw);
5233                 if (ret_val) {
5234                         /* When auto config read does not complete, do not
5235                          * return with an error. This can happen in situations
5236                          * where there is no eeprom and prevents getting link.
5237                          */
5238                         DEBUGOUT("Auto Read Done did not complete\n");
5239                         ret_val = E1000_SUCCESS;
5240                 }
5241         }
5242
5243         /* Clear PHY Reset Asserted bit */
5244         status = E1000_READ_REG(hw, E1000_STATUS);
5245         if (status & E1000_STATUS_PHYRA)
5246                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5247         else
5248                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5249
5250         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5251         if (hw->mac.type <= e1000_ich9lan) {
5252                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5253                     (hw->phy.type == e1000_phy_igp_3)) {
5254                         e1000_phy_init_script_igp3(hw);
5255                 }
5256         } else {
5257                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5258                         /* Maybe we should do a basic PHY config */
5259                         DEBUGOUT("EEPROM not present\n");
5260                         ret_val = -E1000_ERR_CONFIG;
5261                 }
5262         }
5263
5264         return ret_val;
5265 }
5266
5267 /**
5268  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5269  * @hw: pointer to the HW structure
5270  *
5271  * In the case of a PHY power down to save power, or to turn off link during a
5272  * driver unload, or wake on lan is not enabled, remove the link.
5273  **/
5274 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5275 {
5276         /* If the management interface is not enabled, then power down */
5277         if (!(hw->mac.ops.check_mng_mode(hw) ||
5278               hw->phy.ops.check_reset_block(hw)))
5279                 e1000_power_down_phy_copper(hw);
5280
5281         return;
5282 }
5283
5284 /**
5285  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5286  *  @hw: pointer to the HW structure
5287  *
5288  *  Clears hardware counters specific to the silicon family and calls
5289  *  clear_hw_cntrs_generic to clear all general purpose counters.
5290  **/
5291 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5292 {
5293         u16 phy_data;
5294         s32 ret_val;
5295
5296         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5297
5298         e1000_clear_hw_cntrs_base_generic(hw);
5299
5300         E1000_READ_REG(hw, E1000_ALGNERRC);
5301         E1000_READ_REG(hw, E1000_RXERRC);
5302         E1000_READ_REG(hw, E1000_TNCRS);
5303         E1000_READ_REG(hw, E1000_CEXTERR);
5304         E1000_READ_REG(hw, E1000_TSCTC);
5305         E1000_READ_REG(hw, E1000_TSCTFC);
5306
5307         E1000_READ_REG(hw, E1000_MGTPRC);
5308         E1000_READ_REG(hw, E1000_MGTPDC);
5309         E1000_READ_REG(hw, E1000_MGTPTC);
5310
5311         E1000_READ_REG(hw, E1000_IAC);
5312         E1000_READ_REG(hw, E1000_ICRXOC);
5313
5314         /* Clear PHY statistics registers */
5315         if ((hw->phy.type == e1000_phy_82578) ||
5316             (hw->phy.type == e1000_phy_82579) ||
5317             (hw->phy.type == e1000_phy_i217) ||
5318             (hw->phy.type == e1000_phy_82577)) {
5319                 ret_val = hw->phy.ops.acquire(hw);
5320                 if (ret_val)
5321                         return;
5322                 ret_val = hw->phy.ops.set_page(hw,
5323                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5324                 if (ret_val)
5325                         goto release;
5326                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5327                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5328                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5329                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5330                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5331                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5332                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5333                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5334                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5335                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5336                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5337                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5338                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5339                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5340 release:
5341                 hw->phy.ops.release(hw);
5342         }
5343 }
5344
5345 /**
5346  *  e1000_configure_k0s_lpt - Configure K0s power state
5347  *  @hw: pointer to the HW structure
5348  *  @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
5349  *      0 corresponds to 128ns, each value over 0 doubles the duration.
5350  *  @min_time: Minimum Tx idle period allowed  - valid values are 0 to 4.
5351  *      0 corresponds to 128ns, each value over 0 doubles the duration.
5352  *
5353  *  Configure the K1 power state based on the provided parameter.
5354  *  Assumes semaphore already acquired.
5355  *
5356  *  Success returns 0, Failure returns:
5357  *      -E1000_ERR_PHY (-2) in case of access error
5358  *      -E1000_ERR_PARAM (-4) in case of parameters error
5359  **/
5360 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
5361 {
5362         s32 ret_val;
5363         u16 kmrn_reg = 0;
5364
5365         DEBUGFUNC("e1000_configure_k0s_lpt");
5366
5367         if (entry_latency > 3 || min_time > 4)
5368                 return -E1000_ERR_PARAM;
5369
5370         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5371                                              &kmrn_reg);
5372         if (ret_val)
5373                 return ret_val;
5374
5375         /* for now don't touch the latency */
5376         kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
5377         kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
5378
5379         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5380                                               kmrn_reg);
5381         if (ret_val)
5382                 return ret_val;
5383
5384         return E1000_SUCCESS;
5385 }