1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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32 ***************************************************************************/
34 /* 82562G 10/100 Network Connection
35 * 82562G-2 10/100 Network Connection
36 * 82562GT 10/100 Network Connection
37 * 82562GT-2 10/100 Network Connection
38 * 82562V 10/100 Network Connection
39 * 82562V-2 10/100 Network Connection
40 * 82566DC-2 Gigabit Network Connection
41 * 82566DC Gigabit Network Connection
42 * 82566DM-2 Gigabit Network Connection
43 * 82566DM Gigabit Network Connection
44 * 82566MC Gigabit Network Connection
45 * 82566MM Gigabit Network Connection
46 * 82567LM Gigabit Network Connection
47 * 82567LF Gigabit Network Connection
48 * 82567V Gigabit Network Connection
49 * 82567LM-2 Gigabit Network Connection
50 * 82567LF-2 Gigabit Network Connection
51 * 82567V-2 Gigabit Network Connection
52 * 82567LF-3 Gigabit Network Connection
53 * 82567LM-3 Gigabit Network Connection
54 * 82567LM-4 Gigabit Network Connection
55 * 82577LM Gigabit Network Connection
56 * 82577LC Gigabit Network Connection
57 * 82578DM Gigabit Network Connection
58 * 82578DC Gigabit Network Connection
59 * 82579LM Gigabit Network Connection
60 * 82579V Gigabit Network Connection
61 * Ethernet Connection I217-LM
62 * Ethernet Connection I217-V
63 * Ethernet Connection I218-V
64 * Ethernet Connection I218-LM
65 * Ethernet Connection (2) I218-LM
66 * Ethernet Connection (2) I218-V
67 * Ethernet Connection (3) I218-LM
68 * Ethernet Connection (3) I218-V
71 #include "e1000_api.h"
73 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
74 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
84 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
87 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
88 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
89 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
90 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
91 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
93 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
95 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
98 u16 words, u16 *data);
99 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
100 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
103 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
104 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
105 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
106 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
107 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
108 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
109 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
110 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
111 u16 *speed, u16 *duplex);
112 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
113 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
114 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
115 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
116 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
117 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
118 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
119 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
120 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
121 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
122 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
123 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
124 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
125 u32 offset, u8 *data);
126 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
128 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
129 u32 offset, u16 *data);
130 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
131 u32 offset, u8 byte);
132 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
133 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
134 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
135 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
136 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
137 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
139 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
140 /* Offset 04h HSFSTS */
141 union ich8_hws_flash_status {
143 u16 flcdone:1; /* bit 0 Flash Cycle Done */
144 u16 flcerr:1; /* bit 1 Flash Cycle Error */
145 u16 dael:1; /* bit 2 Direct Access error Log */
146 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
147 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
148 u16 reserved1:2; /* bit 13:6 Reserved */
149 u16 reserved2:6; /* bit 13:6 Reserved */
150 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
151 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
156 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
157 /* Offset 06h FLCTL */
158 union ich8_hws_flash_ctrl {
159 struct ich8_hsflctl {
160 u16 flcgo:1; /* 0 Flash Cycle Go */
161 u16 flcycle:2; /* 2:1 Flash Cycle */
162 u16 reserved:5; /* 7:3 Reserved */
163 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
164 u16 flockdn:6; /* 15:10 Reserved */
169 /* ICH Flash Region Access Permissions */
170 union ich8_hws_flash_regacc {
172 u32 grra:8; /* 0:7 GbE region Read Access */
173 u32 grwa:8; /* 8:15 GbE region Write Access */
174 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
175 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
181 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
182 * @hw: pointer to the HW structure
184 * Test access to the PHY registers by reading the PHY ID registers. If
185 * the PHY ID is already known (e.g. resume path) compare it with known ID,
186 * otherwise assume the read PHY ID is correct if it is valid.
188 * Assumes the sw/fw/hw semaphore is already acquired.
190 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
198 for (retry_count = 0; retry_count < 2; retry_count++) {
199 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
200 if (ret_val || (phy_reg == 0xFFFF))
202 phy_id = (u32)(phy_reg << 16);
204 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
205 if (ret_val || (phy_reg == 0xFFFF)) {
209 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
214 if (hw->phy.id == phy_id)
218 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
222 /* In case the PHY needs to be in mdio slow mode,
223 * set slow mode and try to get the PHY id again.
225 if (hw->mac.type < e1000_pch_lpt) {
226 hw->phy.ops.release(hw);
227 ret_val = e1000_set_mdio_slow_mode_hv(hw);
229 ret_val = e1000_get_phy_id(hw);
230 hw->phy.ops.acquire(hw);
236 if (hw->mac.type == e1000_pch_lpt) {
237 /* Unforce SMBus mode in PHY */
238 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
239 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
240 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
242 /* Unforce SMBus mode in MAC */
243 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
244 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
245 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
252 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
253 * @hw: pointer to the HW structure
255 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
256 * used to reset the PHY to a quiescent state when necessary.
258 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
262 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
264 /* Set Phy Config Counter to 50msec */
265 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
266 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
267 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
268 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
270 /* Toggle LANPHYPC Value bit */
271 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
272 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
273 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
274 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
275 E1000_WRITE_FLUSH(hw);
277 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
278 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
279 E1000_WRITE_FLUSH(hw);
281 if (hw->mac.type < e1000_pch_lpt) {
288 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
289 E1000_CTRL_EXT_LPCD) && count--);
296 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
297 * @hw: pointer to the HW structure
299 * Workarounds/flow necessary for PHY initialization during driver load
302 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
304 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
307 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
309 /* Gate automatic PHY configuration by hardware on managed and
310 * non-managed 82579 and newer adapters.
312 e1000_gate_hw_phy_config_ich8lan(hw, true);
315 /* It is not possible to be certain of the current state of ULP
316 * so forcibly disable it.
318 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
320 #endif /* ULP_SUPPORT */
321 ret_val = hw->phy.ops.acquire(hw);
323 DEBUGOUT("Failed to initialize PHY flow\n");
327 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
328 * inaccessible and resetting the PHY is not blocked, toggle the
329 * LANPHYPC Value bit to force the interconnect to PCIe mode.
331 switch (hw->mac.type) {
333 if (e1000_phy_is_accessible_pchlan(hw))
336 /* Before toggling LANPHYPC, see if PHY is accessible by
337 * forcing MAC to SMBus mode first.
339 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
340 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
341 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
343 /* Wait 50 milliseconds for MAC to finish any retries
344 * that it might be trying to perform from previous
345 * attempts to acknowledge any phy read requests.
351 if (e1000_phy_is_accessible_pchlan(hw))
356 if ((hw->mac.type == e1000_pchlan) &&
357 (fwsm & E1000_ICH_FWSM_FW_VALID))
360 if (hw->phy.ops.check_reset_block(hw)) {
361 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
362 ret_val = -E1000_ERR_PHY;
366 /* Toggle LANPHYPC Value bit */
367 e1000_toggle_lanphypc_pch_lpt(hw);
368 if (hw->mac.type >= e1000_pch_lpt) {
369 if (e1000_phy_is_accessible_pchlan(hw))
372 /* Toggling LANPHYPC brings the PHY out of SMBus mode
373 * so ensure that the MAC is also out of SMBus mode
375 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
376 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
377 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
379 if (e1000_phy_is_accessible_pchlan(hw))
382 ret_val = -E1000_ERR_PHY;
389 hw->phy.ops.release(hw);
392 /* Check to see if able to reset PHY. Print error if not */
393 if (hw->phy.ops.check_reset_block(hw)) {
394 ERROR_REPORT("Reset blocked by ME\n");
398 /* Reset the PHY before any access to it. Doing so, ensures
399 * that the PHY is in a known good state before we read/write
400 * PHY registers. The generic reset is sufficient here,
401 * because we haven't determined the PHY type yet.
403 ret_val = e1000_phy_hw_reset_generic(hw);
407 /* On a successful reset, possibly need to wait for the PHY
408 * to quiesce to an accessible state before returning control
409 * to the calling function. If the PHY does not quiesce, then
410 * return E1000E_BLK_PHY_RESET, as this is the condition that
413 ret_val = hw->phy.ops.check_reset_block(hw);
415 ERROR_REPORT("ME blocked access to PHY after reset\n");
419 /* Ungate automatic PHY configuration on non-managed 82579 */
420 if ((hw->mac.type == e1000_pch2lan) &&
421 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
423 e1000_gate_hw_phy_config_ich8lan(hw, false);
430 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
431 * @hw: pointer to the HW structure
433 * Initialize family-specific PHY parameters and function pointers.
435 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
437 struct e1000_phy_info *phy = &hw->phy;
440 DEBUGFUNC("e1000_init_phy_params_pchlan");
443 phy->reset_delay_us = 100;
445 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
446 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
447 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
448 phy->ops.set_page = e1000_set_page_igp;
449 phy->ops.read_reg = e1000_read_phy_reg_hv;
450 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
451 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
452 phy->ops.release = e1000_release_swflag_ich8lan;
453 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
454 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
455 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
456 phy->ops.write_reg = e1000_write_phy_reg_hv;
457 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
458 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
459 phy->ops.power_up = e1000_power_up_phy_copper;
460 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
461 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
463 phy->id = e1000_phy_unknown;
465 ret_val = e1000_init_phy_workarounds_pchlan(hw);
469 if (phy->id == e1000_phy_unknown)
470 switch (hw->mac.type) {
472 ret_val = e1000_get_phy_id(hw);
475 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
480 /* In case the PHY needs to be in mdio slow mode,
481 * set slow mode and try to get the PHY id again.
483 ret_val = e1000_set_mdio_slow_mode_hv(hw);
486 ret_val = e1000_get_phy_id(hw);
491 phy->type = e1000_get_phy_type_from_id(phy->id);
494 case e1000_phy_82577:
495 case e1000_phy_82579:
497 phy->ops.check_polarity = e1000_check_polarity_82577;
498 phy->ops.force_speed_duplex =
499 e1000_phy_force_speed_duplex_82577;
500 phy->ops.get_cable_length = e1000_get_cable_length_82577;
501 phy->ops.get_info = e1000_get_phy_info_82577;
502 phy->ops.commit = e1000_phy_sw_reset_generic;
504 case e1000_phy_82578:
505 phy->ops.check_polarity = e1000_check_polarity_m88;
506 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
507 phy->ops.get_cable_length = e1000_get_cable_length_m88;
508 phy->ops.get_info = e1000_get_phy_info_m88;
511 ret_val = -E1000_ERR_PHY;
519 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
520 * @hw: pointer to the HW structure
522 * Initialize family-specific PHY parameters and function pointers.
524 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
526 struct e1000_phy_info *phy = &hw->phy;
530 DEBUGFUNC("e1000_init_phy_params_ich8lan");
533 phy->reset_delay_us = 100;
535 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
536 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
537 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
538 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
539 phy->ops.read_reg = e1000_read_phy_reg_igp;
540 phy->ops.release = e1000_release_swflag_ich8lan;
541 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
542 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
543 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
544 phy->ops.write_reg = e1000_write_phy_reg_igp;
545 phy->ops.power_up = e1000_power_up_phy_copper;
546 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
548 /* We may need to do this twice - once for IGP and if that fails,
549 * we'll set BM func pointers and try again
551 ret_val = e1000_determine_phy_address(hw);
553 phy->ops.write_reg = e1000_write_phy_reg_bm;
554 phy->ops.read_reg = e1000_read_phy_reg_bm;
555 ret_val = e1000_determine_phy_address(hw);
557 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
563 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
566 ret_val = e1000_get_phy_id(hw);
573 case IGP03E1000_E_PHY_ID:
574 phy->type = e1000_phy_igp_3;
575 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
576 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
577 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
578 phy->ops.get_info = e1000_get_phy_info_igp;
579 phy->ops.check_polarity = e1000_check_polarity_igp;
580 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
583 case IFE_PLUS_E_PHY_ID:
585 phy->type = e1000_phy_ife;
586 phy->autoneg_mask = E1000_ALL_NOT_GIG;
587 phy->ops.get_info = e1000_get_phy_info_ife;
588 phy->ops.check_polarity = e1000_check_polarity_ife;
589 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
591 case BME1000_E_PHY_ID:
592 phy->type = e1000_phy_bm;
593 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
594 phy->ops.read_reg = e1000_read_phy_reg_bm;
595 phy->ops.write_reg = e1000_write_phy_reg_bm;
596 phy->ops.commit = e1000_phy_sw_reset_generic;
597 phy->ops.get_info = e1000_get_phy_info_m88;
598 phy->ops.check_polarity = e1000_check_polarity_m88;
599 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
602 return -E1000_ERR_PHY;
606 return E1000_SUCCESS;
610 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
611 * @hw: pointer to the HW structure
613 * Initialize family-specific NVM parameters and function
616 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
618 struct e1000_nvm_info *nvm = &hw->nvm;
619 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
620 u32 gfpreg, sector_base_addr, sector_end_addr;
623 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
625 /* Can't read flash registers if the register set isn't mapped. */
626 nvm->type = e1000_nvm_flash_sw;
627 if (!hw->flash_address) {
628 DEBUGOUT("ERROR: Flash registers not mapped\n");
629 return -E1000_ERR_CONFIG;
632 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
634 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
635 * Add 1 to sector_end_addr since this sector is included in
638 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
639 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
641 /* flash_base_addr is byte-aligned */
642 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
644 /* find total size of the NVM, then cut in half since the total
645 * size represents two separate NVM banks.
647 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
648 << FLASH_SECTOR_ADDR_SHIFT);
649 nvm->flash_bank_size /= 2;
650 /* Adjust to word count */
651 nvm->flash_bank_size /= sizeof(u16);
653 nvm->word_size = E1000_SHADOW_RAM_WORDS;
655 /* Clear shadow ram */
656 for (i = 0; i < nvm->word_size; i++) {
657 dev_spec->shadow_ram[i].modified = false;
658 dev_spec->shadow_ram[i].value = 0xFFFF;
661 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
662 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
664 /* Function Pointers */
665 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
666 nvm->ops.release = e1000_release_nvm_ich8lan;
667 nvm->ops.read = e1000_read_nvm_ich8lan;
668 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
669 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
670 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
671 nvm->ops.write = e1000_write_nvm_ich8lan;
673 return E1000_SUCCESS;
677 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
678 * @hw: pointer to the HW structure
680 * Initialize family-specific MAC parameters and function
683 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
685 struct e1000_mac_info *mac = &hw->mac;
686 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
688 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
690 DEBUGFUNC("e1000_init_mac_params_ich8lan");
692 /* Set media type function pointer */
693 hw->phy.media_type = e1000_media_type_copper;
695 /* Set mta register count */
696 mac->mta_reg_count = 32;
697 /* Set rar entry count */
698 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
699 if (mac->type == e1000_ich8lan)
700 mac->rar_entry_count--;
701 /* Set if part includes ASF firmware */
702 mac->asf_firmware_present = true;
704 mac->has_fwsm = true;
705 /* ARC subsystem not supported */
706 mac->arc_subsystem_valid = false;
707 /* Adaptive IFS supported */
708 mac->adaptive_ifs = true;
710 /* Function pointers */
712 /* bus type/speed/width */
713 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
715 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
717 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
718 /* hw initialization */
719 mac->ops.init_hw = e1000_init_hw_ich8lan;
721 mac->ops.setup_link = e1000_setup_link_ich8lan;
722 /* physical interface setup */
723 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
725 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
727 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
728 /* multicast address update */
729 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
730 /* clear hardware counters */
731 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
733 /* LED and other operations */
738 /* check management mode */
739 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
741 mac->ops.id_led_init = e1000_id_led_init_generic;
743 mac->ops.blink_led = e1000_blink_led_generic;
745 mac->ops.setup_led = e1000_setup_led_generic;
747 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
748 /* turn on/off LED */
749 mac->ops.led_on = e1000_led_on_ich8lan;
750 mac->ops.led_off = e1000_led_off_ich8lan;
753 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
754 mac->ops.rar_set = e1000_rar_set_pch2lan;
757 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
758 /* multicast address update for pch2 */
759 mac->ops.update_mc_addr_list =
760 e1000_update_mc_addr_list_pch2lan;
764 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
765 /* save PCH revision_id */
766 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
767 hw->revision_id = (u8)(pci_cfg &= 0x000F);
768 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
769 /* check management mode */
770 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
772 mac->ops.id_led_init = e1000_id_led_init_pchlan;
774 mac->ops.setup_led = e1000_setup_led_pchlan;
776 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
777 /* turn on/off LED */
778 mac->ops.led_on = e1000_led_on_pchlan;
779 mac->ops.led_off = e1000_led_off_pchlan;
785 if (mac->type == e1000_pch_lpt) {
786 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
787 mac->ops.rar_set = e1000_rar_set_pch_lpt;
788 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
791 /* Enable PCS Lock-loss workaround for ICH8 */
792 if (mac->type == e1000_ich8lan)
793 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
795 return E1000_SUCCESS;
799 * __e1000_access_emi_reg_locked - Read/write EMI register
800 * @hw: pointer to the HW structure
801 * @addr: EMI address to program
802 * @data: pointer to value to read/write from/to the EMI address
803 * @read: boolean flag to indicate read or write
805 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
807 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
808 u16 *data, bool read)
812 DEBUGFUNC("__e1000_access_emi_reg_locked");
814 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
819 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
822 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
829 * e1000_read_emi_reg_locked - Read Extended Management Interface register
830 * @hw: pointer to the HW structure
831 * @addr: EMI address to program
832 * @data: value to be read from the EMI address
834 * Assumes the SW/FW/HW Semaphore is already acquired.
836 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
838 DEBUGFUNC("e1000_read_emi_reg_locked");
840 return __e1000_access_emi_reg_locked(hw, addr, data, true);
844 * e1000_write_emi_reg_locked - Write Extended Management Interface register
845 * @hw: pointer to the HW structure
846 * @addr: EMI address to program
847 * @data: value to be written to the EMI address
849 * Assumes the SW/FW/HW Semaphore is already acquired.
851 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
853 DEBUGFUNC("e1000_read_emi_reg_locked");
855 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
859 * e1000_set_eee_pchlan - Enable/disable EEE support
860 * @hw: pointer to the HW structure
862 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
863 * the link and the EEE capabilities of the link partner. The LPI Control
864 * register bits will remain set only if/when link is up.
866 * EEE LPI must not be asserted earlier than one second after link is up.
867 * On 82579, EEE LPI should not be enabled until such time otherwise there
868 * can be link issues with some switches. Other devices can have EEE LPI
869 * enabled immediately upon link up since they have a timer in hardware which
870 * prevents LPI from being asserted too early.
872 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
874 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
876 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
878 DEBUGFUNC("e1000_set_eee_pchlan");
880 switch (hw->phy.type) {
881 case e1000_phy_82579:
882 lpa = I82579_EEE_LP_ABILITY;
883 pcs_status = I82579_EEE_PCS_STATUS;
884 adv_addr = I82579_EEE_ADVERTISEMENT;
887 lpa = I217_EEE_LP_ABILITY;
888 pcs_status = I217_EEE_PCS_STATUS;
889 adv_addr = I217_EEE_ADVERTISEMENT;
892 return E1000_SUCCESS;
895 ret_val = hw->phy.ops.acquire(hw);
899 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
903 /* Clear bits that enable EEE in various speeds */
904 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
906 /* Enable EEE if not disabled by user */
907 if (!dev_spec->eee_disable) {
908 /* Save off link partner's EEE ability */
909 ret_val = e1000_read_emi_reg_locked(hw, lpa,
910 &dev_spec->eee_lp_ability);
914 /* Read EEE advertisement */
915 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
919 /* Enable EEE only for speeds in which the link partner is
920 * EEE capable and for which we advertise EEE.
922 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
923 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
925 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
926 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
927 if (data & NWAY_LPAR_100TX_FD_CAPS)
928 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
930 /* EEE is not supported in 100Half, so ignore
931 * partner's EEE in 100 ability if full-duplex
934 dev_spec->eee_lp_ability &=
935 ~I82579_EEE_100_SUPPORTED;
939 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
940 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
944 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
946 hw->phy.ops.release(hw);
952 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
953 * @hw: pointer to the HW structure
954 * @link: link up bool flag
956 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
957 * preventing further DMA write requests. Workaround the issue by disabling
958 * the de-assertion of the clock request when in 1Gpbs mode.
959 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
960 * speeds in order to avoid Tx hangs.
962 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
964 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
965 u32 status = E1000_READ_REG(hw, E1000_STATUS);
966 s32 ret_val = E1000_SUCCESS;
969 if (link && (status & E1000_STATUS_SPEED_1000)) {
970 ret_val = hw->phy.ops.acquire(hw);
975 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
981 e1000_write_kmrn_reg_locked(hw,
982 E1000_KMRNCTRLSTA_K1_CONFIG,
984 ~E1000_KMRNCTRLSTA_K1_ENABLE);
990 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
991 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
994 e1000_write_kmrn_reg_locked(hw,
995 E1000_KMRNCTRLSTA_K1_CONFIG,
998 hw->phy.ops.release(hw);
1000 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1001 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1003 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1004 (status & E1000_STATUS_FD)))
1005 goto update_fextnvm6;
1007 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1011 /* Clear link status transmit timeout */
1012 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1014 if (status & E1000_STATUS_SPEED_100) {
1015 /* Set inband Tx timeout to 5x10us for 100Half */
1016 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1018 /* Do not extend the K1 entry latency for 100Half */
1019 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1021 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1023 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1025 /* Extend the K1 entry latency for 10 Mbps */
1026 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1029 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1034 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1042 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1043 * @hw: pointer to the HW structure
1044 * @to_sx: boolean indicating a system power state transition to Sx
1046 * When link is down, configure ULP mode to significantly reduce the power
1047 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1048 * ME firmware to start the ULP configuration. If not on an ME enabled
1049 * system, configure the ULP mode by software.
1051 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1054 s32 ret_val = E1000_SUCCESS;
1057 if ((hw->mac.type < e1000_pch_lpt) ||
1058 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1059 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1060 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1061 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1062 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1067 /* Poll up to 5 seconds for Cable Disconnected indication */
1068 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1069 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1070 /* Bail if link is re-acquired */
1071 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1072 return -E1000_ERR_PHY;
1078 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1079 (E1000_READ_REG(hw, E1000_FEXT) &
1080 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1084 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1085 /* Request ME configure ULP mode in the PHY */
1086 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1087 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1088 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1093 ret_val = hw->phy.ops.acquire(hw);
1097 /* During S0 Idle keep the phy in PCI-E mode */
1098 if (hw->dev_spec.ich8lan.smbus_disable)
1101 /* Force SMBus mode in PHY */
1102 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1105 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1106 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1108 /* Force SMBus mode in MAC */
1109 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1110 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1111 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1115 /* Change the 'Link Status Change' interrupt to trigger
1116 * on 'Cable Status Change'
1118 ret_val = e1000_read_kmrn_reg_locked(hw,
1119 E1000_KMRNCTRLSTA_OP_MODES,
1123 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1124 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1128 /* Set Inband ULP Exit, Reset to SMBus mode and
1129 * Disable SMBus Release on PERST# in PHY
1131 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1134 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1135 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1137 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1138 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1140 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1142 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1144 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1146 /* Set Disable SMBus Release on PERST# in MAC */
1147 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1148 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1149 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1151 /* Commit ULP changes in PHY by starting auto ULP configuration */
1152 phy_reg |= I218_ULP_CONFIG1_START;
1153 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1156 /* Disable Tx so that the MAC doesn't send any (buffered)
1157 * packets to the PHY.
1159 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1160 mac_reg &= ~E1000_TCTL_EN;
1161 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1164 hw->phy.ops.release(hw);
1167 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1169 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1175 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1176 * @hw: pointer to the HW structure
1177 * @force: boolean indicating whether or not to force disabling ULP
1179 * Un-configure ULP mode when link is up, the system is transitioned from
1180 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1181 * system, poll for an indication from ME that ULP has been un-configured.
1182 * If not on an ME enabled system, un-configure the ULP mode by software.
1184 * During nominal operation, this function is called when link is acquired
1185 * to disable ULP mode (force=false); otherwise, for example when unloading
1186 * the driver or during Sx->S0 transitions, this is called with force=true
1187 * to forcibly disable ULP.
1189 * When the cable is plugged in while the device is in D0, a Cable Status
1190 * Change interrupt is generated which causes this function to be called
1191 * to partially disable ULP mode and restart autonegotiation. This function
1192 * is then called again due to the resulting Link Status Change interrupt
1193 * to finish cleaning up after the ULP flow.
1195 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1197 s32 ret_val = E1000_SUCCESS;
1202 if ((hw->mac.type < e1000_pch_lpt) ||
1203 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1204 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1205 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1206 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1207 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1210 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1212 /* Request ME un-configure ULP mode in the PHY */
1213 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1214 mac_reg &= ~E1000_H2ME_ULP;
1215 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1216 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1219 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1220 while (E1000_READ_REG(hw, E1000_FWSM) &
1221 E1000_FWSM_ULP_CFG_DONE) {
1223 ret_val = -E1000_ERR_PHY;
1229 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1232 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1233 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1234 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1236 /* Clear H2ME.ULP after ME ULP configuration */
1237 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1238 mac_reg &= ~E1000_H2ME_ULP;
1239 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1241 /* Restore link speed advertisements and restart
1244 ret_val = e1000_phy_setup_autoneg(hw);
1248 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1254 ret_val = hw->phy.ops.acquire(hw);
1258 /* Revert the change to the 'Link Status Change'
1259 * interrupt to trigger on 'Cable Status Change'
1261 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1265 phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1266 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1269 /* Toggle LANPHYPC Value bit */
1270 e1000_toggle_lanphypc_pch_lpt(hw);
1272 /* Unforce SMBus mode in PHY */
1273 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1275 /* The MAC might be in PCIe mode, so temporarily force to
1276 * SMBus mode in order to access the PHY.
1278 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1279 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1280 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1284 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1289 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1290 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1292 /* Unforce SMBus mode in MAC */
1293 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1294 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1295 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1297 /* When ULP mode was previously entered, K1 was disabled by the
1298 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1300 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1303 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1304 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1306 /* Clear ULP enabled configuration */
1307 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1310 /* CSC interrupt received due to ULP Indication */
1311 if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1312 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1313 I218_ULP_CONFIG1_STICKY_ULP |
1314 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1315 I218_ULP_CONFIG1_WOL_HOST |
1316 I218_ULP_CONFIG1_INBAND_EXIT |
1317 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1318 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1320 /* Commit ULP changes by starting auto ULP configuration */
1321 phy_reg |= I218_ULP_CONFIG1_START;
1322 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1324 /* Clear Disable SMBus Release on PERST# in MAC */
1325 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1326 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1327 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1330 hw->phy.ops.release(hw);
1332 if (hw->mac.autoneg)
1333 e1000_phy_setup_autoneg(hw);
1335 e1000_sw_lcd_config_ich8lan(hw);
1337 e1000_oem_bits_config_ich8lan(hw, true);
1339 /* Set ULP state to unknown and return non-zero to
1340 * indicate no link (yet) and re-enter on the next LSC
1341 * to finish disabling ULP flow.
1343 hw->dev_spec.ich8lan.ulp_state =
1344 e1000_ulp_state_unknown;
1351 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1352 mac_reg |= E1000_TCTL_EN;
1353 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1356 hw->phy.ops.release(hw);
1358 hw->phy.ops.reset(hw);
1363 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1365 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1370 #endif /* ULP_SUPPORT */
1372 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1373 * @hw: pointer to the HW structure
1375 * Checks to see of the link status of the hardware has changed. If a
1376 * change in link status has been detected, then we read the PHY registers
1377 * to get the current speed/duplex if link exists.
1379 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1381 struct e1000_mac_info *mac = &hw->mac;
1386 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1388 /* We only want to go out to the PHY registers to see if Auto-Neg
1389 * has completed and/or if our link status has changed. The
1390 * get_link_status flag is set upon receiving a Link Status
1391 * Change or Rx Sequence Error interrupt.
1393 if (!mac->get_link_status)
1394 return E1000_SUCCESS;
1396 if ((hw->mac.type < e1000_pch_lpt) ||
1397 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1398 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1399 /* First we want to see if the MII Status Register reports
1400 * link. If so, then we want to get the current speed/duplex
1403 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1407 /* Check the MAC's STATUS register to determine link state
1408 * since the PHY could be inaccessible while in ULP mode.
1410 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1412 ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1414 ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1420 if (hw->mac.type == e1000_pchlan) {
1421 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1426 /* When connected at 10Mbps half-duplex, some parts are excessively
1427 * aggressive resulting in many collisions. To avoid this, increase
1428 * the IPG and reduce Rx latency in the PHY.
1430 if (((hw->mac.type == e1000_pch2lan) ||
1431 (hw->mac.type == e1000_pch_lpt)) && link) {
1433 reg = E1000_READ_REG(hw, E1000_STATUS);
1434 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1437 reg = E1000_READ_REG(hw, E1000_TIPG);
1438 reg &= ~E1000_TIPG_IPGT_MASK;
1440 E1000_WRITE_REG(hw, E1000_TIPG, reg);
1442 /* Reduce Rx latency in analog PHY */
1443 ret_val = hw->phy.ops.acquire(hw);
1447 if (hw->mac.type == e1000_pch2lan)
1448 emi_addr = I82579_RX_CONFIG;
1450 emi_addr = I217_RX_CONFIG;
1451 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1453 hw->phy.ops.release(hw);
1460 /* Work-around I218 hang issue */
1461 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1462 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1463 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1464 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1465 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1470 /* Clear link partner's EEE ability */
1471 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1474 return E1000_SUCCESS; /* No link detected */
1476 mac->get_link_status = false;
1478 switch (hw->mac.type) {
1480 ret_val = e1000_k1_workaround_lv(hw);
1485 if (hw->phy.type == e1000_phy_82578) {
1486 ret_val = e1000_link_stall_workaround_hv(hw);
1491 /* Workaround for PCHx parts in half-duplex:
1492 * Set the number of preambles removed from the packet
1493 * when it is passed from the PHY to the MAC to prevent
1494 * the MAC from misinterpreting the packet type.
1496 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1497 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1499 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1501 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1503 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1509 /* Check if there was DownShift, must be checked
1510 * immediately after link-up
1512 e1000_check_downshift_generic(hw);
1514 /* Enable/Disable EEE after link up */
1515 if (hw->phy.type > e1000_phy_82579) {
1516 ret_val = e1000_set_eee_pchlan(hw);
1521 /* If we are forcing speed/duplex, then we simply return since
1522 * we have already determined whether we have link or not.
1525 return -E1000_ERR_CONFIG;
1527 /* Auto-Neg is enabled. Auto Speed Detection takes care
1528 * of MAC speed/duplex configuration. So we only need to
1529 * configure Collision Distance in the MAC.
1531 mac->ops.config_collision_dist(hw);
1533 /* Configure Flow Control now that Auto-Neg has completed.
1534 * First, we need to restore the desired flow control
1535 * settings because we may have had to re-autoneg with a
1536 * different link partner.
1538 ret_val = e1000_config_fc_after_link_up_generic(hw);
1540 DEBUGOUT("Error configuring flow control\n");
1546 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1547 * @hw: pointer to the HW structure
1549 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1551 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1553 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1555 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1556 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1557 switch (hw->mac.type) {
1560 case e1000_ich10lan:
1561 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1566 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1574 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1575 * @hw: pointer to the HW structure
1577 * Acquires the mutex for performing NVM operations.
1579 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1581 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1583 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1585 return E1000_SUCCESS;
1589 * e1000_release_nvm_ich8lan - Release NVM mutex
1590 * @hw: pointer to the HW structure
1592 * Releases the mutex used while performing NVM operations.
1594 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1596 DEBUGFUNC("e1000_release_nvm_ich8lan");
1598 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1604 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1605 * @hw: pointer to the HW structure
1607 * Acquires the software control flag for performing PHY and select
1610 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1612 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1613 s32 ret_val = E1000_SUCCESS;
1615 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1617 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1620 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1621 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1629 DEBUGOUT("SW has already locked the resource.\n");
1630 ret_val = -E1000_ERR_CONFIG;
1634 timeout = SW_FLAG_TIMEOUT;
1636 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1637 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1640 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1641 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1649 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1650 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1651 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1652 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1653 ret_val = -E1000_ERR_CONFIG;
1659 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1665 * e1000_release_swflag_ich8lan - Release software control flag
1666 * @hw: pointer to the HW structure
1668 * Releases the software control flag for performing PHY and select
1671 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1675 DEBUGFUNC("e1000_release_swflag_ich8lan");
1677 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1679 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1680 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1681 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1683 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1686 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1692 * e1000_check_mng_mode_ich8lan - Checks management mode
1693 * @hw: pointer to the HW structure
1695 * This checks if the adapter has any manageability enabled.
1696 * This is a function pointer entry point only called by read/write
1697 * routines for the PHY and NVM parts.
1699 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1703 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1705 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1707 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1708 ((fwsm & E1000_FWSM_MODE_MASK) ==
1709 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1713 * e1000_check_mng_mode_pchlan - Checks management mode
1714 * @hw: pointer to the HW structure
1716 * This checks if the adapter has iAMT enabled.
1717 * This is a function pointer entry point only called by read/write
1718 * routines for the PHY and NVM parts.
1720 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1724 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1726 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1728 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1729 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1733 * e1000_rar_set_pch2lan - Set receive address register
1734 * @hw: pointer to the HW structure
1735 * @addr: pointer to the receive address
1736 * @index: receive address array register
1738 * Sets the receive address array register at index to the address passed
1739 * in by addr. For 82579, RAR[0] is the base address register that is to
1740 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1741 * Use SHRA[0-3] in place of those reserved for ME.
1743 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1745 u32 rar_low, rar_high;
1747 DEBUGFUNC("e1000_rar_set_pch2lan");
1749 /* HW expects these in little endian so we reverse the byte order
1750 * from network order (big endian) to little endian
1752 rar_low = ((u32) addr[0] |
1753 ((u32) addr[1] << 8) |
1754 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1756 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1758 /* If MAC address zero, no need to set the AV bit */
1759 if (rar_low || rar_high)
1760 rar_high |= E1000_RAH_AV;
1763 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1764 E1000_WRITE_FLUSH(hw);
1765 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1766 E1000_WRITE_FLUSH(hw);
1767 return E1000_SUCCESS;
1770 /* RAR[1-6] are owned by manageability. Skip those and program the
1771 * next address into the SHRA register array.
1773 if (index < (u32) (hw->mac.rar_entry_count)) {
1776 ret_val = e1000_acquire_swflag_ich8lan(hw);
1780 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1781 E1000_WRITE_FLUSH(hw);
1782 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1783 E1000_WRITE_FLUSH(hw);
1785 e1000_release_swflag_ich8lan(hw);
1787 /* verify the register updates */
1788 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1789 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1790 return E1000_SUCCESS;
1792 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1793 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1797 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1798 return -E1000_ERR_CONFIG;
1802 * e1000_rar_set_pch_lpt - Set receive address registers
1803 * @hw: pointer to the HW structure
1804 * @addr: pointer to the receive address
1805 * @index: receive address array register
1807 * Sets the receive address register array at index to the address passed
1808 * in by addr. For LPT, RAR[0] is the base address register that is to
1809 * contain the MAC address. SHRA[0-10] are the shared receive address
1810 * registers that are shared between the Host and manageability engine (ME).
1812 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1814 u32 rar_low, rar_high;
1817 DEBUGFUNC("e1000_rar_set_pch_lpt");
1819 /* HW expects these in little endian so we reverse the byte order
1820 * from network order (big endian) to little endian
1822 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1823 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1825 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1827 /* If MAC address zero, no need to set the AV bit */
1828 if (rar_low || rar_high)
1829 rar_high |= E1000_RAH_AV;
1832 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1833 E1000_WRITE_FLUSH(hw);
1834 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1835 E1000_WRITE_FLUSH(hw);
1836 return E1000_SUCCESS;
1839 /* The manageability engine (ME) can lock certain SHRAR registers that
1840 * it is using - those registers are unavailable for use.
1842 if (index < hw->mac.rar_entry_count) {
1843 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1844 E1000_FWSM_WLOCK_MAC_MASK;
1845 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1847 /* Check if all SHRAR registers are locked */
1851 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1854 ret_val = e1000_acquire_swflag_ich8lan(hw);
1859 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1861 E1000_WRITE_FLUSH(hw);
1862 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1864 E1000_WRITE_FLUSH(hw);
1866 e1000_release_swflag_ich8lan(hw);
1868 /* verify the register updates */
1869 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1870 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1871 return E1000_SUCCESS;
1876 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1877 return -E1000_ERR_CONFIG;
1880 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1882 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1883 * @hw: pointer to the HW structure
1884 * @mc_addr_list: array of multicast addresses to program
1885 * @mc_addr_count: number of multicast addresses to program
1887 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1888 * The caller must have a packed mc_addr_list of multicast addresses.
1890 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1898 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1900 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1902 ret_val = hw->phy.ops.acquire(hw);
1906 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1910 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1911 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1912 (u16)(hw->mac.mta_shadow[i] &
1914 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1915 (u16)((hw->mac.mta_shadow[i] >> 16) &
1919 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1922 hw->phy.ops.release(hw);
1925 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1927 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1928 * @hw: pointer to the HW structure
1930 * Checks if firmware is blocking the reset of the PHY.
1931 * This is a function pointer entry point only called by
1934 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1937 bool blocked = false;
1940 DEBUGFUNC("e1000_check_reset_block_ich8lan");
1943 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1944 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
1950 } while (blocked && (i++ < 10));
1951 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
1955 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1956 * @hw: pointer to the HW structure
1958 * Assumes semaphore already acquired.
1961 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1964 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
1965 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1966 E1000_STRAP_SMT_FREQ_SHIFT;
1969 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1971 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1975 phy_data &= ~HV_SMB_ADDR_MASK;
1976 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1977 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1979 if (hw->phy.type == e1000_phy_i217) {
1980 /* Restore SMBus frequency */
1982 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1983 phy_data |= (freq & (1 << 0)) <<
1984 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1985 phy_data |= (freq & (1 << 1)) <<
1986 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1988 DEBUGOUT("Unsupported SMB frequency in PHY\n");
1992 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1996 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1997 * @hw: pointer to the HW structure
1999 * SW should configure the LCD from the NVM extended configuration region
2000 * as a workaround for certain parts.
2002 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2004 struct e1000_phy_info *phy = &hw->phy;
2005 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2006 s32 ret_val = E1000_SUCCESS;
2007 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2009 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2011 /* Initialize the PHY from the NVM on ICH platforms. This
2012 * is needed due to an issue where the NVM configuration is
2013 * not properly autoloaded after power transitions.
2014 * Therefore, after each PHY reset, we will load the
2015 * configuration data out of the NVM manually.
2017 switch (hw->mac.type) {
2019 if (phy->type != e1000_phy_igp_3)
2022 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2023 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2024 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2031 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2037 ret_val = hw->phy.ops.acquire(hw);
2041 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2042 if (!(data & sw_cfg_mask))
2045 /* Make sure HW does not configure LCD from PHY
2046 * extended configuration before SW configuration
2048 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2049 if ((hw->mac.type < e1000_pch2lan) &&
2050 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2053 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2054 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2055 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2059 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2060 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2062 if (((hw->mac.type == e1000_pchlan) &&
2063 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2064 (hw->mac.type > e1000_pchlan)) {
2065 /* HW configures the SMBus address and LEDs when the
2066 * OEM and LCD Write Enable bits are set in the NVM.
2067 * When both NVM bits are cleared, SW will configure
2070 ret_val = e1000_write_smbus_addr(hw);
2074 data = E1000_READ_REG(hw, E1000_LEDCTL);
2075 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2081 /* Configure LCD from extended configuration region. */
2083 /* cnf_base_addr is in DWORD */
2084 word_addr = (u16)(cnf_base_addr << 1);
2086 for (i = 0; i < cnf_size; i++) {
2087 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2092 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2097 /* Save off the PHY page for future writes. */
2098 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2099 phy_page = reg_data;
2103 reg_addr &= PHY_REG_MASK;
2104 reg_addr |= phy_page;
2106 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2113 hw->phy.ops.release(hw);
2118 * e1000_k1_gig_workaround_hv - K1 Si workaround
2119 * @hw: pointer to the HW structure
2120 * @link: link up bool flag
2122 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2123 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2124 * If link is down, the function will restore the default K1 setting located
2127 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2129 s32 ret_val = E1000_SUCCESS;
2131 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2133 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2135 if (hw->mac.type != e1000_pchlan)
2136 return E1000_SUCCESS;
2138 /* Wrap the whole flow with the sw flag */
2139 ret_val = hw->phy.ops.acquire(hw);
2143 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2145 if (hw->phy.type == e1000_phy_82578) {
2146 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2151 status_reg &= (BM_CS_STATUS_LINK_UP |
2152 BM_CS_STATUS_RESOLVED |
2153 BM_CS_STATUS_SPEED_MASK);
2155 if (status_reg == (BM_CS_STATUS_LINK_UP |
2156 BM_CS_STATUS_RESOLVED |
2157 BM_CS_STATUS_SPEED_1000))
2161 if (hw->phy.type == e1000_phy_82577) {
2162 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2167 status_reg &= (HV_M_STATUS_LINK_UP |
2168 HV_M_STATUS_AUTONEG_COMPLETE |
2169 HV_M_STATUS_SPEED_MASK);
2171 if (status_reg == (HV_M_STATUS_LINK_UP |
2172 HV_M_STATUS_AUTONEG_COMPLETE |
2173 HV_M_STATUS_SPEED_1000))
2177 /* Link stall fix for link up */
2178 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2184 /* Link stall fix for link down */
2185 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2191 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2194 hw->phy.ops.release(hw);
2200 * e1000_configure_k1_ich8lan - Configure K1 power state
2201 * @hw: pointer to the HW structure
2202 * @enable: K1 state to configure
2204 * Configure the K1 power state based on the provided parameter.
2205 * Assumes semaphore already acquired.
2207 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2209 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2217 DEBUGFUNC("e1000_configure_k1_ich8lan");
2219 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2225 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2227 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2229 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2235 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2236 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2238 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2239 reg |= E1000_CTRL_FRCSPD;
2240 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2242 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2243 E1000_WRITE_FLUSH(hw);
2245 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2246 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2247 E1000_WRITE_FLUSH(hw);
2250 return E1000_SUCCESS;
2254 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2255 * @hw: pointer to the HW structure
2256 * @d0_state: boolean if entering d0 or d3 device state
2258 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2259 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2260 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2262 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2268 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2270 if (hw->mac.type < e1000_pchlan)
2273 ret_val = hw->phy.ops.acquire(hw);
2277 if (hw->mac.type == e1000_pchlan) {
2278 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2279 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2283 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2284 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2287 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2289 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2293 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2296 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2297 oem_reg |= HV_OEM_BITS_GBE_DIS;
2299 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2300 oem_reg |= HV_OEM_BITS_LPLU;
2302 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2303 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2304 oem_reg |= HV_OEM_BITS_GBE_DIS;
2306 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2307 E1000_PHY_CTRL_NOND0A_LPLU))
2308 oem_reg |= HV_OEM_BITS_LPLU;
2311 /* Set Restart auto-neg to activate the bits */
2312 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2313 !hw->phy.ops.check_reset_block(hw))
2314 oem_reg |= HV_OEM_BITS_RESTART_AN;
2316 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2319 hw->phy.ops.release(hw);
2326 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2327 * @hw: pointer to the HW structure
2329 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2334 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2336 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2340 data |= HV_KMRN_MDIO_SLOW;
2342 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2348 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2349 * done after every PHY reset.
2351 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2353 s32 ret_val = E1000_SUCCESS;
2356 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2358 if (hw->mac.type != e1000_pchlan)
2359 return E1000_SUCCESS;
2361 /* Set MDIO slow mode before any other MDIO access */
2362 if (hw->phy.type == e1000_phy_82577) {
2363 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2368 if (((hw->phy.type == e1000_phy_82577) &&
2369 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2370 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2371 /* Disable generation of early preamble */
2372 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2376 /* Preamble tuning for SSC */
2377 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2383 if (hw->phy.type == e1000_phy_82578) {
2384 /* Return registers to default by doing a soft reset then
2385 * writing 0x3140 to the control register.
2387 if (hw->phy.revision < 2) {
2388 e1000_phy_sw_reset_generic(hw);
2389 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2395 ret_val = hw->phy.ops.acquire(hw);
2400 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2401 hw->phy.ops.release(hw);
2405 /* Configure the K1 Si workaround during phy reset assuming there is
2406 * link so that it disables K1 if link is in 1Gbps.
2408 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2412 /* Workaround for link disconnects on a busy hub in half duplex */
2413 ret_val = hw->phy.ops.acquire(hw);
2416 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2419 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2424 /* set MSE higher to enable link to stay up when noise is high */
2425 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2427 hw->phy.ops.release(hw);
2433 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2434 * @hw: pointer to the HW structure
2436 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2442 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2444 ret_val = hw->phy.ops.acquire(hw);
2447 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2451 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2452 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2453 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2454 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2455 (u16)(mac_reg & 0xFFFF));
2456 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2457 (u16)((mac_reg >> 16) & 0xFFFF));
2459 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2460 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2461 (u16)(mac_reg & 0xFFFF));
2462 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2463 (u16)((mac_reg & E1000_RAH_AV)
2467 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2470 hw->phy.ops.release(hw);
2473 #ifndef CRC32_OS_SUPPORT
2474 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2476 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2477 u32 i, j, mask, crc;
2479 DEBUGFUNC("e1000_calc_rx_da_crc");
2482 for (i = 0; i < 6; i++) {
2484 for (j = 8; j > 0; j--) {
2485 mask = (crc & 1) * (-1);
2486 crc = (crc >> 1) ^ (poly & mask);
2492 #endif /* CRC32_OS_SUPPORT */
2494 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2496 * @hw: pointer to the HW structure
2497 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2499 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2501 s32 ret_val = E1000_SUCCESS;
2506 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2508 if (hw->mac.type < e1000_pch2lan)
2509 return E1000_SUCCESS;
2511 /* disable Rx path while enabling/disabling workaround */
2512 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2513 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2514 phy_reg | (1 << 14));
2519 /* Write Rx addresses (rar_entry_count for RAL/H, and
2520 * SHRAL/H) and initial CRC values to the MAC
2522 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2523 u8 mac_addr[ETH_ADDR_LEN] = {0};
2524 u32 addr_high, addr_low;
2526 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2527 if (!(addr_high & E1000_RAH_AV))
2529 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2530 mac_addr[0] = (addr_low & 0xFF);
2531 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2532 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2533 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2534 mac_addr[4] = (addr_high & 0xFF);
2535 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2537 #ifndef CRC32_OS_SUPPORT
2538 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2539 e1000_calc_rx_da_crc(mac_addr));
2540 #else /* CRC32_OS_SUPPORT */
2541 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2542 E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2543 #endif /* CRC32_OS_SUPPORT */
2546 /* Write Rx addresses to the PHY */
2547 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2549 /* Enable jumbo frame workaround in the MAC */
2550 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2551 mac_reg &= ~(1 << 14);
2552 mac_reg |= (7 << 15);
2553 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2555 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2556 mac_reg |= E1000_RCTL_SECRC;
2557 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2559 ret_val = e1000_read_kmrn_reg_generic(hw,
2560 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2564 ret_val = e1000_write_kmrn_reg_generic(hw,
2565 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2569 ret_val = e1000_read_kmrn_reg_generic(hw,
2570 E1000_KMRNCTRLSTA_HD_CTRL,
2574 data &= ~(0xF << 8);
2576 ret_val = e1000_write_kmrn_reg_generic(hw,
2577 E1000_KMRNCTRLSTA_HD_CTRL,
2582 /* Enable jumbo frame workaround in the PHY */
2583 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2584 data &= ~(0x7F << 5);
2585 data |= (0x37 << 5);
2586 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2589 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2591 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2594 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2595 data &= ~(0x3FF << 2);
2596 data |= (0x1A << 2);
2597 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2600 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2603 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2604 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2609 /* Write MAC register values back to h/w defaults */
2610 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2611 mac_reg &= ~(0xF << 14);
2612 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2614 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2615 mac_reg &= ~E1000_RCTL_SECRC;
2616 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2618 ret_val = e1000_read_kmrn_reg_generic(hw,
2619 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2623 ret_val = e1000_write_kmrn_reg_generic(hw,
2624 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2628 ret_val = e1000_read_kmrn_reg_generic(hw,
2629 E1000_KMRNCTRLSTA_HD_CTRL,
2633 data &= ~(0xF << 8);
2635 ret_val = e1000_write_kmrn_reg_generic(hw,
2636 E1000_KMRNCTRLSTA_HD_CTRL,
2641 /* Write PHY register values back to h/w defaults */
2642 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2643 data &= ~(0x7F << 5);
2644 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2647 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2649 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2652 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2653 data &= ~(0x3FF << 2);
2655 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2658 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2661 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2662 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2668 /* re-enable Rx path after enabling/disabling workaround */
2669 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2674 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2675 * done after every PHY reset.
2677 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2679 s32 ret_val = E1000_SUCCESS;
2681 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2683 if (hw->mac.type != e1000_pch2lan)
2684 return E1000_SUCCESS;
2686 /* Set MDIO slow mode before any other MDIO access */
2687 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2691 ret_val = hw->phy.ops.acquire(hw);
2694 /* set MSE higher to enable link to stay up when noise is high */
2695 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2698 /* drop link after 5 times MSE threshold was reached */
2699 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2701 hw->phy.ops.release(hw);
2707 * e1000_k1_gig_workaround_lv - K1 Si workaround
2708 * @hw: pointer to the HW structure
2710 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2711 * Disable K1 for 1000 and 100 speeds
2713 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2715 s32 ret_val = E1000_SUCCESS;
2718 DEBUGFUNC("e1000_k1_workaround_lv");
2720 if (hw->mac.type != e1000_pch2lan)
2721 return E1000_SUCCESS;
2723 /* Set K1 beacon duration based on 10Mbs speed */
2724 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2728 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2729 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2731 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2734 /* LV 1G/100 Packet drop issue wa */
2735 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2739 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2740 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2746 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2747 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2748 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2749 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2757 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2758 * @hw: pointer to the HW structure
2759 * @gate: boolean set to true to gate, false to ungate
2761 * Gate/ungate the automatic PHY configuration via hardware; perform
2762 * the configuration via software instead.
2764 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2768 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2770 if (hw->mac.type < e1000_pch2lan)
2773 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2776 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2778 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2780 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2784 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2785 * @hw: pointer to the HW structure
2787 * Check the appropriate indication the MAC has finished configuring the
2788 * PHY after a software reset.
2790 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2792 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2794 DEBUGFUNC("e1000_lan_init_done_ich8lan");
2796 /* Wait for basic configuration completes before proceeding */
2798 data = E1000_READ_REG(hw, E1000_STATUS);
2799 data &= E1000_STATUS_LAN_INIT_DONE;
2801 } while ((!data) && --loop);
2803 /* If basic configuration is incomplete before the above loop
2804 * count reaches 0, loading the configuration from NVM will
2805 * leave the PHY in a bad state possibly resulting in no link.
2808 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2810 /* Clear the Init Done bit for the next init event */
2811 data = E1000_READ_REG(hw, E1000_STATUS);
2812 data &= ~E1000_STATUS_LAN_INIT_DONE;
2813 E1000_WRITE_REG(hw, E1000_STATUS, data);
2817 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2818 * @hw: pointer to the HW structure
2820 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2822 s32 ret_val = E1000_SUCCESS;
2825 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2827 if (hw->phy.ops.check_reset_block(hw))
2828 return E1000_SUCCESS;
2830 /* Allow time for h/w to get to quiescent state after reset */
2833 /* Perform any necessary post-reset workarounds */
2834 switch (hw->mac.type) {
2836 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2841 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2849 /* Clear the host wakeup bit after lcd reset */
2850 if (hw->mac.type >= e1000_pchlan) {
2851 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
2852 reg &= ~BM_WUC_HOST_WU_BIT;
2853 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2856 /* Configure the LCD with the extended configuration region in NVM */
2857 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2861 /* Configure the LCD with the OEM bits in NVM */
2862 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2864 if (hw->mac.type == e1000_pch2lan) {
2865 /* Ungate automatic PHY configuration on non-managed 82579 */
2866 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2867 E1000_ICH_FWSM_FW_VALID)) {
2869 e1000_gate_hw_phy_config_ich8lan(hw, false);
2872 /* Set EEE LPI Update Timer to 200usec */
2873 ret_val = hw->phy.ops.acquire(hw);
2876 ret_val = e1000_write_emi_reg_locked(hw,
2877 I82579_LPI_UPDATE_TIMER,
2879 hw->phy.ops.release(hw);
2886 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2887 * @hw: pointer to the HW structure
2890 * This is a function pointer entry point called by drivers
2891 * or other shared routines.
2893 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2895 s32 ret_val = E1000_SUCCESS;
2897 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2899 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2900 if ((hw->mac.type == e1000_pch2lan) &&
2901 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2902 e1000_gate_hw_phy_config_ich8lan(hw, true);
2904 ret_val = e1000_phy_hw_reset_generic(hw);
2908 return e1000_post_phy_reset_ich8lan(hw);
2912 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2913 * @hw: pointer to the HW structure
2914 * @active: true to enable LPLU, false to disable
2916 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2917 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2918 * the phy speed. This function will manually set the LPLU bit and restart
2919 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2920 * since it configures the same bit.
2922 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2927 DEBUGFUNC("e1000_set_lplu_state_pchlan");
2929 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2934 oem_reg |= HV_OEM_BITS_LPLU;
2936 oem_reg &= ~HV_OEM_BITS_LPLU;
2938 if (!hw->phy.ops.check_reset_block(hw))
2939 oem_reg |= HV_OEM_BITS_RESTART_AN;
2941 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2945 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2946 * @hw: pointer to the HW structure
2947 * @active: true to enable LPLU, false to disable
2949 * Sets the LPLU D0 state according to the active flag. When
2950 * activating LPLU this function also disables smart speed
2951 * and vice versa. LPLU will not be activated unless the
2952 * device autonegotiation advertisement meets standards of
2953 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2954 * This is a function pointer entry point only called by
2955 * PHY setup routines.
2957 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2959 struct e1000_phy_info *phy = &hw->phy;
2961 s32 ret_val = E1000_SUCCESS;
2964 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
2966 if (phy->type == e1000_phy_ife)
2967 return E1000_SUCCESS;
2969 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2972 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2973 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2975 if (phy->type != e1000_phy_igp_3)
2976 return E1000_SUCCESS;
2978 /* Call gig speed drop workaround on LPLU before accessing
2981 if (hw->mac.type == e1000_ich8lan)
2982 e1000_gig_downshift_workaround_ich8lan(hw);
2984 /* When LPLU is enabled, we should disable SmartSpeed */
2985 ret_val = phy->ops.read_reg(hw,
2986 IGP01E1000_PHY_PORT_CONFIG,
2990 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2991 ret_val = phy->ops.write_reg(hw,
2992 IGP01E1000_PHY_PORT_CONFIG,
2997 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2998 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3000 if (phy->type != e1000_phy_igp_3)
3001 return E1000_SUCCESS;
3003 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3004 * during Dx states where the power conservation is most
3005 * important. During driver activity we should enable
3006 * SmartSpeed, so performance is maintained.
3008 if (phy->smart_speed == e1000_smart_speed_on) {
3009 ret_val = phy->ops.read_reg(hw,
3010 IGP01E1000_PHY_PORT_CONFIG,
3015 data |= IGP01E1000_PSCFR_SMART_SPEED;
3016 ret_val = phy->ops.write_reg(hw,
3017 IGP01E1000_PHY_PORT_CONFIG,
3021 } else if (phy->smart_speed == e1000_smart_speed_off) {
3022 ret_val = phy->ops.read_reg(hw,
3023 IGP01E1000_PHY_PORT_CONFIG,
3028 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3029 ret_val = phy->ops.write_reg(hw,
3030 IGP01E1000_PHY_PORT_CONFIG,
3037 return E1000_SUCCESS;
3041 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3042 * @hw: pointer to the HW structure
3043 * @active: true to enable LPLU, false to disable
3045 * Sets the LPLU D3 state according to the active flag. When
3046 * activating LPLU this function also disables smart speed
3047 * and vice versa. LPLU will not be activated unless the
3048 * device autonegotiation advertisement meets standards of
3049 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3050 * This is a function pointer entry point only called by
3051 * PHY setup routines.
3053 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3055 struct e1000_phy_info *phy = &hw->phy;
3057 s32 ret_val = E1000_SUCCESS;
3060 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3062 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3065 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3066 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3068 if (phy->type != e1000_phy_igp_3)
3069 return E1000_SUCCESS;
3071 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3072 * during Dx states where the power conservation is most
3073 * important. During driver activity we should enable
3074 * SmartSpeed, so performance is maintained.
3076 if (phy->smart_speed == e1000_smart_speed_on) {
3077 ret_val = phy->ops.read_reg(hw,
3078 IGP01E1000_PHY_PORT_CONFIG,
3083 data |= IGP01E1000_PSCFR_SMART_SPEED;
3084 ret_val = phy->ops.write_reg(hw,
3085 IGP01E1000_PHY_PORT_CONFIG,
3089 } else if (phy->smart_speed == e1000_smart_speed_off) {
3090 ret_val = phy->ops.read_reg(hw,
3091 IGP01E1000_PHY_PORT_CONFIG,
3096 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3097 ret_val = phy->ops.write_reg(hw,
3098 IGP01E1000_PHY_PORT_CONFIG,
3103 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3104 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3105 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3106 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3107 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3109 if (phy->type != e1000_phy_igp_3)
3110 return E1000_SUCCESS;
3112 /* Call gig speed drop workaround on LPLU before accessing
3115 if (hw->mac.type == e1000_ich8lan)
3116 e1000_gig_downshift_workaround_ich8lan(hw);
3118 /* When LPLU is enabled, we should disable SmartSpeed */
3119 ret_val = phy->ops.read_reg(hw,
3120 IGP01E1000_PHY_PORT_CONFIG,
3125 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3126 ret_val = phy->ops.write_reg(hw,
3127 IGP01E1000_PHY_PORT_CONFIG,
3135 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3136 * @hw: pointer to the HW structure
3137 * @bank: pointer to the variable that returns the active bank
3139 * Reads signature byte from the NVM using the flash access registers.
3140 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3142 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3145 struct e1000_nvm_info *nvm = &hw->nvm;
3146 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3147 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3151 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3153 switch (hw->mac.type) {
3156 eecd = E1000_READ_REG(hw, E1000_EECD);
3157 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3158 E1000_EECD_SEC1VAL_VALID_MASK) {
3159 if (eecd & E1000_EECD_SEC1VAL)
3164 return E1000_SUCCESS;
3166 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3169 /* set bank to 0 in case flash read fails */
3173 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3177 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3178 E1000_ICH_NVM_SIG_VALUE) {
3180 return E1000_SUCCESS;
3184 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3189 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3190 E1000_ICH_NVM_SIG_VALUE) {
3192 return E1000_SUCCESS;
3195 DEBUGOUT("ERROR: No valid NVM bank present\n");
3196 return -E1000_ERR_NVM;
3201 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3202 * @hw: pointer to the HW structure
3203 * @offset: The offset (in bytes) of the word(s) to read.
3204 * @words: Size of data to read in words
3205 * @data: Pointer to the word(s) to read at offset.
3207 * Reads a word(s) from the NVM using the flash access registers.
3209 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3212 struct e1000_nvm_info *nvm = &hw->nvm;
3213 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3215 s32 ret_val = E1000_SUCCESS;
3219 DEBUGFUNC("e1000_read_nvm_ich8lan");
3221 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3223 DEBUGOUT("nvm parameter(s) out of bounds\n");
3224 ret_val = -E1000_ERR_NVM;
3228 nvm->ops.acquire(hw);
3230 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3231 if (ret_val != E1000_SUCCESS) {
3232 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3236 act_offset = (bank) ? nvm->flash_bank_size : 0;
3237 act_offset += offset;
3239 ret_val = E1000_SUCCESS;
3240 for (i = 0; i < words; i++) {
3241 if (dev_spec->shadow_ram[offset+i].modified) {
3242 data[i] = dev_spec->shadow_ram[offset+i].value;
3244 ret_val = e1000_read_flash_word_ich8lan(hw,
3253 nvm->ops.release(hw);
3257 DEBUGOUT1("NVM read error: %d\n", ret_val);
3263 * e1000_flash_cycle_init_ich8lan - Initialize flash
3264 * @hw: pointer to the HW structure
3266 * This function does initial flash setup so that a new read/write/erase cycle
3269 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3271 union ich8_hws_flash_status hsfsts;
3272 s32 ret_val = -E1000_ERR_NVM;
3274 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3276 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3278 /* Check if the flash descriptor is valid */
3279 if (!hsfsts.hsf_status.fldesvalid) {
3280 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3281 return -E1000_ERR_NVM;
3284 /* Clear FCERR and DAEL in hw status by writing 1 */
3285 hsfsts.hsf_status.flcerr = 1;
3286 hsfsts.hsf_status.dael = 1;
3287 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3289 /* Either we should have a hardware SPI cycle in progress
3290 * bit to check against, in order to start a new cycle or
3291 * FDONE bit should be changed in the hardware so that it
3292 * is 1 after hardware reset, which can then be used as an
3293 * indication whether a cycle is in progress or has been
3297 if (!hsfsts.hsf_status.flcinprog) {
3298 /* There is no cycle running at present,
3299 * so we can start a cycle.
3300 * Begin by setting Flash Cycle Done.
3302 hsfsts.hsf_status.flcdone = 1;
3303 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3304 ret_val = E1000_SUCCESS;
3308 /* Otherwise poll for sometime so the current
3309 * cycle has a chance to end before giving up.
3311 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3312 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3314 if (!hsfsts.hsf_status.flcinprog) {
3315 ret_val = E1000_SUCCESS;
3320 if (ret_val == E1000_SUCCESS) {
3321 /* Successful in waiting for previous cycle to timeout,
3322 * now set the Flash Cycle Done.
3324 hsfsts.hsf_status.flcdone = 1;
3325 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3328 DEBUGOUT("Flash controller busy, cannot get access\n");
3336 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3337 * @hw: pointer to the HW structure
3338 * @timeout: maximum time to wait for completion
3340 * This function starts a flash cycle and waits for its completion.
3342 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3344 union ich8_hws_flash_ctrl hsflctl;
3345 union ich8_hws_flash_status hsfsts;
3348 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3350 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3351 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3352 hsflctl.hsf_ctrl.flcgo = 1;
3354 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3356 /* wait till FDONE bit is set to 1 */
3358 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3359 if (hsfsts.hsf_status.flcdone)
3362 } while (i++ < timeout);
3364 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3365 return E1000_SUCCESS;
3367 return -E1000_ERR_NVM;
3371 * e1000_read_flash_word_ich8lan - Read word from flash
3372 * @hw: pointer to the HW structure
3373 * @offset: offset to data location
3374 * @data: pointer to the location for storing the data
3376 * Reads the flash word at offset into data. Offset is converted
3377 * to bytes before read.
3379 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3382 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3385 return -E1000_ERR_NVM;
3387 /* Must convert offset into bytes. */
3390 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3394 * e1000_read_flash_byte_ich8lan - Read byte from flash
3395 * @hw: pointer to the HW structure
3396 * @offset: The offset of the byte to read.
3397 * @data: Pointer to a byte to store the value read.
3399 * Reads a single byte from the NVM using the flash access registers.
3401 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3407 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3414 return E1000_SUCCESS;
3418 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3419 * @hw: pointer to the HW structure
3420 * @offset: The offset (in bytes) of the byte or word to read.
3421 * @size: Size of data to read, 1=byte 2=word
3422 * @data: Pointer to the word to store the value read.
3424 * Reads a byte or word from the NVM using the flash access registers.
3426 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3429 union ich8_hws_flash_status hsfsts;
3430 union ich8_hws_flash_ctrl hsflctl;
3431 u32 flash_linear_addr;
3433 s32 ret_val = -E1000_ERR_NVM;
3436 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3438 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3439 return -E1000_ERR_NVM;
3440 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3441 hw->nvm.flash_base_addr);
3446 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3447 if (ret_val != E1000_SUCCESS)
3449 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3451 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3452 hsflctl.hsf_ctrl.fldbcount = size - 1;
3453 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3454 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3456 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3459 e1000_flash_cycle_ich8lan(hw,
3460 ICH_FLASH_READ_COMMAND_TIMEOUT);
3462 /* Check if FCERR is set to 1, if set to 1, clear it
3463 * and try the whole sequence a few more times, else
3464 * read in (shift in) the Flash Data0, the order is
3465 * least significant byte first msb to lsb
3467 if (ret_val == E1000_SUCCESS) {
3468 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3470 *data = (u8)(flash_data & 0x000000FF);
3472 *data = (u16)(flash_data & 0x0000FFFF);
3475 /* If we've gotten here, then things are probably
3476 * completely hosed, but if the error condition is
3477 * detected, it won't hurt to give it another try...
3478 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3480 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3482 if (hsfsts.hsf_status.flcerr) {
3483 /* Repeat for some time before giving up. */
3485 } else if (!hsfsts.hsf_status.flcdone) {
3486 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3490 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3496 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3497 * @hw: pointer to the HW structure
3498 * @offset: The offset (in bytes) of the word(s) to write.
3499 * @words: Size of data to write in words
3500 * @data: Pointer to the word(s) to write at offset.
3502 * Writes a byte or word to the NVM using the flash access registers.
3504 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3507 struct e1000_nvm_info *nvm = &hw->nvm;
3508 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3511 DEBUGFUNC("e1000_write_nvm_ich8lan");
3513 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3515 DEBUGOUT("nvm parameter(s) out of bounds\n");
3516 return -E1000_ERR_NVM;
3519 nvm->ops.acquire(hw);
3521 for (i = 0; i < words; i++) {
3522 dev_spec->shadow_ram[offset+i].modified = true;
3523 dev_spec->shadow_ram[offset+i].value = data[i];
3526 nvm->ops.release(hw);
3528 return E1000_SUCCESS;
3532 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3533 * @hw: pointer to the HW structure
3535 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3536 * which writes the checksum to the shadow ram. The changes in the shadow
3537 * ram are then committed to the EEPROM by processing each bank at a time
3538 * checking for the modified bit and writing only the pending changes.
3539 * After a successful commit, the shadow ram is cleared and is ready for
3542 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3544 struct e1000_nvm_info *nvm = &hw->nvm;
3545 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3546 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3550 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3552 ret_val = e1000_update_nvm_checksum_generic(hw);
3556 if (nvm->type != e1000_nvm_flash_sw)
3559 nvm->ops.acquire(hw);
3561 /* We're writing to the opposite bank so if we're on bank 1,
3562 * write to bank 0 etc. We also need to erase the segment that
3563 * is going to be written
3565 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3566 if (ret_val != E1000_SUCCESS) {
3567 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3572 new_bank_offset = nvm->flash_bank_size;
3573 old_bank_offset = 0;
3574 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3578 old_bank_offset = nvm->flash_bank_size;
3579 new_bank_offset = 0;
3580 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3585 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3586 /* Determine whether to write the value stored
3587 * in the other NVM bank or a modified value stored
3590 if (dev_spec->shadow_ram[i].modified) {
3591 data = dev_spec->shadow_ram[i].value;
3593 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3600 /* If the word is 0x13, then make sure the signature bits
3601 * (15:14) are 11b until the commit has completed.
3602 * This will allow us to write 10b which indicates the
3603 * signature is valid. We want to do this after the write
3604 * has completed so that we don't mark the segment valid
3605 * while the write is still in progress
3607 if (i == E1000_ICH_NVM_SIG_WORD)
3608 data |= E1000_ICH_NVM_SIG_MASK;
3610 /* Convert offset to bytes. */
3611 act_offset = (i + new_bank_offset) << 1;
3614 /* Write the bytes to the new bank. */
3615 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3622 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3629 /* Don't bother writing the segment valid bits if sector
3630 * programming failed.
3633 DEBUGOUT("Flash commit failed.\n");
3637 /* Finally validate the new segment by setting bit 15:14
3638 * to 10b in word 0x13 , this can be done without an
3639 * erase as well since these bits are 11 to start with
3640 * and we need to change bit 14 to 0b
3642 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3643 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3648 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3654 /* And invalidate the previously valid segment by setting
3655 * its signature word (0x13) high_byte to 0b. This can be
3656 * done without an erase because flash erase sets all bits
3657 * to 1's. We can write 1's to 0's without an erase
3659 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3660 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3664 /* Great! Everything worked, we can now clear the cached entries. */
3665 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3666 dev_spec->shadow_ram[i].modified = false;
3667 dev_spec->shadow_ram[i].value = 0xFFFF;
3671 nvm->ops.release(hw);
3673 /* Reload the EEPROM, or else modifications will not appear
3674 * until after the next adapter reset.
3677 nvm->ops.reload(hw);
3683 DEBUGOUT1("NVM update error: %d\n", ret_val);
3689 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3690 * @hw: pointer to the HW structure
3692 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3693 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3694 * calculated, in which case we need to calculate the checksum and set bit 6.
3696 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3701 u16 valid_csum_mask;
3703 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3705 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3706 * the checksum needs to be fixed. This bit is an indication that
3707 * the NVM was prepared by OEM software and did not calculate
3708 * the checksum...a likely scenario.
3710 switch (hw->mac.type) {
3713 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3716 word = NVM_FUTURE_INIT_WORD1;
3717 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3721 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3725 if (!(data & valid_csum_mask)) {
3726 data |= valid_csum_mask;
3727 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3730 ret_val = hw->nvm.ops.update(hw);
3735 return e1000_validate_nvm_checksum_generic(hw);
3739 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3740 * @hw: pointer to the HW structure
3741 * @offset: The offset (in bytes) of the byte/word to read.
3742 * @size: Size of data to read, 1=byte 2=word
3743 * @data: The byte(s) to write to the NVM.
3745 * Writes one/two bytes to the NVM using the flash access registers.
3747 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3750 union ich8_hws_flash_status hsfsts;
3751 union ich8_hws_flash_ctrl hsflctl;
3752 u32 flash_linear_addr;
3757 DEBUGFUNC("e1000_write_ich8_data");
3759 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3760 return -E1000_ERR_NVM;
3762 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3763 hw->nvm.flash_base_addr);
3768 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3769 if (ret_val != E1000_SUCCESS)
3771 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3773 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3774 hsflctl.hsf_ctrl.fldbcount = size - 1;
3775 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3776 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3778 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3781 flash_data = (u32)data & 0x00FF;
3783 flash_data = (u32)data;
3785 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3787 /* check if FCERR is set to 1 , if set to 1, clear it
3788 * and try the whole sequence a few more times else done
3791 e1000_flash_cycle_ich8lan(hw,
3792 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3793 if (ret_val == E1000_SUCCESS)
3796 /* If we're here, then things are most likely
3797 * completely hosed, but if the error condition
3798 * is detected, it won't hurt to give it another
3799 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3801 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3802 if (hsfsts.hsf_status.flcerr)
3803 /* Repeat for some time before giving up. */
3805 if (!hsfsts.hsf_status.flcdone) {
3806 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3809 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3815 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3816 * @hw: pointer to the HW structure
3817 * @offset: The index of the byte to read.
3818 * @data: The byte to write to the NVM.
3820 * Writes a single byte to the NVM using the flash access registers.
3822 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3825 u16 word = (u16)data;
3827 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3829 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3833 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3834 * @hw: pointer to the HW structure
3835 * @offset: The offset of the byte to write.
3836 * @byte: The byte to write to the NVM.
3838 * Writes a single byte to the NVM using the flash access registers.
3839 * Goes through a retry algorithm before giving up.
3841 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3842 u32 offset, u8 byte)
3845 u16 program_retries;
3847 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3849 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3853 for (program_retries = 0; program_retries < 100; program_retries++) {
3854 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3856 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3857 if (ret_val == E1000_SUCCESS)
3860 if (program_retries == 100)
3861 return -E1000_ERR_NVM;
3863 return E1000_SUCCESS;
3867 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3868 * @hw: pointer to the HW structure
3869 * @bank: 0 for first bank, 1 for second bank, etc.
3871 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3872 * bank N is 4096 * N + flash_reg_addr.
3874 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3876 struct e1000_nvm_info *nvm = &hw->nvm;
3877 union ich8_hws_flash_status hsfsts;
3878 union ich8_hws_flash_ctrl hsflctl;
3879 u32 flash_linear_addr;
3880 /* bank size is in 16bit words - adjust to bytes */
3881 u32 flash_bank_size = nvm->flash_bank_size * 2;
3884 s32 j, iteration, sector_size;
3886 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3888 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3890 /* Determine HW Sector size: Read BERASE bits of hw flash status
3892 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3893 * consecutive sectors. The start index for the nth Hw sector
3894 * can be calculated as = bank * 4096 + n * 256
3895 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3896 * The start index for the nth Hw sector can be calculated
3898 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3899 * (ich9 only, otherwise error condition)
3900 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3902 switch (hsfsts.hsf_status.berasesz) {
3904 /* Hw sector size 256 */
3905 sector_size = ICH_FLASH_SEG_SIZE_256;
3906 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3909 sector_size = ICH_FLASH_SEG_SIZE_4K;
3913 sector_size = ICH_FLASH_SEG_SIZE_8K;
3917 sector_size = ICH_FLASH_SEG_SIZE_64K;
3921 return -E1000_ERR_NVM;
3924 /* Start with the base address, then add the sector offset. */
3925 flash_linear_addr = hw->nvm.flash_base_addr;
3926 flash_linear_addr += (bank) ? flash_bank_size : 0;
3928 for (j = 0; j < iteration; j++) {
3930 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3933 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3937 /* Write a value 11 (block Erase) in Flash
3938 * Cycle field in hw flash control
3941 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3943 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3944 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3947 /* Write the last 24 bits of an index within the
3948 * block into Flash Linear address field in Flash
3951 flash_linear_addr += (j * sector_size);
3952 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
3955 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3956 if (ret_val == E1000_SUCCESS)
3959 /* Check if FCERR is set to 1. If 1,
3960 * clear it and try the whole sequence
3961 * a few more times else Done
3963 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3965 if (hsfsts.hsf_status.flcerr)
3966 /* repeat for some time before giving up */
3968 else if (!hsfsts.hsf_status.flcdone)
3970 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3973 return E1000_SUCCESS;
3977 * e1000_valid_led_default_ich8lan - Set the default LED settings
3978 * @hw: pointer to the HW structure
3979 * @data: Pointer to the LED settings
3981 * Reads the LED default settings from the NVM to data. If the NVM LED
3982 * settings is all 0's or F's, set the LED default to a valid LED default
3985 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3989 DEBUGFUNC("e1000_valid_led_default_ich8lan");
3991 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
3993 DEBUGOUT("NVM Read Error\n");
3997 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3998 *data = ID_LED_DEFAULT_ICH8LAN;
4000 return E1000_SUCCESS;
4004 * e1000_id_led_init_pchlan - store LED configurations
4005 * @hw: pointer to the HW structure
4007 * PCH does not control LEDs via the LEDCTL register, rather it uses
4008 * the PHY LED configuration register.
4010 * PCH also does not have an "always on" or "always off" mode which
4011 * complicates the ID feature. Instead of using the "on" mode to indicate
4012 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4013 * use "link_up" mode. The LEDs will still ID on request if there is no
4014 * link based on logic in e1000_led_[on|off]_pchlan().
4016 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4018 struct e1000_mac_info *mac = &hw->mac;
4020 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4021 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4022 u16 data, i, temp, shift;
4024 DEBUGFUNC("e1000_id_led_init_pchlan");
4026 /* Get default ID LED modes */
4027 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4031 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4032 mac->ledctl_mode1 = mac->ledctl_default;
4033 mac->ledctl_mode2 = mac->ledctl_default;
4035 for (i = 0; i < 4; i++) {
4036 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4039 case ID_LED_ON1_DEF2:
4040 case ID_LED_ON1_ON2:
4041 case ID_LED_ON1_OFF2:
4042 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4043 mac->ledctl_mode1 |= (ledctl_on << shift);
4045 case ID_LED_OFF1_DEF2:
4046 case ID_LED_OFF1_ON2:
4047 case ID_LED_OFF1_OFF2:
4048 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4049 mac->ledctl_mode1 |= (ledctl_off << shift);
4056 case ID_LED_DEF1_ON2:
4057 case ID_LED_ON1_ON2:
4058 case ID_LED_OFF1_ON2:
4059 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4060 mac->ledctl_mode2 |= (ledctl_on << shift);
4062 case ID_LED_DEF1_OFF2:
4063 case ID_LED_ON1_OFF2:
4064 case ID_LED_OFF1_OFF2:
4065 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4066 mac->ledctl_mode2 |= (ledctl_off << shift);
4074 return E1000_SUCCESS;
4078 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4079 * @hw: pointer to the HW structure
4081 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4082 * register, so the the bus width is hard coded.
4084 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4086 struct e1000_bus_info *bus = &hw->bus;
4089 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4091 ret_val = e1000_get_bus_info_pcie_generic(hw);
4093 /* ICH devices are "PCI Express"-ish. They have
4094 * a configuration space, but do not contain
4095 * PCI Express Capability registers, so bus width
4096 * must be hardcoded.
4098 if (bus->width == e1000_bus_width_unknown)
4099 bus->width = e1000_bus_width_pcie_x1;
4105 * e1000_reset_hw_ich8lan - Reset the hardware
4106 * @hw: pointer to the HW structure
4108 * Does a full reset of the hardware which includes a reset of the PHY and
4111 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4113 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4118 DEBUGFUNC("e1000_reset_hw_ich8lan");
4120 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4121 * on the last TLP read/write transaction when MAC is reset.
4123 ret_val = e1000_disable_pcie_master_generic(hw);
4125 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4127 DEBUGOUT("Masking off all interrupts\n");
4128 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4130 /* Disable the Transmit and Receive units. Then delay to allow
4131 * any pending transactions to complete before we hit the MAC
4132 * with the global reset.
4134 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4135 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4136 E1000_WRITE_FLUSH(hw);
4140 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4141 if (hw->mac.type == e1000_ich8lan) {
4142 /* Set Tx and Rx buffer allocation to 8k apiece. */
4143 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4144 /* Set Packet Buffer Size to 16k. */
4145 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4148 if (hw->mac.type == e1000_pchlan) {
4149 /* Save the NVM K1 bit setting*/
4150 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4154 if (kum_cfg & E1000_NVM_K1_ENABLE)
4155 dev_spec->nvm_k1_enabled = true;
4157 dev_spec->nvm_k1_enabled = false;
4160 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4162 if (!hw->phy.ops.check_reset_block(hw)) {
4163 /* Full-chip reset requires MAC and PHY reset at the same
4164 * time to make sure the interface between MAC and the
4165 * external PHY is reset.
4167 ctrl |= E1000_CTRL_PHY_RST;
4169 /* Gate automatic PHY configuration by hardware on
4172 if ((hw->mac.type == e1000_pch2lan) &&
4173 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4174 e1000_gate_hw_phy_config_ich8lan(hw, true);
4176 ret_val = e1000_acquire_swflag_ich8lan(hw);
4177 DEBUGOUT("Issuing a global reset to ich8lan\n");
4178 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4179 /* cannot issue a flush here because it hangs the hardware */
4182 /* Set Phy Config Counter to 50msec */
4183 if (hw->mac.type == e1000_pch2lan) {
4184 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4185 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4186 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4187 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4191 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4193 if (ctrl & E1000_CTRL_PHY_RST) {
4194 ret_val = hw->phy.ops.get_cfg_done(hw);
4198 ret_val = e1000_post_phy_reset_ich8lan(hw);
4203 /* For PCH, this write will make sure that any noise
4204 * will be detected as a CRC error and be dropped rather than show up
4205 * as a bad packet to the DMA engine.
4207 if (hw->mac.type == e1000_pchlan)
4208 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4210 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4211 E1000_READ_REG(hw, E1000_ICR);
4213 reg = E1000_READ_REG(hw, E1000_KABGTXD);
4214 reg |= E1000_KABGTXD_BGSQLBIAS;
4215 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4217 return E1000_SUCCESS;
4221 * e1000_init_hw_ich8lan - Initialize the hardware
4222 * @hw: pointer to the HW structure
4224 * Prepares the hardware for transmit and receive by doing the following:
4225 * - initialize hardware bits
4226 * - initialize LED identification
4227 * - setup receive address registers
4228 * - setup flow control
4229 * - setup transmit descriptors
4230 * - clear statistics
4232 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4234 struct e1000_mac_info *mac = &hw->mac;
4235 u32 ctrl_ext, txdctl, snoop;
4239 DEBUGFUNC("e1000_init_hw_ich8lan");
4241 e1000_initialize_hw_bits_ich8lan(hw);
4243 /* Initialize identification LED */
4244 ret_val = mac->ops.id_led_init(hw);
4245 /* An error is not fatal and we should not stop init due to this */
4247 DEBUGOUT("Error initializing identification LED\n");
4249 /* Setup the receive address. */
4250 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4252 /* Zero out the Multicast HASH table */
4253 DEBUGOUT("Zeroing the MTA\n");
4254 for (i = 0; i < mac->mta_reg_count; i++)
4255 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4257 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4258 * the ME. Disable wakeup by clearing the host wakeup bit.
4259 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4261 if (hw->phy.type == e1000_phy_82578) {
4262 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4263 i &= ~BM_WUC_HOST_WU_BIT;
4264 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4265 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4270 /* Setup link and flow control */
4271 ret_val = mac->ops.setup_link(hw);
4273 /* Set the transmit descriptor write-back policy for both queues */
4274 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4275 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4276 E1000_TXDCTL_FULL_TX_DESC_WB);
4277 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4278 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4279 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4280 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4281 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4282 E1000_TXDCTL_FULL_TX_DESC_WB);
4283 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4284 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4285 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4287 /* ICH8 has opposite polarity of no_snoop bits.
4288 * By default, we should use snoop behavior.
4290 if (mac->type == e1000_ich8lan)
4291 snoop = PCIE_ICH8_SNOOP_ALL;
4293 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4294 e1000_set_pcie_no_snoop_generic(hw, snoop);
4296 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4297 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4298 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4300 /* Clear all of the statistics registers (clear on read). It is
4301 * important that we do this after we have tried to establish link
4302 * because the symbol error count will increment wildly if there
4305 e1000_clear_hw_cntrs_ich8lan(hw);
4311 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4312 * @hw: pointer to the HW structure
4314 * Sets/Clears required hardware bits necessary for correctly setting up the
4315 * hardware for transmit and receive.
4317 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4321 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4323 /* Extended Device Control */
4324 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4326 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4327 if (hw->mac.type >= e1000_pchlan)
4328 reg |= E1000_CTRL_EXT_PHYPDEN;
4329 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4331 /* Transmit Descriptor Control 0 */
4332 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4334 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4336 /* Transmit Descriptor Control 1 */
4337 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4339 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4341 /* Transmit Arbitration Control 0 */
4342 reg = E1000_READ_REG(hw, E1000_TARC(0));
4343 if (hw->mac.type == e1000_ich8lan)
4344 reg |= (1 << 28) | (1 << 29);
4345 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4346 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4348 /* Transmit Arbitration Control 1 */
4349 reg = E1000_READ_REG(hw, E1000_TARC(1));
4350 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4354 reg |= (1 << 24) | (1 << 26) | (1 << 30);
4355 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4358 if (hw->mac.type == e1000_ich8lan) {
4359 reg = E1000_READ_REG(hw, E1000_STATUS);
4361 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4364 /* work-around descriptor data corruption issue during nfs v2 udp
4365 * traffic, just disable the nfs filtering capability
4367 reg = E1000_READ_REG(hw, E1000_RFCTL);
4368 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4370 /* Disable IPv6 extension header parsing because some malformed
4371 * IPv6 headers can hang the Rx.
4373 if (hw->mac.type == e1000_ich8lan)
4374 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4375 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4377 /* Enable ECC on Lynxpoint */
4378 if (hw->mac.type == e1000_pch_lpt) {
4379 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4380 reg |= E1000_PBECCSTS_ECC_ENABLE;
4381 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4383 reg = E1000_READ_REG(hw, E1000_CTRL);
4384 reg |= E1000_CTRL_MEHE;
4385 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4392 * e1000_setup_link_ich8lan - Setup flow control and link settings
4393 * @hw: pointer to the HW structure
4395 * Determines which flow control settings to use, then configures flow
4396 * control. Calls the appropriate media-specific link configuration
4397 * function. Assuming the adapter has a valid link partner, a valid link
4398 * should be established. Assumes the hardware has previously been reset
4399 * and the transmitter and receiver are not enabled.
4401 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4405 DEBUGFUNC("e1000_setup_link_ich8lan");
4407 if (hw->phy.ops.check_reset_block(hw))
4408 return E1000_SUCCESS;
4410 /* ICH parts do not have a word in the NVM to determine
4411 * the default flow control setting, so we explicitly
4414 if (hw->fc.requested_mode == e1000_fc_default)
4415 hw->fc.requested_mode = e1000_fc_full;
4417 /* Save off the requested flow control mode for use later. Depending
4418 * on the link partner's capabilities, we may or may not use this mode.
4420 hw->fc.current_mode = hw->fc.requested_mode;
4422 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4423 hw->fc.current_mode);
4425 /* Continue to configure the copper link. */
4426 ret_val = hw->mac.ops.setup_physical_interface(hw);
4430 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4431 if ((hw->phy.type == e1000_phy_82578) ||
4432 (hw->phy.type == e1000_phy_82579) ||
4433 (hw->phy.type == e1000_phy_i217) ||
4434 (hw->phy.type == e1000_phy_82577)) {
4435 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4437 ret_val = hw->phy.ops.write_reg(hw,
4438 PHY_REG(BM_PORT_CTRL_PAGE, 27),
4444 return e1000_set_fc_watermarks_generic(hw);
4448 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4449 * @hw: pointer to the HW structure
4451 * Configures the kumeran interface to the PHY to wait the appropriate time
4452 * when polling the PHY, then call the generic setup_copper_link to finish
4453 * configuring the copper link.
4455 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4461 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4463 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4464 ctrl |= E1000_CTRL_SLU;
4465 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4466 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4468 /* Set the mac to wait the maximum time between each iteration
4469 * and increase the max iterations when polling the phy;
4470 * this fixes erroneous timeouts at 10Mbps.
4472 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4476 ret_val = e1000_read_kmrn_reg_generic(hw,
4477 E1000_KMRNCTRLSTA_INBAND_PARAM,
4482 ret_val = e1000_write_kmrn_reg_generic(hw,
4483 E1000_KMRNCTRLSTA_INBAND_PARAM,
4488 switch (hw->phy.type) {
4489 case e1000_phy_igp_3:
4490 ret_val = e1000_copper_link_setup_igp(hw);
4495 case e1000_phy_82578:
4496 ret_val = e1000_copper_link_setup_m88(hw);
4500 case e1000_phy_82577:
4501 case e1000_phy_82579:
4502 ret_val = e1000_copper_link_setup_82577(hw);
4507 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4512 reg_data &= ~IFE_PMC_AUTO_MDIX;
4514 switch (hw->phy.mdix) {
4516 reg_data &= ~IFE_PMC_FORCE_MDIX;
4519 reg_data |= IFE_PMC_FORCE_MDIX;
4523 reg_data |= IFE_PMC_AUTO_MDIX;
4526 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4535 return e1000_setup_copper_link_generic(hw);
4539 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4540 * @hw: pointer to the HW structure
4542 * Calls the PHY specific link setup function and then calls the
4543 * generic setup_copper_link to finish configuring the link for
4544 * Lynxpoint PCH devices
4546 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4551 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4553 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4554 ctrl |= E1000_CTRL_SLU;
4555 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4556 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4558 ret_val = e1000_copper_link_setup_82577(hw);
4562 return e1000_setup_copper_link_generic(hw);
4566 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4567 * @hw: pointer to the HW structure
4568 * @speed: pointer to store current link speed
4569 * @duplex: pointer to store the current link duplex
4571 * Calls the generic get_speed_and_duplex to retrieve the current link
4572 * information and then calls the Kumeran lock loss workaround for links at
4575 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4580 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4582 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4586 if ((hw->mac.type == e1000_ich8lan) &&
4587 (hw->phy.type == e1000_phy_igp_3) &&
4588 (*speed == SPEED_1000)) {
4589 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4596 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4597 * @hw: pointer to the HW structure
4599 * Work-around for 82566 Kumeran PCS lock loss:
4600 * On link status change (i.e. PCI reset, speed change) and link is up and
4602 * 0) if workaround is optionally disabled do nothing
4603 * 1) wait 1ms for Kumeran link to come up
4604 * 2) check Kumeran Diagnostic register PCS lock loss bit
4605 * 3) if not set the link is locked (all is good), otherwise...
4607 * 5) repeat up to 10 times
4608 * Note: this is only called for IGP3 copper when speed is 1gb.
4610 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4612 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4618 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4620 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4621 return E1000_SUCCESS;
4623 /* Make sure link is up before proceeding. If not just return.
4624 * Attempting this while link is negotiating fouled up link
4627 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4629 return E1000_SUCCESS;
4631 for (i = 0; i < 10; i++) {
4632 /* read once to clear */
4633 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4636 /* and again to get new status */
4637 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4641 /* check for PCS lock */
4642 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4643 return E1000_SUCCESS;
4645 /* Issue PHY reset */
4646 hw->phy.ops.reset(hw);
4649 /* Disable GigE link negotiation */
4650 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4651 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4652 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4653 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4655 /* Call gig speed drop workaround on Gig disable before accessing
4658 e1000_gig_downshift_workaround_ich8lan(hw);
4660 /* unable to acquire PCS lock */
4661 return -E1000_ERR_PHY;
4665 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4666 * @hw: pointer to the HW structure
4667 * @state: boolean value used to set the current Kumeran workaround state
4669 * If ICH8, set the current Kumeran workaround state (enabled - true
4670 * /disabled - false).
4672 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4675 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4677 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4679 if (hw->mac.type != e1000_ich8lan) {
4680 DEBUGOUT("Workaround applies to ICH8 only.\n");
4684 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4690 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4691 * @hw: pointer to the HW structure
4693 * Workaround for 82566 power-down on D3 entry:
4694 * 1) disable gigabit link
4695 * 2) write VR power-down enable
4697 * Continue if successful, else issue LCD reset and repeat
4699 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4705 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4707 if (hw->phy.type != e1000_phy_igp_3)
4710 /* Try the workaround twice (if needed) */
4713 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4714 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4715 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4716 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4718 /* Call gig speed drop workaround on Gig disable before
4719 * accessing any PHY registers
4721 if (hw->mac.type == e1000_ich8lan)
4722 e1000_gig_downshift_workaround_ich8lan(hw);
4724 /* Write VR power-down enable */
4725 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4726 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4727 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4728 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4730 /* Read it back and test */
4731 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4732 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4733 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4736 /* Issue PHY reset and repeat at most one more time */
4737 reg = E1000_READ_REG(hw, E1000_CTRL);
4738 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4744 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4745 * @hw: pointer to the HW structure
4747 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4748 * LPLU, Gig disable, MDIC PHY reset):
4749 * 1) Set Kumeran Near-end loopback
4750 * 2) Clear Kumeran Near-end loopback
4751 * Should only be called for ICH8[m] devices with any 1G Phy.
4753 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4758 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4760 if ((hw->mac.type != e1000_ich8lan) ||
4761 (hw->phy.type == e1000_phy_ife))
4764 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4768 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4769 ret_val = e1000_write_kmrn_reg_generic(hw,
4770 E1000_KMRNCTRLSTA_DIAG_OFFSET,
4774 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4775 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4780 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4781 * @hw: pointer to the HW structure
4783 * During S0 to Sx transition, it is possible the link remains at gig
4784 * instead of negotiating to a lower speed. Before going to Sx, set
4785 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4786 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4787 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4788 * needs to be written.
4789 * Parts that support (and are linked to a partner which support) EEE in
4790 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4791 * than 10Mbps w/o EEE.
4793 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4795 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4799 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4801 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4802 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4804 if (hw->phy.type == e1000_phy_i217) {
4805 u16 phy_reg, device_id = hw->device_id;
4807 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4808 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4809 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4810 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4811 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4813 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4814 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4817 ret_val = hw->phy.ops.acquire(hw);
4821 if (!dev_spec->eee_disable) {
4825 e1000_read_emi_reg_locked(hw,
4826 I217_EEE_ADVERTISEMENT,
4831 /* Disable LPLU if both link partners support 100BaseT
4832 * EEE and 100Full is advertised on both ends of the
4833 * link, and enable Auto Enable LPI since there will
4834 * be no driver to enable LPI while in Sx.
4836 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4837 (dev_spec->eee_lp_ability &
4838 I82579_EEE_100_SUPPORTED) &&
4839 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4840 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4841 E1000_PHY_CTRL_NOND0A_LPLU);
4843 /* Set Auto Enable LPI after link up */
4844 hw->phy.ops.read_reg_locked(hw,
4847 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4848 hw->phy.ops.write_reg_locked(hw,
4854 /* For i217 Intel Rapid Start Technology support,
4855 * when the system is going into Sx and no manageability engine
4856 * is present, the driver must configure proxy to reset only on
4857 * power good. LPI (Low Power Idle) state must also reset only
4858 * on power good, as well as the MTA (Multicast table array).
4859 * The SMBus release must also be disabled on LCD reset.
4861 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4862 E1000_ICH_FWSM_FW_VALID)) {
4863 /* Enable proxy to reset only on power good. */
4864 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4866 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4867 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4870 /* Set bit enable LPI (EEE) to reset only on
4873 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4874 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4875 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4877 /* Disable the SMB release on LCD reset. */
4878 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4879 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4880 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4883 /* Enable MTA to reset for Intel Rapid Start Technology
4886 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4887 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4888 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4891 hw->phy.ops.release(hw);
4894 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4896 if (hw->mac.type == e1000_ich8lan)
4897 e1000_gig_downshift_workaround_ich8lan(hw);
4899 if (hw->mac.type >= e1000_pchlan) {
4900 e1000_oem_bits_config_ich8lan(hw, false);
4902 /* Reset PHY to activate OEM bits on 82577/8 */
4903 if (hw->mac.type == e1000_pchlan)
4904 e1000_phy_hw_reset_generic(hw);
4906 ret_val = hw->phy.ops.acquire(hw);
4909 e1000_write_smbus_addr(hw);
4910 hw->phy.ops.release(hw);
4917 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4918 * @hw: pointer to the HW structure
4920 * During Sx to S0 transitions on non-managed devices or managed devices
4921 * on which PHY resets are not blocked, if the PHY registers cannot be
4922 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4924 * On i217, setup Intel Rapid Start Technology.
4926 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4930 DEBUGFUNC("e1000_resume_workarounds_pchlan");
4931 if (hw->mac.type < e1000_pch2lan)
4932 return E1000_SUCCESS;
4934 ret_val = e1000_init_phy_workarounds_pchlan(hw);
4936 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4940 /* For i217 Intel Rapid Start Technology support when the system
4941 * is transitioning from Sx and no manageability engine is present
4942 * configure SMBus to restore on reset, disable proxy, and enable
4943 * the reset on MTA (Multicast table array).
4945 if (hw->phy.type == e1000_phy_i217) {
4948 ret_val = hw->phy.ops.acquire(hw);
4950 DEBUGOUT("Failed to setup iRST\n");
4954 /* Clear Auto Enable LPI after link up */
4955 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
4956 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4957 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
4959 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4960 E1000_ICH_FWSM_FW_VALID)) {
4961 /* Restore clear on SMB if no manageability engine
4964 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
4968 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4969 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4972 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
4974 /* Enable reset on MTA */
4975 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
4979 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4980 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4983 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
4984 hw->phy.ops.release(hw);
4987 return E1000_SUCCESS;
4991 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4992 * @hw: pointer to the HW structure
4994 * Return the LED back to the default configuration.
4996 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4998 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5000 if (hw->phy.type == e1000_phy_ife)
5001 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5004 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5005 return E1000_SUCCESS;
5009 * e1000_led_on_ich8lan - Turn LEDs on
5010 * @hw: pointer to the HW structure
5014 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5016 DEBUGFUNC("e1000_led_on_ich8lan");
5018 if (hw->phy.type == e1000_phy_ife)
5019 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5020 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5022 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5023 return E1000_SUCCESS;
5027 * e1000_led_off_ich8lan - Turn LEDs off
5028 * @hw: pointer to the HW structure
5030 * Turn off the LEDs.
5032 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5034 DEBUGFUNC("e1000_led_off_ich8lan");
5036 if (hw->phy.type == e1000_phy_ife)
5037 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5038 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5040 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5041 return E1000_SUCCESS;
5045 * e1000_setup_led_pchlan - Configures SW controllable LED
5046 * @hw: pointer to the HW structure
5048 * This prepares the SW controllable LED for use.
5050 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5052 DEBUGFUNC("e1000_setup_led_pchlan");
5054 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5055 (u16)hw->mac.ledctl_mode1);
5059 * e1000_cleanup_led_pchlan - Restore the default LED operation
5060 * @hw: pointer to the HW structure
5062 * Return the LED back to the default configuration.
5064 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5066 DEBUGFUNC("e1000_cleanup_led_pchlan");
5068 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5069 (u16)hw->mac.ledctl_default);
5073 * e1000_led_on_pchlan - Turn LEDs on
5074 * @hw: pointer to the HW structure
5078 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5080 u16 data = (u16)hw->mac.ledctl_mode2;
5083 DEBUGFUNC("e1000_led_on_pchlan");
5085 /* If no link, then turn LED on by setting the invert bit
5086 * for each LED that's mode is "link_up" in ledctl_mode2.
5088 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5089 for (i = 0; i < 3; i++) {
5090 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5091 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5092 E1000_LEDCTL_MODE_LINK_UP)
5094 if (led & E1000_PHY_LED0_IVRT)
5095 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5097 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5101 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5105 * e1000_led_off_pchlan - Turn LEDs off
5106 * @hw: pointer to the HW structure
5108 * Turn off the LEDs.
5110 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5112 u16 data = (u16)hw->mac.ledctl_mode1;
5115 DEBUGFUNC("e1000_led_off_pchlan");
5117 /* If no link, then turn LED off by clearing the invert bit
5118 * for each LED that's mode is "link_up" in ledctl_mode1.
5120 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5121 for (i = 0; i < 3; i++) {
5122 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5123 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5124 E1000_LEDCTL_MODE_LINK_UP)
5126 if (led & E1000_PHY_LED0_IVRT)
5127 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5129 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5133 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5137 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5138 * @hw: pointer to the HW structure
5140 * Read appropriate register for the config done bit for completion status
5141 * and configure the PHY through s/w for EEPROM-less parts.
5143 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5144 * config done bit, so only an error is logged and continues. If we were
5145 * to return with error, EEPROM-less silicon would not be able to be reset
5148 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5150 s32 ret_val = E1000_SUCCESS;
5154 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5156 e1000_get_cfg_done_generic(hw);
5158 /* Wait for indication from h/w that it has completed basic config */
5159 if (hw->mac.type >= e1000_ich10lan) {
5160 e1000_lan_init_done_ich8lan(hw);
5162 ret_val = e1000_get_auto_rd_done_generic(hw);
5164 /* When auto config read does not complete, do not
5165 * return with an error. This can happen in situations
5166 * where there is no eeprom and prevents getting link.
5168 DEBUGOUT("Auto Read Done did not complete\n");
5169 ret_val = E1000_SUCCESS;
5173 /* Clear PHY Reset Asserted bit */
5174 status = E1000_READ_REG(hw, E1000_STATUS);
5175 if (status & E1000_STATUS_PHYRA)
5176 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5178 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5180 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5181 if (hw->mac.type <= e1000_ich9lan) {
5182 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5183 (hw->phy.type == e1000_phy_igp_3)) {
5184 e1000_phy_init_script_igp3(hw);
5187 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5188 /* Maybe we should do a basic PHY config */
5189 DEBUGOUT("EEPROM not present\n");
5190 ret_val = -E1000_ERR_CONFIG;
5198 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5199 * @hw: pointer to the HW structure
5201 * In the case of a PHY power down to save power, or to turn off link during a
5202 * driver unload, or wake on lan is not enabled, remove the link.
5204 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5206 /* If the management interface is not enabled, then power down */
5207 if (!(hw->mac.ops.check_mng_mode(hw) ||
5208 hw->phy.ops.check_reset_block(hw)))
5209 e1000_power_down_phy_copper(hw);
5215 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5216 * @hw: pointer to the HW structure
5218 * Clears hardware counters specific to the silicon family and calls
5219 * clear_hw_cntrs_generic to clear all general purpose counters.
5221 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5226 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5228 e1000_clear_hw_cntrs_base_generic(hw);
5230 E1000_READ_REG(hw, E1000_ALGNERRC);
5231 E1000_READ_REG(hw, E1000_RXERRC);
5232 E1000_READ_REG(hw, E1000_TNCRS);
5233 E1000_READ_REG(hw, E1000_CEXTERR);
5234 E1000_READ_REG(hw, E1000_TSCTC);
5235 E1000_READ_REG(hw, E1000_TSCTFC);
5237 E1000_READ_REG(hw, E1000_MGTPRC);
5238 E1000_READ_REG(hw, E1000_MGTPDC);
5239 E1000_READ_REG(hw, E1000_MGTPTC);
5241 E1000_READ_REG(hw, E1000_IAC);
5242 E1000_READ_REG(hw, E1000_ICRXOC);
5244 /* Clear PHY statistics registers */
5245 if ((hw->phy.type == e1000_phy_82578) ||
5246 (hw->phy.type == e1000_phy_82579) ||
5247 (hw->phy.type == e1000_phy_i217) ||
5248 (hw->phy.type == e1000_phy_82577)) {
5249 ret_val = hw->phy.ops.acquire(hw);
5252 ret_val = hw->phy.ops.set_page(hw,
5253 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5256 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5257 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5258 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5259 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5260 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5261 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5262 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5263 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5264 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5265 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5266 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5267 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5268 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5269 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5271 hw->phy.ops.release(hw);