1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
5 /* 82562G 10/100 Network Connection
6 * 82562G-2 10/100 Network Connection
7 * 82562GT 10/100 Network Connection
8 * 82562GT-2 10/100 Network Connection
9 * 82562V 10/100 Network Connection
10 * 82562V-2 10/100 Network Connection
11 * 82566DC-2 Gigabit Network Connection
12 * 82566DC Gigabit Network Connection
13 * 82566DM-2 Gigabit Network Connection
14 * 82566DM Gigabit Network Connection
15 * 82566MC Gigabit Network Connection
16 * 82566MM Gigabit Network Connection
17 * 82567LM Gigabit Network Connection
18 * 82567LF Gigabit Network Connection
19 * 82567V Gigabit Network Connection
20 * 82567LM-2 Gigabit Network Connection
21 * 82567LF-2 Gigabit Network Connection
22 * 82567V-2 Gigabit Network Connection
23 * 82567LF-3 Gigabit Network Connection
24 * 82567LM-3 Gigabit Network Connection
25 * 82567LM-4 Gigabit Network Connection
26 * 82577LM Gigabit Network Connection
27 * 82577LC Gigabit Network Connection
28 * 82578DM Gigabit Network Connection
29 * 82578DC Gigabit Network Connection
30 * 82579LM Gigabit Network Connection
31 * 82579V Gigabit Network Connection
32 * Ethernet Connection I217-LM
33 * Ethernet Connection I217-V
34 * Ethernet Connection I218-V
35 * Ethernet Connection I218-LM
36 * Ethernet Connection (2) I218-LM
37 * Ethernet Connection (2) I218-V
38 * Ethernet Connection (3) I218-LM
39 * Ethernet Connection (3) I218-V
42 #include "e1000_api.h"
44 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
45 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
46 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
47 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
48 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
49 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
50 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
51 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
52 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
53 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
54 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
55 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
58 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
59 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
60 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
61 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
62 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
64 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
66 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
67 u16 words, u16 *data);
68 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
70 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
71 u16 words, u16 *data);
72 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
73 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
74 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
75 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
77 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
78 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
79 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
80 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
81 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
82 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
83 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
84 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
85 u16 *speed, u16 *duplex);
86 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
87 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
88 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
89 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
90 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
91 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
92 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
93 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
94 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
95 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
96 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
97 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
98 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
99 u32 offset, u8 *data);
100 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
102 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
104 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
105 u32 offset, u32 *data);
106 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
107 u32 offset, u32 data);
108 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
109 u32 offset, u32 dword);
110 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
111 u32 offset, u16 *data);
112 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
113 u32 offset, u8 byte);
114 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
115 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
116 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
117 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
118 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
119 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
121 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
122 /* Offset 04h HSFSTS */
123 union ich8_hws_flash_status {
125 u16 flcdone:1; /* bit 0 Flash Cycle Done */
126 u16 flcerr:1; /* bit 1 Flash Cycle Error */
127 u16 dael:1; /* bit 2 Direct Access error Log */
128 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
129 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
130 u16 reserved1:2; /* bit 13:6 Reserved */
131 u16 reserved2:6; /* bit 13:6 Reserved */
132 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
133 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
138 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
139 /* Offset 06h FLCTL */
140 union ich8_hws_flash_ctrl {
141 struct ich8_hsflctl {
142 u16 flcgo:1; /* 0 Flash Cycle Go */
143 u16 flcycle:2; /* 2:1 Flash Cycle */
144 u16 reserved:5; /* 7:3 Reserved */
145 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
146 u16 flockdn:6; /* 15:10 Reserved */
151 /* ICH Flash Region Access Permissions */
152 union ich8_hws_flash_regacc {
154 u32 grra:8; /* 0:7 GbE region Read Access */
155 u32 grwa:8; /* 8:15 GbE region Write Access */
156 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
157 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
163 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
164 * @hw: pointer to the HW structure
166 * Test access to the PHY registers by reading the PHY ID registers. If
167 * the PHY ID is already known (e.g. resume path) compare it with known ID,
168 * otherwise assume the read PHY ID is correct if it is valid.
170 * Assumes the sw/fw/hw semaphore is already acquired.
172 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
180 for (retry_count = 0; retry_count < 2; retry_count++) {
181 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
182 if (ret_val || (phy_reg == 0xFFFF))
184 phy_id = (u32)(phy_reg << 16);
186 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
187 if (ret_val || (phy_reg == 0xFFFF)) {
191 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 if (hw->phy.id == phy_id)
200 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
204 /* In case the PHY needs to be in mdio slow mode,
205 * set slow mode and try to get the PHY id again.
207 if (hw->mac.type < e1000_pch_lpt) {
208 hw->phy.ops.release(hw);
209 ret_val = e1000_set_mdio_slow_mode_hv(hw);
211 ret_val = e1000_get_phy_id(hw);
212 hw->phy.ops.acquire(hw);
218 if (hw->mac.type >= e1000_pch_lpt) {
219 /* Only unforce SMBus if ME is not active */
220 if (!(E1000_READ_REG(hw, E1000_FWSM) &
221 E1000_ICH_FWSM_FW_VALID)) {
222 /* Unforce SMBus mode in PHY */
223 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
224 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
225 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
227 /* Unforce SMBus mode in MAC */
228 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
229 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
230 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
238 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
239 * @hw: pointer to the HW structure
241 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
242 * used to reset the PHY to a quiescent state when necessary.
244 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
250 /* Set Phy Config Counter to 50msec */
251 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
252 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
253 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
254 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
256 /* Toggle LANPHYPC Value bit */
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
258 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
259 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
260 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
261 E1000_WRITE_FLUSH(hw);
263 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
264 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
265 E1000_WRITE_FLUSH(hw);
267 if (hw->mac.type < e1000_pch_lpt) {
274 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
275 E1000_CTRL_EXT_LPCD) && count--);
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
285 * Workarounds/flow necessary for PHY initialization during driver load
288 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
290 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
293 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
295 /* Gate automatic PHY configuration by hardware on managed and
296 * non-managed 82579 and newer adapters.
298 e1000_gate_hw_phy_config_ich8lan(hw, true);
301 /* It is not possible to be certain of the current state of ULP
302 * so forcibly disable it.
304 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
306 #endif /* ULP_SUPPORT */
307 ret_val = hw->phy.ops.acquire(hw);
309 DEBUGOUT("Failed to initialize PHY flow\n");
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
317 switch (hw->mac.type) {
322 if (e1000_phy_is_accessible_pchlan(hw))
325 /* Before toggling LANPHYPC, see if PHY is accessible by
326 * forcing MAC to SMBus mode first.
328 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
329 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
330 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
332 /* Wait 50 milliseconds for MAC to finish any retries
333 * that it might be trying to perform from previous
334 * attempts to acknowledge any phy read requests.
340 if (e1000_phy_is_accessible_pchlan(hw))
345 if ((hw->mac.type == e1000_pchlan) &&
346 (fwsm & E1000_ICH_FWSM_FW_VALID))
349 if (hw->phy.ops.check_reset_block(hw)) {
350 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
351 ret_val = -E1000_ERR_PHY;
355 /* Toggle LANPHYPC Value bit */
356 e1000_toggle_lanphypc_pch_lpt(hw);
357 if (hw->mac.type >= e1000_pch_lpt) {
358 if (e1000_phy_is_accessible_pchlan(hw))
361 /* Toggling LANPHYPC brings the PHY out of SMBus mode
362 * so ensure that the MAC is also out of SMBus mode
364 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
365 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
366 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
368 if (e1000_phy_is_accessible_pchlan(hw))
371 ret_val = -E1000_ERR_PHY;
378 hw->phy.ops.release(hw);
381 /* Check to see if able to reset PHY. Print error if not */
382 if (hw->phy.ops.check_reset_block(hw)) {
383 ERROR_REPORT("Reset blocked by ME\n");
387 /* Reset the PHY before any access to it. Doing so, ensures
388 * that the PHY is in a known good state before we read/write
389 * PHY registers. The generic reset is sufficient here,
390 * because we haven't determined the PHY type yet.
392 ret_val = e1000_phy_hw_reset_generic(hw);
396 /* On a successful reset, possibly need to wait for the PHY
397 * to quiesce to an accessible state before returning control
398 * to the calling function. If the PHY does not quiesce, then
399 * return E1000E_BLK_PHY_RESET, as this is the condition that
402 ret_val = hw->phy.ops.check_reset_block(hw);
404 ERROR_REPORT("ME blocked access to PHY after reset\n");
408 /* Ungate automatic PHY configuration on non-managed 82579 */
409 if ((hw->mac.type == e1000_pch2lan) &&
410 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
412 e1000_gate_hw_phy_config_ich8lan(hw, false);
419 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
420 * @hw: pointer to the HW structure
422 * Initialize family-specific PHY parameters and function pointers.
424 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
426 struct e1000_phy_info *phy = &hw->phy;
429 DEBUGFUNC("e1000_init_phy_params_pchlan");
432 phy->reset_delay_us = 100;
434 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
435 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
436 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
437 phy->ops.set_page = e1000_set_page_igp;
438 phy->ops.read_reg = e1000_read_phy_reg_hv;
439 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
440 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
441 phy->ops.release = e1000_release_swflag_ich8lan;
442 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
443 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
444 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
445 phy->ops.write_reg = e1000_write_phy_reg_hv;
446 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
447 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
448 phy->ops.power_up = e1000_power_up_phy_copper;
449 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
450 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
452 phy->id = e1000_phy_unknown;
454 ret_val = e1000_init_phy_workarounds_pchlan(hw);
458 if (phy->id == e1000_phy_unknown)
459 switch (hw->mac.type) {
461 ret_val = e1000_get_phy_id(hw);
464 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
472 /* In case the PHY needs to be in mdio slow mode,
473 * set slow mode and try to get the PHY id again.
475 ret_val = e1000_set_mdio_slow_mode_hv(hw);
478 ret_val = e1000_get_phy_id(hw);
483 phy->type = e1000_get_phy_type_from_id(phy->id);
486 case e1000_phy_82577:
487 case e1000_phy_82579:
489 phy->ops.check_polarity = e1000_check_polarity_82577;
490 phy->ops.force_speed_duplex =
491 e1000_phy_force_speed_duplex_82577;
492 phy->ops.get_cable_length = e1000_get_cable_length_82577;
493 phy->ops.get_info = e1000_get_phy_info_82577;
494 phy->ops.commit = e1000_phy_sw_reset_generic;
496 case e1000_phy_82578:
497 phy->ops.check_polarity = e1000_check_polarity_m88;
498 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
499 phy->ops.get_cable_length = e1000_get_cable_length_m88;
500 phy->ops.get_info = e1000_get_phy_info_m88;
503 ret_val = -E1000_ERR_PHY;
511 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
512 * @hw: pointer to the HW structure
514 * Initialize family-specific PHY parameters and function pointers.
516 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
518 struct e1000_phy_info *phy = &hw->phy;
522 DEBUGFUNC("e1000_init_phy_params_ich8lan");
525 phy->reset_delay_us = 100;
527 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
528 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
529 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
530 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
531 phy->ops.read_reg = e1000_read_phy_reg_igp;
532 phy->ops.release = e1000_release_swflag_ich8lan;
533 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
534 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
535 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
536 phy->ops.write_reg = e1000_write_phy_reg_igp;
537 phy->ops.power_up = e1000_power_up_phy_copper;
538 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
540 /* We may need to do this twice - once for IGP and if that fails,
541 * we'll set BM func pointers and try again
543 ret_val = e1000_determine_phy_address(hw);
545 phy->ops.write_reg = e1000_write_phy_reg_bm;
546 phy->ops.read_reg = e1000_read_phy_reg_bm;
547 ret_val = e1000_determine_phy_address(hw);
549 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
555 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
558 ret_val = e1000_get_phy_id(hw);
565 case IGP03E1000_E_PHY_ID:
566 phy->type = e1000_phy_igp_3;
567 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
568 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
569 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
570 phy->ops.get_info = e1000_get_phy_info_igp;
571 phy->ops.check_polarity = e1000_check_polarity_igp;
572 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
575 case IFE_PLUS_E_PHY_ID:
577 phy->type = e1000_phy_ife;
578 phy->autoneg_mask = E1000_ALL_NOT_GIG;
579 phy->ops.get_info = e1000_get_phy_info_ife;
580 phy->ops.check_polarity = e1000_check_polarity_ife;
581 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
583 case BME1000_E_PHY_ID:
584 phy->type = e1000_phy_bm;
585 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
586 phy->ops.read_reg = e1000_read_phy_reg_bm;
587 phy->ops.write_reg = e1000_write_phy_reg_bm;
588 phy->ops.commit = e1000_phy_sw_reset_generic;
589 phy->ops.get_info = e1000_get_phy_info_m88;
590 phy->ops.check_polarity = e1000_check_polarity_m88;
591 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
594 return -E1000_ERR_PHY;
598 return E1000_SUCCESS;
602 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
603 * @hw: pointer to the HW structure
605 * Initialize family-specific NVM parameters and function
608 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
610 struct e1000_nvm_info *nvm = &hw->nvm;
611 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
612 u32 gfpreg, sector_base_addr, sector_end_addr;
616 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
618 nvm->type = e1000_nvm_flash_sw;
620 if (hw->mac.type >= e1000_pch_spt) {
621 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
622 * STRAP register. This is because in SPT the GbE Flash region
623 * is no longer accessed through the flash registers. Instead,
624 * the mechanism has changed, and the Flash region access
625 * registers are now implemented in GbE memory space.
627 nvm->flash_base_addr = 0;
629 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
630 * NVM_SIZE_MULTIPLIER;
631 nvm->flash_bank_size = nvm_size / 2;
632 /* Adjust to word count */
633 nvm->flash_bank_size /= sizeof(u16);
634 /* Set the base address for flash register access */
635 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
637 /* Can't read flash registers if register set isn't mapped. */
638 if (!hw->flash_address) {
639 DEBUGOUT("ERROR: Flash registers not mapped\n");
640 return -E1000_ERR_CONFIG;
643 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
645 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
646 * Add 1 to sector_end_addr since this sector is included in
649 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
650 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
652 /* flash_base_addr is byte-aligned */
653 nvm->flash_base_addr = sector_base_addr
654 << FLASH_SECTOR_ADDR_SHIFT;
656 /* find total size of the NVM, then cut in half since the total
657 * size represents two separate NVM banks.
659 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
660 << FLASH_SECTOR_ADDR_SHIFT);
661 nvm->flash_bank_size /= 2;
662 /* Adjust to word count */
663 nvm->flash_bank_size /= sizeof(u16);
666 nvm->word_size = E1000_SHADOW_RAM_WORDS;
668 /* Clear shadow ram */
669 for (i = 0; i < nvm->word_size; i++) {
670 dev_spec->shadow_ram[i].modified = false;
671 dev_spec->shadow_ram[i].value = 0xFFFF;
674 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
675 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
677 /* Function Pointers */
678 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
679 nvm->ops.release = e1000_release_nvm_ich8lan;
680 if (hw->mac.type >= e1000_pch_spt) {
681 nvm->ops.read = e1000_read_nvm_spt;
682 nvm->ops.update = e1000_update_nvm_checksum_spt;
684 nvm->ops.read = e1000_read_nvm_ich8lan;
685 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
687 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
688 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
689 nvm->ops.write = e1000_write_nvm_ich8lan;
691 return E1000_SUCCESS;
695 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
696 * @hw: pointer to the HW structure
698 * Initialize family-specific MAC parameters and function
701 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
703 struct e1000_mac_info *mac = &hw->mac;
704 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
706 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
708 DEBUGFUNC("e1000_init_mac_params_ich8lan");
710 /* Set media type function pointer */
711 hw->phy.media_type = e1000_media_type_copper;
713 /* Set mta register count */
714 mac->mta_reg_count = 32;
715 /* Set rar entry count */
716 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
717 if (mac->type == e1000_ich8lan)
718 mac->rar_entry_count--;
719 /* Set if part includes ASF firmware */
720 mac->asf_firmware_present = true;
722 mac->has_fwsm = true;
723 /* ARC subsystem not supported */
724 mac->arc_subsystem_valid = false;
725 /* Adaptive IFS supported */
726 mac->adaptive_ifs = true;
728 /* Function pointers */
730 /* bus type/speed/width */
731 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
733 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
735 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
736 /* hw initialization */
737 mac->ops.init_hw = e1000_init_hw_ich8lan;
739 mac->ops.setup_link = e1000_setup_link_ich8lan;
740 /* physical interface setup */
741 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
743 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
745 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
746 /* multicast address update */
747 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
748 /* clear hardware counters */
749 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
751 /* LED and other operations */
756 /* check management mode */
757 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
759 mac->ops.id_led_init = e1000_id_led_init_generic;
761 mac->ops.blink_led = e1000_blink_led_generic;
763 mac->ops.setup_led = e1000_setup_led_generic;
765 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
766 /* turn on/off LED */
767 mac->ops.led_on = e1000_led_on_ich8lan;
768 mac->ops.led_off = e1000_led_off_ich8lan;
771 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
772 mac->ops.rar_set = e1000_rar_set_pch2lan;
778 /* multicast address update for pch2 */
779 mac->ops.update_mc_addr_list =
780 e1000_update_mc_addr_list_pch2lan;
783 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
784 /* save PCH revision_id */
785 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
786 /* SPT uses full byte for revision ID,
787 * as opposed to previous generations
789 if (hw->mac.type >= e1000_pch_spt)
790 hw->revision_id = (u8)(pci_cfg &= 0x00FF);
792 hw->revision_id = (u8)(pci_cfg &= 0x000F);
793 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
794 /* check management mode */
795 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
797 mac->ops.id_led_init = e1000_id_led_init_pchlan;
799 mac->ops.setup_led = e1000_setup_led_pchlan;
801 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
802 /* turn on/off LED */
803 mac->ops.led_on = e1000_led_on_pchlan;
804 mac->ops.led_off = e1000_led_off_pchlan;
810 if (mac->type >= e1000_pch_lpt) {
811 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
812 mac->ops.rar_set = e1000_rar_set_pch_lpt;
813 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
816 /* Enable PCS Lock-loss workaround for ICH8 */
817 if (mac->type == e1000_ich8lan)
818 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
820 return E1000_SUCCESS;
824 * __e1000_access_emi_reg_locked - Read/write EMI register
825 * @hw: pointer to the HW structure
826 * @address: EMI address to program
827 * @data: pointer to value to read/write from/to the EMI address
828 * @read: boolean flag to indicate read or write
830 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
832 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
833 u16 *data, bool read)
837 DEBUGFUNC("__e1000_access_emi_reg_locked");
839 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
844 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
847 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
854 * e1000_read_emi_reg_locked - Read Extended Management Interface register
855 * @hw: pointer to the HW structure
856 * @addr: EMI address to program
857 * @data: value to be read from the EMI address
859 * Assumes the SW/FW/HW Semaphore is already acquired.
861 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
863 DEBUGFUNC("e1000_read_emi_reg_locked");
865 return __e1000_access_emi_reg_locked(hw, addr, data, true);
869 * e1000_write_emi_reg_locked - Write Extended Management Interface register
870 * @hw: pointer to the HW structure
871 * @addr: EMI address to program
872 * @data: value to be written to the EMI address
874 * Assumes the SW/FW/HW Semaphore is already acquired.
876 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
878 DEBUGFUNC("e1000_read_emi_reg_locked");
880 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
884 * e1000_set_eee_pchlan - Enable/disable EEE support
885 * @hw: pointer to the HW structure
887 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
888 * the link and the EEE capabilities of the link partner. The LPI Control
889 * register bits will remain set only if/when link is up.
891 * EEE LPI must not be asserted earlier than one second after link is up.
892 * On 82579, EEE LPI should not be enabled until such time otherwise there
893 * can be link issues with some switches. Other devices can have EEE LPI
894 * enabled immediately upon link up since they have a timer in hardware which
895 * prevents LPI from being asserted too early.
897 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
899 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
901 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
903 DEBUGFUNC("e1000_set_eee_pchlan");
905 switch (hw->phy.type) {
906 case e1000_phy_82579:
907 lpa = I82579_EEE_LP_ABILITY;
908 pcs_status = I82579_EEE_PCS_STATUS;
909 adv_addr = I82579_EEE_ADVERTISEMENT;
912 lpa = I217_EEE_LP_ABILITY;
913 pcs_status = I217_EEE_PCS_STATUS;
914 adv_addr = I217_EEE_ADVERTISEMENT;
917 return E1000_SUCCESS;
920 ret_val = hw->phy.ops.acquire(hw);
924 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
928 /* Clear bits that enable EEE in various speeds */
929 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
931 /* Enable EEE if not disabled by user */
932 if (!dev_spec->eee_disable) {
933 /* Save off link partner's EEE ability */
934 ret_val = e1000_read_emi_reg_locked(hw, lpa,
935 &dev_spec->eee_lp_ability);
939 /* Read EEE advertisement */
940 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
944 /* Enable EEE only for speeds in which the link partner is
945 * EEE capable and for which we advertise EEE.
947 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
948 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
950 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
951 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
952 if (data & NWAY_LPAR_100TX_FD_CAPS)
953 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
955 /* EEE is not supported in 100Half, so ignore
956 * partner's EEE in 100 ability if full-duplex
959 dev_spec->eee_lp_ability &=
960 ~I82579_EEE_100_SUPPORTED;
964 if (hw->phy.type == e1000_phy_82579) {
965 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
970 data &= ~I82579_LPI_100_PLL_SHUT;
971 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
975 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
976 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
980 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
982 hw->phy.ops.release(hw);
988 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
989 * @hw: pointer to the HW structure
990 * @link: link up bool flag
992 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
993 * preventing further DMA write requests. Workaround the issue by disabling
994 * the de-assertion of the clock request when in 1Gpbs mode.
995 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
996 * speeds in order to avoid Tx hangs.
998 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1000 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1001 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1002 s32 ret_val = E1000_SUCCESS;
1005 if (link && (status & E1000_STATUS_SPEED_1000)) {
1006 ret_val = hw->phy.ops.acquire(hw);
1011 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1017 e1000_write_kmrn_reg_locked(hw,
1018 E1000_KMRNCTRLSTA_K1_CONFIG,
1020 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1026 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1027 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1030 e1000_write_kmrn_reg_locked(hw,
1031 E1000_KMRNCTRLSTA_K1_CONFIG,
1034 hw->phy.ops.release(hw);
1036 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1037 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1039 if ((hw->phy.revision > 5) || !link ||
1040 ((status & E1000_STATUS_SPEED_100) &&
1041 (status & E1000_STATUS_FD)))
1042 goto update_fextnvm6;
1044 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1048 /* Clear link status transmit timeout */
1049 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1051 if (status & E1000_STATUS_SPEED_100) {
1052 /* Set inband Tx timeout to 5x10us for 100Half */
1053 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1055 /* Do not extend the K1 entry latency for 100Half */
1056 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1058 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1060 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1062 /* Extend the K1 entry latency for 10 Mbps */
1063 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1066 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1071 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1079 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1080 * @hw: pointer to the HW structure
1081 * @to_sx: boolean indicating a system power state transition to Sx
1083 * When link is down, configure ULP mode to significantly reduce the power
1084 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1085 * ME firmware to start the ULP configuration. If not on an ME enabled
1086 * system, configure the ULP mode by software.
1088 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1091 s32 ret_val = E1000_SUCCESS;
1095 if ((hw->mac.type < e1000_pch_lpt) ||
1096 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1097 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1098 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1099 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1100 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1105 /* Poll up to 5 seconds for Cable Disconnected indication */
1106 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1107 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1108 /* Bail if link is re-acquired */
1109 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1110 return -E1000_ERR_PHY;
1116 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1117 (E1000_READ_REG(hw, E1000_FEXT) &
1118 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1120 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1121 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1125 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1126 /* Request ME configure ULP mode in the PHY */
1127 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1128 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1129 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1134 ret_val = hw->phy.ops.acquire(hw);
1138 /* During S0 Idle keep the phy in PCI-E mode */
1139 if (hw->dev_spec.ich8lan.smbus_disable)
1142 /* Force SMBus mode in PHY */
1143 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1146 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1147 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1149 /* Force SMBus mode in MAC */
1150 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1151 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1152 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1154 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1155 * LPLU and disable Gig speed when entering ULP
1157 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1158 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1164 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1166 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1175 /* Change the 'Link Status Change' interrupt to trigger
1176 * on 'Cable Status Change'
1178 ret_val = e1000_read_kmrn_reg_locked(hw,
1179 E1000_KMRNCTRLSTA_OP_MODES,
1183 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1184 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1188 /* Set Inband ULP Exit, Reset to SMBus mode and
1189 * Disable SMBus Release on PERST# in PHY
1191 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1194 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1195 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1197 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1198 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1200 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1202 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1203 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1205 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1206 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1207 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1209 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1211 /* Set Disable SMBus Release on PERST# in MAC */
1212 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1213 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1214 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1216 /* Commit ULP changes in PHY by starting auto ULP configuration */
1217 phy_reg |= I218_ULP_CONFIG1_START;
1218 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1221 /* Disable Tx so that the MAC doesn't send any (buffered)
1222 * packets to the PHY.
1224 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1225 mac_reg &= ~E1000_TCTL_EN;
1226 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1229 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1230 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1231 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1238 hw->phy.ops.release(hw);
1241 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1243 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1249 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1250 * @hw: pointer to the HW structure
1251 * @force: boolean indicating whether or not to force disabling ULP
1253 * Un-configure ULP mode when link is up, the system is transitioned from
1254 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1255 * system, poll for an indication from ME that ULP has been un-configured.
1256 * If not on an ME enabled system, un-configure the ULP mode by software.
1258 * During nominal operation, this function is called when link is acquired
1259 * to disable ULP mode (force=false); otherwise, for example when unloading
1260 * the driver or during Sx->S0 transitions, this is called with force=true
1261 * to forcibly disable ULP.
1263 * When the cable is plugged in while the device is in D0, a Cable Status
1264 * Change interrupt is generated which causes this function to be called
1265 * to partially disable ULP mode and restart autonegotiation. This function
1266 * is then called again due to the resulting Link Status Change interrupt
1267 * to finish cleaning up after the ULP flow.
1269 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1271 s32 ret_val = E1000_SUCCESS;
1272 u8 ulp_exit_timeout = 30;
1277 if ((hw->mac.type < e1000_pch_lpt) ||
1278 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1279 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1280 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1281 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1282 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1285 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1287 /* Request ME un-configure ULP mode in the PHY */
1288 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1289 mac_reg &= ~E1000_H2ME_ULP;
1290 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1291 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1294 if (hw->mac.type == e1000_pch_cnp)
1295 ulp_exit_timeout = 100;
1297 while (E1000_READ_REG(hw, E1000_FWSM) &
1298 E1000_FWSM_ULP_CFG_DONE) {
1299 if (i++ == ulp_exit_timeout) {
1300 ret_val = -E1000_ERR_PHY;
1306 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1309 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1310 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1311 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1313 /* Clear H2ME.ULP after ME ULP configuration */
1314 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1315 mac_reg &= ~E1000_H2ME_ULP;
1316 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1318 /* Restore link speed advertisements and restart
1321 if (hw->mac.autoneg) {
1322 ret_val = e1000_phy_setup_autoneg(hw);
1326 ret_val = e1000_setup_copper_link_generic(hw);
1330 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1336 ret_val = hw->phy.ops.acquire(hw);
1340 /* Revert the change to the 'Link Status Change'
1341 * interrupt to trigger on 'Cable Status Change'
1343 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1347 phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1348 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1351 /* Toggle LANPHYPC Value bit */
1352 e1000_toggle_lanphypc_pch_lpt(hw);
1354 /* Unforce SMBus mode in PHY */
1355 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1357 /* The MAC might be in PCIe mode, so temporarily force to
1358 * SMBus mode in order to access the PHY.
1360 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1361 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1362 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1366 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1371 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1372 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1374 /* Unforce SMBus mode in MAC */
1375 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1376 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1377 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1379 /* When ULP mode was previously entered, K1 was disabled by the
1380 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1382 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1385 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1386 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1388 /* Clear ULP enabled configuration */
1389 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1392 /* CSC interrupt received due to ULP Indication */
1393 if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1394 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1395 I218_ULP_CONFIG1_STICKY_ULP |
1396 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1397 I218_ULP_CONFIG1_WOL_HOST |
1398 I218_ULP_CONFIG1_INBAND_EXIT |
1399 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1400 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1401 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1402 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1404 /* Commit ULP changes by starting auto ULP configuration */
1405 phy_reg |= I218_ULP_CONFIG1_START;
1406 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1408 /* Clear Disable SMBus Release on PERST# in MAC */
1409 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1410 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1411 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1414 hw->phy.ops.release(hw);
1416 if (hw->mac.autoneg)
1417 e1000_phy_setup_autoneg(hw);
1419 e1000_setup_copper_link_generic(hw);
1421 e1000_sw_lcd_config_ich8lan(hw);
1423 e1000_oem_bits_config_ich8lan(hw, true);
1425 /* Set ULP state to unknown and return non-zero to
1426 * indicate no link (yet) and re-enter on the next LSC
1427 * to finish disabling ULP flow.
1429 hw->dev_spec.ich8lan.ulp_state =
1430 e1000_ulp_state_unknown;
1437 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1438 mac_reg |= E1000_TCTL_EN;
1439 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1442 hw->phy.ops.release(hw);
1444 hw->phy.ops.reset(hw);
1449 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1451 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1456 #endif /* ULP_SUPPORT */
1460 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1461 * @hw: pointer to the HW structure
1463 * Checks to see of the link status of the hardware has changed. If a
1464 * change in link status has been detected, then we read the PHY registers
1465 * to get the current speed/duplex if link exists.
1467 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1469 struct e1000_mac_info *mac = &hw->mac;
1470 s32 ret_val, tipg_reg = 0;
1471 u16 emi_addr, emi_val = 0;
1475 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1477 /* We only want to go out to the PHY registers to see if Auto-Neg
1478 * has completed and/or if our link status has changed. The
1479 * get_link_status flag is set upon receiving a Link Status
1480 * Change or Rx Sequence Error interrupt.
1482 if (!mac->get_link_status)
1483 return E1000_SUCCESS;
1485 if ((hw->mac.type < e1000_pch_lpt) ||
1486 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1487 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1488 /* First we want to see if the MII Status Register reports
1489 * link. If so, then we want to get the current speed/duplex
1492 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1496 /* Check the MAC's STATUS register to determine link state
1497 * since the PHY could be inaccessible while in ULP mode.
1499 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1501 ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1503 ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1508 if (hw->mac.type == e1000_pchlan) {
1509 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1514 /* When connected at 10Mbps half-duplex, some parts are excessively
1515 * aggressive resulting in many collisions. To avoid this, increase
1516 * the IPG and reduce Rx latency in the PHY.
1518 if ((hw->mac.type >= e1000_pch2lan) && link) {
1521 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1522 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1523 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1525 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1527 /* Reduce Rx latency in analog PHY */
1529 } else if (hw->mac.type >= e1000_pch_spt &&
1530 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1534 /* Roll back the default values */
1539 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1541 ret_val = hw->phy.ops.acquire(hw);
1545 if (hw->mac.type == e1000_pch2lan)
1546 emi_addr = I82579_RX_CONFIG;
1548 emi_addr = I217_RX_CONFIG;
1549 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1552 if (hw->mac.type >= e1000_pch_lpt) {
1553 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1555 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1556 if (speed == SPEED_100 || speed == SPEED_10)
1560 hw->phy.ops.write_reg_locked(hw,
1561 I217_PLL_CLOCK_GATE_REG,
1564 if (speed == SPEED_1000) {
1565 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1568 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1570 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1574 hw->phy.ops.release(hw);
1579 if (hw->mac.type >= e1000_pch_spt) {
1583 if (speed == SPEED_1000) {
1584 ret_val = hw->phy.ops.acquire(hw);
1588 ret_val = hw->phy.ops.read_reg_locked(hw,
1592 hw->phy.ops.release(hw);
1596 ptr_gap = (data & (0x3FF << 2)) >> 2;
1597 if (ptr_gap < 0x18) {
1598 data &= ~(0x3FF << 2);
1599 data |= (0x18 << 2);
1601 hw->phy.ops.write_reg_locked(hw,
1602 PHY_REG(776, 20), data);
1604 hw->phy.ops.release(hw);
1608 ret_val = hw->phy.ops.acquire(hw);
1612 ret_val = hw->phy.ops.write_reg_locked(hw,
1615 hw->phy.ops.release(hw);
1623 /* I217 Packet Loss issue:
1624 * ensure that FEXTNVM4 Beacon Duration is set correctly
1626 * Set the Beacon Duration for I217 to 8 usec
1628 if (hw->mac.type >= e1000_pch_lpt) {
1631 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1632 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1633 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1634 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1637 /* Work-around I218 hang issue */
1638 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1639 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1640 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1641 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1642 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1646 /* Clear link partner's EEE ability */
1647 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1649 /* Configure K0s minimum time */
1650 if (hw->mac.type >= e1000_pch_lpt) {
1651 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1654 if (hw->mac.type >= e1000_pch_lpt) {
1655 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1657 if (hw->mac.type == e1000_pch_spt) {
1658 /* FEXTNVM6 K1-off workaround - for SPT only */
1659 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1661 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1662 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1664 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1667 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1668 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1670 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1674 return E1000_SUCCESS; /* No link detected */
1676 mac->get_link_status = false;
1678 switch (hw->mac.type) {
1680 ret_val = e1000_k1_workaround_lv(hw);
1685 if (hw->phy.type == e1000_phy_82578) {
1686 ret_val = e1000_link_stall_workaround_hv(hw);
1691 /* Workaround for PCHx parts in half-duplex:
1692 * Set the number of preambles removed from the packet
1693 * when it is passed from the PHY to the MAC to prevent
1694 * the MAC from misinterpreting the packet type.
1696 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1697 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1699 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1701 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1703 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1709 /* Check if there was DownShift, must be checked
1710 * immediately after link-up
1712 e1000_check_downshift_generic(hw);
1714 /* Enable/Disable EEE after link up */
1715 if (hw->phy.type > e1000_phy_82579) {
1716 ret_val = e1000_set_eee_pchlan(hw);
1721 /* If we are forcing speed/duplex, then we simply return since
1722 * we have already determined whether we have link or not.
1725 return -E1000_ERR_CONFIG;
1727 /* Auto-Neg is enabled. Auto Speed Detection takes care
1728 * of MAC speed/duplex configuration. So we only need to
1729 * configure Collision Distance in the MAC.
1731 mac->ops.config_collision_dist(hw);
1733 /* Configure Flow Control now that Auto-Neg has completed.
1734 * First, we need to restore the desired flow control
1735 * settings because we may have had to re-autoneg with a
1736 * different link partner.
1738 ret_val = e1000_config_fc_after_link_up_generic(hw);
1740 DEBUGOUT("Error configuring flow control\n");
1746 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1747 * @hw: pointer to the HW structure
1749 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1751 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1753 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1755 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1756 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1757 switch (hw->mac.type) {
1760 case e1000_ich10lan:
1761 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1769 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1777 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1778 * @hw: pointer to the HW structure
1780 * Acquires the mutex for performing NVM operations.
1782 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1784 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1786 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1788 return E1000_SUCCESS;
1792 * e1000_release_nvm_ich8lan - Release NVM mutex
1793 * @hw: pointer to the HW structure
1795 * Releases the mutex used while performing NVM operations.
1797 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1799 DEBUGFUNC("e1000_release_nvm_ich8lan");
1801 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1807 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1808 * @hw: pointer to the HW structure
1810 * Acquires the software control flag for performing PHY and select
1813 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1815 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1816 s32 ret_val = E1000_SUCCESS;
1818 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1820 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1823 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1824 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1832 DEBUGOUT("SW has already locked the resource.\n");
1833 ret_val = -E1000_ERR_CONFIG;
1837 timeout = SW_FLAG_TIMEOUT;
1839 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1840 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1843 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1844 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1852 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1853 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1854 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1855 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1856 ret_val = -E1000_ERR_CONFIG;
1862 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1868 * e1000_release_swflag_ich8lan - Release software control flag
1869 * @hw: pointer to the HW structure
1871 * Releases the software control flag for performing PHY and select
1874 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1878 DEBUGFUNC("e1000_release_swflag_ich8lan");
1880 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1882 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1883 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1884 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1886 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1889 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1895 * e1000_check_mng_mode_ich8lan - Checks management mode
1896 * @hw: pointer to the HW structure
1898 * This checks if the adapter has any manageability enabled.
1899 * This is a function pointer entry point only called by read/write
1900 * routines for the PHY and NVM parts.
1902 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1906 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1908 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1910 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1911 ((fwsm & E1000_FWSM_MODE_MASK) ==
1912 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1916 * e1000_check_mng_mode_pchlan - Checks management mode
1917 * @hw: pointer to the HW structure
1919 * This checks if the adapter has iAMT enabled.
1920 * This is a function pointer entry point only called by read/write
1921 * routines for the PHY and NVM parts.
1923 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1927 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1929 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1931 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1932 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1936 * e1000_rar_set_pch2lan - Set receive address register
1937 * @hw: pointer to the HW structure
1938 * @addr: pointer to the receive address
1939 * @index: receive address array register
1941 * Sets the receive address array register at index to the address passed
1942 * in by addr. For 82579, RAR[0] is the base address register that is to
1943 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1944 * Use SHRA[0-3] in place of those reserved for ME.
1946 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1948 u32 rar_low, rar_high;
1950 DEBUGFUNC("e1000_rar_set_pch2lan");
1952 /* HW expects these in little endian so we reverse the byte order
1953 * from network order (big endian) to little endian
1955 rar_low = ((u32) addr[0] |
1956 ((u32) addr[1] << 8) |
1957 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1959 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1961 /* If MAC address zero, no need to set the AV bit */
1962 if (rar_low || rar_high)
1963 rar_high |= E1000_RAH_AV;
1966 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1967 E1000_WRITE_FLUSH(hw);
1968 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1969 E1000_WRITE_FLUSH(hw);
1970 return E1000_SUCCESS;
1973 /* RAR[1-6] are owned by manageability. Skip those and program the
1974 * next address into the SHRA register array.
1976 if (index < (u32) (hw->mac.rar_entry_count)) {
1979 ret_val = e1000_acquire_swflag_ich8lan(hw);
1983 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1984 E1000_WRITE_FLUSH(hw);
1985 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1986 E1000_WRITE_FLUSH(hw);
1988 e1000_release_swflag_ich8lan(hw);
1990 /* verify the register updates */
1991 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1992 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1993 return E1000_SUCCESS;
1995 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1996 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2000 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2001 return -E1000_ERR_CONFIG;
2005 * e1000_rar_set_pch_lpt - Set receive address registers
2006 * @hw: pointer to the HW structure
2007 * @addr: pointer to the receive address
2008 * @index: receive address array register
2010 * Sets the receive address register array at index to the address passed
2011 * in by addr. For LPT, RAR[0] is the base address register that is to
2012 * contain the MAC address. SHRA[0-10] are the shared receive address
2013 * registers that are shared between the Host and manageability engine (ME).
2015 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2017 u32 rar_low, rar_high;
2020 DEBUGFUNC("e1000_rar_set_pch_lpt");
2022 /* HW expects these in little endian so we reverse the byte order
2023 * from network order (big endian) to little endian
2025 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2026 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2028 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2030 /* If MAC address zero, no need to set the AV bit */
2031 if (rar_low || rar_high)
2032 rar_high |= E1000_RAH_AV;
2035 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2036 E1000_WRITE_FLUSH(hw);
2037 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2038 E1000_WRITE_FLUSH(hw);
2039 return E1000_SUCCESS;
2042 /* The manageability engine (ME) can lock certain SHRAR registers that
2043 * it is using - those registers are unavailable for use.
2045 if (index < hw->mac.rar_entry_count) {
2046 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2047 E1000_FWSM_WLOCK_MAC_MASK;
2048 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2050 /* Check if all SHRAR registers are locked */
2054 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2057 ret_val = e1000_acquire_swflag_ich8lan(hw);
2062 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2064 E1000_WRITE_FLUSH(hw);
2065 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2067 E1000_WRITE_FLUSH(hw);
2069 e1000_release_swflag_ich8lan(hw);
2071 /* verify the register updates */
2072 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2073 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2074 return E1000_SUCCESS;
2079 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2080 return -E1000_ERR_CONFIG;
2083 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
2085 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2086 * @hw: pointer to the HW structure
2087 * @mc_addr_list: array of multicast addresses to program
2088 * @mc_addr_count: number of multicast addresses to program
2090 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2091 * The caller must have a packed mc_addr_list of multicast addresses.
2093 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2101 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2103 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2105 ret_val = hw->phy.ops.acquire(hw);
2109 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2113 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2114 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2115 (u16)(hw->mac.mta_shadow[i] &
2117 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2118 (u16)((hw->mac.mta_shadow[i] >> 16) &
2122 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2125 hw->phy.ops.release(hw);
2128 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
2130 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2131 * @hw: pointer to the HW structure
2133 * Checks if firmware is blocking the reset of the PHY.
2134 * This is a function pointer entry point only called by
2137 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2140 bool blocked = false;
2143 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2146 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2147 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2153 } while (blocked && (i++ < 30));
2154 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2158 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2159 * @hw: pointer to the HW structure
2161 * Assumes semaphore already acquired.
2164 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2167 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2168 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2169 E1000_STRAP_SMT_FREQ_SHIFT;
2172 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2174 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2178 phy_data &= ~HV_SMB_ADDR_MASK;
2179 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2180 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2182 if (hw->phy.type == e1000_phy_i217) {
2183 /* Restore SMBus frequency */
2185 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2186 phy_data |= (freq & (1 << 0)) <<
2187 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2188 phy_data |= (freq & (1 << 1)) <<
2189 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2191 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2195 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2199 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2200 * @hw: pointer to the HW structure
2202 * SW should configure the LCD from the NVM extended configuration region
2203 * as a workaround for certain parts.
2205 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2207 struct e1000_phy_info *phy = &hw->phy;
2208 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2209 s32 ret_val = E1000_SUCCESS;
2210 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2212 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2214 /* Initialize the PHY from the NVM on ICH platforms. This
2215 * is needed due to an issue where the NVM configuration is
2216 * not properly autoloaded after power transitions.
2217 * Therefore, after each PHY reset, we will load the
2218 * configuration data out of the NVM manually.
2220 switch (hw->mac.type) {
2222 if (phy->type != e1000_phy_igp_3)
2225 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2226 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2227 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2237 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2243 ret_val = hw->phy.ops.acquire(hw);
2247 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2248 if (!(data & sw_cfg_mask))
2251 /* Make sure HW does not configure LCD from PHY
2252 * extended configuration before SW configuration
2254 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2255 if ((hw->mac.type < e1000_pch2lan) &&
2256 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2259 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2260 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2261 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2265 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2266 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2268 if (((hw->mac.type == e1000_pchlan) &&
2269 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2270 (hw->mac.type > e1000_pchlan)) {
2271 /* HW configures the SMBus address and LEDs when the
2272 * OEM and LCD Write Enable bits are set in the NVM.
2273 * When both NVM bits are cleared, SW will configure
2276 ret_val = e1000_write_smbus_addr(hw);
2280 data = E1000_READ_REG(hw, E1000_LEDCTL);
2281 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2287 /* Configure LCD from extended configuration region. */
2289 /* cnf_base_addr is in DWORD */
2290 word_addr = (u16)(cnf_base_addr << 1);
2292 for (i = 0; i < cnf_size; i++) {
2293 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2298 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2303 /* Save off the PHY page for future writes. */
2304 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2305 phy_page = reg_data;
2309 reg_addr &= PHY_REG_MASK;
2310 reg_addr |= phy_page;
2312 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2319 hw->phy.ops.release(hw);
2324 * e1000_k1_gig_workaround_hv - K1 Si workaround
2325 * @hw: pointer to the HW structure
2326 * @link: link up bool flag
2328 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2329 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2330 * If link is down, the function will restore the default K1 setting located
2333 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2335 s32 ret_val = E1000_SUCCESS;
2337 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2339 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2341 if (hw->mac.type != e1000_pchlan)
2342 return E1000_SUCCESS;
2344 /* Wrap the whole flow with the sw flag */
2345 ret_val = hw->phy.ops.acquire(hw);
2349 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2351 if (hw->phy.type == e1000_phy_82578) {
2352 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2357 status_reg &= (BM_CS_STATUS_LINK_UP |
2358 BM_CS_STATUS_RESOLVED |
2359 BM_CS_STATUS_SPEED_MASK);
2361 if (status_reg == (BM_CS_STATUS_LINK_UP |
2362 BM_CS_STATUS_RESOLVED |
2363 BM_CS_STATUS_SPEED_1000))
2367 if (hw->phy.type == e1000_phy_82577) {
2368 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2373 status_reg &= (HV_M_STATUS_LINK_UP |
2374 HV_M_STATUS_AUTONEG_COMPLETE |
2375 HV_M_STATUS_SPEED_MASK);
2377 if (status_reg == (HV_M_STATUS_LINK_UP |
2378 HV_M_STATUS_AUTONEG_COMPLETE |
2379 HV_M_STATUS_SPEED_1000))
2383 /* Link stall fix for link up */
2384 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2390 /* Link stall fix for link down */
2391 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2397 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2400 hw->phy.ops.release(hw);
2406 * e1000_configure_k1_ich8lan - Configure K1 power state
2407 * @hw: pointer to the HW structure
2408 * @k1_enable: K1 state to configure
2410 * Configure the K1 power state based on the provided parameter.
2411 * Assumes semaphore already acquired.
2413 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2415 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2423 DEBUGFUNC("e1000_configure_k1_ich8lan");
2425 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2431 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2433 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2435 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2441 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2442 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2444 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2445 reg |= E1000_CTRL_FRCSPD;
2446 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2448 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2449 E1000_WRITE_FLUSH(hw);
2451 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2452 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2453 E1000_WRITE_FLUSH(hw);
2456 return E1000_SUCCESS;
2460 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2461 * @hw: pointer to the HW structure
2462 * @d0_state: boolean if entering d0 or d3 device state
2464 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2465 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2466 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2468 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2474 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2476 if (hw->mac.type < e1000_pchlan)
2479 ret_val = hw->phy.ops.acquire(hw);
2483 if (hw->mac.type == e1000_pchlan) {
2484 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2485 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2489 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2490 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2493 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2495 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2499 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2502 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2503 oem_reg |= HV_OEM_BITS_GBE_DIS;
2505 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2506 oem_reg |= HV_OEM_BITS_LPLU;
2508 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2509 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2510 oem_reg |= HV_OEM_BITS_GBE_DIS;
2512 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2513 E1000_PHY_CTRL_NOND0A_LPLU))
2514 oem_reg |= HV_OEM_BITS_LPLU;
2517 /* Set Restart auto-neg to activate the bits */
2518 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2519 !hw->phy.ops.check_reset_block(hw))
2520 oem_reg |= HV_OEM_BITS_RESTART_AN;
2522 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2525 hw->phy.ops.release(hw);
2532 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2533 * @hw: pointer to the HW structure
2535 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2540 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2542 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2546 data |= HV_KMRN_MDIO_SLOW;
2548 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2554 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2555 * done after every PHY reset.
2556 * @hw: pointer to the HW structure
2558 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2560 s32 ret_val = E1000_SUCCESS;
2563 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2565 if (hw->mac.type != e1000_pchlan)
2566 return E1000_SUCCESS;
2568 /* Set MDIO slow mode before any other MDIO access */
2569 if (hw->phy.type == e1000_phy_82577) {
2570 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2575 if (((hw->phy.type == e1000_phy_82577) &&
2576 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2577 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2578 /* Disable generation of early preamble */
2579 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2583 /* Preamble tuning for SSC */
2584 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2590 if (hw->phy.type == e1000_phy_82578) {
2591 /* Return registers to default by doing a soft reset then
2592 * writing 0x3140 to the control register.
2594 if (hw->phy.revision < 2) {
2595 e1000_phy_sw_reset_generic(hw);
2596 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2602 ret_val = hw->phy.ops.acquire(hw);
2607 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2608 hw->phy.ops.release(hw);
2612 /* Configure the K1 Si workaround during phy reset assuming there is
2613 * link so that it disables K1 if link is in 1Gbps.
2615 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2619 /* Workaround for link disconnects on a busy hub in half duplex */
2620 ret_val = hw->phy.ops.acquire(hw);
2623 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2626 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2631 /* set MSE higher to enable link to stay up when noise is high */
2632 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2634 hw->phy.ops.release(hw);
2640 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2641 * @hw: pointer to the HW structure
2643 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2649 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2651 ret_val = hw->phy.ops.acquire(hw);
2654 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2658 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2659 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2660 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2661 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2662 (u16)(mac_reg & 0xFFFF));
2663 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2664 (u16)((mac_reg >> 16) & 0xFFFF));
2666 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2667 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2668 (u16)(mac_reg & 0xFFFF));
2669 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2670 (u16)((mac_reg & E1000_RAH_AV)
2674 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2677 hw->phy.ops.release(hw);
2680 #ifndef CRC32_OS_SUPPORT
2681 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2683 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2684 u32 i, j, mask, crc;
2686 DEBUGFUNC("e1000_calc_rx_da_crc");
2689 for (i = 0; i < 6; i++) {
2691 for (j = 8; j > 0; j--) {
2692 mask = (crc & 1) * (-1);
2693 crc = (crc >> 1) ^ (poly & mask);
2699 #endif /* CRC32_OS_SUPPORT */
2701 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2703 * @hw: pointer to the HW structure
2704 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2706 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2708 s32 ret_val = E1000_SUCCESS;
2713 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2715 if (hw->mac.type < e1000_pch2lan)
2716 return E1000_SUCCESS;
2718 /* disable Rx path while enabling/disabling workaround */
2719 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2720 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2721 phy_reg | (1 << 14));
2726 /* Write Rx addresses (rar_entry_count for RAL/H, and
2727 * SHRAL/H) and initial CRC values to the MAC
2729 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2730 u8 mac_addr[ETH_ADDR_LEN] = {0};
2731 u32 addr_high, addr_low;
2733 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2734 if (!(addr_high & E1000_RAH_AV))
2736 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2737 mac_addr[0] = (addr_low & 0xFF);
2738 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2739 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2740 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2741 mac_addr[4] = (addr_high & 0xFF);
2742 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2744 #ifndef CRC32_OS_SUPPORT
2745 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2746 e1000_calc_rx_da_crc(mac_addr));
2747 #else /* CRC32_OS_SUPPORT */
2748 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2749 E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2750 #endif /* CRC32_OS_SUPPORT */
2753 /* Write Rx addresses to the PHY */
2754 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2756 /* Enable jumbo frame workaround in the MAC */
2757 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2758 mac_reg &= ~(1 << 14);
2759 mac_reg |= (7 << 15);
2760 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2762 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2763 mac_reg |= E1000_RCTL_SECRC;
2764 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2766 ret_val = e1000_read_kmrn_reg_generic(hw,
2767 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2771 ret_val = e1000_write_kmrn_reg_generic(hw,
2772 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2776 ret_val = e1000_read_kmrn_reg_generic(hw,
2777 E1000_KMRNCTRLSTA_HD_CTRL,
2781 data &= ~(0xF << 8);
2783 ret_val = e1000_write_kmrn_reg_generic(hw,
2784 E1000_KMRNCTRLSTA_HD_CTRL,
2789 /* Enable jumbo frame workaround in the PHY */
2790 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2791 data &= ~(0x7F << 5);
2792 data |= (0x37 << 5);
2793 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2796 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2798 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2801 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2802 data &= ~(0x3FF << 2);
2803 data |= (E1000_TX_PTR_GAP << 2);
2804 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2807 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2810 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2811 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2816 /* Write MAC register values back to h/w defaults */
2817 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2818 mac_reg &= ~(0xF << 14);
2819 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2821 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2822 mac_reg &= ~E1000_RCTL_SECRC;
2823 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2825 ret_val = e1000_read_kmrn_reg_generic(hw,
2826 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2830 ret_val = e1000_write_kmrn_reg_generic(hw,
2831 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2835 ret_val = e1000_read_kmrn_reg_generic(hw,
2836 E1000_KMRNCTRLSTA_HD_CTRL,
2840 data &= ~(0xF << 8);
2842 ret_val = e1000_write_kmrn_reg_generic(hw,
2843 E1000_KMRNCTRLSTA_HD_CTRL,
2848 /* Write PHY register values back to h/w defaults */
2849 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2850 data &= ~(0x7F << 5);
2851 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2854 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2856 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2859 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2860 data &= ~(0x3FF << 2);
2862 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2865 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2868 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2869 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2875 /* re-enable Rx path after enabling/disabling workaround */
2876 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2881 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2882 * done after every PHY reset.
2883 * @hw: pointer to the HW structure
2885 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2887 s32 ret_val = E1000_SUCCESS;
2889 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2891 if (hw->mac.type != e1000_pch2lan)
2892 return E1000_SUCCESS;
2894 /* Set MDIO slow mode before any other MDIO access */
2895 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2899 ret_val = hw->phy.ops.acquire(hw);
2902 /* set MSE higher to enable link to stay up when noise is high */
2903 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2906 /* drop link after 5 times MSE threshold was reached */
2907 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2909 hw->phy.ops.release(hw);
2915 * e1000_k1_gig_workaround_lv - K1 Si workaround
2916 * @hw: pointer to the HW structure
2918 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2919 * Disable K1 for 1000 and 100 speeds
2921 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2923 s32 ret_val = E1000_SUCCESS;
2926 DEBUGFUNC("e1000_k1_workaround_lv");
2928 if (hw->mac.type != e1000_pch2lan)
2929 return E1000_SUCCESS;
2931 /* Set K1 beacon duration based on 10Mbs speed */
2932 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2936 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2937 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2939 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2942 /* LV 1G/100 Packet drop issue wa */
2943 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2947 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2948 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2954 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2955 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2956 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2957 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2965 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2966 * @hw: pointer to the HW structure
2967 * @gate: boolean set to true to gate, false to ungate
2969 * Gate/ungate the automatic PHY configuration via hardware; perform
2970 * the configuration via software instead.
2972 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2976 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2978 if (hw->mac.type < e1000_pch2lan)
2981 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2984 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2986 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2988 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2992 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2993 * @hw: pointer to the HW structure
2995 * Check the appropriate indication the MAC has finished configuring the
2996 * PHY after a software reset.
2998 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3000 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3002 DEBUGFUNC("e1000_lan_init_done_ich8lan");
3004 /* Wait for basic configuration completes before proceeding */
3006 data = E1000_READ_REG(hw, E1000_STATUS);
3007 data &= E1000_STATUS_LAN_INIT_DONE;
3009 } while ((!data) && --loop);
3011 /* If basic configuration is incomplete before the above loop
3012 * count reaches 0, loading the configuration from NVM will
3013 * leave the PHY in a bad state possibly resulting in no link.
3016 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3018 /* Clear the Init Done bit for the next init event */
3019 data = E1000_READ_REG(hw, E1000_STATUS);
3020 data &= ~E1000_STATUS_LAN_INIT_DONE;
3021 E1000_WRITE_REG(hw, E1000_STATUS, data);
3025 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3026 * @hw: pointer to the HW structure
3028 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3030 s32 ret_val = E1000_SUCCESS;
3033 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3035 if (hw->phy.ops.check_reset_block(hw))
3036 return E1000_SUCCESS;
3038 /* Allow time for h/w to get to quiescent state after reset */
3041 /* Perform any necessary post-reset workarounds */
3042 switch (hw->mac.type) {
3044 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3049 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3057 /* Clear the host wakeup bit after lcd reset */
3058 if (hw->mac.type >= e1000_pchlan) {
3059 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3060 reg &= ~BM_WUC_HOST_WU_BIT;
3061 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3064 /* Configure the LCD with the extended configuration region in NVM */
3065 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3069 /* Configure the LCD with the OEM bits in NVM */
3070 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3072 if (hw->mac.type == e1000_pch2lan) {
3073 /* Ungate automatic PHY configuration on non-managed 82579 */
3074 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3075 E1000_ICH_FWSM_FW_VALID)) {
3077 e1000_gate_hw_phy_config_ich8lan(hw, false);
3080 /* Set EEE LPI Update Timer to 200usec */
3081 ret_val = hw->phy.ops.acquire(hw);
3084 ret_val = e1000_write_emi_reg_locked(hw,
3085 I82579_LPI_UPDATE_TIMER,
3087 hw->phy.ops.release(hw);
3094 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3095 * @hw: pointer to the HW structure
3098 * This is a function pointer entry point called by drivers
3099 * or other shared routines.
3101 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3103 s32 ret_val = E1000_SUCCESS;
3105 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3107 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3108 if ((hw->mac.type == e1000_pch2lan) &&
3109 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3110 e1000_gate_hw_phy_config_ich8lan(hw, true);
3112 ret_val = e1000_phy_hw_reset_generic(hw);
3116 return e1000_post_phy_reset_ich8lan(hw);
3120 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3121 * @hw: pointer to the HW structure
3122 * @active: true to enable LPLU, false to disable
3124 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3125 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3126 * the phy speed. This function will manually set the LPLU bit and restart
3127 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3128 * since it configures the same bit.
3130 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3135 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3136 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3141 oem_reg |= HV_OEM_BITS_LPLU;
3143 oem_reg &= ~HV_OEM_BITS_LPLU;
3145 if (!hw->phy.ops.check_reset_block(hw))
3146 oem_reg |= HV_OEM_BITS_RESTART_AN;
3148 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3152 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3153 * @hw: pointer to the HW structure
3154 * @active: true to enable LPLU, false to disable
3156 * Sets the LPLU D0 state according to the active flag. When
3157 * activating LPLU this function also disables smart speed
3158 * and vice versa. LPLU will not be activated unless the
3159 * device autonegotiation advertisement meets standards of
3160 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3161 * This is a function pointer entry point only called by
3162 * PHY setup routines.
3164 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3166 struct e1000_phy_info *phy = &hw->phy;
3168 s32 ret_val = E1000_SUCCESS;
3171 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3173 if (phy->type == e1000_phy_ife)
3174 return E1000_SUCCESS;
3176 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3179 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3180 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3182 if (phy->type != e1000_phy_igp_3)
3183 return E1000_SUCCESS;
3185 /* Call gig speed drop workaround on LPLU before accessing
3188 if (hw->mac.type == e1000_ich8lan)
3189 e1000_gig_downshift_workaround_ich8lan(hw);
3191 /* When LPLU is enabled, we should disable SmartSpeed */
3192 ret_val = phy->ops.read_reg(hw,
3193 IGP01E1000_PHY_PORT_CONFIG,
3197 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3198 ret_val = phy->ops.write_reg(hw,
3199 IGP01E1000_PHY_PORT_CONFIG,
3204 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3205 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3207 if (phy->type != e1000_phy_igp_3)
3208 return E1000_SUCCESS;
3210 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3211 * during Dx states where the power conservation is most
3212 * important. During driver activity we should enable
3213 * SmartSpeed, so performance is maintained.
3215 if (phy->smart_speed == e1000_smart_speed_on) {
3216 ret_val = phy->ops.read_reg(hw,
3217 IGP01E1000_PHY_PORT_CONFIG,
3222 data |= IGP01E1000_PSCFR_SMART_SPEED;
3223 ret_val = phy->ops.write_reg(hw,
3224 IGP01E1000_PHY_PORT_CONFIG,
3228 } else if (phy->smart_speed == e1000_smart_speed_off) {
3229 ret_val = phy->ops.read_reg(hw,
3230 IGP01E1000_PHY_PORT_CONFIG,
3235 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3236 ret_val = phy->ops.write_reg(hw,
3237 IGP01E1000_PHY_PORT_CONFIG,
3244 return E1000_SUCCESS;
3248 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3249 * @hw: pointer to the HW structure
3250 * @active: true to enable LPLU, false to disable
3252 * Sets the LPLU D3 state according to the active flag. When
3253 * activating LPLU this function also disables smart speed
3254 * and vice versa. LPLU will not be activated unless the
3255 * device autonegotiation advertisement meets standards of
3256 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3257 * This is a function pointer entry point only called by
3258 * PHY setup routines.
3260 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3262 struct e1000_phy_info *phy = &hw->phy;
3264 s32 ret_val = E1000_SUCCESS;
3267 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3269 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3272 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3273 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3275 if (phy->type != e1000_phy_igp_3)
3276 return E1000_SUCCESS;
3278 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3279 * during Dx states where the power conservation is most
3280 * important. During driver activity we should enable
3281 * SmartSpeed, so performance is maintained.
3283 if (phy->smart_speed == e1000_smart_speed_on) {
3284 ret_val = phy->ops.read_reg(hw,
3285 IGP01E1000_PHY_PORT_CONFIG,
3290 data |= IGP01E1000_PSCFR_SMART_SPEED;
3291 ret_val = phy->ops.write_reg(hw,
3292 IGP01E1000_PHY_PORT_CONFIG,
3296 } else if (phy->smart_speed == e1000_smart_speed_off) {
3297 ret_val = phy->ops.read_reg(hw,
3298 IGP01E1000_PHY_PORT_CONFIG,
3303 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3304 ret_val = phy->ops.write_reg(hw,
3305 IGP01E1000_PHY_PORT_CONFIG,
3310 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3311 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3312 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3313 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3314 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3316 if (phy->type != e1000_phy_igp_3)
3317 return E1000_SUCCESS;
3319 /* Call gig speed drop workaround on LPLU before accessing
3322 if (hw->mac.type == e1000_ich8lan)
3323 e1000_gig_downshift_workaround_ich8lan(hw);
3325 /* When LPLU is enabled, we should disable SmartSpeed */
3326 ret_val = phy->ops.read_reg(hw,
3327 IGP01E1000_PHY_PORT_CONFIG,
3332 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3333 ret_val = phy->ops.write_reg(hw,
3334 IGP01E1000_PHY_PORT_CONFIG,
3342 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3343 * @hw: pointer to the HW structure
3344 * @bank: pointer to the variable that returns the active bank
3346 * Reads signature byte from the NVM using the flash access registers.
3347 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3349 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3352 struct e1000_nvm_info *nvm = &hw->nvm;
3353 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3354 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3359 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3361 switch (hw->mac.type) {
3365 bank1_offset = nvm->flash_bank_size;
3366 act_offset = E1000_ICH_NVM_SIG_WORD;
3368 /* set bank to 0 in case flash read fails */
3372 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3376 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3377 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3378 E1000_ICH_NVM_SIG_VALUE) {
3380 return E1000_SUCCESS;
3384 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3389 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3390 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3391 E1000_ICH_NVM_SIG_VALUE) {
3393 return E1000_SUCCESS;
3396 DEBUGOUT("ERROR: No valid NVM bank present\n");
3397 return -E1000_ERR_NVM;
3400 eecd = E1000_READ_REG(hw, E1000_EECD);
3401 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3402 E1000_EECD_SEC1VAL_VALID_MASK) {
3403 if (eecd & E1000_EECD_SEC1VAL)
3408 return E1000_SUCCESS;
3410 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3413 /* set bank to 0 in case flash read fails */
3417 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3421 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3422 E1000_ICH_NVM_SIG_VALUE) {
3424 return E1000_SUCCESS;
3428 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3433 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3434 E1000_ICH_NVM_SIG_VALUE) {
3436 return E1000_SUCCESS;
3439 DEBUGOUT("ERROR: No valid NVM bank present\n");
3440 return -E1000_ERR_NVM;
3445 * e1000_read_nvm_spt - NVM access for SPT
3446 * @hw: pointer to the HW structure
3447 * @offset: The offset (in bytes) of the word(s) to read.
3448 * @words: Size of data to read in words.
3449 * @data: pointer to the word(s) to read at offset.
3451 * Reads a word(s) from the NVM
3453 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3456 struct e1000_nvm_info *nvm = &hw->nvm;
3457 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3459 s32 ret_val = E1000_SUCCESS;
3465 DEBUGFUNC("e1000_read_nvm_spt");
3467 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3469 DEBUGOUT("nvm parameter(s) out of bounds\n");
3470 ret_val = -E1000_ERR_NVM;
3474 nvm->ops.acquire(hw);
3476 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3477 if (ret_val != E1000_SUCCESS) {
3478 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3482 act_offset = (bank) ? nvm->flash_bank_size : 0;
3483 act_offset += offset;
3485 ret_val = E1000_SUCCESS;
3487 for (i = 0; i < words; i += 2) {
3488 if (words - i == 1) {
3489 if (dev_spec->shadow_ram[offset + i].modified) {
3491 dev_spec->shadow_ram[offset + i].value;
3493 offset_to_read = act_offset + i -
3494 ((act_offset + i) % 2);
3496 e1000_read_flash_dword_ich8lan(hw,
3501 if ((act_offset + i) % 2 == 0)
3502 data[i] = (u16)(dword & 0xFFFF);
3504 data[i] = (u16)((dword >> 16) & 0xFFFF);
3507 offset_to_read = act_offset + i;
3508 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3509 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3511 e1000_read_flash_dword_ich8lan(hw,
3517 if (dev_spec->shadow_ram[offset + i].modified)
3519 dev_spec->shadow_ram[offset + i].value;
3521 data[i] = (u16)(dword & 0xFFFF);
3522 if (dev_spec->shadow_ram[offset + i + 1].modified)
3524 dev_spec->shadow_ram[offset + i + 1].value;
3526 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3530 nvm->ops.release(hw);
3534 DEBUGOUT1("NVM read error: %d\n", ret_val);
3540 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3541 * @hw: pointer to the HW structure
3542 * @offset: The offset (in bytes) of the word(s) to read.
3543 * @words: Size of data to read in words
3544 * @data: Pointer to the word(s) to read at offset.
3546 * Reads a word(s) from the NVM using the flash access registers.
3548 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3551 struct e1000_nvm_info *nvm = &hw->nvm;
3552 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3554 s32 ret_val = E1000_SUCCESS;
3558 DEBUGFUNC("e1000_read_nvm_ich8lan");
3560 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3562 DEBUGOUT("nvm parameter(s) out of bounds\n");
3563 ret_val = -E1000_ERR_NVM;
3567 nvm->ops.acquire(hw);
3569 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3570 if (ret_val != E1000_SUCCESS) {
3571 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3575 act_offset = (bank) ? nvm->flash_bank_size : 0;
3576 act_offset += offset;
3578 ret_val = E1000_SUCCESS;
3579 for (i = 0; i < words; i++) {
3580 if (dev_spec->shadow_ram[offset + i].modified) {
3581 data[i] = dev_spec->shadow_ram[offset + i].value;
3583 ret_val = e1000_read_flash_word_ich8lan(hw,
3592 nvm->ops.release(hw);
3596 DEBUGOUT1("NVM read error: %d\n", ret_val);
3602 * e1000_flash_cycle_init_ich8lan - Initialize flash
3603 * @hw: pointer to the HW structure
3605 * This function does initial flash setup so that a new read/write/erase cycle
3608 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3610 union ich8_hws_flash_status hsfsts;
3611 s32 ret_val = -E1000_ERR_NVM;
3613 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3615 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3617 /* Check if the flash descriptor is valid */
3618 if (!hsfsts.hsf_status.fldesvalid) {
3619 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3620 return -E1000_ERR_NVM;
3623 /* Clear FCERR and DAEL in hw status by writing 1 */
3624 hsfsts.hsf_status.flcerr = 1;
3625 hsfsts.hsf_status.dael = 1;
3626 if (hw->mac.type >= e1000_pch_spt)
3627 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3628 hsfsts.regval & 0xFFFF);
3630 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3632 /* Either we should have a hardware SPI cycle in progress
3633 * bit to check against, in order to start a new cycle or
3634 * FDONE bit should be changed in the hardware so that it
3635 * is 1 after hardware reset, which can then be used as an
3636 * indication whether a cycle is in progress or has been
3640 if (!hsfsts.hsf_status.flcinprog) {
3641 /* There is no cycle running at present,
3642 * so we can start a cycle.
3643 * Begin by setting Flash Cycle Done.
3645 hsfsts.hsf_status.flcdone = 1;
3646 if (hw->mac.type >= e1000_pch_spt)
3647 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3648 hsfsts.regval & 0xFFFF);
3650 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3652 ret_val = E1000_SUCCESS;
3656 /* Otherwise poll for sometime so the current
3657 * cycle has a chance to end before giving up.
3659 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3660 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3662 if (!hsfsts.hsf_status.flcinprog) {
3663 ret_val = E1000_SUCCESS;
3668 if (ret_val == E1000_SUCCESS) {
3669 /* Successful in waiting for previous cycle to timeout,
3670 * now set the Flash Cycle Done.
3672 hsfsts.hsf_status.flcdone = 1;
3673 if (hw->mac.type >= e1000_pch_spt)
3674 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3675 hsfsts.regval & 0xFFFF);
3677 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3680 DEBUGOUT("Flash controller busy, cannot get access\n");
3688 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3689 * @hw: pointer to the HW structure
3690 * @timeout: maximum time to wait for completion
3692 * This function starts a flash cycle and waits for its completion.
3694 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3696 union ich8_hws_flash_ctrl hsflctl;
3697 union ich8_hws_flash_status hsfsts;
3700 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3702 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3703 if (hw->mac.type >= e1000_pch_spt)
3704 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3706 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3707 hsflctl.hsf_ctrl.flcgo = 1;
3709 if (hw->mac.type >= e1000_pch_spt)
3710 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3711 hsflctl.regval << 16);
3713 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3715 /* wait till FDONE bit is set to 1 */
3717 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3718 if (hsfsts.hsf_status.flcdone)
3721 } while (i++ < timeout);
3723 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3724 return E1000_SUCCESS;
3726 return -E1000_ERR_NVM;
3730 * e1000_read_flash_dword_ich8lan - Read dword from flash
3731 * @hw: pointer to the HW structure
3732 * @offset: offset to data location
3733 * @data: pointer to the location for storing the data
3735 * Reads the flash dword at offset into data. Offset is converted
3736 * to bytes before read.
3738 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3741 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3744 return -E1000_ERR_NVM;
3746 /* Must convert word offset into bytes. */
3749 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3753 * e1000_read_flash_word_ich8lan - Read word from flash
3754 * @hw: pointer to the HW structure
3755 * @offset: offset to data location
3756 * @data: pointer to the location for storing the data
3758 * Reads the flash word at offset into data. Offset is converted
3759 * to bytes before read.
3761 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3764 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3767 return -E1000_ERR_NVM;
3769 /* Must convert offset into bytes. */
3772 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3776 * e1000_read_flash_byte_ich8lan - Read byte from flash
3777 * @hw: pointer to the HW structure
3778 * @offset: The offset of the byte to read.
3779 * @data: Pointer to a byte to store the value read.
3781 * Reads a single byte from the NVM using the flash access registers.
3783 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3789 /* In SPT, only 32 bits access is supported,
3790 * so this function should not be called.
3792 if (hw->mac.type >= e1000_pch_spt)
3793 return -E1000_ERR_NVM;
3795 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3802 return E1000_SUCCESS;
3806 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3807 * @hw: pointer to the HW structure
3808 * @offset: The offset (in bytes) of the byte or word to read.
3809 * @size: Size of data to read, 1=byte 2=word
3810 * @data: Pointer to the word to store the value read.
3812 * Reads a byte or word from the NVM using the flash access registers.
3814 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3817 union ich8_hws_flash_status hsfsts;
3818 union ich8_hws_flash_ctrl hsflctl;
3819 u32 flash_linear_addr;
3821 s32 ret_val = -E1000_ERR_NVM;
3824 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3826 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3827 return -E1000_ERR_NVM;
3828 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3829 hw->nvm.flash_base_addr);
3834 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3835 if (ret_val != E1000_SUCCESS)
3837 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3839 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3840 hsflctl.hsf_ctrl.fldbcount = size - 1;
3841 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3842 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3843 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3845 ret_val = e1000_flash_cycle_ich8lan(hw,
3846 ICH_FLASH_READ_COMMAND_TIMEOUT);
3848 /* Check if FCERR is set to 1, if set to 1, clear it
3849 * and try the whole sequence a few more times, else
3850 * read in (shift in) the Flash Data0, the order is
3851 * least significant byte first msb to lsb
3853 if (ret_val == E1000_SUCCESS) {
3854 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3856 *data = (u8)(flash_data & 0x000000FF);
3858 *data = (u16)(flash_data & 0x0000FFFF);
3861 /* If we've gotten here, then things are probably
3862 * completely hosed, but if the error condition is
3863 * detected, it won't hurt to give it another try...
3864 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3866 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3868 if (hsfsts.hsf_status.flcerr) {
3869 /* Repeat for some time before giving up. */
3871 } else if (!hsfsts.hsf_status.flcdone) {
3872 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3876 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3882 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3883 * @hw: pointer to the HW structure
3884 * @offset: The offset (in bytes) of the dword to read.
3885 * @data: Pointer to the dword to store the value read.
3887 * Reads a byte or word from the NVM using the flash access registers.
3889 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3892 union ich8_hws_flash_status hsfsts;
3893 union ich8_hws_flash_ctrl hsflctl;
3894 u32 flash_linear_addr;
3895 s32 ret_val = -E1000_ERR_NVM;
3898 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3900 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3901 hw->mac.type < e1000_pch_spt)
3902 return -E1000_ERR_NVM;
3903 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3904 hw->nvm.flash_base_addr);
3909 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3910 if (ret_val != E1000_SUCCESS)
3912 /* In SPT, This register is in Lan memory space, not flash.
3913 * Therefore, only 32 bit access is supported
3915 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3917 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3918 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3919 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3920 /* In SPT, This register is in Lan memory space, not flash.
3921 * Therefore, only 32 bit access is supported
3923 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3924 (u32)hsflctl.regval << 16);
3925 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3927 ret_val = e1000_flash_cycle_ich8lan(hw,
3928 ICH_FLASH_READ_COMMAND_TIMEOUT);
3930 /* Check if FCERR is set to 1, if set to 1, clear it
3931 * and try the whole sequence a few more times, else
3932 * read in (shift in) the Flash Data0, the order is
3933 * least significant byte first msb to lsb
3935 if (ret_val == E1000_SUCCESS) {
3936 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3939 /* If we've gotten here, then things are probably
3940 * completely hosed, but if the error condition is
3941 * detected, it won't hurt to give it another try...
3942 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3944 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3946 if (hsfsts.hsf_status.flcerr) {
3947 /* Repeat for some time before giving up. */
3949 } else if (!hsfsts.hsf_status.flcdone) {
3950 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3954 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3960 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3961 * @hw: pointer to the HW structure
3962 * @offset: The offset (in bytes) of the word(s) to write.
3963 * @words: Size of data to write in words
3964 * @data: Pointer to the word(s) to write at offset.
3966 * Writes a byte or word to the NVM using the flash access registers.
3968 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3971 struct e1000_nvm_info *nvm = &hw->nvm;
3972 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3975 DEBUGFUNC("e1000_write_nvm_ich8lan");
3977 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3979 DEBUGOUT("nvm parameter(s) out of bounds\n");
3980 return -E1000_ERR_NVM;
3983 nvm->ops.acquire(hw);
3985 for (i = 0; i < words; i++) {
3986 dev_spec->shadow_ram[offset + i].modified = true;
3987 dev_spec->shadow_ram[offset + i].value = data[i];
3990 nvm->ops.release(hw);
3992 return E1000_SUCCESS;
3996 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3997 * @hw: pointer to the HW structure
3999 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4000 * which writes the checksum to the shadow ram. The changes in the shadow
4001 * ram are then committed to the EEPROM by processing each bank at a time
4002 * checking for the modified bit and writing only the pending changes.
4003 * After a successful commit, the shadow ram is cleared and is ready for
4006 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4008 struct e1000_nvm_info *nvm = &hw->nvm;
4009 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4010 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4014 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4016 ret_val = e1000_update_nvm_checksum_generic(hw);
4020 if (nvm->type != e1000_nvm_flash_sw)
4023 nvm->ops.acquire(hw);
4025 /* We're writing to the opposite bank so if we're on bank 1,
4026 * write to bank 0 etc. We also need to erase the segment that
4027 * is going to be written
4029 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4030 if (ret_val != E1000_SUCCESS) {
4031 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4036 new_bank_offset = nvm->flash_bank_size;
4037 old_bank_offset = 0;
4038 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4042 old_bank_offset = nvm->flash_bank_size;
4043 new_bank_offset = 0;
4044 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4048 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4049 /* Determine whether to write the value stored
4050 * in the other NVM bank or a modified value stored
4053 ret_val = e1000_read_flash_dword_ich8lan(hw,
4054 i + old_bank_offset,
4057 if (dev_spec->shadow_ram[i].modified) {
4058 dword &= 0xffff0000;
4059 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4061 if (dev_spec->shadow_ram[i + 1].modified) {
4062 dword &= 0x0000ffff;
4063 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4069 /* If the word is 0x13, then make sure the signature bits
4070 * (15:14) are 11b until the commit has completed.
4071 * This will allow us to write 10b which indicates the
4072 * signature is valid. We want to do this after the write
4073 * has completed so that we don't mark the segment valid
4074 * while the write is still in progress
4076 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4077 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4079 /* Convert offset to bytes. */
4080 act_offset = (i + new_bank_offset) << 1;
4084 /* Write the data to the new bank. Offset in words*/
4085 act_offset = i + new_bank_offset;
4086 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4092 /* Don't bother writing the segment valid bits if sector
4093 * programming failed.
4096 DEBUGOUT("Flash commit failed.\n");
4100 /* Finally validate the new segment by setting bit 15:14
4101 * to 10b in word 0x13 , this can be done without an
4102 * erase as well since these bits are 11 to start with
4103 * and we need to change bit 14 to 0b
4105 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4107 /*offset in words but we read dword*/
4109 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4114 dword &= 0xBFFFFFFF;
4115 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4120 /* offset in words but we read dword*/
4121 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4122 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4127 dword &= 0x00FFFFFF;
4128 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4133 /* Great! Everything worked, we can now clear the cached entries. */
4134 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4135 dev_spec->shadow_ram[i].modified = false;
4136 dev_spec->shadow_ram[i].value = 0xFFFF;
4140 nvm->ops.release(hw);
4142 /* Reload the EEPROM, or else modifications will not appear
4143 * until after the next adapter reset.
4146 nvm->ops.reload(hw);
4152 DEBUGOUT1("NVM update error: %d\n", ret_val);
4158 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4159 * @hw: pointer to the HW structure
4161 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4162 * which writes the checksum to the shadow ram. The changes in the shadow
4163 * ram are then committed to the EEPROM by processing each bank at a time
4164 * checking for the modified bit and writing only the pending changes.
4165 * After a successful commit, the shadow ram is cleared and is ready for
4168 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4170 struct e1000_nvm_info *nvm = &hw->nvm;
4171 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4172 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4176 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4178 ret_val = e1000_update_nvm_checksum_generic(hw);
4182 if (nvm->type != e1000_nvm_flash_sw)
4185 nvm->ops.acquire(hw);
4187 /* We're writing to the opposite bank so if we're on bank 1,
4188 * write to bank 0 etc. We also need to erase the segment that
4189 * is going to be written
4191 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4192 if (ret_val != E1000_SUCCESS) {
4193 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4198 new_bank_offset = nvm->flash_bank_size;
4199 old_bank_offset = 0;
4200 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4204 old_bank_offset = nvm->flash_bank_size;
4205 new_bank_offset = 0;
4206 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4210 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4211 if (dev_spec->shadow_ram[i].modified) {
4212 data = dev_spec->shadow_ram[i].value;
4214 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4220 /* If the word is 0x13, then make sure the signature bits
4221 * (15:14) are 11b until the commit has completed.
4222 * This will allow us to write 10b which indicates the
4223 * signature is valid. We want to do this after the write
4224 * has completed so that we don't mark the segment valid
4225 * while the write is still in progress
4227 if (i == E1000_ICH_NVM_SIG_WORD)
4228 data |= E1000_ICH_NVM_SIG_MASK;
4230 /* Convert offset to bytes. */
4231 act_offset = (i + new_bank_offset) << 1;
4235 /* Write the bytes to the new bank. */
4236 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4243 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4250 /* Don't bother writing the segment valid bits if sector
4251 * programming failed.
4254 DEBUGOUT("Flash commit failed.\n");
4258 /* Finally validate the new segment by setting bit 15:14
4259 * to 10b in word 0x13 , this can be done without an
4260 * erase as well since these bits are 11 to start with
4261 * and we need to change bit 14 to 0b
4263 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4264 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4269 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4274 /* And invalidate the previously valid segment by setting
4275 * its signature word (0x13) high_byte to 0b. This can be
4276 * done without an erase because flash erase sets all bits
4277 * to 1's. We can write 1's to 0's without an erase
4279 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4281 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4286 /* Great! Everything worked, we can now clear the cached entries. */
4287 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4288 dev_spec->shadow_ram[i].modified = false;
4289 dev_spec->shadow_ram[i].value = 0xFFFF;
4293 nvm->ops.release(hw);
4295 /* Reload the EEPROM, or else modifications will not appear
4296 * until after the next adapter reset.
4299 nvm->ops.reload(hw);
4305 DEBUGOUT1("NVM update error: %d\n", ret_val);
4311 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4312 * @hw: pointer to the HW structure
4314 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4315 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4316 * calculated, in which case we need to calculate the checksum and set bit 6.
4318 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4323 u16 valid_csum_mask;
4325 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4327 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4328 * the checksum needs to be fixed. This bit is an indication that
4329 * the NVM was prepared by OEM software and did not calculate
4330 * the checksum...a likely scenario.
4332 switch (hw->mac.type) {
4338 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4341 word = NVM_FUTURE_INIT_WORD1;
4342 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4346 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4350 if (!(data & valid_csum_mask)) {
4351 data |= valid_csum_mask;
4352 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4355 ret_val = hw->nvm.ops.update(hw);
4360 return e1000_validate_nvm_checksum_generic(hw);
4364 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4365 * @hw: pointer to the HW structure
4366 * @offset: The offset (in bytes) of the byte/word to read.
4367 * @size: Size of data to read, 1=byte 2=word
4368 * @data: The byte(s) to write to the NVM.
4370 * Writes one/two bytes to the NVM using the flash access registers.
4372 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4375 union ich8_hws_flash_status hsfsts;
4376 union ich8_hws_flash_ctrl hsflctl;
4377 u32 flash_linear_addr;
4382 DEBUGFUNC("e1000_write_ich8_data");
4384 if (hw->mac.type >= e1000_pch_spt) {
4385 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4386 return -E1000_ERR_NVM;
4388 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4389 return -E1000_ERR_NVM;
4392 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4393 hw->nvm.flash_base_addr);
4398 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4399 if (ret_val != E1000_SUCCESS)
4401 /* In SPT, This register is in Lan memory space, not
4402 * flash. Therefore, only 32 bit access is supported
4404 if (hw->mac.type >= e1000_pch_spt)
4406 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4409 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4411 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4412 hsflctl.hsf_ctrl.fldbcount = size - 1;
4413 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4414 /* In SPT, This register is in Lan memory space,
4415 * not flash. Therefore, only 32 bit access is
4418 if (hw->mac.type >= e1000_pch_spt)
4419 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4420 hsflctl.regval << 16);
4422 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4425 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4428 flash_data = (u32)data & 0x00FF;
4430 flash_data = (u32)data;
4432 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4434 /* check if FCERR is set to 1 , if set to 1, clear it
4435 * and try the whole sequence a few more times else done
4438 e1000_flash_cycle_ich8lan(hw,
4439 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4440 if (ret_val == E1000_SUCCESS)
4443 /* If we're here, then things are most likely
4444 * completely hosed, but if the error condition
4445 * is detected, it won't hurt to give it another
4446 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4448 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4449 if (hsfsts.hsf_status.flcerr)
4450 /* Repeat for some time before giving up. */
4452 if (!hsfsts.hsf_status.flcdone) {
4453 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4456 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4462 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4463 * @hw: pointer to the HW structure
4464 * @offset: The offset (in bytes) of the dwords to read.
4465 * @data: The 4 bytes to write to the NVM.
4467 * Writes one/two/four bytes to the NVM using the flash access registers.
4469 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4472 union ich8_hws_flash_status hsfsts;
4473 union ich8_hws_flash_ctrl hsflctl;
4474 u32 flash_linear_addr;
4478 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4480 if (hw->mac.type >= e1000_pch_spt) {
4481 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4482 return -E1000_ERR_NVM;
4484 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4485 hw->nvm.flash_base_addr);
4489 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4490 if (ret_val != E1000_SUCCESS)
4493 /* In SPT, This register is in Lan memory space, not
4494 * flash. Therefore, only 32 bit access is supported
4496 if (hw->mac.type >= e1000_pch_spt)
4497 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4501 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4504 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4505 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4507 /* In SPT, This register is in Lan memory space,
4508 * not flash. Therefore, only 32 bit access is
4511 if (hw->mac.type >= e1000_pch_spt)
4512 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4513 hsflctl.regval << 16);
4515 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4518 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4520 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4522 /* check if FCERR is set to 1 , if set to 1, clear it
4523 * and try the whole sequence a few more times else done
4525 ret_val = e1000_flash_cycle_ich8lan(hw,
4526 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4528 if (ret_val == E1000_SUCCESS)
4531 /* If we're here, then things are most likely
4532 * completely hosed, but if the error condition
4533 * is detected, it won't hurt to give it another
4534 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4536 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4538 if (hsfsts.hsf_status.flcerr)
4539 /* Repeat for some time before giving up. */
4541 if (!hsfsts.hsf_status.flcdone) {
4542 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4545 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4551 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4552 * @hw: pointer to the HW structure
4553 * @offset: The index of the byte to read.
4554 * @data: The byte to write to the NVM.
4556 * Writes a single byte to the NVM using the flash access registers.
4558 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4561 u16 word = (u16)data;
4563 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4565 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4569 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4570 * @hw: pointer to the HW structure
4571 * @offset: The offset of the word to write.
4572 * @dword: The dword to write to the NVM.
4574 * Writes a single dword to the NVM using the flash access registers.
4575 * Goes through a retry algorithm before giving up.
4577 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4578 u32 offset, u32 dword)
4581 u16 program_retries;
4583 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4585 /* Must convert word offset into bytes. */
4588 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4592 for (program_retries = 0; program_retries < 100; program_retries++) {
4593 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4595 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4596 if (ret_val == E1000_SUCCESS)
4599 if (program_retries == 100)
4600 return -E1000_ERR_NVM;
4602 return E1000_SUCCESS;
4606 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4607 * @hw: pointer to the HW structure
4608 * @offset: The offset of the byte to write.
4609 * @byte: The byte to write to the NVM.
4611 * Writes a single byte to the NVM using the flash access registers.
4612 * Goes through a retry algorithm before giving up.
4614 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4615 u32 offset, u8 byte)
4618 u16 program_retries;
4620 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4622 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4626 for (program_retries = 0; program_retries < 100; program_retries++) {
4627 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4629 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4630 if (ret_val == E1000_SUCCESS)
4633 if (program_retries == 100)
4634 return -E1000_ERR_NVM;
4636 return E1000_SUCCESS;
4640 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4641 * @hw: pointer to the HW structure
4642 * @bank: 0 for first bank, 1 for second bank, etc.
4644 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4645 * bank N is 4096 * N + flash_reg_addr.
4647 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4649 struct e1000_nvm_info *nvm = &hw->nvm;
4650 union ich8_hws_flash_status hsfsts;
4651 union ich8_hws_flash_ctrl hsflctl;
4652 u32 flash_linear_addr;
4653 /* bank size is in 16bit words - adjust to bytes */
4654 u32 flash_bank_size = nvm->flash_bank_size * 2;
4657 s32 j, iteration, sector_size;
4659 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4661 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4663 /* Determine HW Sector size: Read BERASE bits of hw flash status
4665 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4666 * consecutive sectors. The start index for the nth Hw sector
4667 * can be calculated as = bank * 4096 + n * 256
4668 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4669 * The start index for the nth Hw sector can be calculated
4671 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4672 * (ich9 only, otherwise error condition)
4673 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4675 switch (hsfsts.hsf_status.berasesz) {
4677 /* Hw sector size 256 */
4678 sector_size = ICH_FLASH_SEG_SIZE_256;
4679 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4682 sector_size = ICH_FLASH_SEG_SIZE_4K;
4686 sector_size = ICH_FLASH_SEG_SIZE_8K;
4690 sector_size = ICH_FLASH_SEG_SIZE_64K;
4694 return -E1000_ERR_NVM;
4697 /* Start with the base address, then add the sector offset. */
4698 flash_linear_addr = hw->nvm.flash_base_addr;
4699 flash_linear_addr += (bank) ? flash_bank_size : 0;
4701 for (j = 0; j < iteration; j++) {
4703 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4706 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4710 /* Write a value 11 (block Erase) in Flash
4711 * Cycle field in hw flash control
4713 if (hw->mac.type >= e1000_pch_spt)
4715 E1000_READ_FLASH_REG(hw,
4716 ICH_FLASH_HSFSTS)>>16;
4719 E1000_READ_FLASH_REG16(hw,
4722 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4723 if (hw->mac.type >= e1000_pch_spt)
4724 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4725 hsflctl.regval << 16);
4727 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4730 /* Write the last 24 bits of an index within the
4731 * block into Flash Linear address field in Flash
4734 flash_linear_addr += (j * sector_size);
4735 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4738 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4739 if (ret_val == E1000_SUCCESS)
4742 /* Check if FCERR is set to 1. If 1,
4743 * clear it and try the whole sequence
4744 * a few more times else Done
4746 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4748 if (hsfsts.hsf_status.flcerr)
4749 /* repeat for some time before giving up */
4751 else if (!hsfsts.hsf_status.flcdone)
4753 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4756 return E1000_SUCCESS;
4760 * e1000_valid_led_default_ich8lan - Set the default LED settings
4761 * @hw: pointer to the HW structure
4762 * @data: Pointer to the LED settings
4764 * Reads the LED default settings from the NVM to data. If the NVM LED
4765 * settings is all 0's or F's, set the LED default to a valid LED default
4768 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4772 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4774 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4776 DEBUGOUT("NVM Read Error\n");
4780 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4781 *data = ID_LED_DEFAULT_ICH8LAN;
4783 return E1000_SUCCESS;
4787 * e1000_id_led_init_pchlan - store LED configurations
4788 * @hw: pointer to the HW structure
4790 * PCH does not control LEDs via the LEDCTL register, rather it uses
4791 * the PHY LED configuration register.
4793 * PCH also does not have an "always on" or "always off" mode which
4794 * complicates the ID feature. Instead of using the "on" mode to indicate
4795 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4796 * use "link_up" mode. The LEDs will still ID on request if there is no
4797 * link based on logic in e1000_led_[on|off]_pchlan().
4799 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4801 struct e1000_mac_info *mac = &hw->mac;
4803 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4804 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4805 u16 data, i, temp, shift;
4807 DEBUGFUNC("e1000_id_led_init_pchlan");
4809 /* Get default ID LED modes */
4810 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4814 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4815 mac->ledctl_mode1 = mac->ledctl_default;
4816 mac->ledctl_mode2 = mac->ledctl_default;
4818 for (i = 0; i < 4; i++) {
4819 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4822 case ID_LED_ON1_DEF2:
4823 case ID_LED_ON1_ON2:
4824 case ID_LED_ON1_OFF2:
4825 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4826 mac->ledctl_mode1 |= (ledctl_on << shift);
4828 case ID_LED_OFF1_DEF2:
4829 case ID_LED_OFF1_ON2:
4830 case ID_LED_OFF1_OFF2:
4831 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4832 mac->ledctl_mode1 |= (ledctl_off << shift);
4839 case ID_LED_DEF1_ON2:
4840 case ID_LED_ON1_ON2:
4841 case ID_LED_OFF1_ON2:
4842 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4843 mac->ledctl_mode2 |= (ledctl_on << shift);
4845 case ID_LED_DEF1_OFF2:
4846 case ID_LED_ON1_OFF2:
4847 case ID_LED_OFF1_OFF2:
4848 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4849 mac->ledctl_mode2 |= (ledctl_off << shift);
4857 return E1000_SUCCESS;
4861 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4862 * @hw: pointer to the HW structure
4864 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4865 * register, so the bus width is hard coded.
4867 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4869 struct e1000_bus_info *bus = &hw->bus;
4872 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4874 ret_val = e1000_get_bus_info_pcie_generic(hw);
4876 /* ICH devices are "PCI Express"-ish. They have
4877 * a configuration space, but do not contain
4878 * PCI Express Capability registers, so bus width
4879 * must be hardcoded.
4881 if (bus->width == e1000_bus_width_unknown)
4882 bus->width = e1000_bus_width_pcie_x1;
4888 * e1000_reset_hw_ich8lan - Reset the hardware
4889 * @hw: pointer to the HW structure
4891 * Does a full reset of the hardware which includes a reset of the PHY and
4894 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4896 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4902 DEBUGFUNC("e1000_reset_hw_ich8lan");
4904 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4905 * on the last TLP read/write transaction when MAC is reset.
4907 ret_val = e1000_disable_pcie_master_generic(hw);
4909 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4911 DEBUGOUT("Masking off all interrupts\n");
4912 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4914 /* Disable the Transmit and Receive units. Then delay to allow
4915 * any pending transactions to complete before we hit the MAC
4916 * with the global reset.
4918 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4919 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4920 E1000_WRITE_FLUSH(hw);
4924 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4925 if (hw->mac.type == e1000_ich8lan) {
4926 /* Set Tx and Rx buffer allocation to 8k apiece. */
4927 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4928 /* Set Packet Buffer Size to 16k. */
4929 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4932 if (hw->mac.type == e1000_pchlan) {
4933 /* Save the NVM K1 bit setting*/
4934 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4938 if (kum_cfg & E1000_NVM_K1_ENABLE)
4939 dev_spec->nvm_k1_enabled = true;
4941 dev_spec->nvm_k1_enabled = false;
4944 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4946 if (!hw->phy.ops.check_reset_block(hw)) {
4947 /* Full-chip reset requires MAC and PHY reset at the same
4948 * time to make sure the interface between MAC and the
4949 * external PHY is reset.
4951 ctrl |= E1000_CTRL_PHY_RST;
4953 /* Gate automatic PHY configuration by hardware on
4956 if ((hw->mac.type == e1000_pch2lan) &&
4957 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4958 e1000_gate_hw_phy_config_ich8lan(hw, true);
4960 ret_val = e1000_acquire_swflag_ich8lan(hw);
4962 /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
4963 * may occur during global reset and cause system hang.
4964 * Configuration space access creates the needed delay.
4965 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
4966 * insures configuration space read is done before global reset.
4968 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4969 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4970 DEBUGOUT("Issuing a global reset to ich8lan\n");
4971 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4972 /* cannot issue a flush here because it hangs the hardware */
4975 /* Configuration space access improve HW level time sync mechanism.
4976 * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
4977 * value to insure configuration space read is done
4978 * before any access to mac register.
4980 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4981 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4983 /* Set Phy Config Counter to 50msec */
4984 if (hw->mac.type == e1000_pch2lan) {
4985 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4986 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4987 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4988 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4992 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4994 if (ctrl & E1000_CTRL_PHY_RST) {
4995 ret_val = hw->phy.ops.get_cfg_done(hw);
4999 ret_val = e1000_post_phy_reset_ich8lan(hw);
5004 /* For PCH, this write will make sure that any noise
5005 * will be detected as a CRC error and be dropped rather than show up
5006 * as a bad packet to the DMA engine.
5008 if (hw->mac.type == e1000_pchlan)
5009 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5011 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5012 E1000_READ_REG(hw, E1000_ICR);
5014 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5015 reg |= E1000_KABGTXD_BGSQLBIAS;
5016 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5018 return E1000_SUCCESS;
5022 * e1000_init_hw_ich8lan - Initialize the hardware
5023 * @hw: pointer to the HW structure
5025 * Prepares the hardware for transmit and receive by doing the following:
5026 * - initialize hardware bits
5027 * - initialize LED identification
5028 * - setup receive address registers
5029 * - setup flow control
5030 * - setup transmit descriptors
5031 * - clear statistics
5033 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5035 struct e1000_mac_info *mac = &hw->mac;
5036 u32 ctrl_ext, txdctl, snoop;
5040 DEBUGFUNC("e1000_init_hw_ich8lan");
5042 e1000_initialize_hw_bits_ich8lan(hw);
5044 /* Initialize identification LED */
5045 ret_val = mac->ops.id_led_init(hw);
5046 /* An error is not fatal and we should not stop init due to this */
5048 DEBUGOUT("Error initializing identification LED\n");
5050 /* Setup the receive address. */
5051 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5053 /* Zero out the Multicast HASH table */
5054 DEBUGOUT("Zeroing the MTA\n");
5055 for (i = 0; i < mac->mta_reg_count; i++)
5056 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5058 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5059 * the ME. Disable wakeup by clearing the host wakeup bit.
5060 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5062 if (hw->phy.type == e1000_phy_82578) {
5063 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5064 i &= ~BM_WUC_HOST_WU_BIT;
5065 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5066 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5071 /* Setup link and flow control */
5072 ret_val = mac->ops.setup_link(hw);
5074 /* Set the transmit descriptor write-back policy for both queues */
5075 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5076 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5077 E1000_TXDCTL_FULL_TX_DESC_WB);
5078 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5079 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5080 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5081 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5082 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5083 E1000_TXDCTL_FULL_TX_DESC_WB);
5084 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5085 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5086 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5088 /* ICH8 has opposite polarity of no_snoop bits.
5089 * By default, we should use snoop behavior.
5091 if (mac->type == e1000_ich8lan)
5092 snoop = PCIE_ICH8_SNOOP_ALL;
5094 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5095 e1000_set_pcie_no_snoop_generic(hw, snoop);
5097 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5098 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5099 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5101 /* Clear all of the statistics registers (clear on read). It is
5102 * important that we do this after we have tried to establish link
5103 * because the symbol error count will increment wildly if there
5106 e1000_clear_hw_cntrs_ich8lan(hw);
5112 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5113 * @hw: pointer to the HW structure
5115 * Sets/Clears required hardware bits necessary for correctly setting up the
5116 * hardware for transmit and receive.
5118 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5122 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5124 /* Extended Device Control */
5125 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5127 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5128 if (hw->mac.type >= e1000_pchlan)
5129 reg |= E1000_CTRL_EXT_PHYPDEN;
5130 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5132 /* Transmit Descriptor Control 0 */
5133 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5135 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5137 /* Transmit Descriptor Control 1 */
5138 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5140 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5142 /* Transmit Arbitration Control 0 */
5143 reg = E1000_READ_REG(hw, E1000_TARC(0));
5144 if (hw->mac.type == e1000_ich8lan)
5145 reg |= (1 << 28) | (1 << 29);
5146 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5147 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5149 /* Transmit Arbitration Control 1 */
5150 reg = E1000_READ_REG(hw, E1000_TARC(1));
5151 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5155 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5156 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5159 if (hw->mac.type == e1000_ich8lan) {
5160 reg = E1000_READ_REG(hw, E1000_STATUS);
5162 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5165 /* work-around descriptor data corruption issue during nfs v2 udp
5166 * traffic, just disable the nfs filtering capability
5168 reg = E1000_READ_REG(hw, E1000_RFCTL);
5169 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5171 /* Disable IPv6 extension header parsing because some malformed
5172 * IPv6 headers can hang the Rx.
5174 if (hw->mac.type == e1000_ich8lan)
5175 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5176 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5178 /* Enable ECC on Lynxpoint */
5179 if (hw->mac.type >= e1000_pch_lpt) {
5180 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5181 reg |= E1000_PBECCSTS_ECC_ENABLE;
5182 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5184 reg = E1000_READ_REG(hw, E1000_CTRL);
5185 reg |= E1000_CTRL_MEHE;
5186 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5193 * e1000_setup_link_ich8lan - Setup flow control and link settings
5194 * @hw: pointer to the HW structure
5196 * Determines which flow control settings to use, then configures flow
5197 * control. Calls the appropriate media-specific link configuration
5198 * function. Assuming the adapter has a valid link partner, a valid link
5199 * should be established. Assumes the hardware has previously been reset
5200 * and the transmitter and receiver are not enabled.
5202 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5206 DEBUGFUNC("e1000_setup_link_ich8lan");
5208 /* ICH parts do not have a word in the NVM to determine
5209 * the default flow control setting, so we explicitly
5212 if (hw->fc.requested_mode == e1000_fc_default)
5213 hw->fc.requested_mode = e1000_fc_full;
5215 /* Save off the requested flow control mode for use later. Depending
5216 * on the link partner's capabilities, we may or may not use this mode.
5218 hw->fc.current_mode = hw->fc.requested_mode;
5220 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5221 hw->fc.current_mode);
5223 if (!hw->phy.ops.check_reset_block(hw)) {
5224 /* Continue to configure the copper link. */
5225 ret_val = hw->mac.ops.setup_physical_interface(hw);
5230 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5231 if ((hw->phy.type == e1000_phy_82578) ||
5232 (hw->phy.type == e1000_phy_82579) ||
5233 (hw->phy.type == e1000_phy_i217) ||
5234 (hw->phy.type == e1000_phy_82577)) {
5235 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5237 ret_val = hw->phy.ops.write_reg(hw,
5238 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5244 return e1000_set_fc_watermarks_generic(hw);
5248 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5249 * @hw: pointer to the HW structure
5251 * Configures the kumeran interface to the PHY to wait the appropriate time
5252 * when polling the PHY, then call the generic setup_copper_link to finish
5253 * configuring the copper link.
5255 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5261 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5263 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5264 ctrl |= E1000_CTRL_SLU;
5265 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5266 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5268 /* Set the mac to wait the maximum time between each iteration
5269 * and increase the max iterations when polling the phy;
5270 * this fixes erroneous timeouts at 10Mbps.
5272 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5276 ret_val = e1000_read_kmrn_reg_generic(hw,
5277 E1000_KMRNCTRLSTA_INBAND_PARAM,
5282 ret_val = e1000_write_kmrn_reg_generic(hw,
5283 E1000_KMRNCTRLSTA_INBAND_PARAM,
5288 switch (hw->phy.type) {
5289 case e1000_phy_igp_3:
5290 ret_val = e1000_copper_link_setup_igp(hw);
5295 case e1000_phy_82578:
5296 ret_val = e1000_copper_link_setup_m88(hw);
5300 case e1000_phy_82577:
5301 case e1000_phy_82579:
5302 ret_val = e1000_copper_link_setup_82577(hw);
5307 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5312 reg_data &= ~IFE_PMC_AUTO_MDIX;
5314 switch (hw->phy.mdix) {
5316 reg_data &= ~IFE_PMC_FORCE_MDIX;
5319 reg_data |= IFE_PMC_FORCE_MDIX;
5323 reg_data |= IFE_PMC_AUTO_MDIX;
5326 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5335 return e1000_setup_copper_link_generic(hw);
5339 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5340 * @hw: pointer to the HW structure
5342 * Calls the PHY specific link setup function and then calls the
5343 * generic setup_copper_link to finish configuring the link for
5344 * Lynxpoint PCH devices
5346 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5351 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5353 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5354 ctrl |= E1000_CTRL_SLU;
5355 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5356 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5358 ret_val = e1000_copper_link_setup_82577(hw);
5362 return e1000_setup_copper_link_generic(hw);
5366 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5367 * @hw: pointer to the HW structure
5368 * @speed: pointer to store current link speed
5369 * @duplex: pointer to store the current link duplex
5371 * Calls the generic get_speed_and_duplex to retrieve the current link
5372 * information and then calls the Kumeran lock loss workaround for links at
5375 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5380 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5382 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5386 if ((hw->mac.type == e1000_ich8lan) &&
5387 (hw->phy.type == e1000_phy_igp_3) &&
5388 (*speed == SPEED_1000)) {
5389 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5396 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5397 * @hw: pointer to the HW structure
5399 * Work-around for 82566 Kumeran PCS lock loss:
5400 * On link status change (i.e. PCI reset, speed change) and link is up and
5402 * 0) if workaround is optionally disabled do nothing
5403 * 1) wait 1ms for Kumeran link to come up
5404 * 2) check Kumeran Diagnostic register PCS lock loss bit
5405 * 3) if not set the link is locked (all is good), otherwise...
5407 * 5) repeat up to 10 times
5408 * Note: this is only called for IGP3 copper when speed is 1gb.
5410 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5412 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5418 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5420 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5421 return E1000_SUCCESS;
5423 /* Make sure link is up before proceeding. If not just return.
5424 * Attempting this while link is negotiating fouled up link
5427 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5429 return E1000_SUCCESS;
5431 for (i = 0; i < 10; i++) {
5432 /* read once to clear */
5433 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5436 /* and again to get new status */
5437 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5441 /* check for PCS lock */
5442 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5443 return E1000_SUCCESS;
5445 /* Issue PHY reset */
5446 hw->phy.ops.reset(hw);
5449 /* Disable GigE link negotiation */
5450 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5451 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5452 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5453 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5455 /* Call gig speed drop workaround on Gig disable before accessing
5458 e1000_gig_downshift_workaround_ich8lan(hw);
5460 /* unable to acquire PCS lock */
5461 return -E1000_ERR_PHY;
5465 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5466 * @hw: pointer to the HW structure
5467 * @state: boolean value used to set the current Kumeran workaround state
5469 * If ICH8, set the current Kumeran workaround state (enabled - true
5470 * /disabled - false).
5472 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5475 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5477 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5479 if (hw->mac.type != e1000_ich8lan) {
5480 DEBUGOUT("Workaround applies to ICH8 only.\n");
5484 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5490 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5491 * @hw: pointer to the HW structure
5493 * Workaround for 82566 power-down on D3 entry:
5494 * 1) disable gigabit link
5495 * 2) write VR power-down enable
5497 * Continue if successful, else issue LCD reset and repeat
5499 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5505 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5507 if (hw->phy.type != e1000_phy_igp_3)
5510 /* Try the workaround twice (if needed) */
5513 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5514 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5515 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5516 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5518 /* Call gig speed drop workaround on Gig disable before
5519 * accessing any PHY registers
5521 if (hw->mac.type == e1000_ich8lan)
5522 e1000_gig_downshift_workaround_ich8lan(hw);
5524 /* Write VR power-down enable */
5525 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5526 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5527 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5528 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5530 /* Read it back and test */
5531 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5532 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5533 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5536 /* Issue PHY reset and repeat at most one more time */
5537 reg = E1000_READ_REG(hw, E1000_CTRL);
5538 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5544 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5545 * @hw: pointer to the HW structure
5547 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5548 * LPLU, Gig disable, MDIC PHY reset):
5549 * 1) Set Kumeran Near-end loopback
5550 * 2) Clear Kumeran Near-end loopback
5551 * Should only be called for ICH8[m] devices with any 1G Phy.
5553 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5558 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5560 if ((hw->mac.type != e1000_ich8lan) ||
5561 (hw->phy.type == e1000_phy_ife))
5564 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5568 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5569 ret_val = e1000_write_kmrn_reg_generic(hw,
5570 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5574 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5575 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5580 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5581 * @hw: pointer to the HW structure
5583 * During S0 to Sx transition, it is possible the link remains at gig
5584 * instead of negotiating to a lower speed. Before going to Sx, set
5585 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5586 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5587 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5588 * needs to be written.
5589 * Parts that support (and are linked to a partner which support) EEE in
5590 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5591 * than 10Mbps w/o EEE.
5593 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5595 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5599 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5601 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5602 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5604 if (hw->phy.type == e1000_phy_i217) {
5605 u16 phy_reg, device_id = hw->device_id;
5607 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5608 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5609 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5610 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5611 (hw->mac.type >= e1000_pch_spt)) {
5612 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5614 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5615 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5618 ret_val = hw->phy.ops.acquire(hw);
5622 if (!dev_spec->eee_disable) {
5626 e1000_read_emi_reg_locked(hw,
5627 I217_EEE_ADVERTISEMENT,
5632 /* Disable LPLU if both link partners support 100BaseT
5633 * EEE and 100Full is advertised on both ends of the
5634 * link, and enable Auto Enable LPI since there will
5635 * be no driver to enable LPI while in Sx.
5637 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5638 (dev_spec->eee_lp_ability &
5639 I82579_EEE_100_SUPPORTED) &&
5640 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5641 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5642 E1000_PHY_CTRL_NOND0A_LPLU);
5644 /* Set Auto Enable LPI after link up */
5645 hw->phy.ops.read_reg_locked(hw,
5648 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5649 hw->phy.ops.write_reg_locked(hw,
5655 /* For i217 Intel Rapid Start Technology support,
5656 * when the system is going into Sx and no manageability engine
5657 * is present, the driver must configure proxy to reset only on
5658 * power good. LPI (Low Power Idle) state must also reset only
5659 * on power good, as well as the MTA (Multicast table array).
5660 * The SMBus release must also be disabled on LCD reset.
5662 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5663 E1000_ICH_FWSM_FW_VALID)) {
5664 /* Enable proxy to reset only on power good. */
5665 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5667 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5668 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5671 /* Set bit enable LPI (EEE) to reset only on
5674 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5675 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5676 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5678 /* Disable the SMB release on LCD reset. */
5679 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5680 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5681 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5684 /* Enable MTA to reset for Intel Rapid Start Technology
5687 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5688 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5689 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5692 hw->phy.ops.release(hw);
5695 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5697 if (hw->mac.type == e1000_ich8lan)
5698 e1000_gig_downshift_workaround_ich8lan(hw);
5700 if (hw->mac.type >= e1000_pchlan) {
5701 e1000_oem_bits_config_ich8lan(hw, false);
5703 /* Reset PHY to activate OEM bits on 82577/8 */
5704 if (hw->mac.type == e1000_pchlan)
5705 e1000_phy_hw_reset_generic(hw);
5707 ret_val = hw->phy.ops.acquire(hw);
5710 e1000_write_smbus_addr(hw);
5711 hw->phy.ops.release(hw);
5718 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5719 * @hw: pointer to the HW structure
5721 * During Sx to S0 transitions on non-managed devices or managed devices
5722 * on which PHY resets are not blocked, if the PHY registers cannot be
5723 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5725 * On i217, setup Intel Rapid Start Technology.
5727 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5731 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5732 if (hw->mac.type < e1000_pch2lan)
5733 return E1000_SUCCESS;
5735 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5737 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5741 /* For i217 Intel Rapid Start Technology support when the system
5742 * is transitioning from Sx and no manageability engine is present
5743 * configure SMBus to restore on reset, disable proxy, and enable
5744 * the reset on MTA (Multicast table array).
5746 if (hw->phy.type == e1000_phy_i217) {
5749 ret_val = hw->phy.ops.acquire(hw);
5751 DEBUGOUT("Failed to setup iRST\n");
5755 /* Clear Auto Enable LPI after link up */
5756 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5757 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5758 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5760 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5761 E1000_ICH_FWSM_FW_VALID)) {
5762 /* Restore clear on SMB if no manageability engine
5765 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5769 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5770 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5773 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5775 /* Enable reset on MTA */
5776 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5780 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5781 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5784 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5785 hw->phy.ops.release(hw);
5788 return E1000_SUCCESS;
5792 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5793 * @hw: pointer to the HW structure
5795 * Return the LED back to the default configuration.
5797 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5799 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5801 if (hw->phy.type == e1000_phy_ife)
5802 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5805 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5806 return E1000_SUCCESS;
5810 * e1000_led_on_ich8lan - Turn LEDs on
5811 * @hw: pointer to the HW structure
5815 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5817 DEBUGFUNC("e1000_led_on_ich8lan");
5819 if (hw->phy.type == e1000_phy_ife)
5820 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5821 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5823 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5824 return E1000_SUCCESS;
5828 * e1000_led_off_ich8lan - Turn LEDs off
5829 * @hw: pointer to the HW structure
5831 * Turn off the LEDs.
5833 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5835 DEBUGFUNC("e1000_led_off_ich8lan");
5837 if (hw->phy.type == e1000_phy_ife)
5838 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5839 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5841 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5842 return E1000_SUCCESS;
5846 * e1000_setup_led_pchlan - Configures SW controllable LED
5847 * @hw: pointer to the HW structure
5849 * This prepares the SW controllable LED for use.
5851 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5853 DEBUGFUNC("e1000_setup_led_pchlan");
5855 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5856 (u16)hw->mac.ledctl_mode1);
5860 * e1000_cleanup_led_pchlan - Restore the default LED operation
5861 * @hw: pointer to the HW structure
5863 * Return the LED back to the default configuration.
5865 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5867 DEBUGFUNC("e1000_cleanup_led_pchlan");
5869 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5870 (u16)hw->mac.ledctl_default);
5874 * e1000_led_on_pchlan - Turn LEDs on
5875 * @hw: pointer to the HW structure
5879 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5881 u16 data = (u16)hw->mac.ledctl_mode2;
5884 DEBUGFUNC("e1000_led_on_pchlan");
5886 /* If no link, then turn LED on by setting the invert bit
5887 * for each LED that's mode is "link_up" in ledctl_mode2.
5889 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5890 for (i = 0; i < 3; i++) {
5891 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5892 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5893 E1000_LEDCTL_MODE_LINK_UP)
5895 if (led & E1000_PHY_LED0_IVRT)
5896 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5898 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5902 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5906 * e1000_led_off_pchlan - Turn LEDs off
5907 * @hw: pointer to the HW structure
5909 * Turn off the LEDs.
5911 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5913 u16 data = (u16)hw->mac.ledctl_mode1;
5916 DEBUGFUNC("e1000_led_off_pchlan");
5918 /* If no link, then turn LED off by clearing the invert bit
5919 * for each LED that's mode is "link_up" in ledctl_mode1.
5921 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5922 for (i = 0; i < 3; i++) {
5923 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5924 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5925 E1000_LEDCTL_MODE_LINK_UP)
5927 if (led & E1000_PHY_LED0_IVRT)
5928 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5930 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5934 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5938 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5939 * @hw: pointer to the HW structure
5941 * Read appropriate register for the config done bit for completion status
5942 * and configure the PHY through s/w for EEPROM-less parts.
5944 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5945 * config done bit, so only an error is logged and continues. If we were
5946 * to return with error, EEPROM-less silicon would not be able to be reset
5949 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5951 s32 ret_val = E1000_SUCCESS;
5955 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5957 e1000_get_cfg_done_generic(hw);
5959 /* Wait for indication from h/w that it has completed basic config */
5960 if (hw->mac.type >= e1000_ich10lan) {
5961 e1000_lan_init_done_ich8lan(hw);
5963 ret_val = e1000_get_auto_rd_done_generic(hw);
5965 /* When auto config read does not complete, do not
5966 * return with an error. This can happen in situations
5967 * where there is no eeprom and prevents getting link.
5969 DEBUGOUT("Auto Read Done did not complete\n");
5970 ret_val = E1000_SUCCESS;
5974 /* Clear PHY Reset Asserted bit */
5975 status = E1000_READ_REG(hw, E1000_STATUS);
5976 if (status & E1000_STATUS_PHYRA)
5977 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5979 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5981 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5982 if (hw->mac.type <= e1000_ich9lan) {
5983 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5984 (hw->phy.type == e1000_phy_igp_3)) {
5985 e1000_phy_init_script_igp3(hw);
5988 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5989 /* Maybe we should do a basic PHY config */
5990 DEBUGOUT("EEPROM not present\n");
5991 ret_val = -E1000_ERR_CONFIG;
5999 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6000 * @hw: pointer to the HW structure
6002 * In the case of a PHY power down to save power, or to turn off link during a
6003 * driver unload, or wake on lan is not enabled, remove the link.
6005 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6007 /* If the management interface is not enabled, then power down */
6008 if (!(hw->mac.ops.check_mng_mode(hw) ||
6009 hw->phy.ops.check_reset_block(hw)))
6010 e1000_power_down_phy_copper(hw);
6016 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6017 * @hw: pointer to the HW structure
6019 * Clears hardware counters specific to the silicon family and calls
6020 * clear_hw_cntrs_generic to clear all general purpose counters.
6022 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6027 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6029 e1000_clear_hw_cntrs_base_generic(hw);
6031 E1000_READ_REG(hw, E1000_ALGNERRC);
6032 E1000_READ_REG(hw, E1000_RXERRC);
6033 E1000_READ_REG(hw, E1000_TNCRS);
6034 E1000_READ_REG(hw, E1000_CEXTERR);
6035 E1000_READ_REG(hw, E1000_TSCTC);
6036 E1000_READ_REG(hw, E1000_TSCTFC);
6038 E1000_READ_REG(hw, E1000_MGTPRC);
6039 E1000_READ_REG(hw, E1000_MGTPDC);
6040 E1000_READ_REG(hw, E1000_MGTPTC);
6042 E1000_READ_REG(hw, E1000_IAC);
6043 E1000_READ_REG(hw, E1000_ICRXOC);
6045 /* Clear PHY statistics registers */
6046 if ((hw->phy.type == e1000_phy_82578) ||
6047 (hw->phy.type == e1000_phy_82579) ||
6048 (hw->phy.type == e1000_phy_i217) ||
6049 (hw->phy.type == e1000_phy_82577)) {
6050 ret_val = hw->phy.ops.acquire(hw);
6053 ret_val = hw->phy.ops.set_page(hw,
6054 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6057 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6058 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6059 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6060 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6061 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6062 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6063 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6064 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6065 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6066 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6067 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6068 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6069 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6070 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6072 hw->phy.ops.release(hw);
6077 * e1000_configure_k0s_lpt - Configure K0s power state
6078 * @hw: pointer to the HW structure
6079 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6080 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6081 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
6082 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6084 * Configure the K1 power state based on the provided parameter.
6085 * Assumes semaphore already acquired.
6087 * Success returns 0, Failure returns:
6088 * -E1000_ERR_PHY (-2) in case of access error
6089 * -E1000_ERR_PARAM (-4) in case of parameters error
6091 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6096 DEBUGFUNC("e1000_configure_k0s_lpt");
6098 if (entry_latency > 3 || min_time > 4)
6099 return -E1000_ERR_PARAM;
6101 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6106 /* for now don't touch the latency */
6107 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6108 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6110 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6115 return E1000_SUCCESS;