1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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32 ***************************************************************************/
34 /* 82562G 10/100 Network Connection
35 * 82562G-2 10/100 Network Connection
36 * 82562GT 10/100 Network Connection
37 * 82562GT-2 10/100 Network Connection
38 * 82562V 10/100 Network Connection
39 * 82562V-2 10/100 Network Connection
40 * 82566DC-2 Gigabit Network Connection
41 * 82566DC Gigabit Network Connection
42 * 82566DM-2 Gigabit Network Connection
43 * 82566DM Gigabit Network Connection
44 * 82566MC Gigabit Network Connection
45 * 82566MM Gigabit Network Connection
46 * 82567LM Gigabit Network Connection
47 * 82567LF Gigabit Network Connection
48 * 82567V Gigabit Network Connection
49 * 82567LM-2 Gigabit Network Connection
50 * 82567LF-2 Gigabit Network Connection
51 * 82567V-2 Gigabit Network Connection
52 * 82567LF-3 Gigabit Network Connection
53 * 82567LM-3 Gigabit Network Connection
54 * 82567LM-4 Gigabit Network Connection
55 * 82577LM Gigabit Network Connection
56 * 82577LC Gigabit Network Connection
57 * 82578DM Gigabit Network Connection
58 * 82578DC Gigabit Network Connection
59 * 82579LM Gigabit Network Connection
60 * 82579V Gigabit Network Connection
61 * Ethernet Connection I217-LM
62 * Ethernet Connection I217-V
63 * Ethernet Connection I218-V
64 * Ethernet Connection I218-LM
65 * Ethernet Connection (2) I218-LM
66 * Ethernet Connection (2) I218-V
67 * Ethernet Connection (3) I218-LM
68 * Ethernet Connection (3) I218-V
71 #include "e1000_api.h"
73 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
74 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
84 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
87 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
88 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
89 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
90 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
91 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
93 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
95 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
98 u16 words, u16 *data);
99 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
100 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
103 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
104 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
105 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
106 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
107 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
108 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
109 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
110 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
111 u16 *speed, u16 *duplex);
112 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
113 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
114 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
115 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
116 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
117 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
118 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
119 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
120 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
121 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
122 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
123 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
124 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
125 u32 offset, u8 *data);
126 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
128 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
129 u32 offset, u16 *data);
130 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
131 u32 offset, u8 byte);
132 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
133 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
134 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
135 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
136 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
137 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
139 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
140 /* Offset 04h HSFSTS */
141 union ich8_hws_flash_status {
143 u16 flcdone:1; /* bit 0 Flash Cycle Done */
144 u16 flcerr:1; /* bit 1 Flash Cycle Error */
145 u16 dael:1; /* bit 2 Direct Access error Log */
146 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
147 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
148 u16 reserved1:2; /* bit 13:6 Reserved */
149 u16 reserved2:6; /* bit 13:6 Reserved */
150 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
151 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
156 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
157 /* Offset 06h FLCTL */
158 union ich8_hws_flash_ctrl {
159 struct ich8_hsflctl {
160 u16 flcgo:1; /* 0 Flash Cycle Go */
161 u16 flcycle:2; /* 2:1 Flash Cycle */
162 u16 reserved:5; /* 7:3 Reserved */
163 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
164 u16 flockdn:6; /* 15:10 Reserved */
169 /* ICH Flash Region Access Permissions */
170 union ich8_hws_flash_regacc {
172 u32 grra:8; /* 0:7 GbE region Read Access */
173 u32 grwa:8; /* 8:15 GbE region Write Access */
174 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
175 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
181 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
182 * @hw: pointer to the HW structure
184 * Test access to the PHY registers by reading the PHY ID registers. If
185 * the PHY ID is already known (e.g. resume path) compare it with known ID,
186 * otherwise assume the read PHY ID is correct if it is valid.
188 * Assumes the sw/fw/hw semaphore is already acquired.
190 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
198 for (retry_count = 0; retry_count < 2; retry_count++) {
199 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
200 if (ret_val || (phy_reg == 0xFFFF))
202 phy_id = (u32)(phy_reg << 16);
204 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
205 if (ret_val || (phy_reg == 0xFFFF)) {
209 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
214 if (hw->phy.id == phy_id)
218 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
222 /* In case the PHY needs to be in mdio slow mode,
223 * set slow mode and try to get the PHY id again.
225 if (hw->mac.type < e1000_pch_lpt) {
226 hw->phy.ops.release(hw);
227 ret_val = e1000_set_mdio_slow_mode_hv(hw);
229 ret_val = e1000_get_phy_id(hw);
230 hw->phy.ops.acquire(hw);
236 if (hw->mac.type == e1000_pch_lpt) {
237 /* Only unforce SMBus if ME is not active */
238 if (!(E1000_READ_REG(hw, E1000_FWSM) &
239 E1000_ICH_FWSM_FW_VALID)) {
240 /* Unforce SMBus mode in PHY */
241 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
242 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
243 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
245 /* Unforce SMBus mode in MAC */
246 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
247 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
248 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
256 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
257 * @hw: pointer to the HW structure
259 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
260 * used to reset the PHY to a quiescent state when necessary.
262 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
266 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
268 /* Set Phy Config Counter to 50msec */
269 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
270 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
271 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
272 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
274 /* Toggle LANPHYPC Value bit */
275 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
276 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
277 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
278 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
279 E1000_WRITE_FLUSH(hw);
281 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
282 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
283 E1000_WRITE_FLUSH(hw);
285 if (hw->mac.type < e1000_pch_lpt) {
292 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
293 E1000_CTRL_EXT_LPCD) && count--);
300 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
301 * @hw: pointer to the HW structure
303 * Workarounds/flow necessary for PHY initialization during driver load
306 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
308 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
311 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
313 /* Gate automatic PHY configuration by hardware on managed and
314 * non-managed 82579 and newer adapters.
316 e1000_gate_hw_phy_config_ich8lan(hw, true);
319 /* It is not possible to be certain of the current state of ULP
320 * so forcibly disable it.
322 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
324 #endif /* ULP_SUPPORT */
325 ret_val = hw->phy.ops.acquire(hw);
327 DEBUGOUT("Failed to initialize PHY flow\n");
331 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
332 * inaccessible and resetting the PHY is not blocked, toggle the
333 * LANPHYPC Value bit to force the interconnect to PCIe mode.
335 switch (hw->mac.type) {
337 if (e1000_phy_is_accessible_pchlan(hw))
340 /* Before toggling LANPHYPC, see if PHY is accessible by
341 * forcing MAC to SMBus mode first.
343 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
344 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
345 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
347 /* Wait 50 milliseconds for MAC to finish any retries
348 * that it might be trying to perform from previous
349 * attempts to acknowledge any phy read requests.
355 if (e1000_phy_is_accessible_pchlan(hw))
360 if ((hw->mac.type == e1000_pchlan) &&
361 (fwsm & E1000_ICH_FWSM_FW_VALID))
364 if (hw->phy.ops.check_reset_block(hw)) {
365 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
366 ret_val = -E1000_ERR_PHY;
370 /* Toggle LANPHYPC Value bit */
371 e1000_toggle_lanphypc_pch_lpt(hw);
372 if (hw->mac.type >= e1000_pch_lpt) {
373 if (e1000_phy_is_accessible_pchlan(hw))
376 /* Toggling LANPHYPC brings the PHY out of SMBus mode
377 * so ensure that the MAC is also out of SMBus mode
379 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
380 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
381 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
383 if (e1000_phy_is_accessible_pchlan(hw))
386 ret_val = -E1000_ERR_PHY;
393 hw->phy.ops.release(hw);
396 /* Check to see if able to reset PHY. Print error if not */
397 if (hw->phy.ops.check_reset_block(hw)) {
398 ERROR_REPORT("Reset blocked by ME\n");
402 /* Reset the PHY before any access to it. Doing so, ensures
403 * that the PHY is in a known good state before we read/write
404 * PHY registers. The generic reset is sufficient here,
405 * because we haven't determined the PHY type yet.
407 ret_val = e1000_phy_hw_reset_generic(hw);
411 /* On a successful reset, possibly need to wait for the PHY
412 * to quiesce to an accessible state before returning control
413 * to the calling function. If the PHY does not quiesce, then
414 * return E1000E_BLK_PHY_RESET, as this is the condition that
417 ret_val = hw->phy.ops.check_reset_block(hw);
419 ERROR_REPORT("ME blocked access to PHY after reset\n");
423 /* Ungate automatic PHY configuration on non-managed 82579 */
424 if ((hw->mac.type == e1000_pch2lan) &&
425 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
427 e1000_gate_hw_phy_config_ich8lan(hw, false);
434 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
435 * @hw: pointer to the HW structure
437 * Initialize family-specific PHY parameters and function pointers.
439 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
441 struct e1000_phy_info *phy = &hw->phy;
444 DEBUGFUNC("e1000_init_phy_params_pchlan");
447 phy->reset_delay_us = 100;
449 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
450 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
451 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
452 phy->ops.set_page = e1000_set_page_igp;
453 phy->ops.read_reg = e1000_read_phy_reg_hv;
454 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
455 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
456 phy->ops.release = e1000_release_swflag_ich8lan;
457 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
458 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
459 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
460 phy->ops.write_reg = e1000_write_phy_reg_hv;
461 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
462 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
463 phy->ops.power_up = e1000_power_up_phy_copper;
464 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
465 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
467 phy->id = e1000_phy_unknown;
469 ret_val = e1000_init_phy_workarounds_pchlan(hw);
473 if (phy->id == e1000_phy_unknown)
474 switch (hw->mac.type) {
476 ret_val = e1000_get_phy_id(hw);
479 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
484 /* In case the PHY needs to be in mdio slow mode,
485 * set slow mode and try to get the PHY id again.
487 ret_val = e1000_set_mdio_slow_mode_hv(hw);
490 ret_val = e1000_get_phy_id(hw);
495 phy->type = e1000_get_phy_type_from_id(phy->id);
498 case e1000_phy_82577:
499 case e1000_phy_82579:
501 phy->ops.check_polarity = e1000_check_polarity_82577;
502 phy->ops.force_speed_duplex =
503 e1000_phy_force_speed_duplex_82577;
504 phy->ops.get_cable_length = e1000_get_cable_length_82577;
505 phy->ops.get_info = e1000_get_phy_info_82577;
506 phy->ops.commit = e1000_phy_sw_reset_generic;
508 case e1000_phy_82578:
509 phy->ops.check_polarity = e1000_check_polarity_m88;
510 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
511 phy->ops.get_cable_length = e1000_get_cable_length_m88;
512 phy->ops.get_info = e1000_get_phy_info_m88;
515 ret_val = -E1000_ERR_PHY;
523 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
524 * @hw: pointer to the HW structure
526 * Initialize family-specific PHY parameters and function pointers.
528 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
530 struct e1000_phy_info *phy = &hw->phy;
534 DEBUGFUNC("e1000_init_phy_params_ich8lan");
537 phy->reset_delay_us = 100;
539 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
540 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
541 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
542 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
543 phy->ops.read_reg = e1000_read_phy_reg_igp;
544 phy->ops.release = e1000_release_swflag_ich8lan;
545 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
546 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
547 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
548 phy->ops.write_reg = e1000_write_phy_reg_igp;
549 phy->ops.power_up = e1000_power_up_phy_copper;
550 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
552 /* We may need to do this twice - once for IGP and if that fails,
553 * we'll set BM func pointers and try again
555 ret_val = e1000_determine_phy_address(hw);
557 phy->ops.write_reg = e1000_write_phy_reg_bm;
558 phy->ops.read_reg = e1000_read_phy_reg_bm;
559 ret_val = e1000_determine_phy_address(hw);
561 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
567 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
570 ret_val = e1000_get_phy_id(hw);
577 case IGP03E1000_E_PHY_ID:
578 phy->type = e1000_phy_igp_3;
579 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
580 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
581 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
582 phy->ops.get_info = e1000_get_phy_info_igp;
583 phy->ops.check_polarity = e1000_check_polarity_igp;
584 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
587 case IFE_PLUS_E_PHY_ID:
589 phy->type = e1000_phy_ife;
590 phy->autoneg_mask = E1000_ALL_NOT_GIG;
591 phy->ops.get_info = e1000_get_phy_info_ife;
592 phy->ops.check_polarity = e1000_check_polarity_ife;
593 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
595 case BME1000_E_PHY_ID:
596 phy->type = e1000_phy_bm;
597 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
598 phy->ops.read_reg = e1000_read_phy_reg_bm;
599 phy->ops.write_reg = e1000_write_phy_reg_bm;
600 phy->ops.commit = e1000_phy_sw_reset_generic;
601 phy->ops.get_info = e1000_get_phy_info_m88;
602 phy->ops.check_polarity = e1000_check_polarity_m88;
603 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
606 return -E1000_ERR_PHY;
610 return E1000_SUCCESS;
614 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
615 * @hw: pointer to the HW structure
617 * Initialize family-specific NVM parameters and function
620 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
622 struct e1000_nvm_info *nvm = &hw->nvm;
623 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
624 u32 gfpreg, sector_base_addr, sector_end_addr;
627 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
629 /* Can't read flash registers if the register set isn't mapped. */
630 nvm->type = e1000_nvm_flash_sw;
631 if (!hw->flash_address) {
632 DEBUGOUT("ERROR: Flash registers not mapped\n");
633 return -E1000_ERR_CONFIG;
636 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
638 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
639 * Add 1 to sector_end_addr since this sector is included in
642 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
643 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
645 /* flash_base_addr is byte-aligned */
646 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
648 /* find total size of the NVM, then cut in half since the total
649 * size represents two separate NVM banks.
651 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
652 << FLASH_SECTOR_ADDR_SHIFT);
653 nvm->flash_bank_size /= 2;
654 /* Adjust to word count */
655 nvm->flash_bank_size /= sizeof(u16);
657 nvm->word_size = E1000_SHADOW_RAM_WORDS;
659 /* Clear shadow ram */
660 for (i = 0; i < nvm->word_size; i++) {
661 dev_spec->shadow_ram[i].modified = false;
662 dev_spec->shadow_ram[i].value = 0xFFFF;
665 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
666 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
668 /* Function Pointers */
669 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
670 nvm->ops.release = e1000_release_nvm_ich8lan;
671 nvm->ops.read = e1000_read_nvm_ich8lan;
672 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
673 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
674 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
675 nvm->ops.write = e1000_write_nvm_ich8lan;
677 return E1000_SUCCESS;
681 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
682 * @hw: pointer to the HW structure
684 * Initialize family-specific MAC parameters and function
687 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
689 struct e1000_mac_info *mac = &hw->mac;
690 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
692 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
694 DEBUGFUNC("e1000_init_mac_params_ich8lan");
696 /* Set media type function pointer */
697 hw->phy.media_type = e1000_media_type_copper;
699 /* Set mta register count */
700 mac->mta_reg_count = 32;
701 /* Set rar entry count */
702 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
703 if (mac->type == e1000_ich8lan)
704 mac->rar_entry_count--;
705 /* Set if part includes ASF firmware */
706 mac->asf_firmware_present = true;
708 mac->has_fwsm = true;
709 /* ARC subsystem not supported */
710 mac->arc_subsystem_valid = false;
711 /* Adaptive IFS supported */
712 mac->adaptive_ifs = true;
714 /* Function pointers */
716 /* bus type/speed/width */
717 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
719 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
721 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
722 /* hw initialization */
723 mac->ops.init_hw = e1000_init_hw_ich8lan;
725 mac->ops.setup_link = e1000_setup_link_ich8lan;
726 /* physical interface setup */
727 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
729 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
731 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
732 /* multicast address update */
733 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
734 /* clear hardware counters */
735 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
737 /* LED and other operations */
742 /* check management mode */
743 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
745 mac->ops.id_led_init = e1000_id_led_init_generic;
747 mac->ops.blink_led = e1000_blink_led_generic;
749 mac->ops.setup_led = e1000_setup_led_generic;
751 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
752 /* turn on/off LED */
753 mac->ops.led_on = e1000_led_on_ich8lan;
754 mac->ops.led_off = e1000_led_off_ich8lan;
757 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
758 mac->ops.rar_set = e1000_rar_set_pch2lan;
761 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
762 /* multicast address update for pch2 */
763 mac->ops.update_mc_addr_list =
764 e1000_update_mc_addr_list_pch2lan;
768 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
769 /* save PCH revision_id */
770 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
771 hw->revision_id = (u8)(pci_cfg &= 0x000F);
772 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
773 /* check management mode */
774 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
776 mac->ops.id_led_init = e1000_id_led_init_pchlan;
778 mac->ops.setup_led = e1000_setup_led_pchlan;
780 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
781 /* turn on/off LED */
782 mac->ops.led_on = e1000_led_on_pchlan;
783 mac->ops.led_off = e1000_led_off_pchlan;
789 if (mac->type == e1000_pch_lpt) {
790 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
791 mac->ops.rar_set = e1000_rar_set_pch_lpt;
792 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
795 /* Enable PCS Lock-loss workaround for ICH8 */
796 if (mac->type == e1000_ich8lan)
797 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
799 return E1000_SUCCESS;
803 * __e1000_access_emi_reg_locked - Read/write EMI register
804 * @hw: pointer to the HW structure
805 * @addr: EMI address to program
806 * @data: pointer to value to read/write from/to the EMI address
807 * @read: boolean flag to indicate read or write
809 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
811 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
812 u16 *data, bool read)
816 DEBUGFUNC("__e1000_access_emi_reg_locked");
818 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
823 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
826 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
833 * e1000_read_emi_reg_locked - Read Extended Management Interface register
834 * @hw: pointer to the HW structure
835 * @addr: EMI address to program
836 * @data: value to be read from the EMI address
838 * Assumes the SW/FW/HW Semaphore is already acquired.
840 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
842 DEBUGFUNC("e1000_read_emi_reg_locked");
844 return __e1000_access_emi_reg_locked(hw, addr, data, true);
848 * e1000_write_emi_reg_locked - Write Extended Management Interface register
849 * @hw: pointer to the HW structure
850 * @addr: EMI address to program
851 * @data: value to be written to the EMI address
853 * Assumes the SW/FW/HW Semaphore is already acquired.
855 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
857 DEBUGFUNC("e1000_read_emi_reg_locked");
859 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
863 * e1000_set_eee_pchlan - Enable/disable EEE support
864 * @hw: pointer to the HW structure
866 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
867 * the link and the EEE capabilities of the link partner. The LPI Control
868 * register bits will remain set only if/when link is up.
870 * EEE LPI must not be asserted earlier than one second after link is up.
871 * On 82579, EEE LPI should not be enabled until such time otherwise there
872 * can be link issues with some switches. Other devices can have EEE LPI
873 * enabled immediately upon link up since they have a timer in hardware which
874 * prevents LPI from being asserted too early.
876 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
878 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
880 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
882 DEBUGFUNC("e1000_set_eee_pchlan");
884 switch (hw->phy.type) {
885 case e1000_phy_82579:
886 lpa = I82579_EEE_LP_ABILITY;
887 pcs_status = I82579_EEE_PCS_STATUS;
888 adv_addr = I82579_EEE_ADVERTISEMENT;
891 lpa = I217_EEE_LP_ABILITY;
892 pcs_status = I217_EEE_PCS_STATUS;
893 adv_addr = I217_EEE_ADVERTISEMENT;
896 return E1000_SUCCESS;
899 ret_val = hw->phy.ops.acquire(hw);
903 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
907 /* Clear bits that enable EEE in various speeds */
908 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
910 /* Enable EEE if not disabled by user */
911 if (!dev_spec->eee_disable) {
912 /* Save off link partner's EEE ability */
913 ret_val = e1000_read_emi_reg_locked(hw, lpa,
914 &dev_spec->eee_lp_ability);
918 /* Read EEE advertisement */
919 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
923 /* Enable EEE only for speeds in which the link partner is
924 * EEE capable and for which we advertise EEE.
926 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
927 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
929 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
930 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
931 if (data & NWAY_LPAR_100TX_FD_CAPS)
932 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
934 /* EEE is not supported in 100Half, so ignore
935 * partner's EEE in 100 ability if full-duplex
938 dev_spec->eee_lp_ability &=
939 ~I82579_EEE_100_SUPPORTED;
943 if (hw->phy.type == e1000_phy_82579) {
944 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
949 data &= ~I82579_LPI_100_PLL_SHUT;
950 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
954 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
955 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
959 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
961 hw->phy.ops.release(hw);
967 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
968 * @hw: pointer to the HW structure
969 * @link: link up bool flag
971 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
972 * preventing further DMA write requests. Workaround the issue by disabling
973 * the de-assertion of the clock request when in 1Gpbs mode.
974 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
975 * speeds in order to avoid Tx hangs.
977 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
979 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
980 u32 status = E1000_READ_REG(hw, E1000_STATUS);
981 s32 ret_val = E1000_SUCCESS;
984 if (link && (status & E1000_STATUS_SPEED_1000)) {
985 ret_val = hw->phy.ops.acquire(hw);
990 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
996 e1000_write_kmrn_reg_locked(hw,
997 E1000_KMRNCTRLSTA_K1_CONFIG,
999 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1005 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1006 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1009 e1000_write_kmrn_reg_locked(hw,
1010 E1000_KMRNCTRLSTA_K1_CONFIG,
1013 hw->phy.ops.release(hw);
1015 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1016 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1018 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1019 (status & E1000_STATUS_FD)))
1020 goto update_fextnvm6;
1022 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1026 /* Clear link status transmit timeout */
1027 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1029 if (status & E1000_STATUS_SPEED_100) {
1030 /* Set inband Tx timeout to 5x10us for 100Half */
1031 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1033 /* Do not extend the K1 entry latency for 100Half */
1034 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1036 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1038 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1040 /* Extend the K1 entry latency for 10 Mbps */
1041 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1044 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1049 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1057 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1058 * @hw: pointer to the HW structure
1059 * @to_sx: boolean indicating a system power state transition to Sx
1061 * When link is down, configure ULP mode to significantly reduce the power
1062 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1063 * ME firmware to start the ULP configuration. If not on an ME enabled
1064 * system, configure the ULP mode by software.
1066 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1069 s32 ret_val = E1000_SUCCESS;
1072 if ((hw->mac.type < e1000_pch_lpt) ||
1073 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1074 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1075 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1076 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1077 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1082 /* Poll up to 5 seconds for Cable Disconnected indication */
1083 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1084 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1085 /* Bail if link is re-acquired */
1086 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1087 return -E1000_ERR_PHY;
1093 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1094 (E1000_READ_REG(hw, E1000_FEXT) &
1095 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1097 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1098 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1102 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103 /* Request ME configure ULP mode in the PHY */
1104 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1105 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1111 ret_val = hw->phy.ops.acquire(hw);
1115 /* During S0 Idle keep the phy in PCI-E mode */
1116 if (hw->dev_spec.ich8lan.smbus_disable)
1119 /* Force SMBus mode in PHY */
1120 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1123 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1124 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1126 /* Force SMBus mode in MAC */
1127 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1128 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1129 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1133 /* Change the 'Link Status Change' interrupt to trigger
1134 * on 'Cable Status Change'
1136 ret_val = e1000_read_kmrn_reg_locked(hw,
1137 E1000_KMRNCTRLSTA_OP_MODES,
1141 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1142 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1146 /* Set Inband ULP Exit, Reset to SMBus mode and
1147 * Disable SMBus Release on PERST# in PHY
1149 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1152 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1153 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1155 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1156 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1158 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1160 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1161 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1163 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1164 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1165 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1167 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1169 /* Set Disable SMBus Release on PERST# in MAC */
1170 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1171 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1172 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1174 /* Commit ULP changes in PHY by starting auto ULP configuration */
1175 phy_reg |= I218_ULP_CONFIG1_START;
1176 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1179 /* Disable Tx so that the MAC doesn't send any (buffered)
1180 * packets to the PHY.
1182 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1183 mac_reg &= ~E1000_TCTL_EN;
1184 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1188 hw->phy.ops.release(hw);
1191 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1193 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1199 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1200 * @hw: pointer to the HW structure
1201 * @force: boolean indicating whether or not to force disabling ULP
1203 * Un-configure ULP mode when link is up, the system is transitioned from
1204 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1205 * system, poll for an indication from ME that ULP has been un-configured.
1206 * If not on an ME enabled system, un-configure the ULP mode by software.
1208 * During nominal operation, this function is called when link is acquired
1209 * to disable ULP mode (force=false); otherwise, for example when unloading
1210 * the driver or during Sx->S0 transitions, this is called with force=true
1211 * to forcibly disable ULP.
1213 * When the cable is plugged in while the device is in D0, a Cable Status
1214 * Change interrupt is generated which causes this function to be called
1215 * to partially disable ULP mode and restart autonegotiation. This function
1216 * is then called again due to the resulting Link Status Change interrupt
1217 * to finish cleaning up after the ULP flow.
1219 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1221 s32 ret_val = E1000_SUCCESS;
1226 if ((hw->mac.type < e1000_pch_lpt) ||
1227 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1228 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1229 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1230 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1231 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1234 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1236 /* Request ME un-configure ULP mode in the PHY */
1237 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1238 mac_reg &= ~E1000_H2ME_ULP;
1239 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1240 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1243 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1244 while (E1000_READ_REG(hw, E1000_FWSM) &
1245 E1000_FWSM_ULP_CFG_DONE) {
1247 ret_val = -E1000_ERR_PHY;
1253 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1256 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1257 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1258 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1260 /* Clear H2ME.ULP after ME ULP configuration */
1261 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1262 mac_reg &= ~E1000_H2ME_ULP;
1263 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1265 /* Restore link speed advertisements and restart
1268 if (hw->mac.autoneg) {
1269 ret_val = e1000_phy_setup_autoneg(hw);
1273 ret_val = e1000_setup_copper_link_generic(hw);
1277 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1283 ret_val = hw->phy.ops.acquire(hw);
1287 /* Revert the change to the 'Link Status Change'
1288 * interrupt to trigger on 'Cable Status Change'
1290 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1294 phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1295 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1298 /* Toggle LANPHYPC Value bit */
1299 e1000_toggle_lanphypc_pch_lpt(hw);
1301 /* Unforce SMBus mode in PHY */
1302 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1304 /* The MAC might be in PCIe mode, so temporarily force to
1305 * SMBus mode in order to access the PHY.
1307 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1308 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1309 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1313 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1318 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1319 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1321 /* Unforce SMBus mode in MAC */
1322 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1323 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1324 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1326 /* When ULP mode was previously entered, K1 was disabled by the
1327 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1329 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1332 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1333 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1335 /* Clear ULP enabled configuration */
1336 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1339 /* CSC interrupt received due to ULP Indication */
1340 if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1341 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1342 I218_ULP_CONFIG1_STICKY_ULP |
1343 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1344 I218_ULP_CONFIG1_WOL_HOST |
1345 I218_ULP_CONFIG1_INBAND_EXIT |
1346 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1347 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1349 /* Commit ULP changes by starting auto ULP configuration */
1350 phy_reg |= I218_ULP_CONFIG1_START;
1351 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1353 /* Clear Disable SMBus Release on PERST# in MAC */
1354 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1355 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1356 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1359 hw->phy.ops.release(hw);
1361 if (hw->mac.autoneg)
1362 e1000_phy_setup_autoneg(hw);
1364 e1000_sw_lcd_config_ich8lan(hw);
1366 e1000_oem_bits_config_ich8lan(hw, true);
1368 /* Set ULP state to unknown and return non-zero to
1369 * indicate no link (yet) and re-enter on the next LSC
1370 * to finish disabling ULP flow.
1372 hw->dev_spec.ich8lan.ulp_state =
1373 e1000_ulp_state_unknown;
1380 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1381 mac_reg |= E1000_TCTL_EN;
1382 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1385 hw->phy.ops.release(hw);
1387 hw->phy.ops.reset(hw);
1392 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1394 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1399 #endif /* ULP_SUPPORT */
1401 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1402 * @hw: pointer to the HW structure
1404 * Checks to see of the link status of the hardware has changed. If a
1405 * change in link status has been detected, then we read the PHY registers
1406 * to get the current speed/duplex if link exists.
1408 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1410 struct e1000_mac_info *mac = &hw->mac;
1411 s32 ret_val, tipg_reg = 0;
1412 u16 emi_addr, emi_val = 0;
1416 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1418 /* We only want to go out to the PHY registers to see if Auto-Neg
1419 * has completed and/or if our link status has changed. The
1420 * get_link_status flag is set upon receiving a Link Status
1421 * Change or Rx Sequence Error interrupt.
1423 if (!mac->get_link_status)
1424 return E1000_SUCCESS;
1426 if ((hw->mac.type < e1000_pch_lpt) ||
1427 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1428 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1429 /* First we want to see if the MII Status Register reports
1430 * link. If so, then we want to get the current speed/duplex
1433 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1437 /* Check the MAC's STATUS register to determine link state
1438 * since the PHY could be inaccessible while in ULP mode.
1440 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1442 ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1444 ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1449 if (hw->mac.type == e1000_pchlan) {
1450 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1455 /* When connected at 10Mbps half-duplex, some parts are excessively
1456 * aggressive resulting in many collisions. To avoid this, increase
1457 * the IPG and reduce Rx latency in the PHY.
1459 if (((hw->mac.type == e1000_pch2lan) ||
1460 (hw->mac.type == e1000_pch_lpt)) && link) {
1463 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1464 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1465 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1467 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1469 /* Reduce Rx latency in analog PHY */
1472 /* Roll back the default values */
1477 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1479 ret_val = hw->phy.ops.acquire(hw);
1483 if (hw->mac.type == e1000_pch2lan)
1484 emi_addr = I82579_RX_CONFIG;
1486 emi_addr = I217_RX_CONFIG;
1487 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1489 hw->phy.ops.release(hw);
1495 /* I217 Packet Loss issue:
1496 * ensure that FEXTNVM4 Beacon Duration is set correctly
1498 * Set the Beacon Duration for I217 to 8 usec
1500 if (hw->mac.type == e1000_pch_lpt) {
1503 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1504 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1505 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1506 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1509 /* Work-around I218 hang issue */
1510 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1511 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1512 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1513 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1514 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1518 /* Clear link partner's EEE ability */
1519 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1521 /* Configure K0s minimum time */
1522 if (hw->mac.type == e1000_pch_lpt) {
1523 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1527 return E1000_SUCCESS; /* No link detected */
1529 mac->get_link_status = false;
1531 switch (hw->mac.type) {
1533 ret_val = e1000_k1_workaround_lv(hw);
1538 if (hw->phy.type == e1000_phy_82578) {
1539 ret_val = e1000_link_stall_workaround_hv(hw);
1544 /* Workaround for PCHx parts in half-duplex:
1545 * Set the number of preambles removed from the packet
1546 * when it is passed from the PHY to the MAC to prevent
1547 * the MAC from misinterpreting the packet type.
1549 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1550 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1552 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1554 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1556 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1562 /* Check if there was DownShift, must be checked
1563 * immediately after link-up
1565 e1000_check_downshift_generic(hw);
1567 /* Enable/Disable EEE after link up */
1568 if (hw->phy.type > e1000_phy_82579) {
1569 ret_val = e1000_set_eee_pchlan(hw);
1574 /* If we are forcing speed/duplex, then we simply return since
1575 * we have already determined whether we have link or not.
1578 return -E1000_ERR_CONFIG;
1580 /* Auto-Neg is enabled. Auto Speed Detection takes care
1581 * of MAC speed/duplex configuration. So we only need to
1582 * configure Collision Distance in the MAC.
1584 mac->ops.config_collision_dist(hw);
1586 /* Configure Flow Control now that Auto-Neg has completed.
1587 * First, we need to restore the desired flow control
1588 * settings because we may have had to re-autoneg with a
1589 * different link partner.
1591 ret_val = e1000_config_fc_after_link_up_generic(hw);
1593 DEBUGOUT("Error configuring flow control\n");
1599 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1600 * @hw: pointer to the HW structure
1602 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1604 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1606 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1608 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1609 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1610 switch (hw->mac.type) {
1613 case e1000_ich10lan:
1614 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1619 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1627 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1628 * @hw: pointer to the HW structure
1630 * Acquires the mutex for performing NVM operations.
1632 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1634 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1636 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1638 return E1000_SUCCESS;
1642 * e1000_release_nvm_ich8lan - Release NVM mutex
1643 * @hw: pointer to the HW structure
1645 * Releases the mutex used while performing NVM operations.
1647 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1649 DEBUGFUNC("e1000_release_nvm_ich8lan");
1651 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1657 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1658 * @hw: pointer to the HW structure
1660 * Acquires the software control flag for performing PHY and select
1663 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1665 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1666 s32 ret_val = E1000_SUCCESS;
1668 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1670 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1673 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1674 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1682 DEBUGOUT("SW has already locked the resource.\n");
1683 ret_val = -E1000_ERR_CONFIG;
1687 timeout = SW_FLAG_TIMEOUT;
1689 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1690 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1693 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1694 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1702 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1703 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1704 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1705 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1706 ret_val = -E1000_ERR_CONFIG;
1712 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1718 * e1000_release_swflag_ich8lan - Release software control flag
1719 * @hw: pointer to the HW structure
1721 * Releases the software control flag for performing PHY and select
1724 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1728 DEBUGFUNC("e1000_release_swflag_ich8lan");
1730 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1732 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1733 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1734 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1736 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1739 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1745 * e1000_check_mng_mode_ich8lan - Checks management mode
1746 * @hw: pointer to the HW structure
1748 * This checks if the adapter has any manageability enabled.
1749 * This is a function pointer entry point only called by read/write
1750 * routines for the PHY and NVM parts.
1752 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1756 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1758 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1760 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1761 ((fwsm & E1000_FWSM_MODE_MASK) ==
1762 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1766 * e1000_check_mng_mode_pchlan - Checks management mode
1767 * @hw: pointer to the HW structure
1769 * This checks if the adapter has iAMT enabled.
1770 * This is a function pointer entry point only called by read/write
1771 * routines for the PHY and NVM parts.
1773 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1777 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1779 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1781 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1782 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1786 * e1000_rar_set_pch2lan - Set receive address register
1787 * @hw: pointer to the HW structure
1788 * @addr: pointer to the receive address
1789 * @index: receive address array register
1791 * Sets the receive address array register at index to the address passed
1792 * in by addr. For 82579, RAR[0] is the base address register that is to
1793 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1794 * Use SHRA[0-3] in place of those reserved for ME.
1796 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1798 u32 rar_low, rar_high;
1800 DEBUGFUNC("e1000_rar_set_pch2lan");
1802 /* HW expects these in little endian so we reverse the byte order
1803 * from network order (big endian) to little endian
1805 rar_low = ((u32) addr[0] |
1806 ((u32) addr[1] << 8) |
1807 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1809 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1811 /* If MAC address zero, no need to set the AV bit */
1812 if (rar_low || rar_high)
1813 rar_high |= E1000_RAH_AV;
1816 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1817 E1000_WRITE_FLUSH(hw);
1818 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1819 E1000_WRITE_FLUSH(hw);
1820 return E1000_SUCCESS;
1823 /* RAR[1-6] are owned by manageability. Skip those and program the
1824 * next address into the SHRA register array.
1826 if (index < (u32) (hw->mac.rar_entry_count)) {
1829 ret_val = e1000_acquire_swflag_ich8lan(hw);
1833 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1834 E1000_WRITE_FLUSH(hw);
1835 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1836 E1000_WRITE_FLUSH(hw);
1838 e1000_release_swflag_ich8lan(hw);
1840 /* verify the register updates */
1841 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1842 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1843 return E1000_SUCCESS;
1845 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1846 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1850 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1851 return -E1000_ERR_CONFIG;
1855 * e1000_rar_set_pch_lpt - Set receive address registers
1856 * @hw: pointer to the HW structure
1857 * @addr: pointer to the receive address
1858 * @index: receive address array register
1860 * Sets the receive address register array at index to the address passed
1861 * in by addr. For LPT, RAR[0] is the base address register that is to
1862 * contain the MAC address. SHRA[0-10] are the shared receive address
1863 * registers that are shared between the Host and manageability engine (ME).
1865 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1867 u32 rar_low, rar_high;
1870 DEBUGFUNC("e1000_rar_set_pch_lpt");
1872 /* HW expects these in little endian so we reverse the byte order
1873 * from network order (big endian) to little endian
1875 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1876 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1878 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1880 /* If MAC address zero, no need to set the AV bit */
1881 if (rar_low || rar_high)
1882 rar_high |= E1000_RAH_AV;
1885 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1886 E1000_WRITE_FLUSH(hw);
1887 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1888 E1000_WRITE_FLUSH(hw);
1889 return E1000_SUCCESS;
1892 /* The manageability engine (ME) can lock certain SHRAR registers that
1893 * it is using - those registers are unavailable for use.
1895 if (index < hw->mac.rar_entry_count) {
1896 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1897 E1000_FWSM_WLOCK_MAC_MASK;
1898 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1900 /* Check if all SHRAR registers are locked */
1904 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1907 ret_val = e1000_acquire_swflag_ich8lan(hw);
1912 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1914 E1000_WRITE_FLUSH(hw);
1915 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1917 E1000_WRITE_FLUSH(hw);
1919 e1000_release_swflag_ich8lan(hw);
1921 /* verify the register updates */
1922 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1923 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1924 return E1000_SUCCESS;
1929 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1930 return -E1000_ERR_CONFIG;
1933 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1935 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1936 * @hw: pointer to the HW structure
1937 * @mc_addr_list: array of multicast addresses to program
1938 * @mc_addr_count: number of multicast addresses to program
1940 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1941 * The caller must have a packed mc_addr_list of multicast addresses.
1943 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1951 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1953 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1955 ret_val = hw->phy.ops.acquire(hw);
1959 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1963 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1964 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1965 (u16)(hw->mac.mta_shadow[i] &
1967 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1968 (u16)((hw->mac.mta_shadow[i] >> 16) &
1972 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1975 hw->phy.ops.release(hw);
1978 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1980 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1981 * @hw: pointer to the HW structure
1983 * Checks if firmware is blocking the reset of the PHY.
1984 * This is a function pointer entry point only called by
1987 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1990 bool blocked = false;
1993 DEBUGFUNC("e1000_check_reset_block_ich8lan");
1996 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1997 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2003 } while (blocked && (i++ < 30));
2004 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2008 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2009 * @hw: pointer to the HW structure
2011 * Assumes semaphore already acquired.
2014 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2017 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2018 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2019 E1000_STRAP_SMT_FREQ_SHIFT;
2022 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2024 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2028 phy_data &= ~HV_SMB_ADDR_MASK;
2029 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2030 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2032 if (hw->phy.type == e1000_phy_i217) {
2033 /* Restore SMBus frequency */
2035 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2036 phy_data |= (freq & (1 << 0)) <<
2037 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2038 phy_data |= (freq & (1 << 1)) <<
2039 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2041 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2045 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2049 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2050 * @hw: pointer to the HW structure
2052 * SW should configure the LCD from the NVM extended configuration region
2053 * as a workaround for certain parts.
2055 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2057 struct e1000_phy_info *phy = &hw->phy;
2058 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2059 s32 ret_val = E1000_SUCCESS;
2060 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2062 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2064 /* Initialize the PHY from the NVM on ICH platforms. This
2065 * is needed due to an issue where the NVM configuration is
2066 * not properly autoloaded after power transitions.
2067 * Therefore, after each PHY reset, we will load the
2068 * configuration data out of the NVM manually.
2070 switch (hw->mac.type) {
2072 if (phy->type != e1000_phy_igp_3)
2075 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2076 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2077 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2084 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2090 ret_val = hw->phy.ops.acquire(hw);
2094 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2095 if (!(data & sw_cfg_mask))
2098 /* Make sure HW does not configure LCD from PHY
2099 * extended configuration before SW configuration
2101 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2102 if ((hw->mac.type < e1000_pch2lan) &&
2103 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2106 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2107 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2108 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2112 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2113 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2115 if (((hw->mac.type == e1000_pchlan) &&
2116 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2117 (hw->mac.type > e1000_pchlan)) {
2118 /* HW configures the SMBus address and LEDs when the
2119 * OEM and LCD Write Enable bits are set in the NVM.
2120 * When both NVM bits are cleared, SW will configure
2123 ret_val = e1000_write_smbus_addr(hw);
2127 data = E1000_READ_REG(hw, E1000_LEDCTL);
2128 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2134 /* Configure LCD from extended configuration region. */
2136 /* cnf_base_addr is in DWORD */
2137 word_addr = (u16)(cnf_base_addr << 1);
2139 for (i = 0; i < cnf_size; i++) {
2140 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2145 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2150 /* Save off the PHY page for future writes. */
2151 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2152 phy_page = reg_data;
2156 reg_addr &= PHY_REG_MASK;
2157 reg_addr |= phy_page;
2159 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2166 hw->phy.ops.release(hw);
2171 * e1000_k1_gig_workaround_hv - K1 Si workaround
2172 * @hw: pointer to the HW structure
2173 * @link: link up bool flag
2175 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2176 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2177 * If link is down, the function will restore the default K1 setting located
2180 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2182 s32 ret_val = E1000_SUCCESS;
2184 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2186 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2188 if (hw->mac.type != e1000_pchlan)
2189 return E1000_SUCCESS;
2191 /* Wrap the whole flow with the sw flag */
2192 ret_val = hw->phy.ops.acquire(hw);
2196 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2198 if (hw->phy.type == e1000_phy_82578) {
2199 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2204 status_reg &= (BM_CS_STATUS_LINK_UP |
2205 BM_CS_STATUS_RESOLVED |
2206 BM_CS_STATUS_SPEED_MASK);
2208 if (status_reg == (BM_CS_STATUS_LINK_UP |
2209 BM_CS_STATUS_RESOLVED |
2210 BM_CS_STATUS_SPEED_1000))
2214 if (hw->phy.type == e1000_phy_82577) {
2215 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2220 status_reg &= (HV_M_STATUS_LINK_UP |
2221 HV_M_STATUS_AUTONEG_COMPLETE |
2222 HV_M_STATUS_SPEED_MASK);
2224 if (status_reg == (HV_M_STATUS_LINK_UP |
2225 HV_M_STATUS_AUTONEG_COMPLETE |
2226 HV_M_STATUS_SPEED_1000))
2230 /* Link stall fix for link up */
2231 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2237 /* Link stall fix for link down */
2238 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2244 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2247 hw->phy.ops.release(hw);
2253 * e1000_configure_k1_ich8lan - Configure K1 power state
2254 * @hw: pointer to the HW structure
2255 * @enable: K1 state to configure
2257 * Configure the K1 power state based on the provided parameter.
2258 * Assumes semaphore already acquired.
2260 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2262 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2270 DEBUGFUNC("e1000_configure_k1_ich8lan");
2272 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2278 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2280 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2282 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2288 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2289 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2291 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2292 reg |= E1000_CTRL_FRCSPD;
2293 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2295 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2296 E1000_WRITE_FLUSH(hw);
2298 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2299 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2300 E1000_WRITE_FLUSH(hw);
2303 return E1000_SUCCESS;
2307 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2308 * @hw: pointer to the HW structure
2309 * @d0_state: boolean if entering d0 or d3 device state
2311 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2312 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2313 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2315 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2321 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2323 if (hw->mac.type < e1000_pchlan)
2326 ret_val = hw->phy.ops.acquire(hw);
2330 if (hw->mac.type == e1000_pchlan) {
2331 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2332 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2336 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2337 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2340 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2342 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2346 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2349 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2350 oem_reg |= HV_OEM_BITS_GBE_DIS;
2352 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2353 oem_reg |= HV_OEM_BITS_LPLU;
2355 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2356 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2357 oem_reg |= HV_OEM_BITS_GBE_DIS;
2359 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2360 E1000_PHY_CTRL_NOND0A_LPLU))
2361 oem_reg |= HV_OEM_BITS_LPLU;
2364 /* Set Restart auto-neg to activate the bits */
2365 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2366 !hw->phy.ops.check_reset_block(hw))
2367 oem_reg |= HV_OEM_BITS_RESTART_AN;
2369 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2372 hw->phy.ops.release(hw);
2379 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2380 * @hw: pointer to the HW structure
2382 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2387 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2389 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2393 data |= HV_KMRN_MDIO_SLOW;
2395 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2401 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2402 * done after every PHY reset.
2404 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2406 s32 ret_val = E1000_SUCCESS;
2409 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2411 if (hw->mac.type != e1000_pchlan)
2412 return E1000_SUCCESS;
2414 /* Set MDIO slow mode before any other MDIO access */
2415 if (hw->phy.type == e1000_phy_82577) {
2416 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2421 if (((hw->phy.type == e1000_phy_82577) &&
2422 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2423 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2424 /* Disable generation of early preamble */
2425 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2429 /* Preamble tuning for SSC */
2430 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2436 if (hw->phy.type == e1000_phy_82578) {
2437 /* Return registers to default by doing a soft reset then
2438 * writing 0x3140 to the control register.
2440 if (hw->phy.revision < 2) {
2441 e1000_phy_sw_reset_generic(hw);
2442 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2448 ret_val = hw->phy.ops.acquire(hw);
2453 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2454 hw->phy.ops.release(hw);
2458 /* Configure the K1 Si workaround during phy reset assuming there is
2459 * link so that it disables K1 if link is in 1Gbps.
2461 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2465 /* Workaround for link disconnects on a busy hub in half duplex */
2466 ret_val = hw->phy.ops.acquire(hw);
2469 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2472 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2477 /* set MSE higher to enable link to stay up when noise is high */
2478 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2480 hw->phy.ops.release(hw);
2486 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2487 * @hw: pointer to the HW structure
2489 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2495 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2497 ret_val = hw->phy.ops.acquire(hw);
2500 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2504 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2505 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2506 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2507 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2508 (u16)(mac_reg & 0xFFFF));
2509 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2510 (u16)((mac_reg >> 16) & 0xFFFF));
2512 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2513 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2514 (u16)(mac_reg & 0xFFFF));
2515 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2516 (u16)((mac_reg & E1000_RAH_AV)
2520 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2523 hw->phy.ops.release(hw);
2526 #ifndef CRC32_OS_SUPPORT
2527 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2529 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2530 u32 i, j, mask, crc;
2532 DEBUGFUNC("e1000_calc_rx_da_crc");
2535 for (i = 0; i < 6; i++) {
2537 for (j = 8; j > 0; j--) {
2538 mask = (crc & 1) * (-1);
2539 crc = (crc >> 1) ^ (poly & mask);
2545 #endif /* CRC32_OS_SUPPORT */
2547 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2549 * @hw: pointer to the HW structure
2550 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2552 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2554 s32 ret_val = E1000_SUCCESS;
2559 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2561 if (hw->mac.type < e1000_pch2lan)
2562 return E1000_SUCCESS;
2564 /* disable Rx path while enabling/disabling workaround */
2565 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2566 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2567 phy_reg | (1 << 14));
2572 /* Write Rx addresses (rar_entry_count for RAL/H, and
2573 * SHRAL/H) and initial CRC values to the MAC
2575 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2576 u8 mac_addr[ETH_ADDR_LEN] = {0};
2577 u32 addr_high, addr_low;
2579 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2580 if (!(addr_high & E1000_RAH_AV))
2582 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2583 mac_addr[0] = (addr_low & 0xFF);
2584 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2585 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2586 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2587 mac_addr[4] = (addr_high & 0xFF);
2588 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2590 #ifndef CRC32_OS_SUPPORT
2591 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2592 e1000_calc_rx_da_crc(mac_addr));
2593 #else /* CRC32_OS_SUPPORT */
2594 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2595 E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2596 #endif /* CRC32_OS_SUPPORT */
2599 /* Write Rx addresses to the PHY */
2600 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2602 /* Enable jumbo frame workaround in the MAC */
2603 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2604 mac_reg &= ~(1 << 14);
2605 mac_reg |= (7 << 15);
2606 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2608 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2609 mac_reg |= E1000_RCTL_SECRC;
2610 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2612 ret_val = e1000_read_kmrn_reg_generic(hw,
2613 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2617 ret_val = e1000_write_kmrn_reg_generic(hw,
2618 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2622 ret_val = e1000_read_kmrn_reg_generic(hw,
2623 E1000_KMRNCTRLSTA_HD_CTRL,
2627 data &= ~(0xF << 8);
2629 ret_val = e1000_write_kmrn_reg_generic(hw,
2630 E1000_KMRNCTRLSTA_HD_CTRL,
2635 /* Enable jumbo frame workaround in the PHY */
2636 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2637 data &= ~(0x7F << 5);
2638 data |= (0x37 << 5);
2639 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2642 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2644 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2647 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2648 data &= ~(0x3FF << 2);
2649 data |= (E1000_TX_PTR_GAP << 2);
2650 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2653 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2656 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2657 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2662 /* Write MAC register values back to h/w defaults */
2663 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2664 mac_reg &= ~(0xF << 14);
2665 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2667 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2668 mac_reg &= ~E1000_RCTL_SECRC;
2669 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2671 ret_val = e1000_read_kmrn_reg_generic(hw,
2672 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2676 ret_val = e1000_write_kmrn_reg_generic(hw,
2677 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2681 ret_val = e1000_read_kmrn_reg_generic(hw,
2682 E1000_KMRNCTRLSTA_HD_CTRL,
2686 data &= ~(0xF << 8);
2688 ret_val = e1000_write_kmrn_reg_generic(hw,
2689 E1000_KMRNCTRLSTA_HD_CTRL,
2694 /* Write PHY register values back to h/w defaults */
2695 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2696 data &= ~(0x7F << 5);
2697 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2700 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2702 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2705 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2706 data &= ~(0x3FF << 2);
2708 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2711 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2714 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2715 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2721 /* re-enable Rx path after enabling/disabling workaround */
2722 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2727 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2728 * done after every PHY reset.
2730 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2732 s32 ret_val = E1000_SUCCESS;
2734 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2736 if (hw->mac.type != e1000_pch2lan)
2737 return E1000_SUCCESS;
2739 /* Set MDIO slow mode before any other MDIO access */
2740 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2744 ret_val = hw->phy.ops.acquire(hw);
2747 /* set MSE higher to enable link to stay up when noise is high */
2748 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2751 /* drop link after 5 times MSE threshold was reached */
2752 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2754 hw->phy.ops.release(hw);
2760 * e1000_k1_gig_workaround_lv - K1 Si workaround
2761 * @hw: pointer to the HW structure
2763 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2764 * Disable K1 for 1000 and 100 speeds
2766 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2768 s32 ret_val = E1000_SUCCESS;
2771 DEBUGFUNC("e1000_k1_workaround_lv");
2773 if (hw->mac.type != e1000_pch2lan)
2774 return E1000_SUCCESS;
2776 /* Set K1 beacon duration based on 10Mbs speed */
2777 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2781 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2782 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2784 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2787 /* LV 1G/100 Packet drop issue wa */
2788 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2792 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2793 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2799 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2800 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2801 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2802 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2810 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2811 * @hw: pointer to the HW structure
2812 * @gate: boolean set to true to gate, false to ungate
2814 * Gate/ungate the automatic PHY configuration via hardware; perform
2815 * the configuration via software instead.
2817 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2821 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2823 if (hw->mac.type < e1000_pch2lan)
2826 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2829 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2831 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2833 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2837 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2838 * @hw: pointer to the HW structure
2840 * Check the appropriate indication the MAC has finished configuring the
2841 * PHY after a software reset.
2843 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2845 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2847 DEBUGFUNC("e1000_lan_init_done_ich8lan");
2849 /* Wait for basic configuration completes before proceeding */
2851 data = E1000_READ_REG(hw, E1000_STATUS);
2852 data &= E1000_STATUS_LAN_INIT_DONE;
2854 } while ((!data) && --loop);
2856 /* If basic configuration is incomplete before the above loop
2857 * count reaches 0, loading the configuration from NVM will
2858 * leave the PHY in a bad state possibly resulting in no link.
2861 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2863 /* Clear the Init Done bit for the next init event */
2864 data = E1000_READ_REG(hw, E1000_STATUS);
2865 data &= ~E1000_STATUS_LAN_INIT_DONE;
2866 E1000_WRITE_REG(hw, E1000_STATUS, data);
2870 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2871 * @hw: pointer to the HW structure
2873 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2875 s32 ret_val = E1000_SUCCESS;
2878 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2880 if (hw->phy.ops.check_reset_block(hw))
2881 return E1000_SUCCESS;
2883 /* Allow time for h/w to get to quiescent state after reset */
2886 /* Perform any necessary post-reset workarounds */
2887 switch (hw->mac.type) {
2889 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2894 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2902 /* Clear the host wakeup bit after lcd reset */
2903 if (hw->mac.type >= e1000_pchlan) {
2904 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
2905 reg &= ~BM_WUC_HOST_WU_BIT;
2906 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2909 /* Configure the LCD with the extended configuration region in NVM */
2910 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2914 /* Configure the LCD with the OEM bits in NVM */
2915 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2917 if (hw->mac.type == e1000_pch2lan) {
2918 /* Ungate automatic PHY configuration on non-managed 82579 */
2919 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2920 E1000_ICH_FWSM_FW_VALID)) {
2922 e1000_gate_hw_phy_config_ich8lan(hw, false);
2925 /* Set EEE LPI Update Timer to 200usec */
2926 ret_val = hw->phy.ops.acquire(hw);
2929 ret_val = e1000_write_emi_reg_locked(hw,
2930 I82579_LPI_UPDATE_TIMER,
2932 hw->phy.ops.release(hw);
2939 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2940 * @hw: pointer to the HW structure
2943 * This is a function pointer entry point called by drivers
2944 * or other shared routines.
2946 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2948 s32 ret_val = E1000_SUCCESS;
2950 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2952 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2953 if ((hw->mac.type == e1000_pch2lan) &&
2954 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2955 e1000_gate_hw_phy_config_ich8lan(hw, true);
2957 ret_val = e1000_phy_hw_reset_generic(hw);
2961 return e1000_post_phy_reset_ich8lan(hw);
2965 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2966 * @hw: pointer to the HW structure
2967 * @active: true to enable LPLU, false to disable
2969 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2970 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2971 * the phy speed. This function will manually set the LPLU bit and restart
2972 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2973 * since it configures the same bit.
2975 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2980 DEBUGFUNC("e1000_set_lplu_state_pchlan");
2981 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2986 oem_reg |= HV_OEM_BITS_LPLU;
2988 oem_reg &= ~HV_OEM_BITS_LPLU;
2990 if (!hw->phy.ops.check_reset_block(hw))
2991 oem_reg |= HV_OEM_BITS_RESTART_AN;
2993 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2997 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2998 * @hw: pointer to the HW structure
2999 * @active: true to enable LPLU, false to disable
3001 * Sets the LPLU D0 state according to the active flag. When
3002 * activating LPLU this function also disables smart speed
3003 * and vice versa. LPLU will not be activated unless the
3004 * device autonegotiation advertisement meets standards of
3005 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3006 * This is a function pointer entry point only called by
3007 * PHY setup routines.
3009 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3011 struct e1000_phy_info *phy = &hw->phy;
3013 s32 ret_val = E1000_SUCCESS;
3016 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3018 if (phy->type == e1000_phy_ife)
3019 return E1000_SUCCESS;
3021 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3024 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3025 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3027 if (phy->type != e1000_phy_igp_3)
3028 return E1000_SUCCESS;
3030 /* Call gig speed drop workaround on LPLU before accessing
3033 if (hw->mac.type == e1000_ich8lan)
3034 e1000_gig_downshift_workaround_ich8lan(hw);
3036 /* When LPLU is enabled, we should disable SmartSpeed */
3037 ret_val = phy->ops.read_reg(hw,
3038 IGP01E1000_PHY_PORT_CONFIG,
3042 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3043 ret_val = phy->ops.write_reg(hw,
3044 IGP01E1000_PHY_PORT_CONFIG,
3049 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3050 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3052 if (phy->type != e1000_phy_igp_3)
3053 return E1000_SUCCESS;
3055 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3056 * during Dx states where the power conservation is most
3057 * important. During driver activity we should enable
3058 * SmartSpeed, so performance is maintained.
3060 if (phy->smart_speed == e1000_smart_speed_on) {
3061 ret_val = phy->ops.read_reg(hw,
3062 IGP01E1000_PHY_PORT_CONFIG,
3067 data |= IGP01E1000_PSCFR_SMART_SPEED;
3068 ret_val = phy->ops.write_reg(hw,
3069 IGP01E1000_PHY_PORT_CONFIG,
3073 } else if (phy->smart_speed == e1000_smart_speed_off) {
3074 ret_val = phy->ops.read_reg(hw,
3075 IGP01E1000_PHY_PORT_CONFIG,
3080 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3081 ret_val = phy->ops.write_reg(hw,
3082 IGP01E1000_PHY_PORT_CONFIG,
3089 return E1000_SUCCESS;
3093 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3094 * @hw: pointer to the HW structure
3095 * @active: true to enable LPLU, false to disable
3097 * Sets the LPLU D3 state according to the active flag. When
3098 * activating LPLU this function also disables smart speed
3099 * and vice versa. LPLU will not be activated unless the
3100 * device autonegotiation advertisement meets standards of
3101 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3102 * This is a function pointer entry point only called by
3103 * PHY setup routines.
3105 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3107 struct e1000_phy_info *phy = &hw->phy;
3109 s32 ret_val = E1000_SUCCESS;
3112 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3114 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3117 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3118 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3120 if (phy->type != e1000_phy_igp_3)
3121 return E1000_SUCCESS;
3123 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3124 * during Dx states where the power conservation is most
3125 * important. During driver activity we should enable
3126 * SmartSpeed, so performance is maintained.
3128 if (phy->smart_speed == e1000_smart_speed_on) {
3129 ret_val = phy->ops.read_reg(hw,
3130 IGP01E1000_PHY_PORT_CONFIG,
3135 data |= IGP01E1000_PSCFR_SMART_SPEED;
3136 ret_val = phy->ops.write_reg(hw,
3137 IGP01E1000_PHY_PORT_CONFIG,
3141 } else if (phy->smart_speed == e1000_smart_speed_off) {
3142 ret_val = phy->ops.read_reg(hw,
3143 IGP01E1000_PHY_PORT_CONFIG,
3148 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3149 ret_val = phy->ops.write_reg(hw,
3150 IGP01E1000_PHY_PORT_CONFIG,
3155 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3156 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3157 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3158 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3159 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3161 if (phy->type != e1000_phy_igp_3)
3162 return E1000_SUCCESS;
3164 /* Call gig speed drop workaround on LPLU before accessing
3167 if (hw->mac.type == e1000_ich8lan)
3168 e1000_gig_downshift_workaround_ich8lan(hw);
3170 /* When LPLU is enabled, we should disable SmartSpeed */
3171 ret_val = phy->ops.read_reg(hw,
3172 IGP01E1000_PHY_PORT_CONFIG,
3177 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3178 ret_val = phy->ops.write_reg(hw,
3179 IGP01E1000_PHY_PORT_CONFIG,
3187 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3188 * @hw: pointer to the HW structure
3189 * @bank: pointer to the variable that returns the active bank
3191 * Reads signature byte from the NVM using the flash access registers.
3192 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3194 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3197 struct e1000_nvm_info *nvm = &hw->nvm;
3198 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3199 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3204 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3206 switch (hw->mac.type) {
3209 eecd = E1000_READ_REG(hw, E1000_EECD);
3210 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3211 E1000_EECD_SEC1VAL_VALID_MASK) {
3212 if (eecd & E1000_EECD_SEC1VAL)
3217 return E1000_SUCCESS;
3219 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3222 /* set bank to 0 in case flash read fails */
3226 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3230 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3231 E1000_ICH_NVM_SIG_VALUE) {
3233 return E1000_SUCCESS;
3237 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3242 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3243 E1000_ICH_NVM_SIG_VALUE) {
3245 return E1000_SUCCESS;
3248 DEBUGOUT("ERROR: No valid NVM bank present\n");
3249 return -E1000_ERR_NVM;
3254 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3255 * @hw: pointer to the HW structure
3256 * @offset: The offset (in bytes) of the word(s) to read.
3257 * @words: Size of data to read in words
3258 * @data: Pointer to the word(s) to read at offset.
3260 * Reads a word(s) from the NVM using the flash access registers.
3262 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3265 struct e1000_nvm_info *nvm = &hw->nvm;
3266 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3268 s32 ret_val = E1000_SUCCESS;
3272 DEBUGFUNC("e1000_read_nvm_ich8lan");
3274 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3276 DEBUGOUT("nvm parameter(s) out of bounds\n");
3277 ret_val = -E1000_ERR_NVM;
3281 nvm->ops.acquire(hw);
3283 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3284 if (ret_val != E1000_SUCCESS) {
3285 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3289 act_offset = (bank) ? nvm->flash_bank_size : 0;
3290 act_offset += offset;
3292 ret_val = E1000_SUCCESS;
3293 for (i = 0; i < words; i++) {
3294 if (dev_spec->shadow_ram[offset+i].modified) {
3295 data[i] = dev_spec->shadow_ram[offset+i].value;
3297 ret_val = e1000_read_flash_word_ich8lan(hw,
3306 nvm->ops.release(hw);
3310 DEBUGOUT1("NVM read error: %d\n", ret_val);
3316 * e1000_flash_cycle_init_ich8lan - Initialize flash
3317 * @hw: pointer to the HW structure
3319 * This function does initial flash setup so that a new read/write/erase cycle
3322 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3324 union ich8_hws_flash_status hsfsts;
3325 s32 ret_val = -E1000_ERR_NVM;
3327 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3329 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3331 /* Check if the flash descriptor is valid */
3332 if (!hsfsts.hsf_status.fldesvalid) {
3333 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3334 return -E1000_ERR_NVM;
3337 /* Clear FCERR and DAEL in hw status by writing 1 */
3338 hsfsts.hsf_status.flcerr = 1;
3339 hsfsts.hsf_status.dael = 1;
3340 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3342 /* Either we should have a hardware SPI cycle in progress
3343 * bit to check against, in order to start a new cycle or
3344 * FDONE bit should be changed in the hardware so that it
3345 * is 1 after hardware reset, which can then be used as an
3346 * indication whether a cycle is in progress or has been
3350 if (!hsfsts.hsf_status.flcinprog) {
3351 /* There is no cycle running at present,
3352 * so we can start a cycle.
3353 * Begin by setting Flash Cycle Done.
3355 hsfsts.hsf_status.flcdone = 1;
3356 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3357 ret_val = E1000_SUCCESS;
3361 /* Otherwise poll for sometime so the current
3362 * cycle has a chance to end before giving up.
3364 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3365 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3367 if (!hsfsts.hsf_status.flcinprog) {
3368 ret_val = E1000_SUCCESS;
3373 if (ret_val == E1000_SUCCESS) {
3374 /* Successful in waiting for previous cycle to timeout,
3375 * now set the Flash Cycle Done.
3377 hsfsts.hsf_status.flcdone = 1;
3378 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3381 DEBUGOUT("Flash controller busy, cannot get access\n");
3389 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3390 * @hw: pointer to the HW structure
3391 * @timeout: maximum time to wait for completion
3393 * This function starts a flash cycle and waits for its completion.
3395 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3397 union ich8_hws_flash_ctrl hsflctl;
3398 union ich8_hws_flash_status hsfsts;
3401 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3403 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3404 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3405 hsflctl.hsf_ctrl.flcgo = 1;
3407 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3409 /* wait till FDONE bit is set to 1 */
3411 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3412 if (hsfsts.hsf_status.flcdone)
3415 } while (i++ < timeout);
3417 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3418 return E1000_SUCCESS;
3420 return -E1000_ERR_NVM;
3424 * e1000_read_flash_word_ich8lan - Read word from flash
3425 * @hw: pointer to the HW structure
3426 * @offset: offset to data location
3427 * @data: pointer to the location for storing the data
3429 * Reads the flash word at offset into data. Offset is converted
3430 * to bytes before read.
3432 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3435 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3438 return -E1000_ERR_NVM;
3440 /* Must convert offset into bytes. */
3443 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3447 * e1000_read_flash_byte_ich8lan - Read byte from flash
3448 * @hw: pointer to the HW structure
3449 * @offset: The offset of the byte to read.
3450 * @data: Pointer to a byte to store the value read.
3452 * Reads a single byte from the NVM using the flash access registers.
3454 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3460 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3467 return E1000_SUCCESS;
3471 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3472 * @hw: pointer to the HW structure
3473 * @offset: The offset (in bytes) of the byte or word to read.
3474 * @size: Size of data to read, 1=byte 2=word
3475 * @data: Pointer to the word to store the value read.
3477 * Reads a byte or word from the NVM using the flash access registers.
3479 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3482 union ich8_hws_flash_status hsfsts;
3483 union ich8_hws_flash_ctrl hsflctl;
3484 u32 flash_linear_addr;
3486 s32 ret_val = -E1000_ERR_NVM;
3489 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3491 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3492 return -E1000_ERR_NVM;
3493 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3494 hw->nvm.flash_base_addr);
3499 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3500 if (ret_val != E1000_SUCCESS)
3502 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3504 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3505 hsflctl.hsf_ctrl.fldbcount = size - 1;
3506 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3507 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3508 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3510 ret_val = e1000_flash_cycle_ich8lan(hw,
3511 ICH_FLASH_READ_COMMAND_TIMEOUT);
3513 /* Check if FCERR is set to 1, if set to 1, clear it
3514 * and try the whole sequence a few more times, else
3515 * read in (shift in) the Flash Data0, the order is
3516 * least significant byte first msb to lsb
3518 if (ret_val == E1000_SUCCESS) {
3519 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3521 *data = (u8)(flash_data & 0x000000FF);
3523 *data = (u16)(flash_data & 0x0000FFFF);
3526 /* If we've gotten here, then things are probably
3527 * completely hosed, but if the error condition is
3528 * detected, it won't hurt to give it another try...
3529 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3531 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3533 if (hsfsts.hsf_status.flcerr) {
3534 /* Repeat for some time before giving up. */
3536 } else if (!hsfsts.hsf_status.flcdone) {
3537 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3541 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3548 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3549 * @hw: pointer to the HW structure
3550 * @offset: The offset (in bytes) of the word(s) to write.
3551 * @words: Size of data to write in words
3552 * @data: Pointer to the word(s) to write at offset.
3554 * Writes a byte or word to the NVM using the flash access registers.
3556 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3559 struct e1000_nvm_info *nvm = &hw->nvm;
3560 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3563 DEBUGFUNC("e1000_write_nvm_ich8lan");
3565 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3567 DEBUGOUT("nvm parameter(s) out of bounds\n");
3568 return -E1000_ERR_NVM;
3571 nvm->ops.acquire(hw);
3573 for (i = 0; i < words; i++) {
3574 dev_spec->shadow_ram[offset+i].modified = true;
3575 dev_spec->shadow_ram[offset+i].value = data[i];
3578 nvm->ops.release(hw);
3580 return E1000_SUCCESS;
3584 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3585 * @hw: pointer to the HW structure
3587 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3588 * which writes the checksum to the shadow ram. The changes in the shadow
3589 * ram are then committed to the EEPROM by processing each bank at a time
3590 * checking for the modified bit and writing only the pending changes.
3591 * After a successful commit, the shadow ram is cleared and is ready for
3594 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3596 struct e1000_nvm_info *nvm = &hw->nvm;
3597 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3598 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3602 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3604 ret_val = e1000_update_nvm_checksum_generic(hw);
3608 if (nvm->type != e1000_nvm_flash_sw)
3611 nvm->ops.acquire(hw);
3613 /* We're writing to the opposite bank so if we're on bank 1,
3614 * write to bank 0 etc. We also need to erase the segment that
3615 * is going to be written
3617 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3618 if (ret_val != E1000_SUCCESS) {
3619 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3624 new_bank_offset = nvm->flash_bank_size;
3625 old_bank_offset = 0;
3626 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3630 old_bank_offset = nvm->flash_bank_size;
3631 new_bank_offset = 0;
3632 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3636 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3637 if (dev_spec->shadow_ram[i].modified) {
3638 data = dev_spec->shadow_ram[i].value;
3640 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3646 /* If the word is 0x13, then make sure the signature bits
3647 * (15:14) are 11b until the commit has completed.
3648 * This will allow us to write 10b which indicates the
3649 * signature is valid. We want to do this after the write
3650 * has completed so that we don't mark the segment valid
3651 * while the write is still in progress
3653 if (i == E1000_ICH_NVM_SIG_WORD)
3654 data |= E1000_ICH_NVM_SIG_MASK;
3656 /* Convert offset to bytes. */
3657 act_offset = (i + new_bank_offset) << 1;
3661 /* Write the bytes to the new bank. */
3662 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3669 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3676 /* Don't bother writing the segment valid bits if sector
3677 * programming failed.
3680 DEBUGOUT("Flash commit failed.\n");
3684 /* Finally validate the new segment by setting bit 15:14
3685 * to 10b in word 0x13 , this can be done without an
3686 * erase as well since these bits are 11 to start with
3687 * and we need to change bit 14 to 0b
3689 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3690 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3695 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
3700 /* And invalidate the previously valid segment by setting
3701 * its signature word (0x13) high_byte to 0b. This can be
3702 * done without an erase because flash erase sets all bits
3703 * to 1's. We can write 1's to 0's without an erase
3705 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3707 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3712 /* Great! Everything worked, we can now clear the cached entries. */
3713 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3714 dev_spec->shadow_ram[i].modified = false;
3715 dev_spec->shadow_ram[i].value = 0xFFFF;
3719 nvm->ops.release(hw);
3721 /* Reload the EEPROM, or else modifications will not appear
3722 * until after the next adapter reset.
3725 nvm->ops.reload(hw);
3731 DEBUGOUT1("NVM update error: %d\n", ret_val);
3737 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3738 * @hw: pointer to the HW structure
3740 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3741 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3742 * calculated, in which case we need to calculate the checksum and set bit 6.
3744 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3749 u16 valid_csum_mask;
3751 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3753 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3754 * the checksum needs to be fixed. This bit is an indication that
3755 * the NVM was prepared by OEM software and did not calculate
3756 * the checksum...a likely scenario.
3758 switch (hw->mac.type) {
3761 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3764 word = NVM_FUTURE_INIT_WORD1;
3765 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3769 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3773 if (!(data & valid_csum_mask)) {
3774 data |= valid_csum_mask;
3775 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3778 ret_val = hw->nvm.ops.update(hw);
3783 return e1000_validate_nvm_checksum_generic(hw);
3787 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3788 * @hw: pointer to the HW structure
3789 * @offset: The offset (in bytes) of the byte/word to read.
3790 * @size: Size of data to read, 1=byte 2=word
3791 * @data: The byte(s) to write to the NVM.
3793 * Writes one/two bytes to the NVM using the flash access registers.
3795 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3798 union ich8_hws_flash_status hsfsts;
3799 union ich8_hws_flash_ctrl hsflctl;
3800 u32 flash_linear_addr;
3805 DEBUGFUNC("e1000_write_ich8_data");
3807 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3808 return -E1000_ERR_NVM;
3810 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3811 hw->nvm.flash_base_addr);
3816 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3817 if (ret_val != E1000_SUCCESS)
3819 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3821 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3822 hsflctl.hsf_ctrl.fldbcount = size - 1;
3823 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3824 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3826 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3829 flash_data = (u32)data & 0x00FF;
3831 flash_data = (u32)data;
3833 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3835 /* check if FCERR is set to 1 , if set to 1, clear it
3836 * and try the whole sequence a few more times else done
3839 e1000_flash_cycle_ich8lan(hw,
3840 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3841 if (ret_val == E1000_SUCCESS)
3844 /* If we're here, then things are most likely
3845 * completely hosed, but if the error condition
3846 * is detected, it won't hurt to give it another
3847 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3849 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3850 if (hsfsts.hsf_status.flcerr)
3851 /* Repeat for some time before giving up. */
3853 if (!hsfsts.hsf_status.flcdone) {
3854 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3857 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3864 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3865 * @hw: pointer to the HW structure
3866 * @offset: The index of the byte to read.
3867 * @data: The byte to write to the NVM.
3869 * Writes a single byte to the NVM using the flash access registers.
3871 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3874 u16 word = (u16)data;
3876 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3878 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3884 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3885 * @hw: pointer to the HW structure
3886 * @offset: The offset of the byte to write.
3887 * @byte: The byte to write to the NVM.
3889 * Writes a single byte to the NVM using the flash access registers.
3890 * Goes through a retry algorithm before giving up.
3892 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3893 u32 offset, u8 byte)
3896 u16 program_retries;
3898 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3900 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3904 for (program_retries = 0; program_retries < 100; program_retries++) {
3905 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3907 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3908 if (ret_val == E1000_SUCCESS)
3911 if (program_retries == 100)
3912 return -E1000_ERR_NVM;
3914 return E1000_SUCCESS;
3918 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3919 * @hw: pointer to the HW structure
3920 * @bank: 0 for first bank, 1 for second bank, etc.
3922 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3923 * bank N is 4096 * N + flash_reg_addr.
3925 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3927 struct e1000_nvm_info *nvm = &hw->nvm;
3928 union ich8_hws_flash_status hsfsts;
3929 union ich8_hws_flash_ctrl hsflctl;
3930 u32 flash_linear_addr;
3931 /* bank size is in 16bit words - adjust to bytes */
3932 u32 flash_bank_size = nvm->flash_bank_size * 2;
3935 s32 j, iteration, sector_size;
3937 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3939 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3941 /* Determine HW Sector size: Read BERASE bits of hw flash status
3943 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3944 * consecutive sectors. The start index for the nth Hw sector
3945 * can be calculated as = bank * 4096 + n * 256
3946 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3947 * The start index for the nth Hw sector can be calculated
3949 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3950 * (ich9 only, otherwise error condition)
3951 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3953 switch (hsfsts.hsf_status.berasesz) {
3955 /* Hw sector size 256 */
3956 sector_size = ICH_FLASH_SEG_SIZE_256;
3957 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3960 sector_size = ICH_FLASH_SEG_SIZE_4K;
3964 sector_size = ICH_FLASH_SEG_SIZE_8K;
3968 sector_size = ICH_FLASH_SEG_SIZE_64K;
3972 return -E1000_ERR_NVM;
3975 /* Start with the base address, then add the sector offset. */
3976 flash_linear_addr = hw->nvm.flash_base_addr;
3977 flash_linear_addr += (bank) ? flash_bank_size : 0;
3979 for (j = 0; j < iteration; j++) {
3981 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3984 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3988 /* Write a value 11 (block Erase) in Flash
3989 * Cycle field in hw flash control
3992 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3994 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3995 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3998 /* Write the last 24 bits of an index within the
3999 * block into Flash Linear address field in Flash
4002 flash_linear_addr += (j * sector_size);
4003 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4006 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4007 if (ret_val == E1000_SUCCESS)
4010 /* Check if FCERR is set to 1. If 1,
4011 * clear it and try the whole sequence
4012 * a few more times else Done
4014 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4016 if (hsfsts.hsf_status.flcerr)
4017 /* repeat for some time before giving up */
4019 else if (!hsfsts.hsf_status.flcdone)
4021 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4024 return E1000_SUCCESS;
4028 * e1000_valid_led_default_ich8lan - Set the default LED settings
4029 * @hw: pointer to the HW structure
4030 * @data: Pointer to the LED settings
4032 * Reads the LED default settings from the NVM to data. If the NVM LED
4033 * settings is all 0's or F's, set the LED default to a valid LED default
4036 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4040 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4042 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4044 DEBUGOUT("NVM Read Error\n");
4048 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4049 *data = ID_LED_DEFAULT_ICH8LAN;
4051 return E1000_SUCCESS;
4055 * e1000_id_led_init_pchlan - store LED configurations
4056 * @hw: pointer to the HW structure
4058 * PCH does not control LEDs via the LEDCTL register, rather it uses
4059 * the PHY LED configuration register.
4061 * PCH also does not have an "always on" or "always off" mode which
4062 * complicates the ID feature. Instead of using the "on" mode to indicate
4063 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4064 * use "link_up" mode. The LEDs will still ID on request if there is no
4065 * link based on logic in e1000_led_[on|off]_pchlan().
4067 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4069 struct e1000_mac_info *mac = &hw->mac;
4071 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4072 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4073 u16 data, i, temp, shift;
4075 DEBUGFUNC("e1000_id_led_init_pchlan");
4077 /* Get default ID LED modes */
4078 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4082 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4083 mac->ledctl_mode1 = mac->ledctl_default;
4084 mac->ledctl_mode2 = mac->ledctl_default;
4086 for (i = 0; i < 4; i++) {
4087 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4090 case ID_LED_ON1_DEF2:
4091 case ID_LED_ON1_ON2:
4092 case ID_LED_ON1_OFF2:
4093 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4094 mac->ledctl_mode1 |= (ledctl_on << shift);
4096 case ID_LED_OFF1_DEF2:
4097 case ID_LED_OFF1_ON2:
4098 case ID_LED_OFF1_OFF2:
4099 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4100 mac->ledctl_mode1 |= (ledctl_off << shift);
4107 case ID_LED_DEF1_ON2:
4108 case ID_LED_ON1_ON2:
4109 case ID_LED_OFF1_ON2:
4110 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4111 mac->ledctl_mode2 |= (ledctl_on << shift);
4113 case ID_LED_DEF1_OFF2:
4114 case ID_LED_ON1_OFF2:
4115 case ID_LED_OFF1_OFF2:
4116 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4117 mac->ledctl_mode2 |= (ledctl_off << shift);
4125 return E1000_SUCCESS;
4129 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4130 * @hw: pointer to the HW structure
4132 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4133 * register, so the the bus width is hard coded.
4135 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4137 struct e1000_bus_info *bus = &hw->bus;
4140 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4142 ret_val = e1000_get_bus_info_pcie_generic(hw);
4144 /* ICH devices are "PCI Express"-ish. They have
4145 * a configuration space, but do not contain
4146 * PCI Express Capability registers, so bus width
4147 * must be hardcoded.
4149 if (bus->width == e1000_bus_width_unknown)
4150 bus->width = e1000_bus_width_pcie_x1;
4156 * e1000_reset_hw_ich8lan - Reset the hardware
4157 * @hw: pointer to the HW structure
4159 * Does a full reset of the hardware which includes a reset of the PHY and
4162 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4164 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4169 DEBUGFUNC("e1000_reset_hw_ich8lan");
4171 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4172 * on the last TLP read/write transaction when MAC is reset.
4174 ret_val = e1000_disable_pcie_master_generic(hw);
4176 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4178 DEBUGOUT("Masking off all interrupts\n");
4179 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4181 /* Disable the Transmit and Receive units. Then delay to allow
4182 * any pending transactions to complete before we hit the MAC
4183 * with the global reset.
4185 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4186 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4187 E1000_WRITE_FLUSH(hw);
4191 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4192 if (hw->mac.type == e1000_ich8lan) {
4193 /* Set Tx and Rx buffer allocation to 8k apiece. */
4194 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4195 /* Set Packet Buffer Size to 16k. */
4196 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4199 if (hw->mac.type == e1000_pchlan) {
4200 /* Save the NVM K1 bit setting*/
4201 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4205 if (kum_cfg & E1000_NVM_K1_ENABLE)
4206 dev_spec->nvm_k1_enabled = true;
4208 dev_spec->nvm_k1_enabled = false;
4211 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4213 if (!hw->phy.ops.check_reset_block(hw)) {
4214 /* Full-chip reset requires MAC and PHY reset at the same
4215 * time to make sure the interface between MAC and the
4216 * external PHY is reset.
4218 ctrl |= E1000_CTRL_PHY_RST;
4220 /* Gate automatic PHY configuration by hardware on
4223 if ((hw->mac.type == e1000_pch2lan) &&
4224 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4225 e1000_gate_hw_phy_config_ich8lan(hw, true);
4227 ret_val = e1000_acquire_swflag_ich8lan(hw);
4228 DEBUGOUT("Issuing a global reset to ich8lan\n");
4229 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4230 /* cannot issue a flush here because it hangs the hardware */
4233 /* Set Phy Config Counter to 50msec */
4234 if (hw->mac.type == e1000_pch2lan) {
4235 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4236 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4237 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4238 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4242 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4244 if (ctrl & E1000_CTRL_PHY_RST) {
4245 ret_val = hw->phy.ops.get_cfg_done(hw);
4249 ret_val = e1000_post_phy_reset_ich8lan(hw);
4254 /* For PCH, this write will make sure that any noise
4255 * will be detected as a CRC error and be dropped rather than show up
4256 * as a bad packet to the DMA engine.
4258 if (hw->mac.type == e1000_pchlan)
4259 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4261 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4262 E1000_READ_REG(hw, E1000_ICR);
4264 reg = E1000_READ_REG(hw, E1000_KABGTXD);
4265 reg |= E1000_KABGTXD_BGSQLBIAS;
4266 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4268 return E1000_SUCCESS;
4272 * e1000_init_hw_ich8lan - Initialize the hardware
4273 * @hw: pointer to the HW structure
4275 * Prepares the hardware for transmit and receive by doing the following:
4276 * - initialize hardware bits
4277 * - initialize LED identification
4278 * - setup receive address registers
4279 * - setup flow control
4280 * - setup transmit descriptors
4281 * - clear statistics
4283 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4285 struct e1000_mac_info *mac = &hw->mac;
4286 u32 ctrl_ext, txdctl, snoop;
4290 DEBUGFUNC("e1000_init_hw_ich8lan");
4292 e1000_initialize_hw_bits_ich8lan(hw);
4294 /* Initialize identification LED */
4295 ret_val = mac->ops.id_led_init(hw);
4296 /* An error is not fatal and we should not stop init due to this */
4298 DEBUGOUT("Error initializing identification LED\n");
4300 /* Setup the receive address. */
4301 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4303 /* Zero out the Multicast HASH table */
4304 DEBUGOUT("Zeroing the MTA\n");
4305 for (i = 0; i < mac->mta_reg_count; i++)
4306 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4308 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4309 * the ME. Disable wakeup by clearing the host wakeup bit.
4310 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4312 if (hw->phy.type == e1000_phy_82578) {
4313 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4314 i &= ~BM_WUC_HOST_WU_BIT;
4315 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4316 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4321 /* Setup link and flow control */
4322 ret_val = mac->ops.setup_link(hw);
4324 /* Set the transmit descriptor write-back policy for both queues */
4325 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4326 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4327 E1000_TXDCTL_FULL_TX_DESC_WB);
4328 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4329 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4330 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4331 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4332 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4333 E1000_TXDCTL_FULL_TX_DESC_WB);
4334 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4335 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4336 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4338 /* ICH8 has opposite polarity of no_snoop bits.
4339 * By default, we should use snoop behavior.
4341 if (mac->type == e1000_ich8lan)
4342 snoop = PCIE_ICH8_SNOOP_ALL;
4344 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4345 e1000_set_pcie_no_snoop_generic(hw, snoop);
4347 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4348 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4349 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4351 /* Clear all of the statistics registers (clear on read). It is
4352 * important that we do this after we have tried to establish link
4353 * because the symbol error count will increment wildly if there
4356 e1000_clear_hw_cntrs_ich8lan(hw);
4362 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4363 * @hw: pointer to the HW structure
4365 * Sets/Clears required hardware bits necessary for correctly setting up the
4366 * hardware for transmit and receive.
4368 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4372 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4374 /* Extended Device Control */
4375 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4377 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4378 if (hw->mac.type >= e1000_pchlan)
4379 reg |= E1000_CTRL_EXT_PHYPDEN;
4380 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4382 /* Transmit Descriptor Control 0 */
4383 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4385 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4387 /* Transmit Descriptor Control 1 */
4388 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4390 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4392 /* Transmit Arbitration Control 0 */
4393 reg = E1000_READ_REG(hw, E1000_TARC(0));
4394 if (hw->mac.type == e1000_ich8lan)
4395 reg |= (1 << 28) | (1 << 29);
4396 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4397 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4399 /* Transmit Arbitration Control 1 */
4400 reg = E1000_READ_REG(hw, E1000_TARC(1));
4401 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4405 reg |= (1 << 24) | (1 << 26) | (1 << 30);
4406 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4409 if (hw->mac.type == e1000_ich8lan) {
4410 reg = E1000_READ_REG(hw, E1000_STATUS);
4412 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4415 /* work-around descriptor data corruption issue during nfs v2 udp
4416 * traffic, just disable the nfs filtering capability
4418 reg = E1000_READ_REG(hw, E1000_RFCTL);
4419 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4421 /* Disable IPv6 extension header parsing because some malformed
4422 * IPv6 headers can hang the Rx.
4424 if (hw->mac.type == e1000_ich8lan)
4425 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4426 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4428 /* Enable ECC on Lynxpoint */
4429 if (hw->mac.type == e1000_pch_lpt) {
4430 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4431 reg |= E1000_PBECCSTS_ECC_ENABLE;
4432 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4434 reg = E1000_READ_REG(hw, E1000_CTRL);
4435 reg |= E1000_CTRL_MEHE;
4436 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4443 * e1000_setup_link_ich8lan - Setup flow control and link settings
4444 * @hw: pointer to the HW structure
4446 * Determines which flow control settings to use, then configures flow
4447 * control. Calls the appropriate media-specific link configuration
4448 * function. Assuming the adapter has a valid link partner, a valid link
4449 * should be established. Assumes the hardware has previously been reset
4450 * and the transmitter and receiver are not enabled.
4452 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4456 DEBUGFUNC("e1000_setup_link_ich8lan");
4458 if (hw->phy.ops.check_reset_block(hw))
4459 return E1000_SUCCESS;
4461 /* ICH parts do not have a word in the NVM to determine
4462 * the default flow control setting, so we explicitly
4465 if (hw->fc.requested_mode == e1000_fc_default)
4466 hw->fc.requested_mode = e1000_fc_full;
4468 /* Save off the requested flow control mode for use later. Depending
4469 * on the link partner's capabilities, we may or may not use this mode.
4471 hw->fc.current_mode = hw->fc.requested_mode;
4473 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4474 hw->fc.current_mode);
4476 /* Continue to configure the copper link. */
4477 ret_val = hw->mac.ops.setup_physical_interface(hw);
4481 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4482 if ((hw->phy.type == e1000_phy_82578) ||
4483 (hw->phy.type == e1000_phy_82579) ||
4484 (hw->phy.type == e1000_phy_i217) ||
4485 (hw->phy.type == e1000_phy_82577)) {
4486 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4488 ret_val = hw->phy.ops.write_reg(hw,
4489 PHY_REG(BM_PORT_CTRL_PAGE, 27),
4495 return e1000_set_fc_watermarks_generic(hw);
4499 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4500 * @hw: pointer to the HW structure
4502 * Configures the kumeran interface to the PHY to wait the appropriate time
4503 * when polling the PHY, then call the generic setup_copper_link to finish
4504 * configuring the copper link.
4506 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4512 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4514 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4515 ctrl |= E1000_CTRL_SLU;
4516 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4517 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4519 /* Set the mac to wait the maximum time between each iteration
4520 * and increase the max iterations when polling the phy;
4521 * this fixes erroneous timeouts at 10Mbps.
4523 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4527 ret_val = e1000_read_kmrn_reg_generic(hw,
4528 E1000_KMRNCTRLSTA_INBAND_PARAM,
4533 ret_val = e1000_write_kmrn_reg_generic(hw,
4534 E1000_KMRNCTRLSTA_INBAND_PARAM,
4539 switch (hw->phy.type) {
4540 case e1000_phy_igp_3:
4541 ret_val = e1000_copper_link_setup_igp(hw);
4546 case e1000_phy_82578:
4547 ret_val = e1000_copper_link_setup_m88(hw);
4551 case e1000_phy_82577:
4552 case e1000_phy_82579:
4553 ret_val = e1000_copper_link_setup_82577(hw);
4558 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4563 reg_data &= ~IFE_PMC_AUTO_MDIX;
4565 switch (hw->phy.mdix) {
4567 reg_data &= ~IFE_PMC_FORCE_MDIX;
4570 reg_data |= IFE_PMC_FORCE_MDIX;
4574 reg_data |= IFE_PMC_AUTO_MDIX;
4577 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4586 return e1000_setup_copper_link_generic(hw);
4590 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4591 * @hw: pointer to the HW structure
4593 * Calls the PHY specific link setup function and then calls the
4594 * generic setup_copper_link to finish configuring the link for
4595 * Lynxpoint PCH devices
4597 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4602 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4604 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4605 ctrl |= E1000_CTRL_SLU;
4606 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4607 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4609 ret_val = e1000_copper_link_setup_82577(hw);
4613 return e1000_setup_copper_link_generic(hw);
4617 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4618 * @hw: pointer to the HW structure
4619 * @speed: pointer to store current link speed
4620 * @duplex: pointer to store the current link duplex
4622 * Calls the generic get_speed_and_duplex to retrieve the current link
4623 * information and then calls the Kumeran lock loss workaround for links at
4626 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4631 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4633 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4637 if ((hw->mac.type == e1000_ich8lan) &&
4638 (hw->phy.type == e1000_phy_igp_3) &&
4639 (*speed == SPEED_1000)) {
4640 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4647 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4648 * @hw: pointer to the HW structure
4650 * Work-around for 82566 Kumeran PCS lock loss:
4651 * On link status change (i.e. PCI reset, speed change) and link is up and
4653 * 0) if workaround is optionally disabled do nothing
4654 * 1) wait 1ms for Kumeran link to come up
4655 * 2) check Kumeran Diagnostic register PCS lock loss bit
4656 * 3) if not set the link is locked (all is good), otherwise...
4658 * 5) repeat up to 10 times
4659 * Note: this is only called for IGP3 copper when speed is 1gb.
4661 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4663 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4669 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4671 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4672 return E1000_SUCCESS;
4674 /* Make sure link is up before proceeding. If not just return.
4675 * Attempting this while link is negotiating fouled up link
4678 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4680 return E1000_SUCCESS;
4682 for (i = 0; i < 10; i++) {
4683 /* read once to clear */
4684 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4687 /* and again to get new status */
4688 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4692 /* check for PCS lock */
4693 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4694 return E1000_SUCCESS;
4696 /* Issue PHY reset */
4697 hw->phy.ops.reset(hw);
4700 /* Disable GigE link negotiation */
4701 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4702 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4703 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4704 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4706 /* Call gig speed drop workaround on Gig disable before accessing
4709 e1000_gig_downshift_workaround_ich8lan(hw);
4711 /* unable to acquire PCS lock */
4712 return -E1000_ERR_PHY;
4716 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4717 * @hw: pointer to the HW structure
4718 * @state: boolean value used to set the current Kumeran workaround state
4720 * If ICH8, set the current Kumeran workaround state (enabled - true
4721 * /disabled - false).
4723 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4726 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4728 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4730 if (hw->mac.type != e1000_ich8lan) {
4731 DEBUGOUT("Workaround applies to ICH8 only.\n");
4735 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4741 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4742 * @hw: pointer to the HW structure
4744 * Workaround for 82566 power-down on D3 entry:
4745 * 1) disable gigabit link
4746 * 2) write VR power-down enable
4748 * Continue if successful, else issue LCD reset and repeat
4750 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4756 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4758 if (hw->phy.type != e1000_phy_igp_3)
4761 /* Try the workaround twice (if needed) */
4764 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4765 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4766 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4767 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4769 /* Call gig speed drop workaround on Gig disable before
4770 * accessing any PHY registers
4772 if (hw->mac.type == e1000_ich8lan)
4773 e1000_gig_downshift_workaround_ich8lan(hw);
4775 /* Write VR power-down enable */
4776 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4777 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4778 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4779 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4781 /* Read it back and test */
4782 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4783 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4784 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4787 /* Issue PHY reset and repeat at most one more time */
4788 reg = E1000_READ_REG(hw, E1000_CTRL);
4789 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4795 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4796 * @hw: pointer to the HW structure
4798 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4799 * LPLU, Gig disable, MDIC PHY reset):
4800 * 1) Set Kumeran Near-end loopback
4801 * 2) Clear Kumeran Near-end loopback
4802 * Should only be called for ICH8[m] devices with any 1G Phy.
4804 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4809 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4811 if ((hw->mac.type != e1000_ich8lan) ||
4812 (hw->phy.type == e1000_phy_ife))
4815 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4819 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4820 ret_val = e1000_write_kmrn_reg_generic(hw,
4821 E1000_KMRNCTRLSTA_DIAG_OFFSET,
4825 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4826 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4831 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4832 * @hw: pointer to the HW structure
4834 * During S0 to Sx transition, it is possible the link remains at gig
4835 * instead of negotiating to a lower speed. Before going to Sx, set
4836 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4837 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4838 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4839 * needs to be written.
4840 * Parts that support (and are linked to a partner which support) EEE in
4841 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4842 * than 10Mbps w/o EEE.
4844 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4846 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4850 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4852 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4853 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4855 if (hw->phy.type == e1000_phy_i217) {
4856 u16 phy_reg, device_id = hw->device_id;
4858 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4859 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4860 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4861 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4862 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4864 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4865 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4868 ret_val = hw->phy.ops.acquire(hw);
4872 if (!dev_spec->eee_disable) {
4876 e1000_read_emi_reg_locked(hw,
4877 I217_EEE_ADVERTISEMENT,
4882 /* Disable LPLU if both link partners support 100BaseT
4883 * EEE and 100Full is advertised on both ends of the
4884 * link, and enable Auto Enable LPI since there will
4885 * be no driver to enable LPI while in Sx.
4887 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4888 (dev_spec->eee_lp_ability &
4889 I82579_EEE_100_SUPPORTED) &&
4890 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4891 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4892 E1000_PHY_CTRL_NOND0A_LPLU);
4894 /* Set Auto Enable LPI after link up */
4895 hw->phy.ops.read_reg_locked(hw,
4898 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4899 hw->phy.ops.write_reg_locked(hw,
4905 /* For i217 Intel Rapid Start Technology support,
4906 * when the system is going into Sx and no manageability engine
4907 * is present, the driver must configure proxy to reset only on
4908 * power good. LPI (Low Power Idle) state must also reset only
4909 * on power good, as well as the MTA (Multicast table array).
4910 * The SMBus release must also be disabled on LCD reset.
4912 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4913 E1000_ICH_FWSM_FW_VALID)) {
4914 /* Enable proxy to reset only on power good. */
4915 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4917 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4918 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4921 /* Set bit enable LPI (EEE) to reset only on
4924 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4925 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4926 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4928 /* Disable the SMB release on LCD reset. */
4929 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4930 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4931 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4934 /* Enable MTA to reset for Intel Rapid Start Technology
4937 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4938 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4939 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4942 hw->phy.ops.release(hw);
4945 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4947 if (hw->mac.type == e1000_ich8lan)
4948 e1000_gig_downshift_workaround_ich8lan(hw);
4950 if (hw->mac.type >= e1000_pchlan) {
4951 e1000_oem_bits_config_ich8lan(hw, false);
4953 /* Reset PHY to activate OEM bits on 82577/8 */
4954 if (hw->mac.type == e1000_pchlan)
4955 e1000_phy_hw_reset_generic(hw);
4957 ret_val = hw->phy.ops.acquire(hw);
4960 e1000_write_smbus_addr(hw);
4961 hw->phy.ops.release(hw);
4968 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4969 * @hw: pointer to the HW structure
4971 * During Sx to S0 transitions on non-managed devices or managed devices
4972 * on which PHY resets are not blocked, if the PHY registers cannot be
4973 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4975 * On i217, setup Intel Rapid Start Technology.
4977 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4981 DEBUGFUNC("e1000_resume_workarounds_pchlan");
4982 if (hw->mac.type < e1000_pch2lan)
4983 return E1000_SUCCESS;
4985 ret_val = e1000_init_phy_workarounds_pchlan(hw);
4987 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4991 /* For i217 Intel Rapid Start Technology support when the system
4992 * is transitioning from Sx and no manageability engine is present
4993 * configure SMBus to restore on reset, disable proxy, and enable
4994 * the reset on MTA (Multicast table array).
4996 if (hw->phy.type == e1000_phy_i217) {
4999 ret_val = hw->phy.ops.acquire(hw);
5001 DEBUGOUT("Failed to setup iRST\n");
5005 /* Clear Auto Enable LPI after link up */
5006 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5007 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5008 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5010 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5011 E1000_ICH_FWSM_FW_VALID)) {
5012 /* Restore clear on SMB if no manageability engine
5015 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5019 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5020 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5023 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5025 /* Enable reset on MTA */
5026 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5030 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5031 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5034 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5035 hw->phy.ops.release(hw);
5038 return E1000_SUCCESS;
5042 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5043 * @hw: pointer to the HW structure
5045 * Return the LED back to the default configuration.
5047 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5049 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5051 if (hw->phy.type == e1000_phy_ife)
5052 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5055 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5056 return E1000_SUCCESS;
5060 * e1000_led_on_ich8lan - Turn LEDs on
5061 * @hw: pointer to the HW structure
5065 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5067 DEBUGFUNC("e1000_led_on_ich8lan");
5069 if (hw->phy.type == e1000_phy_ife)
5070 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5071 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5073 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5074 return E1000_SUCCESS;
5078 * e1000_led_off_ich8lan - Turn LEDs off
5079 * @hw: pointer to the HW structure
5081 * Turn off the LEDs.
5083 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5085 DEBUGFUNC("e1000_led_off_ich8lan");
5087 if (hw->phy.type == e1000_phy_ife)
5088 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5089 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5091 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5092 return E1000_SUCCESS;
5096 * e1000_setup_led_pchlan - Configures SW controllable LED
5097 * @hw: pointer to the HW structure
5099 * This prepares the SW controllable LED for use.
5101 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5103 DEBUGFUNC("e1000_setup_led_pchlan");
5105 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5106 (u16)hw->mac.ledctl_mode1);
5110 * e1000_cleanup_led_pchlan - Restore the default LED operation
5111 * @hw: pointer to the HW structure
5113 * Return the LED back to the default configuration.
5115 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5117 DEBUGFUNC("e1000_cleanup_led_pchlan");
5119 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5120 (u16)hw->mac.ledctl_default);
5124 * e1000_led_on_pchlan - Turn LEDs on
5125 * @hw: pointer to the HW structure
5129 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5131 u16 data = (u16)hw->mac.ledctl_mode2;
5134 DEBUGFUNC("e1000_led_on_pchlan");
5136 /* If no link, then turn LED on by setting the invert bit
5137 * for each LED that's mode is "link_up" in ledctl_mode2.
5139 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5140 for (i = 0; i < 3; i++) {
5141 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5142 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5143 E1000_LEDCTL_MODE_LINK_UP)
5145 if (led & E1000_PHY_LED0_IVRT)
5146 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5148 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5152 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5156 * e1000_led_off_pchlan - Turn LEDs off
5157 * @hw: pointer to the HW structure
5159 * Turn off the LEDs.
5161 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5163 u16 data = (u16)hw->mac.ledctl_mode1;
5166 DEBUGFUNC("e1000_led_off_pchlan");
5168 /* If no link, then turn LED off by clearing the invert bit
5169 * for each LED that's mode is "link_up" in ledctl_mode1.
5171 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5172 for (i = 0; i < 3; i++) {
5173 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5174 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5175 E1000_LEDCTL_MODE_LINK_UP)
5177 if (led & E1000_PHY_LED0_IVRT)
5178 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5180 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5184 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5188 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5189 * @hw: pointer to the HW structure
5191 * Read appropriate register for the config done bit for completion status
5192 * and configure the PHY through s/w for EEPROM-less parts.
5194 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5195 * config done bit, so only an error is logged and continues. If we were
5196 * to return with error, EEPROM-less silicon would not be able to be reset
5199 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5201 s32 ret_val = E1000_SUCCESS;
5205 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5207 e1000_get_cfg_done_generic(hw);
5209 /* Wait for indication from h/w that it has completed basic config */
5210 if (hw->mac.type >= e1000_ich10lan) {
5211 e1000_lan_init_done_ich8lan(hw);
5213 ret_val = e1000_get_auto_rd_done_generic(hw);
5215 /* When auto config read does not complete, do not
5216 * return with an error. This can happen in situations
5217 * where there is no eeprom and prevents getting link.
5219 DEBUGOUT("Auto Read Done did not complete\n");
5220 ret_val = E1000_SUCCESS;
5224 /* Clear PHY Reset Asserted bit */
5225 status = E1000_READ_REG(hw, E1000_STATUS);
5226 if (status & E1000_STATUS_PHYRA)
5227 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5229 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5231 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5232 if (hw->mac.type <= e1000_ich9lan) {
5233 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5234 (hw->phy.type == e1000_phy_igp_3)) {
5235 e1000_phy_init_script_igp3(hw);
5238 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5239 /* Maybe we should do a basic PHY config */
5240 DEBUGOUT("EEPROM not present\n");
5241 ret_val = -E1000_ERR_CONFIG;
5249 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5250 * @hw: pointer to the HW structure
5252 * In the case of a PHY power down to save power, or to turn off link during a
5253 * driver unload, or wake on lan is not enabled, remove the link.
5255 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5257 /* If the management interface is not enabled, then power down */
5258 if (!(hw->mac.ops.check_mng_mode(hw) ||
5259 hw->phy.ops.check_reset_block(hw)))
5260 e1000_power_down_phy_copper(hw);
5266 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5267 * @hw: pointer to the HW structure
5269 * Clears hardware counters specific to the silicon family and calls
5270 * clear_hw_cntrs_generic to clear all general purpose counters.
5272 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5277 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5279 e1000_clear_hw_cntrs_base_generic(hw);
5281 E1000_READ_REG(hw, E1000_ALGNERRC);
5282 E1000_READ_REG(hw, E1000_RXERRC);
5283 E1000_READ_REG(hw, E1000_TNCRS);
5284 E1000_READ_REG(hw, E1000_CEXTERR);
5285 E1000_READ_REG(hw, E1000_TSCTC);
5286 E1000_READ_REG(hw, E1000_TSCTFC);
5288 E1000_READ_REG(hw, E1000_MGTPRC);
5289 E1000_READ_REG(hw, E1000_MGTPDC);
5290 E1000_READ_REG(hw, E1000_MGTPTC);
5292 E1000_READ_REG(hw, E1000_IAC);
5293 E1000_READ_REG(hw, E1000_ICRXOC);
5295 /* Clear PHY statistics registers */
5296 if ((hw->phy.type == e1000_phy_82578) ||
5297 (hw->phy.type == e1000_phy_82579) ||
5298 (hw->phy.type == e1000_phy_i217) ||
5299 (hw->phy.type == e1000_phy_82577)) {
5300 ret_val = hw->phy.ops.acquire(hw);
5303 ret_val = hw->phy.ops.set_page(hw,
5304 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5307 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5308 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5309 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5310 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5311 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5312 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5313 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5314 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5315 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5316 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5317 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5318 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5319 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5320 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5322 hw->phy.ops.release(hw);
5327 * e1000_configure_k0s_lpt - Configure K0s power state
5328 * @hw: pointer to the HW structure
5329 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
5330 * 0 corresponds to 128ns, each value over 0 doubles the duration.
5331 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
5332 * 0 corresponds to 128ns, each value over 0 doubles the duration.
5334 * Configure the K1 power state based on the provided parameter.
5335 * Assumes semaphore already acquired.
5337 * Success returns 0, Failure returns:
5338 * -E1000_ERR_PHY (-2) in case of access error
5339 * -E1000_ERR_PARAM (-4) in case of parameters error
5341 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
5346 DEBUGFUNC("e1000_configure_k0s_lpt");
5348 if (entry_latency > 3 || min_time > 4)
5349 return -E1000_ERR_PARAM;
5351 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5356 /* for now don't touch the latency */
5357 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
5358 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
5360 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5365 return E1000_SUCCESS;