drivers/net/e1000/base/e1000_ich8lan.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 /* 82562G 10/100 Network Connection
   6  * 82562G-2 10/100 Network Connection
   7  * 82562GT 10/100 Network Connection
   8  * 82562GT-2 10/100 Network Connection
   9  * 82562V 10/100 Network Connection
  10  * 82562V-2 10/100 Network Connection
  11  * 82566DC-2 Gigabit Network Connection
  12  * 82566DC Gigabit Network Connection
  13  * 82566DM-2 Gigabit Network Connection
  14  * 82566DM Gigabit Network Connection
  15  * 82566MC Gigabit Network Connection
  16  * 82566MM Gigabit Network Connection
  17  * 82567LM Gigabit Network Connection
  18  * 82567LF Gigabit Network Connection
  19  * 82567V Gigabit Network Connection
  20  * 82567LM-2 Gigabit Network Connection
  21  * 82567LF-2 Gigabit Network Connection
  22  * 82567V-2 Gigabit Network Connection
  23  * 82567LF-3 Gigabit Network Connection
  24  * 82567LM-3 Gigabit Network Connection
  25  * 82567LM-4 Gigabit Network Connection
  26  * 82577LM Gigabit Network Connection
  27  * 82577LC Gigabit Network Connection
  28  * 82578DM Gigabit Network Connection
  29  * 82578DC Gigabit Network Connection
  30  * 82579LM Gigabit Network Connection
  31  * 82579V Gigabit Network Connection
  32  * Ethernet Connection I217-LM
  33  * Ethernet Connection I217-V
  34  * Ethernet Connection I218-V
  35  * Ethernet Connection I218-LM
  36  * Ethernet Connection (2) I218-LM
  37  * Ethernet Connection (2) I218-V
  38  * Ethernet Connection (3) I218-LM
  39  * Ethernet Connection (3) I218-V
  40  */
  41
  42 #include "e1000_api.h"
  43
  44 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  45 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  46 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  47 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  48 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  49 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  50 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  51 STATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  52 STATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  53 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  54 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  55 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  56                                               u8 *mc_addr_list,
  57                                               u32 mc_addr_count);
  58 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  59 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  60 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  61 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  62 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  63                                             bool active);
  64 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  65                                             bool active);
  66 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  67                                    u16 words, u16 *data);
  68 STATIC s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
  69                                u16 *data);
  70 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  71                                     u16 words, u16 *data);
  72 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  73 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  74 STATIC s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
  75 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  76                                             u16 *data);
  77 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
  78 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
  79 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
  80 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
  81 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
  82 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
  83 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
  84 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
  85                                            u16 *speed, u16 *duplex);
  86 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
  87 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
  88 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
  90 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
  91 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
  92 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
  93 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
  94 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  95 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
  96 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  97 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
  98 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
  99                                           u32 offset, u8 *data);
 100 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 101                                           u8 size, u16 *data);
 102 STATIC s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 103                                             u32 *data);
 104 STATIC s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 105                                            u32 offset, u32 *data);
 106 STATIC s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 107                                              u32 offset, u32 data);
 108 STATIC s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 109                                                   u32 offset, u32 dword);
 110 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 111                                           u32 offset, u16 *data);
 112 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 113                                                  u32 offset, u8 byte);
 114 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 115 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 116 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 117 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 118 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 119 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 120
 121 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 122 /* Offset 04h HSFSTS */
 123 union ich8_hws_flash_status {
 124         struct ich8_hsfsts {
 125                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 126                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 127                 u16 dael:1; /* bit 2 Direct Access error Log */
 128                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 129                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 130                 u16 reserved1:2; /* bit 13:6 Reserved */
 131                 u16 reserved2:6; /* bit 13:6 Reserved */
 132                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 133                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 134         } hsf_status;
 135         u16 regval;
 136 };
 137
 138 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 139 /* Offset 06h FLCTL */
 140 union ich8_hws_flash_ctrl {
 141         struct ich8_hsflctl {
 142                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 143                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 144                 u16 reserved:5;   /* 7:3 Reserved  */
 145                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 146                 u16 flockdn:6;   /* 15:10 Reserved */
 147         } hsf_ctrl;
 148         u16 regval;
 149 };
 150
 151 /* ICH Flash Region Access Permissions */
 152 union ich8_hws_flash_regacc {
 153         struct ich8_flracc {
 154                 u32 grra:8; /* 0:7 GbE region Read Access */
 155                 u32 grwa:8; /* 8:15 GbE region Write Access */
 156                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 157                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 158         } hsf_flregacc;
 159         u16 regval;
 160 };
 161
 162 /**
 163  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 164  *  @hw: pointer to the HW structure
 165  *
 166  *  Test access to the PHY registers by reading the PHY ID registers.  If
 167  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 168  *  otherwise assume the read PHY ID is correct if it is valid.
 169  *
 170  *  Assumes the sw/fw/hw semaphore is already acquired.
 171  **/
 172 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 173 {
 174         u16 phy_reg = 0;
 175         u32 phy_id = 0;
 176         s32 ret_val = 0;
 177         u16 retry_count;
 178         u32 mac_reg = 0;
 179
 180         for (retry_count = 0; retry_count < 2; retry_count++) {
 181                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 182                 if (ret_val || (phy_reg == 0xFFFF))
 183                         continue;
 184                 phy_id = (u32)(phy_reg << 16);
 185
 186                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 187                 if (ret_val || (phy_reg == 0xFFFF)) {
 188                         phy_id = 0;
 189                         continue;
 190                 }
 191                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 192                 break;
 193         }
 194
 195         if (hw->phy.id) {
 196                 if  (hw->phy.id == phy_id)
 197                         goto out;
 198         } else if (phy_id) {
 199                 hw->phy.id = phy_id;
 200                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 201                 goto out;
 202         }
 203
 204         /* In case the PHY needs to be in mdio slow mode,
 205          * set slow mode and try to get the PHY id again.
 206          */
 207         if (hw->mac.type < e1000_pch_lpt) {
 208                 hw->phy.ops.release(hw);
 209                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 210                 if (!ret_val)
 211                         ret_val = e1000_get_phy_id(hw);
 212                 hw->phy.ops.acquire(hw);
 213         }
 214
 215         if (ret_val)
 216                 return false;
 217 out:
 218         if (hw->mac.type >= e1000_pch_lpt) {
 219                 /* Only unforce SMBus if ME is not active */
 220                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
 221                     E1000_ICH_FWSM_FW_VALID)) {
 222                         /* Unforce SMBus mode in PHY */
 223                         hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 224                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 225                         hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 226
 227                         /* Unforce SMBus mode in MAC */
 228                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 229                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 230                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 231                 }
 232         }
 233
 234         return true;
 235 }
 236
 237 /**
 238  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 239  *  @hw: pointer to the HW structure
 240  *
 241  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 242  *  used to reset the PHY to a quiescent state when necessary.
 243  **/
 244 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 245 {
 246         u32 mac_reg;
 247
 248         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 249
 250         /* Set Phy Config Counter to 50msec */
 251         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 252         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 253         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 254         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 255
 256         /* Toggle LANPHYPC Value bit */
 257         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 258         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 259         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 260         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 261         E1000_WRITE_FLUSH(hw);
 262         msec_delay(1);
 263         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 264         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 265         E1000_WRITE_FLUSH(hw);
 266
 267         if (hw->mac.type < e1000_pch_lpt) {
 268                 msec_delay(50);
 269         } else {
 270                 u16 count = 20;
 271
 272                 do {
 273                         msec_delay(5);
 274                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 275                            E1000_CTRL_EXT_LPCD) && count--);
 276
 277                 msec_delay(30);
 278         }
 279 }
 280
 281 /**
 282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  Workarounds/flow necessary for PHY initialization during driver load
 286  *  and resume paths.
 287  **/
 288 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 289 {
 290         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 291         s32 ret_val;
 292
 293         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 294
 295         /* Gate automatic PHY configuration by hardware on managed and
 296          * non-managed 82579 and newer adapters.
 297          */
 298         e1000_gate_hw_phy_config_ich8lan(hw, true);
 299
 300 #ifdef ULP_SUPPORT
 301         /* It is not possible to be certain of the current state of ULP
 302          * so forcibly disable it.
 303          */
 304         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 305
 306 #endif /* ULP_SUPPORT */
 307         ret_val = hw->phy.ops.acquire(hw);
 308         if (ret_val) {
 309                 DEBUGOUT("Failed to initialize PHY flow\n");
 310                 goto out;
 311         }
 312
 313         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 314          * inaccessible and resetting the PHY is not blocked, toggle the
 315          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 316          */
 317         switch (hw->mac.type) {
 318         case e1000_pch_lpt:
 319         case e1000_pch_spt:
 320         case e1000_pch_cnp:
 321                 if (e1000_phy_is_accessible_pchlan(hw))
 322                         break;
 323
 324                 /* Before toggling LANPHYPC, see if PHY is accessible by
 325                  * forcing MAC to SMBus mode first.
 326                  */
 327                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 328                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 329                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 330
 331                 /* Wait 50 milliseconds for MAC to finish any retries
 332                  * that it might be trying to perform from previous
 333                  * attempts to acknowledge any phy read requests.
 334                  */
 335                  msec_delay(50);
 336
 337                 /* fall-through */
 338         case e1000_pch2lan:
 339                 if (e1000_phy_is_accessible_pchlan(hw))
 340                         break;
 341
 342                 /* fall-through */
 343         case e1000_pchlan:
 344                 if ((hw->mac.type == e1000_pchlan) &&
 345                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 346                         break;
 347
 348                 if (hw->phy.ops.check_reset_block(hw)) {
 349                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 350                         ret_val = -E1000_ERR_PHY;
 351                         break;
 352                 }
 353
 354                 /* Toggle LANPHYPC Value bit */
 355                 e1000_toggle_lanphypc_pch_lpt(hw);
 356                 if (hw->mac.type >= e1000_pch_lpt) {
 357                         if (e1000_phy_is_accessible_pchlan(hw))
 358                                 break;
 359
 360                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 361                          * so ensure that the MAC is also out of SMBus mode
 362                          */
 363                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 364                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 365                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 366
 367                         if (e1000_phy_is_accessible_pchlan(hw))
 368                                 break;
 369
 370                         ret_val = -E1000_ERR_PHY;
 371                 }
 372                 break;
 373         default:
 374                 break;
 375         }
 376
 377         hw->phy.ops.release(hw);
 378         if (!ret_val) {
 379
 380                 /* Check to see if able to reset PHY.  Print error if not */
 381                 if (hw->phy.ops.check_reset_block(hw)) {
 382                         ERROR_REPORT("Reset blocked by ME\n");
 383                         goto out;
 384                 }
 385
 386                 /* Reset the PHY before any access to it.  Doing so, ensures
 387                  * that the PHY is in a known good state before we read/write
 388                  * PHY registers.  The generic reset is sufficient here,
 389                  * because we haven't determined the PHY type yet.
 390                  */
 391                 ret_val = e1000_phy_hw_reset_generic(hw);
 392                 if (ret_val)
 393                         goto out;
 394
 395                 /* On a successful reset, possibly need to wait for the PHY
 396                  * to quiesce to an accessible state before returning control
 397                  * to the calling function.  If the PHY does not quiesce, then
 398                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 399                  *  the PHY is in.
 400                  */
 401                 ret_val = hw->phy.ops.check_reset_block(hw);
 402                 if (ret_val)
 403                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 404         }
 405
 406 out:
 407         /* Ungate automatic PHY configuration on non-managed 82579 */
 408         if ((hw->mac.type == e1000_pch2lan) &&
 409             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 410                 msec_delay(10);
 411                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 412         }
 413
 414         return ret_val;
 415 }
 416
 417 /**
 418  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 419  *  @hw: pointer to the HW structure
 420  *
 421  *  Initialize family-specific PHY parameters and function pointers.
 422  **/
 423 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 424 {
 425         struct e1000_phy_info *phy = &hw->phy;
 426         s32 ret_val;
 427
 428         DEBUGFUNC("e1000_init_phy_params_pchlan");
 429
 430         phy->addr               = 1;
 431         phy->reset_delay_us     = 100;
 432
 433         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 434         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 435         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 436         phy->ops.set_page       = e1000_set_page_igp;
 437         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 438         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 439         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 440         phy->ops.release        = e1000_release_swflag_ich8lan;
 441         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 442         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 443         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 444         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 445         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 446         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 447         phy->ops.power_up       = e1000_power_up_phy_copper;
 448         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 449         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 450
 451         phy->id = e1000_phy_unknown;
 452
 453         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 454         if (ret_val)
 455                 return ret_val;
 456
 457         if (phy->id == e1000_phy_unknown)
 458                 switch (hw->mac.type) {
 459                 default:
 460                         ret_val = e1000_get_phy_id(hw);
 461                         if (ret_val)
 462                                 return ret_val;
 463                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 464                                 break;
 465                         /* fall-through */
 466                 case e1000_pch2lan:
 467                 case e1000_pch_lpt:
 468                 case e1000_pch_spt:
 469                 case e1000_pch_cnp:
 470                         /* In case the PHY needs to be in mdio slow mode,
 471                          * set slow mode and try to get the PHY id again.
 472                          */
 473                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 474                         if (ret_val)
 475                                 return ret_val;
 476                         ret_val = e1000_get_phy_id(hw);
 477                         if (ret_val)
 478                                 return ret_val;
 479                         break;
 480                 }
 481         phy->type = e1000_get_phy_type_from_id(phy->id);
 482
 483         switch (phy->type) {
 484         case e1000_phy_82577:
 485         case e1000_phy_82579:
 486         case e1000_phy_i217:
 487                 phy->ops.check_polarity = e1000_check_polarity_82577;
 488                 phy->ops.force_speed_duplex =
 489                         e1000_phy_force_speed_duplex_82577;
 490                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 491                 phy->ops.get_info = e1000_get_phy_info_82577;
 492                 phy->ops.commit = e1000_phy_sw_reset_generic;
 493                 break;
 494         case e1000_phy_82578:
 495                 phy->ops.check_polarity = e1000_check_polarity_m88;
 496                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 497                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 498                 phy->ops.get_info = e1000_get_phy_info_m88;
 499                 break;
 500         default:
 501                 ret_val = -E1000_ERR_PHY;
 502                 break;
 503         }
 504
 505         return ret_val;
 506 }
 507
 508 /**
 509  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 510  *  @hw: pointer to the HW structure
 511  *
 512  *  Initialize family-specific PHY parameters and function pointers.
 513  **/
 514 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 515 {
 516         struct e1000_phy_info *phy = &hw->phy;
 517         s32 ret_val;
 518         u16 i = 0;
 519
 520         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 521
 522         phy->addr               = 1;
 523         phy->reset_delay_us     = 100;
 524
 525         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 526         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 527         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 528         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 529         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 530         phy->ops.release        = e1000_release_swflag_ich8lan;
 531         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 532         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 533         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 534         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 535         phy->ops.power_up       = e1000_power_up_phy_copper;
 536         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 537
 538         /* We may need to do this twice - once for IGP and if that fails,
 539          * we'll set BM func pointers and try again
 540          */
 541         ret_val = e1000_determine_phy_address(hw);
 542         if (ret_val) {
 543                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 544                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 545                 ret_val = e1000_determine_phy_address(hw);
 546                 if (ret_val) {
 547                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 548                         return ret_val;
 549                 }
 550         }
 551
 552         phy->id = 0;
 553         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 554                (i++ < 100)) {
 555                 msec_delay(1);
 556                 ret_val = e1000_get_phy_id(hw);
 557                 if (ret_val)
 558                         return ret_val;
 559         }
 560
 561         /* Verify phy id */
 562         switch (phy->id) {
 563         case IGP03E1000_E_PHY_ID:
 564                 phy->type = e1000_phy_igp_3;
 565                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 566                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 567                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 568                 phy->ops.get_info = e1000_get_phy_info_igp;
 569                 phy->ops.check_polarity = e1000_check_polarity_igp;
 570                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 571                 break;
 572         case IFE_E_PHY_ID:
 573         case IFE_PLUS_E_PHY_ID:
 574         case IFE_C_E_PHY_ID:
 575                 phy->type = e1000_phy_ife;
 576                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 577                 phy->ops.get_info = e1000_get_phy_info_ife;
 578                 phy->ops.check_polarity = e1000_check_polarity_ife;
 579                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 580                 break;
 581         case BME1000_E_PHY_ID:
 582                 phy->type = e1000_phy_bm;
 583                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 584                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 585                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 586                 phy->ops.commit = e1000_phy_sw_reset_generic;
 587                 phy->ops.get_info = e1000_get_phy_info_m88;
 588                 phy->ops.check_polarity = e1000_check_polarity_m88;
 589                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 590                 break;
 591         default:
 592                 return -E1000_ERR_PHY;
 593                 break;
 594         }
 595
 596         return E1000_SUCCESS;
 597 }
 598
 599 /**
 600  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 601  *  @hw: pointer to the HW structure
 602  *
 603  *  Initialize family-specific NVM parameters and function
 604  *  pointers.
 605  **/
 606 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 607 {
 608         struct e1000_nvm_info *nvm = &hw->nvm;
 609         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 610         u32 gfpreg, sector_base_addr, sector_end_addr;
 611         u16 i;
 612         u32 nvm_size;
 613
 614         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 615
 616         nvm->type = e1000_nvm_flash_sw;
 617
 618         if (hw->mac.type >= e1000_pch_spt) {
 619                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 620                  * STRAP register. This is because in SPT the GbE Flash region
 621                  * is no longer accessed through the flash registers. Instead,
 622                  * the mechanism has changed, and the Flash region access
 623                  * registers are now implemented in GbE memory space.
 624                  */
 625                 nvm->flash_base_addr = 0;
 626                 nvm_size =
 627                     (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
 628                     * NVM_SIZE_MULTIPLIER;
 629                 nvm->flash_bank_size = nvm_size / 2;
 630                 /* Adjust to word count */
 631                 nvm->flash_bank_size /= sizeof(u16);
 632                 /* Set the base address for flash register access */
 633                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 634         } else {
 635                 /* Can't read flash registers if register set isn't mapped. */
 636                 if (!hw->flash_address) {
 637                         DEBUGOUT("ERROR: Flash registers not mapped\n");
 638                         return -E1000_ERR_CONFIG;
 639                 }
 640
 641                 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 642
 643                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 644                  * Add 1 to sector_end_addr since this sector is included in
 645                  * the overall size.
 646                  */
 647                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 648                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 649
 650                 /* flash_base_addr is byte-aligned */
 651                 nvm->flash_base_addr = sector_base_addr
 652                                        << FLASH_SECTOR_ADDR_SHIFT;
 653
 654                 /* find total size of the NVM, then cut in half since the total
 655                  * size represents two separate NVM banks.
 656                  */
 657                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 658                                         << FLASH_SECTOR_ADDR_SHIFT);
 659                 nvm->flash_bank_size /= 2;
 660                 /* Adjust to word count */
 661                 nvm->flash_bank_size /= sizeof(u16);
 662         }
 663
 664         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 665
 666         /* Clear shadow ram */
 667         for (i = 0; i < nvm->word_size; i++) {
 668                 dev_spec->shadow_ram[i].modified = false;
 669                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 670         }
 671
 672         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 673         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 674
 675         /* Function Pointers */
 676         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 677         nvm->ops.release        = e1000_release_nvm_ich8lan;
 678         if (hw->mac.type >= e1000_pch_spt) {
 679                 nvm->ops.read   = e1000_read_nvm_spt;
 680                 nvm->ops.update = e1000_update_nvm_checksum_spt;
 681         } else {
 682                 nvm->ops.read   = e1000_read_nvm_ich8lan;
 683                 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
 684         }
 685         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 686         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 687         nvm->ops.write          = e1000_write_nvm_ich8lan;
 688
 689         return E1000_SUCCESS;
 690 }
 691
 692 /**
 693  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 694  *  @hw: pointer to the HW structure
 695  *
 696  *  Initialize family-specific MAC parameters and function
 697  *  pointers.
 698  **/
 699 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 700 {
 701         struct e1000_mac_info *mac = &hw->mac;
 702 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 703         u16 pci_cfg;
 704 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 705
 706         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 707
 708         /* Set media type function pointer */
 709         hw->phy.media_type = e1000_media_type_copper;
 710
 711         /* Set mta register count */
 712         mac->mta_reg_count = 32;
 713         /* Set rar entry count */
 714         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 715         if (mac->type == e1000_ich8lan)
 716                 mac->rar_entry_count--;
 717         /* Set if part includes ASF firmware */
 718         mac->asf_firmware_present = true;
 719         /* FWSM register */
 720         mac->has_fwsm = true;
 721         /* ARC subsystem not supported */
 722         mac->arc_subsystem_valid = false;
 723         /* Adaptive IFS supported */
 724         mac->adaptive_ifs = true;
 725
 726         /* Function pointers */
 727
 728         /* bus type/speed/width */
 729         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 730         /* function id */
 731         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 732         /* reset */
 733         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 734         /* hw initialization */
 735         mac->ops.init_hw = e1000_init_hw_ich8lan;
 736         /* link setup */
 737         mac->ops.setup_link = e1000_setup_link_ich8lan;
 738         /* physical interface setup */
 739         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 740         /* check for link */
 741         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 742         /* link info */
 743         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 744         /* multicast address update */
 745         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 746         /* clear hardware counters */
 747         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 748
 749         /* LED and other operations */
 750         switch (mac->type) {
 751         case e1000_ich8lan:
 752         case e1000_ich9lan:
 753         case e1000_ich10lan:
 754                 /* check management mode */
 755                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 756                 /* ID LED init */
 757                 mac->ops.id_led_init = e1000_id_led_init_generic;
 758                 /* blink LED */
 759                 mac->ops.blink_led = e1000_blink_led_generic;
 760                 /* setup LED */
 761                 mac->ops.setup_led = e1000_setup_led_generic;
 762                 /* cleanup LED */
 763                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 764                 /* turn on/off LED */
 765                 mac->ops.led_on = e1000_led_on_ich8lan;
 766                 mac->ops.led_off = e1000_led_off_ich8lan;
 767                 break;
 768         case e1000_pch2lan:
 769                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 770                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 771                 /* fall-through */
 772         case e1000_pch_lpt:
 773         case e1000_pch_spt:
 774         case e1000_pch_cnp:
 775 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 776                 /* multicast address update for pch2 */
 777                 mac->ops.update_mc_addr_list =
 778                         e1000_update_mc_addr_list_pch2lan;
 779                 /* fall-through */
 780 #endif
 781         case e1000_pchlan:
 782 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 783                 /* save PCH revision_id */
 784                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 785                 /* SPT uses full byte for revision ID,
 786                  * as opposed to previous generations
 787                  */
 788                 if (hw->mac.type >= e1000_pch_spt)
 789                         hw->revision_id = (u8)(pci_cfg &= 0x00FF);
 790                 else
 791                         hw->revision_id = (u8)(pci_cfg &= 0x000F);
 792 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 793                 /* check management mode */
 794                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 795                 /* ID LED init */
 796                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 797                 /* setup LED */
 798                 mac->ops.setup_led = e1000_setup_led_pchlan;
 799                 /* cleanup LED */
 800                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 801                 /* turn on/off LED */
 802                 mac->ops.led_on = e1000_led_on_pchlan;
 803                 mac->ops.led_off = e1000_led_off_pchlan;
 804                 break;
 805         default:
 806                 break;
 807         }
 808
 809         if (mac->type >= e1000_pch_lpt) {
 810                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 811                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 812                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 813         }
 814
 815         /* Enable PCS Lock-loss workaround for ICH8 */
 816         if (mac->type == e1000_ich8lan)
 817                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 818
 819         return E1000_SUCCESS;
 820 }
 821
 822 /**
 823  *  __e1000_access_emi_reg_locked - Read/write EMI register
 824  *  @hw: pointer to the HW structure
 825  *  @address: EMI address to program
 826  *  @data: pointer to value to read/write from/to the EMI address
 827  *  @read: boolean flag to indicate read or write
 828  *
 829  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 830  **/
 831 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 832                                          u16 *data, bool read)
 833 {
 834         s32 ret_val;
 835
 836         DEBUGFUNC("__e1000_access_emi_reg_locked");
 837
 838         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 839         if (ret_val)
 840                 return ret_val;
 841
 842         if (read)
 843                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 844                                                       data);
 845         else
 846                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 847                                                        *data);
 848
 849         return ret_val;
 850 }
 851
 852 /**
 853  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 854  *  @hw: pointer to the HW structure
 855  *  @addr: EMI address to program
 856  *  @data: value to be read from the EMI address
 857  *
 858  *  Assumes the SW/FW/HW Semaphore is already acquired.
 859  **/
 860 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 861 {
 862         DEBUGFUNC("e1000_read_emi_reg_locked");
 863
 864         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 865 }
 866
 867 /**
 868  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 869  *  @hw: pointer to the HW structure
 870  *  @addr: EMI address to program
 871  *  @data: value to be written to the EMI address
 872  *
 873  *  Assumes the SW/FW/HW Semaphore is already acquired.
 874  **/
 875 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 876 {
 877         DEBUGFUNC("e1000_read_emi_reg_locked");
 878
 879         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 880 }
 881
 882 /**
 883  *  e1000_set_eee_pchlan - Enable/disable EEE support
 884  *  @hw: pointer to the HW structure
 885  *
 886  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 887  *  the link and the EEE capabilities of the link partner.  The LPI Control
 888  *  register bits will remain set only if/when link is up.
 889  *
 890  *  EEE LPI must not be asserted earlier than one second after link is up.
 891  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 892  *  can be link issues with some switches.  Other devices can have EEE LPI
 893  *  enabled immediately upon link up since they have a timer in hardware which
 894  *  prevents LPI from being asserted too early.
 895  **/
 896 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 897 {
 898         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 899         s32 ret_val;
 900         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 901
 902         DEBUGFUNC("e1000_set_eee_pchlan");
 903
 904         switch (hw->phy.type) {
 905         case e1000_phy_82579:
 906                 lpa = I82579_EEE_LP_ABILITY;
 907                 pcs_status = I82579_EEE_PCS_STATUS;
 908                 adv_addr = I82579_EEE_ADVERTISEMENT;
 909                 break;
 910         case e1000_phy_i217:
 911                 lpa = I217_EEE_LP_ABILITY;
 912                 pcs_status = I217_EEE_PCS_STATUS;
 913                 adv_addr = I217_EEE_ADVERTISEMENT;
 914                 break;
 915         default:
 916                 return E1000_SUCCESS;
 917         }
 918
 919         ret_val = hw->phy.ops.acquire(hw);
 920         if (ret_val)
 921                 return ret_val;
 922
 923         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 924         if (ret_val)
 925                 goto release;
 926
 927         /* Clear bits that enable EEE in various speeds */
 928         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 929
 930         /* Enable EEE if not disabled by user */
 931         if (!dev_spec->eee_disable) {
 932                 /* Save off link partner's EEE ability */
 933                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 934                                                     &dev_spec->eee_lp_ability);
 935                 if (ret_val)
 936                         goto release;
 937
 938                 /* Read EEE advertisement */
 939                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 940                 if (ret_val)
 941                         goto release;
 942
 943                 /* Enable EEE only for speeds in which the link partner is
 944                  * EEE capable and for which we advertise EEE.
 945                  */
 946                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 947                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 948
 949                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 950                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 951                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 952                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 953                         else
 954                                 /* EEE is not supported in 100Half, so ignore
 955                                  * partner's EEE in 100 ability if full-duplex
 956                                  * is not advertised.
 957                                  */
 958                                 dev_spec->eee_lp_ability &=
 959                                     ~I82579_EEE_100_SUPPORTED;
 960                 }
 961         }
 962
 963         if (hw->phy.type == e1000_phy_82579) {
 964                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 965                                                     &data);
 966                 if (ret_val)
 967                         goto release;
 968
 969                 data &= ~I82579_LPI_100_PLL_SHUT;
 970                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 971                                                      data);
 972         }
 973
 974         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 975         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 976         if (ret_val)
 977                 goto release;
 978
 979         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 980 release:
 981         hw->phy.ops.release(hw);
 982
 983         return ret_val;
 984 }
 985
 986 /**
 987  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 988  *  @hw:   pointer to the HW structure
 989  *  @link: link up bool flag
 990  *
 991  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 992  *  preventing further DMA write requests.  Workaround the issue by disabling
 993  *  the de-assertion of the clock request when in 1Gpbs mode.
 994  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 995  *  speeds in order to avoid Tx hangs.
 996  **/
 997 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 998 {
 999         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1000         u32 status = E1000_READ_REG(hw, E1000_STATUS);
1001         s32 ret_val = E1000_SUCCESS;
1002         u16 reg;
1003
1004         if (link && (status & E1000_STATUS_SPEED_1000)) {
1005                 ret_val = hw->phy.ops.acquire(hw);
1006                 if (ret_val)
1007                         return ret_val;
1008
1009                 ret_val =
1010                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1011                                                &reg);
1012                 if (ret_val)
1013                         goto release;
1014
1015                 ret_val =
1016                     e1000_write_kmrn_reg_locked(hw,
1017                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1018                                                 reg &
1019                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1020                 if (ret_val)
1021                         goto release;
1022
1023                 usec_delay(10);
1024
1025                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1026                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1027
1028                 ret_val =
1029                     e1000_write_kmrn_reg_locked(hw,
1030                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1031                                                 reg);
1032 release:
1033                 hw->phy.ops.release(hw);
1034         } else {
1035                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1036                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1037
1038                 if ((hw->phy.revision > 5) || !link ||
1039                     ((status & E1000_STATUS_SPEED_100) &&
1040                      (status & E1000_STATUS_FD)))
1041                         goto update_fextnvm6;
1042
1043                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1044                 if (ret_val)
1045                         return ret_val;
1046
1047                 /* Clear link status transmit timeout */
1048                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1049
1050                 if (status & E1000_STATUS_SPEED_100) {
1051                         /* Set inband Tx timeout to 5x10us for 100Half */
1052                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1053
1054                         /* Do not extend the K1 entry latency for 100Half */
1055                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1056                 } else {
1057                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1058                         reg |= 50 <<
1059                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1060
1061                         /* Extend the K1 entry latency for 10 Mbps */
1062                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1063                 }
1064
1065                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1066                 if (ret_val)
1067                         return ret_val;
1068
1069 update_fextnvm6:
1070                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1071         }
1072
1073         return ret_val;
1074 }
1075
1076 #ifdef ULP_SUPPORT
1077 /**
1078  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1079  *  @hw: pointer to the HW structure
1080  *  @to_sx: boolean indicating a system power state transition to Sx
1081  *
1082  *  When link is down, configure ULP mode to significantly reduce the power
1083  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1084  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1085  *  system, configure the ULP mode by software.
1086  */
1087 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1088 {
1089         u32 mac_reg;
1090         s32 ret_val = E1000_SUCCESS;
1091         u16 phy_reg;
1092         u16 oem_reg = 0;
1093
1094         if ((hw->mac.type < e1000_pch_lpt) ||
1095             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1096             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1097             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1098             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1099             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1100                 return 0;
1101
1102         if (!to_sx) {
1103                 int i = 0;
1104                 /* Poll up to 5 seconds for Cable Disconnected indication */
1105                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1106                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1107                         /* Bail if link is re-acquired */
1108                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1109                                 return -E1000_ERR_PHY;
1110                         if (i++ == 100)
1111                                 break;
1112
1113                         msec_delay(50);
1114                 }
1115                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1116                           (E1000_READ_REG(hw, E1000_FEXT) &
1117                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1118                           i * 50);
1119                 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1120                     E1000_FEXT_PHY_CABLE_DISCONNECTED))
1121                         return 0;
1122         }
1123
1124         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1125                 /* Request ME configure ULP mode in the PHY */
1126                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1127                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1128                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1129
1130                 goto out;
1131         }
1132
1133         ret_val = hw->phy.ops.acquire(hw);
1134         if (ret_val)
1135                 goto out;
1136
1137         /* During S0 Idle keep the phy in PCI-E mode */
1138         if (hw->dev_spec.ich8lan.smbus_disable)
1139                 goto skip_smbus;
1140
1141         /* Force SMBus mode in PHY */
1142         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1143         if (ret_val)
1144                 goto release;
1145         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1146         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1147
1148         /* Force SMBus mode in MAC */
1149         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1150         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1151         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1152
1153         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1154          * LPLU and disable Gig speed when entering ULP
1155          */
1156         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1157                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1158                                                        &oem_reg);
1159                 if (ret_val)
1160                         goto release;
1161
1162                 phy_reg = oem_reg;
1163                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1164
1165                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1166                                                         phy_reg);
1167
1168                 if (ret_val)
1169                         goto release;
1170         }
1171
1172 skip_smbus:
1173         if (!to_sx) {
1174                 /* Change the 'Link Status Change' interrupt to trigger
1175                  * on 'Cable Status Change'
1176                  */
1177                 ret_val = e1000_read_kmrn_reg_locked(hw,
1178                                                      E1000_KMRNCTRLSTA_OP_MODES,
1179                                                      &phy_reg);
1180                 if (ret_val)
1181                         goto release;
1182                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1183                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1184                                             phy_reg);
1185         }
1186
1187         /* Set Inband ULP Exit, Reset to SMBus mode and
1188          * Disable SMBus Release on PERST# in PHY
1189          */
1190         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1191         if (ret_val)
1192                 goto release;
1193         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1194                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1195         if (to_sx) {
1196                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1197                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1198                 else
1199                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1200
1201                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1202                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1203         } else {
1204                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1205                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1206                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1207         }
1208         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1209
1210         /* Set Disable SMBus Release on PERST# in MAC */
1211         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1212         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1213         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1214
1215         /* Commit ULP changes in PHY by starting auto ULP configuration */
1216         phy_reg |= I218_ULP_CONFIG1_START;
1217         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1218
1219         if (!to_sx) {
1220                 /* Disable Tx so that the MAC doesn't send any (buffered)
1221                  * packets to the PHY.
1222                  */
1223                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1224                 mac_reg &= ~E1000_TCTL_EN;
1225                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1226         }
1227
1228         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1229             to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1230                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1231                                                         oem_reg);
1232                 if (ret_val)
1233                         goto release;
1234         }
1235
1236 release:
1237         hw->phy.ops.release(hw);
1238 out:
1239         if (ret_val)
1240                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1241         else
1242                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1243
1244         return ret_val;
1245 }
1246
1247 /**
1248  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1249  *  @hw: pointer to the HW structure
1250  *  @force: boolean indicating whether or not to force disabling ULP
1251  *
1252  *  Un-configure ULP mode when link is up, the system is transitioned from
1253  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1254  *  system, poll for an indication from ME that ULP has been un-configured.
1255  *  If not on an ME enabled system, un-configure the ULP mode by software.
1256  *
1257  *  During nominal operation, this function is called when link is acquired
1258  *  to disable ULP mode (force=false); otherwise, for example when unloading
1259  *  the driver or during Sx->S0 transitions, this is called with force=true
1260  *  to forcibly disable ULP.
1261
1262  *  When the cable is plugged in while the device is in D0, a Cable Status
1263  *  Change interrupt is generated which causes this function to be called
1264  *  to partially disable ULP mode and restart autonegotiation.  This function
1265  *  is then called again due to the resulting Link Status Change interrupt
1266  *  to finish cleaning up after the ULP flow.
1267  */
1268 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1269 {
1270         s32 ret_val = E1000_SUCCESS;
1271         u8 ulp_exit_timeout = 30;
1272         u32 mac_reg;
1273         u16 phy_reg;
1274         int i = 0;
1275
1276         if ((hw->mac.type < e1000_pch_lpt) ||
1277             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1278             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1279             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1280             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1281             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1282                 return 0;
1283
1284         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1285                 if (force) {
1286                         /* Request ME un-configure ULP mode in the PHY */
1287                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1288                         mac_reg &= ~E1000_H2ME_ULP;
1289                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1290                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1291                 }
1292
1293                 if (hw->mac.type == e1000_pch_cnp)
1294                         ulp_exit_timeout = 100;
1295
1296                 while (E1000_READ_REG(hw, E1000_FWSM) &
1297                        E1000_FWSM_ULP_CFG_DONE) {
1298                         if (i++ == ulp_exit_timeout) {
1299                                 ret_val = -E1000_ERR_PHY;
1300                                 goto out;
1301                         }
1302
1303                         msec_delay(10);
1304                 }
1305                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1306
1307                 if (force) {
1308                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1309                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1310                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1311                 } else {
1312                         /* Clear H2ME.ULP after ME ULP configuration */
1313                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1314                         mac_reg &= ~E1000_H2ME_ULP;
1315                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1316
1317                         /* Restore link speed advertisements and restart
1318                          * Auto-negotiation
1319                          */
1320                         if (hw->mac.autoneg) {
1321                                 ret_val = e1000_phy_setup_autoneg(hw);
1322                                 if (ret_val)
1323                                         goto out;
1324                         } else {
1325                                 ret_val = e1000_setup_copper_link_generic(hw);
1326                                 if (ret_val)
1327                                         goto out;
1328                         }
1329                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1330                 }
1331
1332                 goto out;
1333         }
1334
1335         ret_val = hw->phy.ops.acquire(hw);
1336         if (ret_val)
1337                 goto out;
1338
1339         /* Revert the change to the 'Link Status Change'
1340          * interrupt to trigger on 'Cable Status Change'
1341          */
1342         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1343                                              &phy_reg);
1344         if (ret_val)
1345                 goto release;
1346         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1347         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1348
1349         if (force)
1350                 /* Toggle LANPHYPC Value bit */
1351                 e1000_toggle_lanphypc_pch_lpt(hw);
1352
1353         /* Unforce SMBus mode in PHY */
1354         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1355         if (ret_val) {
1356                 /* The MAC might be in PCIe mode, so temporarily force to
1357                  * SMBus mode in order to access the PHY.
1358                  */
1359                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1360                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1361                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1362
1363                 msec_delay(50);
1364
1365                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1366                                                        &phy_reg);
1367                 if (ret_val)
1368                         goto release;
1369         }
1370         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1371         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1372
1373         /* Unforce SMBus mode in MAC */
1374         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1375         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1376         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1377
1378         /* When ULP mode was previously entered, K1 was disabled by the
1379          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1380          */
1381         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1382         if (ret_val)
1383                 goto release;
1384         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1385         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1386
1387         /* Clear ULP enabled configuration */
1388         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1389         if (ret_val)
1390                 goto release;
1391         /* CSC interrupt received due to ULP Indication */
1392         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1393                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1394                              I218_ULP_CONFIG1_STICKY_ULP |
1395                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1396                              I218_ULP_CONFIG1_WOL_HOST |
1397                              I218_ULP_CONFIG1_INBAND_EXIT |
1398                              I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1399                              I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1400                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1401                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1402
1403                 /* Commit ULP changes by starting auto ULP configuration */
1404                 phy_reg |= I218_ULP_CONFIG1_START;
1405                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1406
1407                 /* Clear Disable SMBus Release on PERST# in MAC */
1408                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1409                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1410                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1411
1412                 if (!force) {
1413                         hw->phy.ops.release(hw);
1414
1415                         if (hw->mac.autoneg)
1416                                 e1000_phy_setup_autoneg(hw);
1417                         else
1418                                 e1000_setup_copper_link_generic(hw);
1419
1420                         e1000_sw_lcd_config_ich8lan(hw);
1421
1422                         e1000_oem_bits_config_ich8lan(hw, true);
1423
1424                         /* Set ULP state to unknown and return non-zero to
1425                          * indicate no link (yet) and re-enter on the next LSC
1426                          * to finish disabling ULP flow.
1427                          */
1428                         hw->dev_spec.ich8lan.ulp_state =
1429                             e1000_ulp_state_unknown;
1430
1431                         return 1;
1432                 }
1433         }
1434
1435         /* Re-enable Tx */
1436         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1437         mac_reg |= E1000_TCTL_EN;
1438         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1439
1440 release:
1441         hw->phy.ops.release(hw);
1442         if (force) {
1443                 hw->phy.ops.reset(hw);
1444                 msec_delay(50);
1445         }
1446 out:
1447         if (ret_val)
1448                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1449         else
1450                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1451
1452         return ret_val;
1453 }
1454
1455 #endif /* ULP_SUPPORT */
1456
1457
1458 /**
1459  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1460  *  @hw: pointer to the HW structure
1461  *
1462  *  Checks to see of the link status of the hardware has changed.  If a
1463  *  change in link status has been detected, then we read the PHY registers
1464  *  to get the current speed/duplex if link exists.
1465  **/
1466 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1467 {
1468         struct e1000_mac_info *mac = &hw->mac;
1469         s32 ret_val, tipg_reg = 0;
1470         u16 emi_addr, emi_val = 0;
1471         bool link = false;
1472         u16 phy_reg;
1473
1474         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1475
1476         /* We only want to go out to the PHY registers to see if Auto-Neg
1477          * has completed and/or if our link status has changed.  The
1478          * get_link_status flag is set upon receiving a Link Status
1479          * Change or Rx Sequence Error interrupt.
1480          */
1481         if (!mac->get_link_status)
1482                 return E1000_SUCCESS;
1483
1484         if ((hw->mac.type < e1000_pch_lpt) ||
1485             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1486             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1487                 /* First we want to see if the MII Status Register reports
1488                  * link.  If so, then we want to get the current speed/duplex
1489                  * of the PHY.
1490                  */
1491                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1492                 if (ret_val)
1493                         return ret_val;
1494         } else {
1495                 /* Check the MAC's STATUS register to determine link state
1496                  * since the PHY could be inaccessible while in ULP mode.
1497                  */
1498                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1499                 if (link)
1500                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1501                 else
1502                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1503                 if (ret_val)
1504                         return ret_val;
1505         }
1506
1507         if (hw->mac.type == e1000_pchlan) {
1508                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1509                 if (ret_val)
1510                         return ret_val;
1511         }
1512
1513         /* When connected at 10Mbps half-duplex, some parts are excessively
1514          * aggressive resulting in many collisions. To avoid this, increase
1515          * the IPG and reduce Rx latency in the PHY.
1516          */
1517         if ((hw->mac.type >= e1000_pch2lan) && link) {
1518                 u16 speed, duplex;
1519
1520                 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1521                 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1522                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1523
1524                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1525                         tipg_reg |= 0xFF;
1526                         /* Reduce Rx latency in analog PHY */
1527                         emi_val = 0;
1528                 } else if (hw->mac.type >= e1000_pch_spt &&
1529                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1530                         tipg_reg |= 0xC;
1531                         emi_val = 1;
1532                 } else {
1533                         /* Roll back the default values */
1534                         tipg_reg |= 0x08;
1535                         emi_val = 1;
1536                 }
1537
1538                 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1539
1540                 ret_val = hw->phy.ops.acquire(hw);
1541                 if (ret_val)
1542                         return ret_val;
1543
1544                 if (hw->mac.type == e1000_pch2lan)
1545                         emi_addr = I82579_RX_CONFIG;
1546                 else
1547                         emi_addr = I217_RX_CONFIG;
1548                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1549
1550
1551                 if (hw->mac.type >= e1000_pch_lpt) {
1552                         hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1553                                                     &phy_reg);
1554                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1555                         if (speed == SPEED_100 || speed == SPEED_10)
1556                                 phy_reg |= 0x3E8;
1557                         else
1558                                 phy_reg |= 0xFA;
1559                         hw->phy.ops.write_reg_locked(hw,
1560                                                      I217_PLL_CLOCK_GATE_REG,
1561                                                      phy_reg);
1562
1563                         if (speed == SPEED_1000) {
1564                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1565                                                             &phy_reg);
1566
1567                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1568
1569                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1570                                                              phy_reg);
1571                                 }
1572                  }
1573                 hw->phy.ops.release(hw);
1574
1575                 if (ret_val)
1576                         return ret_val;
1577
1578                 if (hw->mac.type >= e1000_pch_spt) {
1579                         u16 data;
1580                         u16 ptr_gap;
1581
1582                         if (speed == SPEED_1000) {
1583                                 ret_val = hw->phy.ops.acquire(hw);
1584                                 if (ret_val)
1585                                         return ret_val;
1586
1587                                 ret_val = hw->phy.ops.read_reg_locked(hw,
1588                                                               PHY_REG(776, 20),
1589                                                               &data);
1590                                 if (ret_val) {
1591                                         hw->phy.ops.release(hw);
1592                                         return ret_val;
1593                                 }
1594
1595                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1596                                 if (ptr_gap < 0x18) {
1597                                         data &= ~(0x3FF << 2);
1598                                         data |= (0x18 << 2);
1599                                         ret_val =
1600                                                 hw->phy.ops.write_reg_locked(hw,
1601                                                         PHY_REG(776, 20), data);
1602                                 }
1603                                 hw->phy.ops.release(hw);
1604                                 if (ret_val)
1605                                         return ret_val;
1606                         } else {
1607                                 ret_val = hw->phy.ops.acquire(hw);
1608                                 if (ret_val)
1609                                         return ret_val;
1610
1611                                 ret_val = hw->phy.ops.write_reg_locked(hw,
1612                                                              PHY_REG(776, 20),
1613                                                              0xC023);
1614                                 hw->phy.ops.release(hw);
1615                                 if (ret_val)
1616                                         return ret_val;
1617
1618                         }
1619                 }
1620         }
1621
1622         /* I217 Packet Loss issue:
1623          * ensure that FEXTNVM4 Beacon Duration is set correctly
1624          * on power up.
1625          * Set the Beacon Duration for I217 to 8 usec
1626          */
1627         if (hw->mac.type >= e1000_pch_lpt) {
1628                 u32 mac_reg;
1629
1630                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1631                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1632                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1633                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1634         }
1635
1636         /* Work-around I218 hang issue */
1637         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1638             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1639             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1640             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1641                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1642                 if (ret_val)
1643                         return ret_val;
1644         }
1645         /* Clear link partner's EEE ability */
1646         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1647
1648         /* Configure K0s minimum time */
1649         if (hw->mac.type >= e1000_pch_lpt) {
1650                 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1651         }
1652
1653         if (hw->mac.type >= e1000_pch_lpt) {
1654                 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1655
1656                 if (hw->mac.type == e1000_pch_spt) {
1657                         /* FEXTNVM6 K1-off workaround - for SPT only */
1658                         u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1659
1660                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1661                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1662                         else
1663                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1664                 }
1665
1666                 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1667                         fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1668
1669                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1670         }
1671
1672         if (!link)
1673                 return E1000_SUCCESS; /* No link detected */
1674
1675         mac->get_link_status = false;
1676
1677         switch (hw->mac.type) {
1678         case e1000_pch2lan:
1679                 ret_val = e1000_k1_workaround_lv(hw);
1680                 if (ret_val)
1681                         return ret_val;
1682                 /* fall-thru */
1683         case e1000_pchlan:
1684                 if (hw->phy.type == e1000_phy_82578) {
1685                         ret_val = e1000_link_stall_workaround_hv(hw);
1686                         if (ret_val)
1687                                 return ret_val;
1688                 }
1689
1690                 /* Workaround for PCHx parts in half-duplex:
1691                  * Set the number of preambles removed from the packet
1692                  * when it is passed from the PHY to the MAC to prevent
1693                  * the MAC from misinterpreting the packet type.
1694                  */
1695                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1696                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1697
1698                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1699                     E1000_STATUS_FD)
1700                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1701
1702                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1703                 break;
1704         default:
1705                 break;
1706         }
1707
1708         /* Check if there was DownShift, must be checked
1709          * immediately after link-up
1710          */
1711         e1000_check_downshift_generic(hw);
1712
1713         /* Enable/Disable EEE after link up */
1714         if (hw->phy.type > e1000_phy_82579) {
1715                 ret_val = e1000_set_eee_pchlan(hw);
1716                 if (ret_val)
1717                         return ret_val;
1718         }
1719
1720         /* If we are forcing speed/duplex, then we simply return since
1721          * we have already determined whether we have link or not.
1722          */
1723         if (!mac->autoneg)
1724                 return -E1000_ERR_CONFIG;
1725
1726         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1727          * of MAC speed/duplex configuration.  So we only need to
1728          * configure Collision Distance in the MAC.
1729          */
1730         mac->ops.config_collision_dist(hw);
1731
1732         /* Configure Flow Control now that Auto-Neg has completed.
1733          * First, we need to restore the desired flow control
1734          * settings because we may have had to re-autoneg with a
1735          * different link partner.
1736          */
1737         ret_val = e1000_config_fc_after_link_up_generic(hw);
1738         if (ret_val)
1739                 DEBUGOUT("Error configuring flow control\n");
1740
1741         return ret_val;
1742 }
1743
1744 /**
1745  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1746  *  @hw: pointer to the HW structure
1747  *
1748  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1749  **/
1750 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1751 {
1752         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1753
1754         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1755         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1756         switch (hw->mac.type) {
1757         case e1000_ich8lan:
1758         case e1000_ich9lan:
1759         case e1000_ich10lan:
1760                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1761                 break;
1762         case e1000_pchlan:
1763         case e1000_pch2lan:
1764         case e1000_pch_lpt:
1765         case e1000_pch_spt:
1766         case e1000_pch_cnp:
1767                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1768                 break;
1769         default:
1770                 break;
1771         }
1772 }
1773
1774 /**
1775  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1776  *  @hw: pointer to the HW structure
1777  *
1778  *  Acquires the mutex for performing NVM operations.
1779  **/
1780 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1781 {
1782         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1783
1784         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1785
1786         return E1000_SUCCESS;
1787 }
1788
1789 /**
1790  *  e1000_release_nvm_ich8lan - Release NVM mutex
1791  *  @hw: pointer to the HW structure
1792  *
1793  *  Releases the mutex used while performing NVM operations.
1794  **/
1795 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1796 {
1797         DEBUGFUNC("e1000_release_nvm_ich8lan");
1798
1799         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1800
1801         return;
1802 }
1803
1804 /**
1805  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1806  *  @hw: pointer to the HW structure
1807  *
1808  *  Acquires the software control flag for performing PHY and select
1809  *  MAC CSR accesses.
1810  **/
1811 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1812 {
1813         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1814         s32 ret_val = E1000_SUCCESS;
1815
1816         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1817
1818         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1819
1820         while (timeout) {
1821                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1822                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1823                         break;
1824
1825                 msec_delay_irq(1);
1826                 timeout--;
1827         }
1828
1829         if (!timeout) {
1830                 DEBUGOUT("SW has already locked the resource.\n");
1831                 ret_val = -E1000_ERR_CONFIG;
1832                 goto out;
1833         }
1834
1835         timeout = SW_FLAG_TIMEOUT;
1836
1837         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1838         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1839
1840         while (timeout) {
1841                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1842                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1843                         break;
1844
1845                 msec_delay_irq(1);
1846                 timeout--;
1847         }
1848
1849         if (!timeout) {
1850                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1851                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1852                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1853                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1854                 ret_val = -E1000_ERR_CONFIG;
1855                 goto out;
1856         }
1857
1858 out:
1859         if (ret_val)
1860                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1861
1862         return ret_val;
1863 }
1864
1865 /**
1866  *  e1000_release_swflag_ich8lan - Release software control flag
1867  *  @hw: pointer to the HW structure
1868  *
1869  *  Releases the software control flag for performing PHY and select
1870  *  MAC CSR accesses.
1871  **/
1872 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1873 {
1874         u32 extcnf_ctrl;
1875
1876         DEBUGFUNC("e1000_release_swflag_ich8lan");
1877
1878         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1879
1880         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1881                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1882                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1883         } else {
1884                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1885         }
1886
1887         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1888
1889         return;
1890 }
1891
1892 /**
1893  *  e1000_check_mng_mode_ich8lan - Checks management mode
1894  *  @hw: pointer to the HW structure
1895  *
1896  *  This checks if the adapter has any manageability enabled.
1897  *  This is a function pointer entry point only called by read/write
1898  *  routines for the PHY and NVM parts.
1899  **/
1900 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1901 {
1902         u32 fwsm;
1903
1904         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1905
1906         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1907
1908         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1909                ((fwsm & E1000_FWSM_MODE_MASK) ==
1910                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1911 }
1912
1913 /**
1914  *  e1000_check_mng_mode_pchlan - Checks management mode
1915  *  @hw: pointer to the HW structure
1916  *
1917  *  This checks if the adapter has iAMT enabled.
1918  *  This is a function pointer entry point only called by read/write
1919  *  routines for the PHY and NVM parts.
1920  **/
1921 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1922 {
1923         u32 fwsm;
1924
1925         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1926
1927         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1928
1929         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1930                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1931 }
1932
1933 /**
1934  *  e1000_rar_set_pch2lan - Set receive address register
1935  *  @hw: pointer to the HW structure
1936  *  @addr: pointer to the receive address
1937  *  @index: receive address array register
1938  *
1939  *  Sets the receive address array register at index to the address passed
1940  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1941  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1942  *  Use SHRA[0-3] in place of those reserved for ME.
1943  **/
1944 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1945 {
1946         u32 rar_low, rar_high;
1947
1948         DEBUGFUNC("e1000_rar_set_pch2lan");
1949
1950         /* HW expects these in little endian so we reverse the byte order
1951          * from network order (big endian) to little endian
1952          */
1953         rar_low = ((u32) addr[0] |
1954                    ((u32) addr[1] << 8) |
1955                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1956
1957         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1958
1959         /* If MAC address zero, no need to set the AV bit */
1960         if (rar_low || rar_high)
1961                 rar_high |= E1000_RAH_AV;
1962
1963         if (index == 0) {
1964                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1965                 E1000_WRITE_FLUSH(hw);
1966                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1967                 E1000_WRITE_FLUSH(hw);
1968                 return E1000_SUCCESS;
1969         }
1970
1971         /* RAR[1-6] are owned by manageability.  Skip those and program the
1972          * next address into the SHRA register array.
1973          */
1974         if (index < (u32) (hw->mac.rar_entry_count)) {
1975                 s32 ret_val;
1976
1977                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1978                 if (ret_val)
1979                         goto out;
1980
1981                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1982                 E1000_WRITE_FLUSH(hw);
1983                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1984                 E1000_WRITE_FLUSH(hw);
1985
1986                 e1000_release_swflag_ich8lan(hw);
1987
1988                 /* verify the register updates */
1989                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1990                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1991                         return E1000_SUCCESS;
1992
1993                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1994                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1995         }
1996
1997 out:
1998         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1999         return -E1000_ERR_CONFIG;
2000 }
2001
2002 /**
2003  *  e1000_rar_set_pch_lpt - Set receive address registers
2004  *  @hw: pointer to the HW structure
2005  *  @addr: pointer to the receive address
2006  *  @index: receive address array register
2007  *
2008  *  Sets the receive address register array at index to the address passed
2009  *  in by addr. For LPT, RAR[0] is the base address register that is to
2010  *  contain the MAC address. SHRA[0-10] are the shared receive address
2011  *  registers that are shared between the Host and manageability engine (ME).
2012  **/
2013 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2014 {
2015         u32 rar_low, rar_high;
2016         u32 wlock_mac;
2017
2018         DEBUGFUNC("e1000_rar_set_pch_lpt");
2019
2020         /* HW expects these in little endian so we reverse the byte order
2021          * from network order (big endian) to little endian
2022          */
2023         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2024                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2025
2026         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2027
2028         /* If MAC address zero, no need to set the AV bit */
2029         if (rar_low || rar_high)
2030                 rar_high |= E1000_RAH_AV;
2031
2032         if (index == 0) {
2033                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2034                 E1000_WRITE_FLUSH(hw);
2035                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2036                 E1000_WRITE_FLUSH(hw);
2037                 return E1000_SUCCESS;
2038         }
2039
2040         /* The manageability engine (ME) can lock certain SHRAR registers that
2041          * it is using - those registers are unavailable for use.
2042          */
2043         if (index < hw->mac.rar_entry_count) {
2044                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2045                             E1000_FWSM_WLOCK_MAC_MASK;
2046                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2047
2048                 /* Check if all SHRAR registers are locked */
2049                 if (wlock_mac == 1)
2050                         goto out;
2051
2052                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2053                         s32 ret_val;
2054
2055                         ret_val = e1000_acquire_swflag_ich8lan(hw);
2056
2057                         if (ret_val)
2058                                 goto out;
2059
2060                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2061                                         rar_low);
2062                         E1000_WRITE_FLUSH(hw);
2063                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2064                                         rar_high);
2065                         E1000_WRITE_FLUSH(hw);
2066
2067                         e1000_release_swflag_ich8lan(hw);
2068
2069                         /* verify the register updates */
2070                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2071                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2072                                 return E1000_SUCCESS;
2073                 }
2074         }
2075
2076 out:
2077         DEBUGOUT1("Failed to write receive address at index %d\n", index);
2078         return -E1000_ERR_CONFIG;
2079 }
2080
2081 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
2082 /**
2083  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2084  *  @hw: pointer to the HW structure
2085  *  @mc_addr_list: array of multicast addresses to program
2086  *  @mc_addr_count: number of multicast addresses to program
2087  *
2088  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2089  *  The caller must have a packed mc_addr_list of multicast addresses.
2090  **/
2091 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2092                                               u8 *mc_addr_list,
2093                                               u32 mc_addr_count)
2094 {
2095         u16 phy_reg = 0;
2096         int i;
2097         s32 ret_val;
2098
2099         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2100
2101         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2102
2103         ret_val = hw->phy.ops.acquire(hw);
2104         if (ret_val)
2105                 return;
2106
2107         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2108         if (ret_val)
2109                 goto release;
2110
2111         for (i = 0; i < hw->mac.mta_reg_count; i++) {
2112                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2113                                            (u16)(hw->mac.mta_shadow[i] &
2114                                                  0xFFFF));
2115                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2116                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
2117                                                  0xFFFF));
2118         }
2119
2120         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2121
2122 release:
2123         hw->phy.ops.release(hw);
2124 }
2125
2126 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
2127 /**
2128  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2129  *  @hw: pointer to the HW structure
2130  *
2131  *  Checks if firmware is blocking the reset of the PHY.
2132  *  This is a function pointer entry point only called by
2133  *  reset routines.
2134  **/
2135 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2136 {
2137         u32 fwsm;
2138         bool blocked = false;
2139         int i = 0;
2140
2141         DEBUGFUNC("e1000_check_reset_block_ich8lan");
2142
2143         do {
2144                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2145                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2146                         blocked = true;
2147                         msec_delay(10);
2148                         continue;
2149                 }
2150                 blocked = false;
2151         } while (blocked && (i++ < 30));
2152         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2153 }
2154
2155 /**
2156  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2157  *  @hw: pointer to the HW structure
2158  *
2159  *  Assumes semaphore already acquired.
2160  *
2161  **/
2162 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2163 {
2164         u16 phy_data;
2165         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2166         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2167                 E1000_STRAP_SMT_FREQ_SHIFT;
2168         s32 ret_val;
2169
2170         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2171
2172         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2173         if (ret_val)
2174                 return ret_val;
2175
2176         phy_data &= ~HV_SMB_ADDR_MASK;
2177         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2178         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2179
2180         if (hw->phy.type == e1000_phy_i217) {
2181                 /* Restore SMBus frequency */
2182                 if (freq--) {
2183                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2184                         phy_data |= (freq & (1 << 0)) <<
2185                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2186                         phy_data |= (freq & (1 << 1)) <<
2187                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2188                 } else {
2189                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2190                 }
2191         }
2192
2193         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2194 }
2195
2196 /**
2197  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2198  *  @hw:   pointer to the HW structure
2199  *
2200  *  SW should configure the LCD from the NVM extended configuration region
2201  *  as a workaround for certain parts.
2202  **/
2203 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2204 {
2205         struct e1000_phy_info *phy = &hw->phy;
2206         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2207         s32 ret_val = E1000_SUCCESS;
2208         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2209
2210         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2211
2212         /* Initialize the PHY from the NVM on ICH platforms.  This
2213          * is needed due to an issue where the NVM configuration is
2214          * not properly autoloaded after power transitions.
2215          * Therefore, after each PHY reset, we will load the
2216          * configuration data out of the NVM manually.
2217          */
2218         switch (hw->mac.type) {
2219         case e1000_ich8lan:
2220                 if (phy->type != e1000_phy_igp_3)
2221                         return ret_val;
2222
2223                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2224                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2225                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2226                         break;
2227                 }
2228                 /* Fall-thru */
2229         case e1000_pchlan:
2230         case e1000_pch2lan:
2231         case e1000_pch_lpt:
2232         case e1000_pch_spt:
2233         case e1000_pch_cnp:
2234                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2235                 break;
2236         default:
2237                 return ret_val;
2238         }
2239
2240         ret_val = hw->phy.ops.acquire(hw);
2241         if (ret_val)
2242                 return ret_val;
2243
2244         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2245         if (!(data & sw_cfg_mask))
2246                 goto release;
2247
2248         /* Make sure HW does not configure LCD from PHY
2249          * extended configuration before SW configuration
2250          */
2251         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2252         if ((hw->mac.type < e1000_pch2lan) &&
2253             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2254                         goto release;
2255
2256         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2257         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2258         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2259         if (!cnf_size)
2260                 goto release;
2261
2262         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2263         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2264
2265         if (((hw->mac.type == e1000_pchlan) &&
2266              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2267             (hw->mac.type > e1000_pchlan)) {
2268                 /* HW configures the SMBus address and LEDs when the
2269                  * OEM and LCD Write Enable bits are set in the NVM.
2270                  * When both NVM bits are cleared, SW will configure
2271                  * them instead.
2272                  */
2273                 ret_val = e1000_write_smbus_addr(hw);
2274                 if (ret_val)
2275                         goto release;
2276
2277                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2278                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2279                                                         (u16)data);
2280                 if (ret_val)
2281                         goto release;
2282         }
2283
2284         /* Configure LCD from extended configuration region. */
2285
2286         /* cnf_base_addr is in DWORD */
2287         word_addr = (u16)(cnf_base_addr << 1);
2288
2289         for (i = 0; i < cnf_size; i++) {
2290                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2291                                            &reg_data);
2292                 if (ret_val)
2293                         goto release;
2294
2295                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2296                                            1, &reg_addr);
2297                 if (ret_val)
2298                         goto release;
2299
2300                 /* Save off the PHY page for future writes. */
2301                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2302                         phy_page = reg_data;
2303                         continue;
2304                 }
2305
2306                 reg_addr &= PHY_REG_MASK;
2307                 reg_addr |= phy_page;
2308
2309                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2310                                                     reg_data);
2311                 if (ret_val)
2312                         goto release;
2313         }
2314
2315 release:
2316         hw->phy.ops.release(hw);
2317         return ret_val;
2318 }
2319
2320 /**
2321  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2322  *  @hw:   pointer to the HW structure
2323  *  @link: link up bool flag
2324  *
2325  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2326  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2327  *  If link is down, the function will restore the default K1 setting located
2328  *  in the NVM.
2329  **/
2330 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2331 {
2332         s32 ret_val = E1000_SUCCESS;
2333         u16 status_reg = 0;
2334         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2335
2336         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2337
2338         if (hw->mac.type != e1000_pchlan)
2339                 return E1000_SUCCESS;
2340
2341         /* Wrap the whole flow with the sw flag */
2342         ret_val = hw->phy.ops.acquire(hw);
2343         if (ret_val)
2344                 return ret_val;
2345
2346         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2347         if (link) {
2348                 if (hw->phy.type == e1000_phy_82578) {
2349                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2350                                                               &status_reg);
2351                         if (ret_val)
2352                                 goto release;
2353
2354                         status_reg &= (BM_CS_STATUS_LINK_UP |
2355                                        BM_CS_STATUS_RESOLVED |
2356                                        BM_CS_STATUS_SPEED_MASK);
2357
2358                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2359                                            BM_CS_STATUS_RESOLVED |
2360                                            BM_CS_STATUS_SPEED_1000))
2361                                 k1_enable = false;
2362                 }
2363
2364                 if (hw->phy.type == e1000_phy_82577) {
2365                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2366                                                               &status_reg);
2367                         if (ret_val)
2368                                 goto release;
2369
2370                         status_reg &= (HV_M_STATUS_LINK_UP |
2371                                        HV_M_STATUS_AUTONEG_COMPLETE |
2372                                        HV_M_STATUS_SPEED_MASK);
2373
2374                         if (status_reg == (HV_M_STATUS_LINK_UP |
2375                                            HV_M_STATUS_AUTONEG_COMPLETE |
2376                                            HV_M_STATUS_SPEED_1000))
2377                                 k1_enable = false;
2378                 }
2379
2380                 /* Link stall fix for link up */
2381                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2382                                                        0x0100);
2383                 if (ret_val)
2384                         goto release;
2385
2386         } else {
2387                 /* Link stall fix for link down */
2388                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2389                                                        0x4100);
2390                 if (ret_val)
2391                         goto release;
2392         }
2393
2394         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2395
2396 release:
2397         hw->phy.ops.release(hw);
2398
2399         return ret_val;
2400 }
2401
2402 /**
2403  *  e1000_configure_k1_ich8lan - Configure K1 power state
2404  *  @hw: pointer to the HW structure
2405  *  @k1_enable: K1 state to configure
2406  *
2407  *  Configure the K1 power state based on the provided parameter.
2408  *  Assumes semaphore already acquired.
2409  *
2410  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2411  **/
2412 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2413 {
2414         s32 ret_val;
2415         u32 ctrl_reg = 0;
2416         u32 ctrl_ext = 0;
2417         u32 reg = 0;
2418         u16 kmrn_reg = 0;
2419
2420         DEBUGFUNC("e1000_configure_k1_ich8lan");
2421
2422         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2423                                              &kmrn_reg);
2424         if (ret_val)
2425                 return ret_val;
2426
2427         if (k1_enable)
2428                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2429         else
2430                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2431
2432         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2433                                               kmrn_reg);
2434         if (ret_val)
2435                 return ret_val;
2436
2437         usec_delay(20);
2438         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2439         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2440
2441         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2442         reg |= E1000_CTRL_FRCSPD;
2443         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2444
2445         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2446         E1000_WRITE_FLUSH(hw);
2447         usec_delay(20);
2448         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2449         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2450         E1000_WRITE_FLUSH(hw);
2451         usec_delay(20);
2452
2453         return E1000_SUCCESS;
2454 }
2455
2456 /**
2457  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2458  *  @hw:       pointer to the HW structure
2459  *  @d0_state: boolean if entering d0 or d3 device state
2460  *
2461  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2462  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2463  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2464  **/
2465 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2466 {
2467         s32 ret_val = 0;
2468         u32 mac_reg;
2469         u16 oem_reg;
2470
2471         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2472
2473         if (hw->mac.type < e1000_pchlan)
2474                 return ret_val;
2475
2476         ret_val = hw->phy.ops.acquire(hw);
2477         if (ret_val)
2478                 return ret_val;
2479
2480         if (hw->mac.type == e1000_pchlan) {
2481                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2482                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2483                         goto release;
2484         }
2485
2486         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2487         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2488                 goto release;
2489
2490         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2491
2492         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2493         if (ret_val)
2494                 goto release;
2495
2496         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2497
2498         if (d0_state) {
2499                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2500                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2501
2502                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2503                         oem_reg |= HV_OEM_BITS_LPLU;
2504         } else {
2505                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2506                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2507                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2508
2509                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2510                     E1000_PHY_CTRL_NOND0A_LPLU))
2511                         oem_reg |= HV_OEM_BITS_LPLU;
2512         }
2513
2514         /* Set Restart auto-neg to activate the bits */
2515         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2516             !hw->phy.ops.check_reset_block(hw))
2517                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2518
2519         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2520
2521 release:
2522         hw->phy.ops.release(hw);
2523
2524         return ret_val;
2525 }
2526
2527
2528 /**
2529  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2530  *  @hw:   pointer to the HW structure
2531  **/
2532 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2533 {
2534         s32 ret_val;
2535         u16 data;
2536
2537         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2538
2539         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2540         if (ret_val)
2541                 return ret_val;
2542
2543         data |= HV_KMRN_MDIO_SLOW;
2544
2545         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2546
2547         return ret_val;
2548 }
2549
2550 /**
2551  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2552  *  done after every PHY reset.
2553  *  @hw: pointer to the HW structure
2554  **/
2555 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2556 {
2557         s32 ret_val = E1000_SUCCESS;
2558         u16 phy_data;
2559
2560         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2561
2562         if (hw->mac.type != e1000_pchlan)
2563                 return E1000_SUCCESS;
2564
2565         /* Set MDIO slow mode before any other MDIO access */
2566         if (hw->phy.type == e1000_phy_82577) {
2567                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2568                 if (ret_val)
2569                         return ret_val;
2570         }
2571
2572         if (((hw->phy.type == e1000_phy_82577) &&
2573              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2574             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2575                 /* Disable generation of early preamble */
2576                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2577                 if (ret_val)
2578                         return ret_val;
2579
2580                 /* Preamble tuning for SSC */
2581                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2582                                                 0xA204);
2583                 if (ret_val)
2584                         return ret_val;
2585         }
2586
2587         if (hw->phy.type == e1000_phy_82578) {
2588                 /* Return registers to default by doing a soft reset then
2589                  * writing 0x3140 to the control register.
2590                  */
2591                 if (hw->phy.revision < 2) {
2592                         e1000_phy_sw_reset_generic(hw);
2593                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2594                                                         0x3140);
2595                 }
2596         }
2597
2598         /* Select page 0 */
2599         ret_val = hw->phy.ops.acquire(hw);
2600         if (ret_val)
2601                 return ret_val;
2602
2603         hw->phy.addr = 1;
2604         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2605         hw->phy.ops.release(hw);
2606         if (ret_val)
2607                 return ret_val;
2608
2609         /* Configure the K1 Si workaround during phy reset assuming there is
2610          * link so that it disables K1 if link is in 1Gbps.
2611          */
2612         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2613         if (ret_val)
2614                 return ret_val;
2615
2616         /* Workaround for link disconnects on a busy hub in half duplex */
2617         ret_val = hw->phy.ops.acquire(hw);
2618         if (ret_val)
2619                 return ret_val;
2620         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2621         if (ret_val)
2622                 goto release;
2623         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2624                                                phy_data & 0x00FF);
2625         if (ret_val)
2626                 goto release;
2627
2628         /* set MSE higher to enable link to stay up when noise is high */
2629         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2630 release:
2631         hw->phy.ops.release(hw);
2632
2633         return ret_val;
2634 }
2635
2636 /**
2637  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2638  *  @hw:   pointer to the HW structure
2639  **/
2640 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2641 {
2642         u32 mac_reg;
2643         u16 i, phy_reg = 0;
2644         s32 ret_val;
2645
2646         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2647
2648         ret_val = hw->phy.ops.acquire(hw);
2649         if (ret_val)
2650                 return;
2651         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2652         if (ret_val)
2653                 goto release;
2654
2655         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2656         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2657                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2658                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2659                                            (u16)(mac_reg & 0xFFFF));
2660                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2661                                            (u16)((mac_reg >> 16) & 0xFFFF));
2662
2663                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2664                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2665                                            (u16)(mac_reg & 0xFFFF));
2666                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2667                                            (u16)((mac_reg & E1000_RAH_AV)
2668                                                  >> 16));
2669         }
2670
2671         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2672
2673 release:
2674         hw->phy.ops.release(hw);
2675 }
2676
2677 #ifndef CRC32_OS_SUPPORT
2678 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2679 {
2680         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2681         u32 i, j, mask, crc;
2682
2683         DEBUGFUNC("e1000_calc_rx_da_crc");
2684
2685         crc = 0xffffffff;
2686         for (i = 0; i < 6; i++) {
2687                 crc = crc ^ mac[i];
2688                 for (j = 8; j > 0; j--) {
2689                         mask = (crc & 1) * (-1);
2690                         crc = (crc >> 1) ^ (poly & mask);
2691                 }
2692         }
2693         return ~crc;
2694 }
2695
2696 #endif /* CRC32_OS_SUPPORT */
2697 /**
2698  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2699  *  with 82579 PHY
2700  *  @hw: pointer to the HW structure
2701  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2702  **/
2703 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2704 {
2705         s32 ret_val = E1000_SUCCESS;
2706         u16 phy_reg, data;
2707         u32 mac_reg;
2708         u16 i;
2709
2710         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2711
2712         if (hw->mac.type < e1000_pch2lan)
2713                 return E1000_SUCCESS;
2714
2715         /* disable Rx path while enabling/disabling workaround */
2716         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2717         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2718                                         phy_reg | (1 << 14));
2719         if (ret_val)
2720                 return ret_val;
2721
2722         if (enable) {
2723                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2724                  * SHRAL/H) and initial CRC values to the MAC
2725                  */
2726                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2727                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2728                         u32 addr_high, addr_low;
2729
2730                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2731                         if (!(addr_high & E1000_RAH_AV))
2732                                 continue;
2733                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2734                         mac_addr[0] = (addr_low & 0xFF);
2735                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2736                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2737                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2738                         mac_addr[4] = (addr_high & 0xFF);
2739                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2740
2741 #ifndef CRC32_OS_SUPPORT
2742                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2743                                         e1000_calc_rx_da_crc(mac_addr));
2744 #else /* CRC32_OS_SUPPORT */
2745                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2746                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2747 #endif /* CRC32_OS_SUPPORT */
2748                 }
2749
2750                 /* Write Rx addresses to the PHY */
2751                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2752
2753                 /* Enable jumbo frame workaround in the MAC */
2754                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2755                 mac_reg &= ~(1 << 14);
2756                 mac_reg |= (7 << 15);
2757                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2758
2759                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2760                 mac_reg |= E1000_RCTL_SECRC;
2761                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2762
2763                 ret_val = e1000_read_kmrn_reg_generic(hw,
2764                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2765                                                 &data);
2766                 if (ret_val)
2767                         return ret_val;
2768                 ret_val = e1000_write_kmrn_reg_generic(hw,
2769                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2770                                                 data | (1 << 0));
2771                 if (ret_val)
2772                         return ret_val;
2773                 ret_val = e1000_read_kmrn_reg_generic(hw,
2774                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2775                                                 &data);
2776                 if (ret_val)
2777                         return ret_val;
2778                 data &= ~(0xF << 8);
2779                 data |= (0xB << 8);
2780                 ret_val = e1000_write_kmrn_reg_generic(hw,
2781                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2782                                                 data);
2783                 if (ret_val)
2784                         return ret_val;
2785
2786                 /* Enable jumbo frame workaround in the PHY */
2787                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2788                 data &= ~(0x7F << 5);
2789                 data |= (0x37 << 5);
2790                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2791                 if (ret_val)
2792                         return ret_val;
2793                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2794                 data &= ~(1 << 13);
2795                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2796                 if (ret_val)
2797                         return ret_val;
2798                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2799                 data &= ~(0x3FF << 2);
2800                 data |= (E1000_TX_PTR_GAP << 2);
2801                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2802                 if (ret_val)
2803                         return ret_val;
2804                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2805                 if (ret_val)
2806                         return ret_val;
2807                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2808                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2809                                                 (1 << 10));
2810                 if (ret_val)
2811                         return ret_val;
2812         } else {
2813                 /* Write MAC register values back to h/w defaults */
2814                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2815                 mac_reg &= ~(0xF << 14);
2816                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2817
2818                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2819                 mac_reg &= ~E1000_RCTL_SECRC;
2820                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2821
2822                 ret_val = e1000_read_kmrn_reg_generic(hw,
2823                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2824                                                 &data);
2825                 if (ret_val)
2826                         return ret_val;
2827                 ret_val = e1000_write_kmrn_reg_generic(hw,
2828                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2829                                                 data & ~(1 << 0));
2830                 if (ret_val)
2831                         return ret_val;
2832                 ret_val = e1000_read_kmrn_reg_generic(hw,
2833                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2834                                                 &data);
2835                 if (ret_val)
2836                         return ret_val;
2837                 data &= ~(0xF << 8);
2838                 data |= (0xB << 8);
2839                 ret_val = e1000_write_kmrn_reg_generic(hw,
2840                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2841                                                 data);
2842                 if (ret_val)
2843                         return ret_val;
2844
2845                 /* Write PHY register values back to h/w defaults */
2846                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2847                 data &= ~(0x7F << 5);
2848                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2849                 if (ret_val)
2850                         return ret_val;
2851                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2852                 data |= (1 << 13);
2853                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2854                 if (ret_val)
2855                         return ret_val;
2856                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2857                 data &= ~(0x3FF << 2);
2858                 data |= (0x8 << 2);
2859                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2860                 if (ret_val)
2861                         return ret_val;
2862                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2863                 if (ret_val)
2864                         return ret_val;
2865                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2866                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2867                                                 ~(1 << 10));
2868                 if (ret_val)
2869                         return ret_val;
2870         }
2871
2872         /* re-enable Rx path after enabling/disabling workaround */
2873         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2874                                      ~(1 << 14));
2875 }
2876
2877 /**
2878  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2879  *  done after every PHY reset.
2880  *  @hw: pointer to the HW structure
2881  **/
2882 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2883 {
2884         s32 ret_val = E1000_SUCCESS;
2885
2886         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2887
2888         if (hw->mac.type != e1000_pch2lan)
2889                 return E1000_SUCCESS;
2890
2891         /* Set MDIO slow mode before any other MDIO access */
2892         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2893         if (ret_val)
2894                 return ret_val;
2895
2896         ret_val = hw->phy.ops.acquire(hw);
2897         if (ret_val)
2898                 return ret_val;
2899         /* set MSE higher to enable link to stay up when noise is high */
2900         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2901         if (ret_val)
2902                 goto release;
2903         /* drop link after 5 times MSE threshold was reached */
2904         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2905 release:
2906         hw->phy.ops.release(hw);
2907
2908         return ret_val;
2909 }
2910
2911 /**
2912  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2913  *  @hw:   pointer to the HW structure
2914  *
2915  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2916  *  Disable K1 for 1000 and 100 speeds
2917  **/
2918 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2919 {
2920         s32 ret_val = E1000_SUCCESS;
2921         u16 status_reg = 0;
2922
2923         DEBUGFUNC("e1000_k1_workaround_lv");
2924
2925         if (hw->mac.type != e1000_pch2lan)
2926                 return E1000_SUCCESS;
2927
2928         /* Set K1 beacon duration based on 10Mbs speed */
2929         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2930         if (ret_val)
2931                 return ret_val;
2932
2933         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2934             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2935                 if (status_reg &
2936                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2937                         u16 pm_phy_reg;
2938
2939                         /* LV 1G/100 Packet drop issue wa  */
2940                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2941                                                        &pm_phy_reg);
2942                         if (ret_val)
2943                                 return ret_val;
2944                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2945                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2946                                                         pm_phy_reg);
2947                         if (ret_val)
2948                                 return ret_val;
2949                 } else {
2950                         u32 mac_reg;
2951                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2952                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2953                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2954                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2955                 }
2956         }
2957
2958         return ret_val;
2959 }
2960
2961 /**
2962  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2963  *  @hw:   pointer to the HW structure
2964  *  @gate: boolean set to true to gate, false to ungate
2965  *
2966  *  Gate/ungate the automatic PHY configuration via hardware; perform
2967  *  the configuration via software instead.
2968  **/
2969 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2970 {
2971         u32 extcnf_ctrl;
2972
2973         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2974
2975         if (hw->mac.type < e1000_pch2lan)
2976                 return;
2977
2978         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2979
2980         if (gate)
2981                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2982         else
2983                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2984
2985         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2986 }
2987
2988 /**
2989  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2990  *  @hw: pointer to the HW structure
2991  *
2992  *  Check the appropriate indication the MAC has finished configuring the
2993  *  PHY after a software reset.
2994  **/
2995 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2996 {
2997         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2998
2999         DEBUGFUNC("e1000_lan_init_done_ich8lan");
3000
3001         /* Wait for basic configuration completes before proceeding */
3002         do {
3003                 data = E1000_READ_REG(hw, E1000_STATUS);
3004                 data &= E1000_STATUS_LAN_INIT_DONE;
3005                 usec_delay(100);
3006         } while ((!data) && --loop);
3007
3008         /* If basic configuration is incomplete before the above loop
3009          * count reaches 0, loading the configuration from NVM will
3010          * leave the PHY in a bad state possibly resulting in no link.
3011          */
3012         if (loop == 0)
3013                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3014
3015         /* Clear the Init Done bit for the next init event */
3016         data = E1000_READ_REG(hw, E1000_STATUS);
3017         data &= ~E1000_STATUS_LAN_INIT_DONE;
3018         E1000_WRITE_REG(hw, E1000_STATUS, data);
3019 }
3020
3021 /**
3022  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3023  *  @hw: pointer to the HW structure
3024  **/
3025 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3026 {
3027         s32 ret_val = E1000_SUCCESS;
3028         u16 reg;
3029
3030         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3031
3032         if (hw->phy.ops.check_reset_block(hw))
3033                 return E1000_SUCCESS;
3034
3035         /* Allow time for h/w to get to quiescent state after reset */
3036         msec_delay(10);
3037
3038         /* Perform any necessary post-reset workarounds */
3039         switch (hw->mac.type) {
3040         case e1000_pchlan:
3041                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3042                 if (ret_val)
3043                         return ret_val;
3044                 break;
3045         case e1000_pch2lan:
3046                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3047                 if (ret_val)
3048                         return ret_val;
3049                 break;
3050         default:
3051                 break;
3052         }
3053
3054         /* Clear the host wakeup bit after lcd reset */
3055         if (hw->mac.type >= e1000_pchlan) {
3056                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
3057                 reg &= ~BM_WUC_HOST_WU_BIT;
3058                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3059         }
3060
3061         /* Configure the LCD with the extended configuration region in NVM */
3062         ret_val = e1000_sw_lcd_config_ich8lan(hw);
3063         if (ret_val)
3064                 return ret_val;
3065
3066         /* Configure the LCD with the OEM bits in NVM */
3067         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3068
3069         if (hw->mac.type == e1000_pch2lan) {
3070                 /* Ungate automatic PHY configuration on non-managed 82579 */
3071                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3072                     E1000_ICH_FWSM_FW_VALID)) {
3073                         msec_delay(10);
3074                         e1000_gate_hw_phy_config_ich8lan(hw, false);
3075                 }
3076
3077                 /* Set EEE LPI Update Timer to 200usec */
3078                 ret_val = hw->phy.ops.acquire(hw);
3079                 if (ret_val)
3080                         return ret_val;
3081                 ret_val = e1000_write_emi_reg_locked(hw,
3082                                                      I82579_LPI_UPDATE_TIMER,
3083                                                      0x1387);
3084                 hw->phy.ops.release(hw);
3085         }
3086
3087         return ret_val;
3088 }
3089
3090 /**
3091  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3092  *  @hw: pointer to the HW structure
3093  *
3094  *  Resets the PHY
3095  *  This is a function pointer entry point called by drivers
3096  *  or other shared routines.
3097  **/
3098 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3099 {
3100         s32 ret_val = E1000_SUCCESS;
3101
3102         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3103
3104         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3105         if ((hw->mac.type == e1000_pch2lan) &&
3106             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3107                 e1000_gate_hw_phy_config_ich8lan(hw, true);
3108
3109         ret_val = e1000_phy_hw_reset_generic(hw);
3110         if (ret_val)
3111                 return ret_val;
3112
3113         return e1000_post_phy_reset_ich8lan(hw);
3114 }
3115
3116 /**
3117  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3118  *  @hw: pointer to the HW structure
3119  *  @active: true to enable LPLU, false to disable
3120  *
3121  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
3122  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3123  *  the phy speed. This function will manually set the LPLU bit and restart
3124  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
3125  *  since it configures the same bit.
3126  **/
3127 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3128 {
3129         s32 ret_val;
3130         u16 oem_reg;
3131
3132         DEBUGFUNC("e1000_set_lplu_state_pchlan");
3133         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3134         if (ret_val)
3135                 return ret_val;
3136
3137         if (active)
3138                 oem_reg |= HV_OEM_BITS_LPLU;
3139         else
3140                 oem_reg &= ~HV_OEM_BITS_LPLU;
3141
3142         if (!hw->phy.ops.check_reset_block(hw))
3143                 oem_reg |= HV_OEM_BITS_RESTART_AN;
3144
3145         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3146 }
3147
3148 /**
3149  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3150  *  @hw: pointer to the HW structure
3151  *  @active: true to enable LPLU, false to disable
3152  *
3153  *  Sets the LPLU D0 state according to the active flag.  When
3154  *  activating LPLU this function also disables smart speed
3155  *  and vice versa.  LPLU will not be activated unless the
3156  *  device autonegotiation advertisement meets standards of
3157  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3158  *  This is a function pointer entry point only called by
3159  *  PHY setup routines.
3160  **/
3161 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3162 {
3163         struct e1000_phy_info *phy = &hw->phy;
3164         u32 phy_ctrl;
3165         s32 ret_val = E1000_SUCCESS;
3166         u16 data;
3167
3168         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3169
3170         if (phy->type == e1000_phy_ife)
3171                 return E1000_SUCCESS;
3172
3173         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3174
3175         if (active) {
3176                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3177                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3178
3179                 if (phy->type != e1000_phy_igp_3)
3180                         return E1000_SUCCESS;
3181
3182                 /* Call gig speed drop workaround on LPLU before accessing
3183                  * any PHY registers
3184                  */
3185                 if (hw->mac.type == e1000_ich8lan)
3186                         e1000_gig_downshift_workaround_ich8lan(hw);
3187
3188                 /* When LPLU is enabled, we should disable SmartSpeed */
3189                 ret_val = phy->ops.read_reg(hw,
3190                                             IGP01E1000_PHY_PORT_CONFIG,
3191                                             &data);
3192                 if (ret_val)
3193                         return ret_val;
3194                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3195                 ret_val = phy->ops.write_reg(hw,
3196                                              IGP01E1000_PHY_PORT_CONFIG,
3197                                              data);
3198                 if (ret_val)
3199                         return ret_val;
3200         } else {
3201                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3202                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3203
3204                 if (phy->type != e1000_phy_igp_3)
3205                         return E1000_SUCCESS;
3206
3207                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3208                  * during Dx states where the power conservation is most
3209                  * important.  During driver activity we should enable
3210                  * SmartSpeed, so performance is maintained.
3211                  */
3212                 if (phy->smart_speed == e1000_smart_speed_on) {
3213                         ret_val = phy->ops.read_reg(hw,
3214                                                     IGP01E1000_PHY_PORT_CONFIG,
3215                                                     &data);
3216                         if (ret_val)
3217                                 return ret_val;
3218
3219                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3220                         ret_val = phy->ops.write_reg(hw,
3221                                                      IGP01E1000_PHY_PORT_CONFIG,
3222                                                      data);
3223                         if (ret_val)
3224                                 return ret_val;
3225                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3226                         ret_val = phy->ops.read_reg(hw,
3227                                                     IGP01E1000_PHY_PORT_CONFIG,
3228                                                     &data);
3229                         if (ret_val)
3230                                 return ret_val;
3231
3232                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3233                         ret_val = phy->ops.write_reg(hw,
3234                                                      IGP01E1000_PHY_PORT_CONFIG,
3235                                                      data);
3236                         if (ret_val)
3237                                 return ret_val;
3238                 }
3239         }
3240
3241         return E1000_SUCCESS;
3242 }
3243
3244 /**
3245  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3246  *  @hw: pointer to the HW structure
3247  *  @active: true to enable LPLU, false to disable
3248  *
3249  *  Sets the LPLU D3 state according to the active flag.  When
3250  *  activating LPLU this function also disables smart speed
3251  *  and vice versa.  LPLU will not be activated unless the
3252  *  device autonegotiation advertisement meets standards of
3253  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3254  *  This is a function pointer entry point only called by
3255  *  PHY setup routines.
3256  **/
3257 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3258 {
3259         struct e1000_phy_info *phy = &hw->phy;
3260         u32 phy_ctrl;
3261         s32 ret_val = E1000_SUCCESS;
3262         u16 data;
3263
3264         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3265
3266         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3267
3268         if (!active) {
3269                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3270                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3271
3272                 if (phy->type != e1000_phy_igp_3)
3273                         return E1000_SUCCESS;
3274
3275                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3276                  * during Dx states where the power conservation is most
3277                  * important.  During driver activity we should enable
3278                  * SmartSpeed, so performance is maintained.
3279                  */
3280                 if (phy->smart_speed == e1000_smart_speed_on) {
3281                         ret_val = phy->ops.read_reg(hw,
3282                                                     IGP01E1000_PHY_PORT_CONFIG,
3283                                                     &data);
3284                         if (ret_val)
3285                                 return ret_val;
3286
3287                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3288                         ret_val = phy->ops.write_reg(hw,
3289                                                      IGP01E1000_PHY_PORT_CONFIG,
3290                                                      data);
3291                         if (ret_val)
3292                                 return ret_val;
3293                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3294                         ret_val = phy->ops.read_reg(hw,
3295                                                     IGP01E1000_PHY_PORT_CONFIG,
3296                                                     &data);
3297                         if (ret_val)
3298                                 return ret_val;
3299
3300                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3301                         ret_val = phy->ops.write_reg(hw,
3302                                                      IGP01E1000_PHY_PORT_CONFIG,
3303                                                      data);
3304                         if (ret_val)
3305                                 return ret_val;
3306                 }
3307         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3308                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3309                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3310                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3311                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3312
3313                 if (phy->type != e1000_phy_igp_3)
3314                         return E1000_SUCCESS;
3315
3316                 /* Call gig speed drop workaround on LPLU before accessing
3317                  * any PHY registers
3318                  */
3319                 if (hw->mac.type == e1000_ich8lan)
3320                         e1000_gig_downshift_workaround_ich8lan(hw);
3321
3322                 /* When LPLU is enabled, we should disable SmartSpeed */
3323                 ret_val = phy->ops.read_reg(hw,
3324                                             IGP01E1000_PHY_PORT_CONFIG,
3325                                             &data);
3326                 if (ret_val)
3327                         return ret_val;
3328
3329                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3330                 ret_val = phy->ops.write_reg(hw,
3331                                              IGP01E1000_PHY_PORT_CONFIG,
3332                                              data);
3333         }
3334
3335         return ret_val;
3336 }
3337
3338 /**
3339  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3340  *  @hw: pointer to the HW structure
3341  *  @bank:  pointer to the variable that returns the active bank
3342  *
3343  *  Reads signature byte from the NVM using the flash access registers.
3344  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3345  **/
3346 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3347 {
3348         u32 eecd;
3349         struct e1000_nvm_info *nvm = &hw->nvm;
3350         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3351         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3352         u32 nvm_dword = 0;
3353         u8 sig_byte = 0;
3354         s32 ret_val;
3355
3356         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3357
3358         switch (hw->mac.type) {
3359         case e1000_pch_spt:
3360         case e1000_pch_cnp:
3361                 bank1_offset = nvm->flash_bank_size;
3362                 act_offset = E1000_ICH_NVM_SIG_WORD;
3363
3364                 /* set bank to 0 in case flash read fails */
3365                 *bank = 0;
3366
3367                 /* Check bank 0 */
3368                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3369                                                          &nvm_dword);
3370                 if (ret_val)
3371                         return ret_val;
3372                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3373                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3374                     E1000_ICH_NVM_SIG_VALUE) {
3375                         *bank = 0;
3376                         return E1000_SUCCESS;
3377                 }
3378
3379                 /* Check bank 1 */
3380                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3381                                                          bank1_offset,
3382                                                          &nvm_dword);
3383                 if (ret_val)
3384                         return ret_val;
3385                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3386                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3387                     E1000_ICH_NVM_SIG_VALUE) {
3388                         *bank = 1;
3389                         return E1000_SUCCESS;
3390                 }
3391
3392                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3393                 return -E1000_ERR_NVM;
3394         case e1000_ich8lan:
3395         case e1000_ich9lan:
3396                 eecd = E1000_READ_REG(hw, E1000_EECD);
3397                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3398                     E1000_EECD_SEC1VAL_VALID_MASK) {
3399                         if (eecd & E1000_EECD_SEC1VAL)
3400                                 *bank = 1;
3401                         else
3402                                 *bank = 0;
3403
3404                         return E1000_SUCCESS;
3405                 }
3406                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3407                 /* fall-thru */
3408         default:
3409                 /* set bank to 0 in case flash read fails */
3410                 *bank = 0;
3411
3412                 /* Check bank 0 */
3413                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3414                                                         &sig_byte);
3415                 if (ret_val)
3416                         return ret_val;
3417                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3418                     E1000_ICH_NVM_SIG_VALUE) {
3419                         *bank = 0;
3420                         return E1000_SUCCESS;
3421                 }
3422
3423                 /* Check bank 1 */
3424                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3425                                                         bank1_offset,
3426                                                         &sig_byte);
3427                 if (ret_val)
3428                         return ret_val;
3429                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3430                     E1000_ICH_NVM_SIG_VALUE) {
3431                         *bank = 1;
3432                         return E1000_SUCCESS;
3433                 }
3434
3435                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3436                 return -E1000_ERR_NVM;
3437         }
3438 }
3439
3440 /**
3441  *  e1000_read_nvm_spt - NVM access for SPT
3442  *  @hw: pointer to the HW structure
3443  *  @offset: The offset (in bytes) of the word(s) to read.
3444  *  @words: Size of data to read in words.
3445  *  @data: pointer to the word(s) to read at offset.
3446  *
3447  *  Reads a word(s) from the NVM
3448  **/
3449 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3450                               u16 *data)
3451 {
3452         struct e1000_nvm_info *nvm = &hw->nvm;
3453         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3454         u32 act_offset;
3455         s32 ret_val = E1000_SUCCESS;
3456         u32 bank = 0;
3457         u32 dword = 0;
3458         u16 offset_to_read;
3459         u16 i;
3460
3461         DEBUGFUNC("e1000_read_nvm_spt");
3462
3463         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3464             (words == 0)) {
3465                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3466                 ret_val = -E1000_ERR_NVM;
3467                 goto out;
3468         }
3469
3470         nvm->ops.acquire(hw);
3471
3472         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3473         if (ret_val != E1000_SUCCESS) {
3474                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3475                 bank = 0;
3476         }
3477
3478         act_offset = (bank) ? nvm->flash_bank_size : 0;
3479         act_offset += offset;
3480
3481         ret_val = E1000_SUCCESS;
3482
3483         for (i = 0; i < words; i += 2) {
3484                 if (words - i == 1) {
3485                         if (dev_spec->shadow_ram[offset + i].modified) {
3486                                 data[i] =
3487                                     dev_spec->shadow_ram[offset + i].value;
3488                         } else {
3489                                 offset_to_read = act_offset + i -
3490                                                  ((act_offset + i) % 2);
3491                                 ret_val =
3492                                    e1000_read_flash_dword_ich8lan(hw,
3493                                                                  offset_to_read,
3494                                                                  &dword);
3495                                 if (ret_val)
3496                                         break;
3497                                 if ((act_offset + i) % 2 == 0)
3498                                         data[i] = (u16)(dword & 0xFFFF);
3499                                 else
3500                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3501                         }
3502                 } else {
3503                         offset_to_read = act_offset + i;
3504                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3505                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3506                                 ret_val =
3507                                    e1000_read_flash_dword_ich8lan(hw,
3508                                                                  offset_to_read,
3509                                                                  &dword);
3510                                 if (ret_val)
3511                                         break;
3512                         }
3513                         if (dev_spec->shadow_ram[offset + i].modified)
3514                                 data[i] =
3515                                     dev_spec->shadow_ram[offset + i].value;
3516                         else
3517                                 data[i] = (u16)(dword & 0xFFFF);
3518                         if (dev_spec->shadow_ram[offset + i + 1].modified)
3519                                 data[i + 1] =
3520                                    dev_spec->shadow_ram[offset + i + 1].value;
3521                         else
3522                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3523                 }
3524         }
3525
3526         nvm->ops.release(hw);
3527
3528 out:
3529         if (ret_val)
3530                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3531
3532         return ret_val;
3533 }
3534
3535 /**
3536  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3537  *  @hw: pointer to the HW structure
3538  *  @offset: The offset (in bytes) of the word(s) to read.
3539  *  @words: Size of data to read in words
3540  *  @data: Pointer to the word(s) to read at offset.
3541  *
3542  *  Reads a word(s) from the NVM using the flash access registers.
3543  **/
3544 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3545                                   u16 *data)
3546 {
3547         struct e1000_nvm_info *nvm = &hw->nvm;
3548         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3549         u32 act_offset;
3550         s32 ret_val = E1000_SUCCESS;
3551         u32 bank = 0;
3552         u16 i, word;
3553
3554         DEBUGFUNC("e1000_read_nvm_ich8lan");
3555
3556         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3557             (words == 0)) {
3558                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3559                 ret_val = -E1000_ERR_NVM;
3560                 goto out;
3561         }
3562
3563         nvm->ops.acquire(hw);
3564
3565         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3566         if (ret_val != E1000_SUCCESS) {
3567                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3568                 bank = 0;
3569         }
3570
3571         act_offset = (bank) ? nvm->flash_bank_size : 0;
3572         act_offset += offset;
3573
3574         ret_val = E1000_SUCCESS;
3575         for (i = 0; i < words; i++) {
3576                 if (dev_spec->shadow_ram[offset + i].modified) {
3577                         data[i] = dev_spec->shadow_ram[offset + i].value;
3578                 } else {
3579                         ret_val = e1000_read_flash_word_ich8lan(hw,
3580                                                                 act_offset + i,
3581                                                                 &word);
3582                         if (ret_val)
3583                                 break;
3584                         data[i] = word;
3585                 }
3586         }
3587
3588         nvm->ops.release(hw);
3589
3590 out:
3591         if (ret_val)
3592                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3593
3594         return ret_val;
3595 }
3596
3597 /**
3598  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3599  *  @hw: pointer to the HW structure
3600  *
3601  *  This function does initial flash setup so that a new read/write/erase cycle
3602  *  can be started.
3603  **/
3604 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3605 {
3606         union ich8_hws_flash_status hsfsts;
3607         s32 ret_val = -E1000_ERR_NVM;
3608
3609         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3610
3611         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3612
3613         /* Check if the flash descriptor is valid */
3614         if (!hsfsts.hsf_status.fldesvalid) {
3615                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3616                 return -E1000_ERR_NVM;
3617         }
3618
3619         /* Clear FCERR and DAEL in hw status by writing 1 */
3620         hsfsts.hsf_status.flcerr = 1;
3621         hsfsts.hsf_status.dael = 1;
3622         if (hw->mac.type >= e1000_pch_spt)
3623                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3624                                       hsfsts.regval & 0xFFFF);
3625         else
3626                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3627
3628         /* Either we should have a hardware SPI cycle in progress
3629          * bit to check against, in order to start a new cycle or
3630          * FDONE bit should be changed in the hardware so that it
3631          * is 1 after hardware reset, which can then be used as an
3632          * indication whether a cycle is in progress or has been
3633          * completed.
3634          */
3635
3636         if (!hsfsts.hsf_status.flcinprog) {
3637                 /* There is no cycle running at present,
3638                  * so we can start a cycle.
3639                  * Begin by setting Flash Cycle Done.
3640                  */
3641                 hsfsts.hsf_status.flcdone = 1;
3642                 if (hw->mac.type >= e1000_pch_spt)
3643                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3644                                               hsfsts.regval & 0xFFFF);
3645                 else
3646                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3647                                                 hsfsts.regval);
3648                 ret_val = E1000_SUCCESS;
3649         } else {
3650                 s32 i;
3651
3652                 /* Otherwise poll for sometime so the current
3653                  * cycle has a chance to end before giving up.
3654                  */
3655                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3656                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3657                                                               ICH_FLASH_HSFSTS);
3658                         if (!hsfsts.hsf_status.flcinprog) {
3659                                 ret_val = E1000_SUCCESS;
3660                                 break;
3661                         }
3662                         usec_delay(1);
3663                 }
3664                 if (ret_val == E1000_SUCCESS) {
3665                         /* Successful in waiting for previous cycle to timeout,
3666                          * now set the Flash Cycle Done.
3667                          */
3668                         hsfsts.hsf_status.flcdone = 1;
3669                         if (hw->mac.type >= e1000_pch_spt)
3670                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3671                                                       hsfsts.regval & 0xFFFF);
3672                         else
3673                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3674                                                         hsfsts.regval);
3675                 } else {
3676                         DEBUGOUT("Flash controller busy, cannot get access\n");
3677                 }
3678         }
3679
3680         return ret_val;
3681 }
3682
3683 /**
3684  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3685  *  @hw: pointer to the HW structure
3686  *  @timeout: maximum time to wait for completion
3687  *
3688  *  This function starts a flash cycle and waits for its completion.
3689  **/
3690 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3691 {
3692         union ich8_hws_flash_ctrl hsflctl;
3693         union ich8_hws_flash_status hsfsts;
3694         u32 i = 0;
3695
3696         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3697
3698         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3699         if (hw->mac.type >= e1000_pch_spt)
3700                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3701         else
3702                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3703         hsflctl.hsf_ctrl.flcgo = 1;
3704
3705         if (hw->mac.type >= e1000_pch_spt)
3706                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3707                                       hsflctl.regval << 16);
3708         else
3709                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3710
3711         /* wait till FDONE bit is set to 1 */
3712         do {
3713                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3714                 if (hsfsts.hsf_status.flcdone)
3715                         break;
3716                 usec_delay(1);
3717         } while (i++ < timeout);
3718
3719         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3720                 return E1000_SUCCESS;
3721
3722         return -E1000_ERR_NVM;
3723 }
3724
3725 /**
3726  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3727  *  @hw: pointer to the HW structure
3728  *  @offset: offset to data location
3729  *  @data: pointer to the location for storing the data
3730  *
3731  *  Reads the flash dword at offset into data.  Offset is converted
3732  *  to bytes before read.
3733  **/
3734 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3735                                           u32 *data)
3736 {
3737         DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3738
3739         if (!data)
3740                 return -E1000_ERR_NVM;
3741
3742         /* Must convert word offset into bytes. */
3743         offset <<= 1;
3744
3745         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3746 }
3747
3748 /**
3749  *  e1000_read_flash_word_ich8lan - Read word from flash
3750  *  @hw: pointer to the HW structure
3751  *  @offset: offset to data location
3752  *  @data: pointer to the location for storing the data
3753  *
3754  *  Reads the flash word at offset into data.  Offset is converted
3755  *  to bytes before read.
3756  **/
3757 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3758                                          u16 *data)
3759 {
3760         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3761
3762         if (!data)
3763                 return -E1000_ERR_NVM;
3764
3765         /* Must convert offset into bytes. */
3766         offset <<= 1;
3767
3768         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3769 }
3770
3771 /**
3772  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3773  *  @hw: pointer to the HW structure
3774  *  @offset: The offset of the byte to read.
3775  *  @data: Pointer to a byte to store the value read.
3776  *
3777  *  Reads a single byte from the NVM using the flash access registers.
3778  **/
3779 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3780                                          u8 *data)
3781 {
3782         s32 ret_val;
3783         u16 word = 0;
3784
3785         /* In SPT, only 32 bits access is supported,
3786          * so this function should not be called.
3787          */
3788         if (hw->mac.type >= e1000_pch_spt)
3789                 return -E1000_ERR_NVM;
3790         else
3791                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3792
3793         if (ret_val)
3794                 return ret_val;
3795
3796         *data = (u8)word;
3797
3798         return E1000_SUCCESS;
3799 }
3800
3801 /**
3802  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3803  *  @hw: pointer to the HW structure
3804  *  @offset: The offset (in bytes) of the byte or word to read.
3805  *  @size: Size of data to read, 1=byte 2=word
3806  *  @data: Pointer to the word to store the value read.
3807  *
3808  *  Reads a byte or word from the NVM using the flash access registers.
3809  **/
3810 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3811                                          u8 size, u16 *data)
3812 {
3813         union ich8_hws_flash_status hsfsts;
3814         union ich8_hws_flash_ctrl hsflctl;
3815         u32 flash_linear_addr;
3816         u32 flash_data = 0;
3817         s32 ret_val = -E1000_ERR_NVM;
3818         u8 count = 0;
3819
3820         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3821
3822         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3823                 return -E1000_ERR_NVM;
3824         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3825                              hw->nvm.flash_base_addr);
3826
3827         do {
3828                 usec_delay(1);
3829                 /* Steps */
3830                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3831                 if (ret_val != E1000_SUCCESS)
3832                         break;
3833                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3834
3835                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3836                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3837                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3838                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3839                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3840
3841                 ret_val = e1000_flash_cycle_ich8lan(hw,
3842                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3843
3844                 /* Check if FCERR is set to 1, if set to 1, clear it
3845                  * and try the whole sequence a few more times, else
3846                  * read in (shift in) the Flash Data0, the order is
3847                  * least significant byte first msb to lsb
3848                  */
3849                 if (ret_val == E1000_SUCCESS) {
3850                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3851                         if (size == 1)
3852                                 *data = (u8)(flash_data & 0x000000FF);
3853                         else if (size == 2)
3854                                 *data = (u16)(flash_data & 0x0000FFFF);
3855                         break;
3856                 } else {
3857                         /* If we've gotten here, then things are probably
3858                          * completely hosed, but if the error condition is
3859                          * detected, it won't hurt to give it another try...
3860                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3861                          */
3862                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3863                                                               ICH_FLASH_HSFSTS);
3864                         if (hsfsts.hsf_status.flcerr) {
3865                                 /* Repeat for some time before giving up. */
3866                                 continue;
3867                         } else if (!hsfsts.hsf_status.flcdone) {
3868                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3869                                 break;
3870                         }
3871                 }
3872         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3873
3874         return ret_val;
3875 }
3876
3877 /**
3878  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3879  *  @hw: pointer to the HW structure
3880  *  @offset: The offset (in bytes) of the dword to read.
3881  *  @data: Pointer to the dword to store the value read.
3882  *
3883  *  Reads a byte or word from the NVM using the flash access registers.
3884  **/
3885 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3886                                            u32 *data)
3887 {
3888         union ich8_hws_flash_status hsfsts;
3889         union ich8_hws_flash_ctrl hsflctl;
3890         u32 flash_linear_addr;
3891         s32 ret_val = -E1000_ERR_NVM;
3892         u8 count = 0;
3893
3894         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3895
3896                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3897                     hw->mac.type < e1000_pch_spt)
3898                         return -E1000_ERR_NVM;
3899         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3900                              hw->nvm.flash_base_addr);
3901
3902         do {
3903                 usec_delay(1);
3904                 /* Steps */
3905                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3906                 if (ret_val != E1000_SUCCESS)
3907                         break;
3908                 /* In SPT, This register is in Lan memory space, not flash.
3909                  * Therefore, only 32 bit access is supported
3910                  */
3911                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3912
3913                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3914                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3915                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3916                 /* In SPT, This register is in Lan memory space, not flash.
3917                  * Therefore, only 32 bit access is supported
3918                  */
3919                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3920                                       (u32)hsflctl.regval << 16);
3921                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3922
3923                 ret_val = e1000_flash_cycle_ich8lan(hw,
3924                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3925
3926                 /* Check if FCERR is set to 1, if set to 1, clear it
3927                  * and try the whole sequence a few more times, else
3928                  * read in (shift in) the Flash Data0, the order is
3929                  * least significant byte first msb to lsb
3930                  */
3931                 if (ret_val == E1000_SUCCESS) {
3932                         *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3933                         break;
3934                 } else {
3935                         /* If we've gotten here, then things are probably
3936                          * completely hosed, but if the error condition is
3937                          * detected, it won't hurt to give it another try...
3938                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3939                          */
3940                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3941                                                               ICH_FLASH_HSFSTS);
3942                         if (hsfsts.hsf_status.flcerr) {
3943                                 /* Repeat for some time before giving up. */
3944                                 continue;
3945                         } else if (!hsfsts.hsf_status.flcdone) {
3946                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3947                                 break;
3948                         }
3949                 }
3950         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3951
3952         return ret_val;
3953 }
3954
3955 /**
3956  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3957  *  @hw: pointer to the HW structure
3958  *  @offset: The offset (in bytes) of the word(s) to write.
3959  *  @words: Size of data to write in words
3960  *  @data: Pointer to the word(s) to write at offset.
3961  *
3962  *  Writes a byte or word to the NVM using the flash access registers.
3963  **/
3964 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3965                                    u16 *data)
3966 {
3967         struct e1000_nvm_info *nvm = &hw->nvm;
3968         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3969         u16 i;
3970
3971         DEBUGFUNC("e1000_write_nvm_ich8lan");
3972
3973         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3974             (words == 0)) {
3975                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3976                 return -E1000_ERR_NVM;
3977         }
3978
3979         nvm->ops.acquire(hw);
3980
3981         for (i = 0; i < words; i++) {
3982                 dev_spec->shadow_ram[offset + i].modified = true;
3983                 dev_spec->shadow_ram[offset + i].value = data[i];
3984         }
3985
3986         nvm->ops.release(hw);
3987
3988         return E1000_SUCCESS;
3989 }
3990
3991 /**
3992  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3993  *  @hw: pointer to the HW structure
3994  *
3995  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3996  *  which writes the checksum to the shadow ram.  The changes in the shadow
3997  *  ram are then committed to the EEPROM by processing each bank at a time
3998  *  checking for the modified bit and writing only the pending changes.
3999  *  After a successful commit, the shadow ram is cleared and is ready for
4000  *  future writes.
4001  **/
4002 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4003 {
4004         struct e1000_nvm_info *nvm = &hw->nvm;
4005         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4006         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4007         s32 ret_val;
4008         u32 dword = 0;
4009
4010         DEBUGFUNC("e1000_update_nvm_checksum_spt");
4011
4012         ret_val = e1000_update_nvm_checksum_generic(hw);
4013         if (ret_val)
4014                 goto out;
4015
4016         if (nvm->type != e1000_nvm_flash_sw)
4017                 goto out;
4018
4019         nvm->ops.acquire(hw);
4020
4021         /* We're writing to the opposite bank so if we're on bank 1,
4022          * write to bank 0 etc.  We also need to erase the segment that
4023          * is going to be written
4024          */
4025         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4026         if (ret_val != E1000_SUCCESS) {
4027                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4028                 bank = 0;
4029         }
4030
4031         if (bank == 0) {
4032                 new_bank_offset = nvm->flash_bank_size;
4033                 old_bank_offset = 0;
4034                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4035                 if (ret_val)
4036                         goto release;
4037         } else {
4038                 old_bank_offset = nvm->flash_bank_size;
4039                 new_bank_offset = 0;
4040                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4041                 if (ret_val)
4042                         goto release;
4043         }
4044         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4045                 /* Determine whether to write the value stored
4046                  * in the other NVM bank or a modified value stored
4047                  * in the shadow RAM
4048                  */
4049                 ret_val = e1000_read_flash_dword_ich8lan(hw,
4050                                                          i + old_bank_offset,
4051                                                          &dword);
4052
4053                 if (dev_spec->shadow_ram[i].modified) {
4054                         dword &= 0xffff0000;
4055                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4056                 }
4057                 if (dev_spec->shadow_ram[i + 1].modified) {
4058                         dword &= 0x0000ffff;
4059                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4060                                   << 16);
4061                 }
4062                 if (ret_val)
4063                         break;
4064
4065                 /* If the word is 0x13, then make sure the signature bits
4066                  * (15:14) are 11b until the commit has completed.
4067                  * This will allow us to write 10b which indicates the
4068                  * signature is valid.  We want to do this after the write
4069                  * has completed so that we don't mark the segment valid
4070                  * while the write is still in progress
4071                  */
4072                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4073                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
4074
4075                 /* Convert offset to bytes. */
4076                 act_offset = (i + new_bank_offset) << 1;
4077
4078                 usec_delay(100);
4079
4080                 /* Write the data to the new bank. Offset in words*/
4081                 act_offset = i + new_bank_offset;
4082                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4083                                                                 dword);
4084                 if (ret_val)
4085                         break;
4086          }
4087
4088         /* Don't bother writing the segment valid bits if sector
4089          * programming failed.
4090          */
4091         if (ret_val) {
4092                 DEBUGOUT("Flash commit failed.\n");
4093                 goto release;
4094         }
4095
4096         /* Finally validate the new segment by setting bit 15:14
4097          * to 10b in word 0x13 , this can be done without an
4098          * erase as well since these bits are 11 to start with
4099          * and we need to change bit 14 to 0b
4100          */
4101         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4102
4103         /*offset in words but we read dword*/
4104         --act_offset;
4105         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4106
4107         if (ret_val)
4108                 goto release;
4109
4110         dword &= 0xBFFFFFFF;
4111         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4112
4113         if (ret_val)
4114                 goto release;
4115
4116         /* offset in words but we read dword*/
4117         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4118         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4119
4120         if (ret_val)
4121                 goto release;
4122
4123         dword &= 0x00FFFFFF;
4124         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4125
4126         if (ret_val)
4127                 goto release;
4128
4129         /* Great!  Everything worked, we can now clear the cached entries. */
4130         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4131                 dev_spec->shadow_ram[i].modified = false;
4132                 dev_spec->shadow_ram[i].value = 0xFFFF;
4133         }
4134
4135 release:
4136         nvm->ops.release(hw);
4137
4138         /* Reload the EEPROM, or else modifications will not appear
4139          * until after the next adapter reset.
4140          */
4141         if (!ret_val) {
4142                 nvm->ops.reload(hw);
4143                 msec_delay(10);
4144         }
4145
4146 out:
4147         if (ret_val)
4148                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4149
4150         return ret_val;
4151 }
4152
4153 /**
4154  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4155  *  @hw: pointer to the HW structure
4156  *
4157  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4158  *  which writes the checksum to the shadow ram.  The changes in the shadow
4159  *  ram are then committed to the EEPROM by processing each bank at a time
4160  *  checking for the modified bit and writing only the pending changes.
4161  *  After a successful commit, the shadow ram is cleared and is ready for
4162  *  future writes.
4163  **/
4164 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4165 {
4166         struct e1000_nvm_info *nvm = &hw->nvm;
4167         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4168         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4169         s32 ret_val;
4170         u16 data = 0;
4171
4172         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4173
4174         ret_val = e1000_update_nvm_checksum_generic(hw);
4175         if (ret_val)
4176                 goto out;
4177
4178         if (nvm->type != e1000_nvm_flash_sw)
4179                 goto out;
4180
4181         nvm->ops.acquire(hw);
4182
4183         /* We're writing to the opposite bank so if we're on bank 1,
4184          * write to bank 0 etc.  We also need to erase the segment that
4185          * is going to be written
4186          */
4187         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4188         if (ret_val != E1000_SUCCESS) {
4189                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4190                 bank = 0;
4191         }
4192
4193         if (bank == 0) {
4194                 new_bank_offset = nvm->flash_bank_size;
4195                 old_bank_offset = 0;
4196                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4197                 if (ret_val)
4198                         goto release;
4199         } else {
4200                 old_bank_offset = nvm->flash_bank_size;
4201                 new_bank_offset = 0;
4202                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4203                 if (ret_val)
4204                         goto release;
4205         }
4206         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4207                 if (dev_spec->shadow_ram[i].modified) {
4208                         data = dev_spec->shadow_ram[i].value;
4209                 } else {
4210                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
4211                                                                 old_bank_offset,
4212                                                                 &data);
4213                         if (ret_val)
4214                                 break;
4215                 }
4216                 /* If the word is 0x13, then make sure the signature bits
4217                  * (15:14) are 11b until the commit has completed.
4218                  * This will allow us to write 10b which indicates the
4219                  * signature is valid.  We want to do this after the write
4220                  * has completed so that we don't mark the segment valid
4221                  * while the write is still in progress
4222                  */
4223                 if (i == E1000_ICH_NVM_SIG_WORD)
4224                         data |= E1000_ICH_NVM_SIG_MASK;
4225
4226                 /* Convert offset to bytes. */
4227                 act_offset = (i + new_bank_offset) << 1;
4228
4229                 usec_delay(100);
4230
4231                 /* Write the bytes to the new bank. */
4232                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4233                                                                act_offset,
4234                                                                (u8)data);
4235                 if (ret_val)
4236                         break;
4237
4238                 usec_delay(100);
4239                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4240                                                           act_offset + 1,
4241                                                           (u8)(data >> 8));
4242                 if (ret_val)
4243                         break;
4244         }
4245
4246         /* Don't bother writing the segment valid bits if sector
4247          * programming failed.
4248          */
4249         if (ret_val) {
4250                 DEBUGOUT("Flash commit failed.\n");
4251                 goto release;
4252         }
4253
4254         /* Finally validate the new segment by setting bit 15:14
4255          * to 10b in word 0x13 , this can be done without an
4256          * erase as well since these bits are 11 to start with
4257          * and we need to change bit 14 to 0b
4258          */
4259         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4260         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4261         if (ret_val)
4262                 goto release;
4263
4264         data &= 0xBFFF;
4265         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4266                                                        (u8)(data >> 8));
4267         if (ret_val)
4268                 goto release;
4269
4270         /* And invalidate the previously valid segment by setting
4271          * its signature word (0x13) high_byte to 0b. This can be
4272          * done without an erase because flash erase sets all bits
4273          * to 1's. We can write 1's to 0's without an erase
4274          */
4275         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4276
4277         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4278
4279         if (ret_val)
4280                 goto release;
4281
4282         /* Great!  Everything worked, we can now clear the cached entries. */
4283         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4284                 dev_spec->shadow_ram[i].modified = false;
4285                 dev_spec->shadow_ram[i].value = 0xFFFF;
4286         }
4287
4288 release:
4289         nvm->ops.release(hw);
4290
4291         /* Reload the EEPROM, or else modifications will not appear
4292          * until after the next adapter reset.
4293          */
4294         if (!ret_val) {
4295                 nvm->ops.reload(hw);
4296                 msec_delay(10);
4297         }
4298
4299 out:
4300         if (ret_val)
4301                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4302
4303         return ret_val;
4304 }
4305
4306 /**
4307  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4308  *  @hw: pointer to the HW structure
4309  *
4310  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4311  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4312  *  calculated, in which case we need to calculate the checksum and set bit 6.
4313  **/
4314 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4315 {
4316         s32 ret_val;
4317         u16 data;
4318         u16 word;
4319         u16 valid_csum_mask;
4320
4321         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4322
4323         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4324          * the checksum needs to be fixed.  This bit is an indication that
4325          * the NVM was prepared by OEM software and did not calculate
4326          * the checksum...a likely scenario.
4327          */
4328         switch (hw->mac.type) {
4329         case e1000_pch_lpt:
4330         case e1000_pch_spt:
4331         case e1000_pch_cnp:
4332                 word = NVM_COMPAT;
4333                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4334                 break;
4335         default:
4336                 word = NVM_FUTURE_INIT_WORD1;
4337                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4338                 break;
4339         }
4340
4341         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4342         if (ret_val)
4343                 return ret_val;
4344
4345         if (!(data & valid_csum_mask)) {
4346                 data |= valid_csum_mask;
4347                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4348                 if (ret_val)
4349                         return ret_val;
4350                 ret_val = hw->nvm.ops.update(hw);
4351                 if (ret_val)
4352                         return ret_val;
4353         }
4354
4355         return e1000_validate_nvm_checksum_generic(hw);
4356 }
4357
4358 /**
4359  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4360  *  @hw: pointer to the HW structure
4361  *  @offset: The offset (in bytes) of the byte/word to read.
4362  *  @size: Size of data to read, 1=byte 2=word
4363  *  @data: The byte(s) to write to the NVM.
4364  *
4365  *  Writes one/two bytes to the NVM using the flash access registers.
4366  **/
4367 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4368                                           u8 size, u16 data)
4369 {
4370         union ich8_hws_flash_status hsfsts;
4371         union ich8_hws_flash_ctrl hsflctl;
4372         u32 flash_linear_addr;
4373         u32 flash_data = 0;
4374         s32 ret_val;
4375         u8 count = 0;
4376
4377         DEBUGFUNC("e1000_write_ich8_data");
4378
4379         if (hw->mac.type >= e1000_pch_spt) {
4380                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4381                         return -E1000_ERR_NVM;
4382         } else {
4383                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4384                         return -E1000_ERR_NVM;
4385         }
4386
4387         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4388                              hw->nvm.flash_base_addr);
4389
4390         do {
4391                 usec_delay(1);
4392                 /* Steps */
4393                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4394                 if (ret_val != E1000_SUCCESS)
4395                         break;
4396                 /* In SPT, This register is in Lan memory space, not
4397                  * flash.  Therefore, only 32 bit access is supported
4398                  */
4399                 if (hw->mac.type >= e1000_pch_spt)
4400                         hsflctl.regval =
4401                             E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4402                 else
4403                         hsflctl.regval =
4404                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4405
4406                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4407                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4408                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4409                 /* In SPT, This register is in Lan memory space,
4410                  * not flash.  Therefore, only 32 bit access is
4411                  * supported
4412                  */
4413                 if (hw->mac.type >= e1000_pch_spt)
4414                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4415                                               hsflctl.regval << 16);
4416                 else
4417                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4418                                                 hsflctl.regval);
4419
4420                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4421
4422                 if (size == 1)
4423                         flash_data = (u32)data & 0x00FF;
4424                 else
4425                         flash_data = (u32)data;
4426
4427                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4428
4429                 /* check if FCERR is set to 1 , if set to 1, clear it
4430                  * and try the whole sequence a few more times else done
4431                  */
4432                 ret_val =
4433                     e1000_flash_cycle_ich8lan(hw,
4434                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4435                 if (ret_val == E1000_SUCCESS)
4436                         break;
4437
4438                 /* If we're here, then things are most likely
4439                  * completely hosed, but if the error condition
4440                  * is detected, it won't hurt to give it another
4441                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4442                  */
4443                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4444                 if (hsfsts.hsf_status.flcerr)
4445                         /* Repeat for some time before giving up. */
4446                         continue;
4447                 if (!hsfsts.hsf_status.flcdone) {
4448                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4449                         break;
4450                 }
4451         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4452
4453         return ret_val;
4454 }
4455
4456 /**
4457 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4458 *  @hw: pointer to the HW structure
4459 *  @offset: The offset (in bytes) of the dwords to read.
4460 *  @data: The 4 bytes to write to the NVM.
4461 *
4462 *  Writes one/two/four bytes to the NVM using the flash access registers.
4463 **/
4464 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4465                                             u32 data)
4466 {
4467         union ich8_hws_flash_status hsfsts;
4468         union ich8_hws_flash_ctrl hsflctl;
4469         u32 flash_linear_addr;
4470         s32 ret_val;
4471         u8 count = 0;
4472
4473         DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4474
4475         if (hw->mac.type >= e1000_pch_spt) {
4476                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4477                         return -E1000_ERR_NVM;
4478         }
4479         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4480                              hw->nvm.flash_base_addr);
4481         do {
4482                 usec_delay(1);
4483                 /* Steps */
4484                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4485                 if (ret_val != E1000_SUCCESS)
4486                         break;
4487
4488                 /* In SPT, This register is in Lan memory space, not
4489                  * flash.  Therefore, only 32 bit access is supported
4490                  */
4491                 if (hw->mac.type >= e1000_pch_spt)
4492                         hsflctl.regval = E1000_READ_FLASH_REG(hw,
4493                                                               ICH_FLASH_HSFSTS)
4494                                          >> 16;
4495                 else
4496                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4497                                                               ICH_FLASH_HSFCTL);
4498
4499                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4500                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4501
4502                 /* In SPT, This register is in Lan memory space,
4503                  * not flash.  Therefore, only 32 bit access is
4504                  * supported
4505                  */
4506                 if (hw->mac.type >= e1000_pch_spt)
4507                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4508                                               hsflctl.regval << 16);
4509                 else
4510                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4511                                                 hsflctl.regval);
4512
4513                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4514
4515                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4516
4517                 /* check if FCERR is set to 1 , if set to 1, clear it
4518                  * and try the whole sequence a few more times else done
4519                  */
4520                 ret_val = e1000_flash_cycle_ich8lan(hw,
4521                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4522
4523                 if (ret_val == E1000_SUCCESS)
4524                         break;
4525
4526                 /* If we're here, then things are most likely
4527                  * completely hosed, but if the error condition
4528                  * is detected, it won't hurt to give it another
4529                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4530                  */
4531                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4532
4533                 if (hsfsts.hsf_status.flcerr)
4534                         /* Repeat for some time before giving up. */
4535                         continue;
4536                 if (!hsfsts.hsf_status.flcdone) {
4537                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4538                         break;
4539                 }
4540         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4541
4542         return ret_val;
4543 }
4544
4545 /**
4546  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4547  *  @hw: pointer to the HW structure
4548  *  @offset: The index of the byte to read.
4549  *  @data: The byte to write to the NVM.
4550  *
4551  *  Writes a single byte to the NVM using the flash access registers.
4552  **/
4553 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4554                                           u8 data)
4555 {
4556         u16 word = (u16)data;
4557
4558         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4559
4560         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4561 }
4562
4563 /**
4564 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4565 *  @hw: pointer to the HW structure
4566 *  @offset: The offset of the word to write.
4567 *  @dword: The dword to write to the NVM.
4568 *
4569 *  Writes a single dword to the NVM using the flash access registers.
4570 *  Goes through a retry algorithm before giving up.
4571 **/
4572 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4573                                                  u32 offset, u32 dword)
4574 {
4575         s32 ret_val;
4576         u16 program_retries;
4577
4578         DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4579
4580         /* Must convert word offset into bytes. */
4581         offset <<= 1;
4582
4583         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4584
4585         if (!ret_val)
4586                 return ret_val;
4587         for (program_retries = 0; program_retries < 100; program_retries++) {
4588                 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4589                 usec_delay(100);
4590                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4591                 if (ret_val == E1000_SUCCESS)
4592                         break;
4593         }
4594         if (program_retries == 100)
4595                 return -E1000_ERR_NVM;
4596
4597         return E1000_SUCCESS;
4598 }
4599
4600 /**
4601  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4602  *  @hw: pointer to the HW structure
4603  *  @offset: The offset of the byte to write.
4604  *  @byte: The byte to write to the NVM.
4605  *
4606  *  Writes a single byte to the NVM using the flash access registers.
4607  *  Goes through a retry algorithm before giving up.
4608  **/
4609 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4610                                                 u32 offset, u8 byte)
4611 {
4612         s32 ret_val;
4613         u16 program_retries;
4614
4615         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4616
4617         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4618         if (!ret_val)
4619                 return ret_val;
4620
4621         for (program_retries = 0; program_retries < 100; program_retries++) {
4622                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4623                 usec_delay(100);
4624                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4625                 if (ret_val == E1000_SUCCESS)
4626                         break;
4627         }
4628         if (program_retries == 100)
4629                 return -E1000_ERR_NVM;
4630
4631         return E1000_SUCCESS;
4632 }
4633
4634 /**
4635  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4636  *  @hw: pointer to the HW structure
4637  *  @bank: 0 for first bank, 1 for second bank, etc.
4638  *
4639  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4640  *  bank N is 4096 * N + flash_reg_addr.
4641  **/
4642 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4643 {
4644         struct e1000_nvm_info *nvm = &hw->nvm;
4645         union ich8_hws_flash_status hsfsts;
4646         union ich8_hws_flash_ctrl hsflctl;
4647         u32 flash_linear_addr;
4648         /* bank size is in 16bit words - adjust to bytes */
4649         u32 flash_bank_size = nvm->flash_bank_size * 2;
4650         s32 ret_val;
4651         s32 count = 0;
4652         s32 j, iteration, sector_size;
4653
4654         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4655
4656         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4657
4658         /* Determine HW Sector size: Read BERASE bits of hw flash status
4659          * register
4660          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4661          *     consecutive sectors.  The start index for the nth Hw sector
4662          *     can be calculated as = bank * 4096 + n * 256
4663          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4664          *     The start index for the nth Hw sector can be calculated
4665          *     as = bank * 4096
4666          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4667          *     (ich9 only, otherwise error condition)
4668          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4669          */
4670         switch (hsfsts.hsf_status.berasesz) {
4671         case 0:
4672                 /* Hw sector size 256 */
4673                 sector_size = ICH_FLASH_SEG_SIZE_256;
4674                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4675                 break;
4676         case 1:
4677                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4678                 iteration = 1;
4679                 break;
4680         case 2:
4681                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4682                 iteration = 1;
4683                 break;
4684         case 3:
4685                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4686                 iteration = 1;
4687                 break;
4688         default:
4689                 return -E1000_ERR_NVM;
4690         }
4691
4692         /* Start with the base address, then add the sector offset. */
4693         flash_linear_addr = hw->nvm.flash_base_addr;
4694         flash_linear_addr += (bank) ? flash_bank_size : 0;
4695
4696         for (j = 0; j < iteration; j++) {
4697                 do {
4698                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4699
4700                         /* Steps */
4701                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4702                         if (ret_val)
4703                                 return ret_val;
4704
4705                         /* Write a value 11 (block Erase) in Flash
4706                          * Cycle field in hw flash control
4707                          */
4708                         if (hw->mac.type >= e1000_pch_spt)
4709                                 hsflctl.regval =
4710                                     E1000_READ_FLASH_REG(hw,
4711                                                          ICH_FLASH_HSFSTS)>>16;
4712                         else
4713                                 hsflctl.regval =
4714                                     E1000_READ_FLASH_REG16(hw,
4715                                                            ICH_FLASH_HSFCTL);
4716
4717                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4718                         if (hw->mac.type >= e1000_pch_spt)
4719                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4720                                                       hsflctl.regval << 16);
4721                         else
4722                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4723                                                         hsflctl.regval);
4724
4725                         /* Write the last 24 bits of an index within the
4726                          * block into Flash Linear address field in Flash
4727                          * Address.
4728                          */
4729                         flash_linear_addr += (j * sector_size);
4730                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4731                                               flash_linear_addr);
4732
4733                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4734                         if (ret_val == E1000_SUCCESS)
4735                                 break;
4736
4737                         /* Check if FCERR is set to 1.  If 1,
4738                          * clear it and try the whole sequence
4739                          * a few more times else Done
4740                          */
4741                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4742                                                       ICH_FLASH_HSFSTS);
4743                         if (hsfsts.hsf_status.flcerr)
4744                                 /* repeat for some time before giving up */
4745                                 continue;
4746                         else if (!hsfsts.hsf_status.flcdone)
4747                                 return ret_val;
4748                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4749         }
4750
4751         return E1000_SUCCESS;
4752 }
4753
4754 /**
4755  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4756  *  @hw: pointer to the HW structure
4757  *  @data: Pointer to the LED settings
4758  *
4759  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4760  *  settings is all 0's or F's, set the LED default to a valid LED default
4761  *  setting.
4762  **/
4763 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4764 {
4765         s32 ret_val;
4766
4767         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4768
4769         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4770         if (ret_val) {
4771                 DEBUGOUT("NVM Read Error\n");
4772                 return ret_val;
4773         }
4774
4775         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4776                 *data = ID_LED_DEFAULT_ICH8LAN;
4777
4778         return E1000_SUCCESS;
4779 }
4780
4781 /**
4782  *  e1000_id_led_init_pchlan - store LED configurations
4783  *  @hw: pointer to the HW structure
4784  *
4785  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4786  *  the PHY LED configuration register.
4787  *
4788  *  PCH also does not have an "always on" or "always off" mode which
4789  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4790  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4791  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4792  *  link based on logic in e1000_led_[on|off]_pchlan().
4793  **/
4794 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4795 {
4796         struct e1000_mac_info *mac = &hw->mac;
4797         s32 ret_val;
4798         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4799         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4800         u16 data, i, temp, shift;
4801
4802         DEBUGFUNC("e1000_id_led_init_pchlan");
4803
4804         /* Get default ID LED modes */
4805         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4806         if (ret_val)
4807                 return ret_val;
4808
4809         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4810         mac->ledctl_mode1 = mac->ledctl_default;
4811         mac->ledctl_mode2 = mac->ledctl_default;
4812
4813         for (i = 0; i < 4; i++) {
4814                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4815                 shift = (i * 5);
4816                 switch (temp) {
4817                 case ID_LED_ON1_DEF2:
4818                 case ID_LED_ON1_ON2:
4819                 case ID_LED_ON1_OFF2:
4820                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4821                         mac->ledctl_mode1 |= (ledctl_on << shift);
4822                         break;
4823                 case ID_LED_OFF1_DEF2:
4824                 case ID_LED_OFF1_ON2:
4825                 case ID_LED_OFF1_OFF2:
4826                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4827                         mac->ledctl_mode1 |= (ledctl_off << shift);
4828                         break;
4829                 default:
4830                         /* Do nothing */
4831                         break;
4832                 }
4833                 switch (temp) {
4834                 case ID_LED_DEF1_ON2:
4835                 case ID_LED_ON1_ON2:
4836                 case ID_LED_OFF1_ON2:
4837                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4838                         mac->ledctl_mode2 |= (ledctl_on << shift);
4839                         break;
4840                 case ID_LED_DEF1_OFF2:
4841                 case ID_LED_ON1_OFF2:
4842                 case ID_LED_OFF1_OFF2:
4843                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4844                         mac->ledctl_mode2 |= (ledctl_off << shift);
4845                         break;
4846                 default:
4847                         /* Do nothing */
4848                         break;
4849                 }
4850         }
4851
4852         return E1000_SUCCESS;
4853 }
4854
4855 /**
4856  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4857  *  @hw: pointer to the HW structure
4858  *
4859  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4860  *  register, so the bus width is hard coded.
4861  **/
4862 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4863 {
4864         struct e1000_bus_info *bus = &hw->bus;
4865         s32 ret_val;
4866
4867         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4868
4869         ret_val = e1000_get_bus_info_pcie_generic(hw);
4870
4871         /* ICH devices are "PCI Express"-ish.  They have
4872          * a configuration space, but do not contain
4873          * PCI Express Capability registers, so bus width
4874          * must be hardcoded.
4875          */
4876         if (bus->width == e1000_bus_width_unknown)
4877                 bus->width = e1000_bus_width_pcie_x1;
4878
4879         return ret_val;
4880 }
4881
4882 /**
4883  *  e1000_reset_hw_ich8lan - Reset the hardware
4884  *  @hw: pointer to the HW structure
4885  *
4886  *  Does a full reset of the hardware which includes a reset of the PHY and
4887  *  MAC.
4888  **/
4889 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4890 {
4891         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4892         u16 kum_cfg;
4893         u32 ctrl, reg;
4894         s32 ret_val;
4895         u16 pci_cfg;
4896
4897         DEBUGFUNC("e1000_reset_hw_ich8lan");
4898
4899         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4900          * on the last TLP read/write transaction when MAC is reset.
4901          */
4902         ret_val = e1000_disable_pcie_master_generic(hw);
4903         if (ret_val)
4904                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4905
4906         DEBUGOUT("Masking off all interrupts\n");
4907         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4908
4909         /* Disable the Transmit and Receive units.  Then delay to allow
4910          * any pending transactions to complete before we hit the MAC
4911          * with the global reset.
4912          */
4913         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4914         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4915         E1000_WRITE_FLUSH(hw);
4916
4917         msec_delay(10);
4918
4919         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4920         if (hw->mac.type == e1000_ich8lan) {
4921                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4922                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4923                 /* Set Packet Buffer Size to 16k. */
4924                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4925         }
4926
4927         if (hw->mac.type == e1000_pchlan) {
4928                 /* Save the NVM K1 bit setting*/
4929                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4930                 if (ret_val)
4931                         return ret_val;
4932
4933                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4934                         dev_spec->nvm_k1_enabled = true;
4935                 else
4936                         dev_spec->nvm_k1_enabled = false;
4937         }
4938
4939         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4940
4941         if (!hw->phy.ops.check_reset_block(hw)) {
4942                 /* Full-chip reset requires MAC and PHY reset at the same
4943                  * time to make sure the interface between MAC and the
4944                  * external PHY is reset.
4945                  */
4946                 ctrl |= E1000_CTRL_PHY_RST;
4947
4948                 /* Gate automatic PHY configuration by hardware on
4949                  * non-managed 82579
4950                  */
4951                 if ((hw->mac.type == e1000_pch2lan) &&
4952                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4953                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4954         }
4955         ret_val = e1000_acquire_swflag_ich8lan(hw);
4956
4957         /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
4958          * may occur during global reset and cause system hang.
4959          * Configuration space access creates the needed delay.
4960          * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
4961          * insures configuration space read is done before global reset.
4962          */
4963         e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4964         E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4965         DEBUGOUT("Issuing a global reset to ich8lan\n");
4966         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4967         /* cannot issue a flush here because it hangs the hardware */
4968         msec_delay(20);
4969
4970         /* Configuration space access improve HW level time sync mechanism.
4971          * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
4972          * value to insure configuration space read is done
4973          * before any access to mac register.
4974          */
4975         e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4976         E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4977
4978         /* Set Phy Config Counter to 50msec */
4979         if (hw->mac.type == e1000_pch2lan) {
4980                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4981                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4982                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4983                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4984         }
4985
4986         if (!ret_val)
4987                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4988
4989         if (ctrl & E1000_CTRL_PHY_RST) {
4990                 ret_val = hw->phy.ops.get_cfg_done(hw);
4991                 if (ret_val)
4992                         return ret_val;
4993
4994                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4995                 if (ret_val)
4996                         return ret_val;
4997         }
4998
4999         /* For PCH, this write will make sure that any noise
5000          * will be detected as a CRC error and be dropped rather than show up
5001          * as a bad packet to the DMA engine.
5002          */
5003         if (hw->mac.type == e1000_pchlan)
5004                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5005
5006         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5007         E1000_READ_REG(hw, E1000_ICR);
5008
5009         reg = E1000_READ_REG(hw, E1000_KABGTXD);
5010         reg |= E1000_KABGTXD_BGSQLBIAS;
5011         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5012
5013         return E1000_SUCCESS;
5014 }
5015
5016 /**
5017  *  e1000_init_hw_ich8lan - Initialize the hardware
5018  *  @hw: pointer to the HW structure
5019  *
5020  *  Prepares the hardware for transmit and receive by doing the following:
5021  *   - initialize hardware bits
5022  *   - initialize LED identification
5023  *   - setup receive address registers
5024  *   - setup flow control
5025  *   - setup transmit descriptors
5026  *   - clear statistics
5027  **/
5028 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5029 {
5030         struct e1000_mac_info *mac = &hw->mac;
5031         u32 ctrl_ext, txdctl, snoop;
5032         s32 ret_val;
5033         u16 i;
5034
5035         DEBUGFUNC("e1000_init_hw_ich8lan");
5036
5037         e1000_initialize_hw_bits_ich8lan(hw);
5038
5039         /* Initialize identification LED */
5040         ret_val = mac->ops.id_led_init(hw);
5041         /* An error is not fatal and we should not stop init due to this */
5042         if (ret_val)
5043                 DEBUGOUT("Error initializing identification LED\n");
5044
5045         /* Setup the receive address. */
5046         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5047
5048         /* Zero out the Multicast HASH table */
5049         DEBUGOUT("Zeroing the MTA\n");
5050         for (i = 0; i < mac->mta_reg_count; i++)
5051                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5052
5053         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5054          * the ME.  Disable wakeup by clearing the host wakeup bit.
5055          * Reset the phy after disabling host wakeup to reset the Rx buffer.
5056          */
5057         if (hw->phy.type == e1000_phy_82578) {
5058                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5059                 i &= ~BM_WUC_HOST_WU_BIT;
5060                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5061                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5062                 if (ret_val)
5063                         return ret_val;
5064         }
5065
5066         /* Setup link and flow control */
5067         ret_val = mac->ops.setup_link(hw);
5068
5069         /* Set the transmit descriptor write-back policy for both queues */
5070         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5071         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5072                   E1000_TXDCTL_FULL_TX_DESC_WB);
5073         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5074                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5075         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5076         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5077         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5078                   E1000_TXDCTL_FULL_TX_DESC_WB);
5079         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5080                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5081         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5082
5083         /* ICH8 has opposite polarity of no_snoop bits.
5084          * By default, we should use snoop behavior.
5085          */
5086         if (mac->type == e1000_ich8lan)
5087                 snoop = PCIE_ICH8_SNOOP_ALL;
5088         else
5089                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5090         e1000_set_pcie_no_snoop_generic(hw, snoop);
5091
5092         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5093         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5094         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5095
5096         /* Clear all of the statistics registers (clear on read).  It is
5097          * important that we do this after we have tried to establish link
5098          * because the symbol error count will increment wildly if there
5099          * is no link.
5100          */
5101         e1000_clear_hw_cntrs_ich8lan(hw);
5102
5103         return ret_val;
5104 }
5105
5106 /**
5107  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5108  *  @hw: pointer to the HW structure
5109  *
5110  *  Sets/Clears required hardware bits necessary for correctly setting up the
5111  *  hardware for transmit and receive.
5112  **/
5113 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5114 {
5115         u32 reg;
5116
5117         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5118
5119         /* Extended Device Control */
5120         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5121         reg |= (1 << 22);
5122         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5123         if (hw->mac.type >= e1000_pchlan)
5124                 reg |= E1000_CTRL_EXT_PHYPDEN;
5125         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5126
5127         /* Transmit Descriptor Control 0 */
5128         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5129         reg |= (1 << 22);
5130         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5131
5132         /* Transmit Descriptor Control 1 */
5133         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5134         reg |= (1 << 22);
5135         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5136
5137         /* Transmit Arbitration Control 0 */
5138         reg = E1000_READ_REG(hw, E1000_TARC(0));
5139         if (hw->mac.type == e1000_ich8lan)
5140                 reg |= (1 << 28) | (1 << 29);
5141         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5142         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5143
5144         /* Transmit Arbitration Control 1 */
5145         reg = E1000_READ_REG(hw, E1000_TARC(1));
5146         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5147                 reg &= ~(1 << 28);
5148         else
5149                 reg |= (1 << 28);
5150         reg |= (1 << 24) | (1 << 26) | (1 << 30);
5151         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5152
5153         /* Device Status */
5154         if (hw->mac.type == e1000_ich8lan) {
5155                 reg = E1000_READ_REG(hw, E1000_STATUS);
5156                 reg &= ~(1U << 31);
5157                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5158         }
5159
5160         /* work-around descriptor data corruption issue during nfs v2 udp
5161          * traffic, just disable the nfs filtering capability
5162          */
5163         reg = E1000_READ_REG(hw, E1000_RFCTL);
5164         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5165
5166         /* Disable IPv6 extension header parsing because some malformed
5167          * IPv6 headers can hang the Rx.
5168          */
5169         if (hw->mac.type == e1000_ich8lan)
5170                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5171         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5172
5173         /* Enable ECC on Lynxpoint */
5174         if (hw->mac.type >= e1000_pch_lpt) {
5175                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5176                 reg |= E1000_PBECCSTS_ECC_ENABLE;
5177                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5178
5179                 reg = E1000_READ_REG(hw, E1000_CTRL);
5180                 reg |= E1000_CTRL_MEHE;
5181                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5182         }
5183
5184         return;
5185 }
5186
5187 /**
5188  *  e1000_setup_link_ich8lan - Setup flow control and link settings
5189  *  @hw: pointer to the HW structure
5190  *
5191  *  Determines which flow control settings to use, then configures flow
5192  *  control.  Calls the appropriate media-specific link configuration
5193  *  function.  Assuming the adapter has a valid link partner, a valid link
5194  *  should be established.  Assumes the hardware has previously been reset
5195  *  and the transmitter and receiver are not enabled.
5196  **/
5197 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5198 {
5199         s32 ret_val;
5200
5201         DEBUGFUNC("e1000_setup_link_ich8lan");
5202
5203         if (hw->phy.ops.check_reset_block(hw))
5204                 return E1000_SUCCESS;
5205
5206         /* ICH parts do not have a word in the NVM to determine
5207          * the default flow control setting, so we explicitly
5208          * set it to full.
5209          */
5210         if (hw->fc.requested_mode == e1000_fc_default)
5211                 hw->fc.requested_mode = e1000_fc_full;
5212
5213         /* Save off the requested flow control mode for use later.  Depending
5214          * on the link partner's capabilities, we may or may not use this mode.
5215          */
5216         hw->fc.current_mode = hw->fc.requested_mode;
5217
5218         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5219                 hw->fc.current_mode);
5220
5221         /* Continue to configure the copper link. */
5222         ret_val = hw->mac.ops.setup_physical_interface(hw);
5223         if (ret_val)
5224                 return ret_val;
5225
5226         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5227         if ((hw->phy.type == e1000_phy_82578) ||
5228             (hw->phy.type == e1000_phy_82579) ||
5229             (hw->phy.type == e1000_phy_i217) ||
5230             (hw->phy.type == e1000_phy_82577)) {
5231                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5232
5233                 ret_val = hw->phy.ops.write_reg(hw,
5234                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
5235                                              hw->fc.pause_time);
5236                 if (ret_val)
5237                         return ret_val;
5238         }
5239
5240         return e1000_set_fc_watermarks_generic(hw);
5241 }
5242
5243 /**
5244  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5245  *  @hw: pointer to the HW structure
5246  *
5247  *  Configures the kumeran interface to the PHY to wait the appropriate time
5248  *  when polling the PHY, then call the generic setup_copper_link to finish
5249  *  configuring the copper link.
5250  **/
5251 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5252 {
5253         u32 ctrl;
5254         s32 ret_val;
5255         u16 reg_data;
5256
5257         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5258
5259         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5260         ctrl |= E1000_CTRL_SLU;
5261         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5262         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5263
5264         /* Set the mac to wait the maximum time between each iteration
5265          * and increase the max iterations when polling the phy;
5266          * this fixes erroneous timeouts at 10Mbps.
5267          */
5268         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5269                                                0xFFFF);
5270         if (ret_val)
5271                 return ret_val;
5272         ret_val = e1000_read_kmrn_reg_generic(hw,
5273                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
5274                                               &reg_data);
5275         if (ret_val)
5276                 return ret_val;
5277         reg_data |= 0x3F;
5278         ret_val = e1000_write_kmrn_reg_generic(hw,
5279                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
5280                                                reg_data);
5281         if (ret_val)
5282                 return ret_val;
5283
5284         switch (hw->phy.type) {
5285         case e1000_phy_igp_3:
5286                 ret_val = e1000_copper_link_setup_igp(hw);
5287                 if (ret_val)
5288                         return ret_val;
5289                 break;
5290         case e1000_phy_bm:
5291         case e1000_phy_82578:
5292                 ret_val = e1000_copper_link_setup_m88(hw);
5293                 if (ret_val)
5294                         return ret_val;
5295                 break;
5296         case e1000_phy_82577:
5297         case e1000_phy_82579:
5298                 ret_val = e1000_copper_link_setup_82577(hw);
5299                 if (ret_val)
5300                         return ret_val;
5301                 break;
5302         case e1000_phy_ife:
5303                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5304                                                &reg_data);
5305                 if (ret_val)
5306                         return ret_val;
5307
5308                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5309
5310                 switch (hw->phy.mdix) {
5311                 case 1:
5312                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5313                         break;
5314                 case 2:
5315                         reg_data |= IFE_PMC_FORCE_MDIX;
5316                         break;
5317                 case 0:
5318                 default:
5319                         reg_data |= IFE_PMC_AUTO_MDIX;
5320                         break;
5321                 }
5322                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5323                                                 reg_data);
5324                 if (ret_val)
5325                         return ret_val;
5326                 break;
5327         default:
5328                 break;
5329         }
5330
5331         return e1000_setup_copper_link_generic(hw);
5332 }
5333
5334 /**
5335  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5336  *  @hw: pointer to the HW structure
5337  *
5338  *  Calls the PHY specific link setup function and then calls the
5339  *  generic setup_copper_link to finish configuring the link for
5340  *  Lynxpoint PCH devices
5341  **/
5342 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5343 {
5344         u32 ctrl;
5345         s32 ret_val;
5346
5347         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5348
5349         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5350         ctrl |= E1000_CTRL_SLU;
5351         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5352         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5353
5354         ret_val = e1000_copper_link_setup_82577(hw);
5355         if (ret_val)
5356                 return ret_val;
5357
5358         return e1000_setup_copper_link_generic(hw);
5359 }
5360
5361 /**
5362  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5363  *  @hw: pointer to the HW structure
5364  *  @speed: pointer to store current link speed
5365  *  @duplex: pointer to store the current link duplex
5366  *
5367  *  Calls the generic get_speed_and_duplex to retrieve the current link
5368  *  information and then calls the Kumeran lock loss workaround for links at
5369  *  gigabit speeds.
5370  **/
5371 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5372                                           u16 *duplex)
5373 {
5374         s32 ret_val;
5375
5376         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5377
5378         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5379         if (ret_val)
5380                 return ret_val;
5381
5382         if ((hw->mac.type == e1000_ich8lan) &&
5383             (hw->phy.type == e1000_phy_igp_3) &&
5384             (*speed == SPEED_1000)) {
5385                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5386         }
5387
5388         return ret_val;
5389 }
5390
5391 /**
5392  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5393  *  @hw: pointer to the HW structure
5394  *
5395  *  Work-around for 82566 Kumeran PCS lock loss:
5396  *  On link status change (i.e. PCI reset, speed change) and link is up and
5397  *  speed is gigabit-
5398  *    0) if workaround is optionally disabled do nothing
5399  *    1) wait 1ms for Kumeran link to come up
5400  *    2) check Kumeran Diagnostic register PCS lock loss bit
5401  *    3) if not set the link is locked (all is good), otherwise...
5402  *    4) reset the PHY
5403  *    5) repeat up to 10 times
5404  *  Note: this is only called for IGP3 copper when speed is 1gb.
5405  **/
5406 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5407 {
5408         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5409         u32 phy_ctrl;
5410         s32 ret_val;
5411         u16 i, data;
5412         bool link;
5413
5414         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5415
5416         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5417                 return E1000_SUCCESS;
5418
5419         /* Make sure link is up before proceeding.  If not just return.
5420          * Attempting this while link is negotiating fouled up link
5421          * stability
5422          */
5423         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5424         if (!link)
5425                 return E1000_SUCCESS;
5426
5427         for (i = 0; i < 10; i++) {
5428                 /* read once to clear */
5429                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5430                 if (ret_val)
5431                         return ret_val;
5432                 /* and again to get new status */
5433                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5434                 if (ret_val)
5435                         return ret_val;
5436
5437                 /* check for PCS lock */
5438                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5439                         return E1000_SUCCESS;
5440
5441                 /* Issue PHY reset */
5442                 hw->phy.ops.reset(hw);
5443                 msec_delay_irq(5);
5444         }
5445         /* Disable GigE link negotiation */
5446         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5447         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5448                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5449         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5450
5451         /* Call gig speed drop workaround on Gig disable before accessing
5452          * any PHY registers
5453          */
5454         e1000_gig_downshift_workaround_ich8lan(hw);
5455
5456         /* unable to acquire PCS lock */
5457         return -E1000_ERR_PHY;
5458 }
5459
5460 /**
5461  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5462  *  @hw: pointer to the HW structure
5463  *  @state: boolean value used to set the current Kumeran workaround state
5464  *
5465  *  If ICH8, set the current Kumeran workaround state (enabled - true
5466  *  /disabled - false).
5467  **/
5468 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5469                                                  bool state)
5470 {
5471         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5472
5473         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5474
5475         if (hw->mac.type != e1000_ich8lan) {
5476                 DEBUGOUT("Workaround applies to ICH8 only.\n");
5477                 return;
5478         }
5479
5480         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5481
5482         return;
5483 }
5484
5485 /**
5486  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5487  *  @hw: pointer to the HW structure
5488  *
5489  *  Workaround for 82566 power-down on D3 entry:
5490  *    1) disable gigabit link
5491  *    2) write VR power-down enable
5492  *    3) read it back
5493  *  Continue if successful, else issue LCD reset and repeat
5494  **/
5495 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5496 {
5497         u32 reg;
5498         u16 data;
5499         u8  retry = 0;
5500
5501         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5502
5503         if (hw->phy.type != e1000_phy_igp_3)
5504                 return;
5505
5506         /* Try the workaround twice (if needed) */
5507         do {
5508                 /* Disable link */
5509                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5510                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5511                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5512                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5513
5514                 /* Call gig speed drop workaround on Gig disable before
5515                  * accessing any PHY registers
5516                  */
5517                 if (hw->mac.type == e1000_ich8lan)
5518                         e1000_gig_downshift_workaround_ich8lan(hw);
5519
5520                 /* Write VR power-down enable */
5521                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5522                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5523                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5524                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5525
5526                 /* Read it back and test */
5527                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5528                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5529                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5530                         break;
5531
5532                 /* Issue PHY reset and repeat at most one more time */
5533                 reg = E1000_READ_REG(hw, E1000_CTRL);
5534                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5535                 retry++;
5536         } while (retry);
5537 }
5538
5539 /**
5540  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5541  *  @hw: pointer to the HW structure
5542  *
5543  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5544  *  LPLU, Gig disable, MDIC PHY reset):
5545  *    1) Set Kumeran Near-end loopback
5546  *    2) Clear Kumeran Near-end loopback
5547  *  Should only be called for ICH8[m] devices with any 1G Phy.
5548  **/
5549 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5550 {
5551         s32 ret_val;
5552         u16 reg_data = 0;
5553
5554         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5555
5556         if ((hw->mac.type != e1000_ich8lan) ||
5557             (hw->phy.type == e1000_phy_ife))
5558                 return;
5559
5560         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5561                                               &reg_data);
5562         if (ret_val)
5563                 return;
5564         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5565         ret_val = e1000_write_kmrn_reg_generic(hw,
5566                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
5567                                                reg_data);
5568         if (ret_val)
5569                 return;
5570         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5571         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5572                                      reg_data);
5573 }
5574
5575 /**
5576  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5577  *  @hw: pointer to the HW structure
5578  *
5579  *  During S0 to Sx transition, it is possible the link remains at gig
5580  *  instead of negotiating to a lower speed.  Before going to Sx, set
5581  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5582  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5583  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5584  *  needs to be written.
5585  *  Parts that support (and are linked to a partner which support) EEE in
5586  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5587  *  than 10Mbps w/o EEE.
5588  **/
5589 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5590 {
5591         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5592         u32 phy_ctrl;
5593         s32 ret_val;
5594
5595         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5596
5597         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5598         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5599
5600         if (hw->phy.type == e1000_phy_i217) {
5601                 u16 phy_reg, device_id = hw->device_id;
5602
5603                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5604                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5605                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5606                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5607                     (hw->mac.type >= e1000_pch_spt)) {
5608                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5609
5610                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5611                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5612                 }
5613
5614                 ret_val = hw->phy.ops.acquire(hw);
5615                 if (ret_val)
5616                         goto out;
5617
5618                 if (!dev_spec->eee_disable) {
5619                         u16 eee_advert;
5620
5621                         ret_val =
5622                             e1000_read_emi_reg_locked(hw,
5623                                                       I217_EEE_ADVERTISEMENT,
5624                                                       &eee_advert);
5625                         if (ret_val)
5626                                 goto release;
5627
5628                         /* Disable LPLU if both link partners support 100BaseT
5629                          * EEE and 100Full is advertised on both ends of the
5630                          * link, and enable Auto Enable LPI since there will
5631                          * be no driver to enable LPI while in Sx.
5632                          */
5633                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5634                             (dev_spec->eee_lp_ability &
5635                              I82579_EEE_100_SUPPORTED) &&
5636                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5637                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5638                                               E1000_PHY_CTRL_NOND0A_LPLU);
5639
5640                                 /* Set Auto Enable LPI after link up */
5641                                 hw->phy.ops.read_reg_locked(hw,
5642                                                             I217_LPI_GPIO_CTRL,
5643                                                             &phy_reg);
5644                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5645                                 hw->phy.ops.write_reg_locked(hw,
5646                                                              I217_LPI_GPIO_CTRL,
5647                                                              phy_reg);
5648                         }
5649                 }
5650
5651                 /* For i217 Intel Rapid Start Technology support,
5652                  * when the system is going into Sx and no manageability engine
5653                  * is present, the driver must configure proxy to reset only on
5654                  * power good.  LPI (Low Power Idle) state must also reset only
5655                  * on power good, as well as the MTA (Multicast table array).
5656                  * The SMBus release must also be disabled on LCD reset.
5657                  */
5658                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5659                       E1000_ICH_FWSM_FW_VALID)) {
5660                         /* Enable proxy to reset only on power good. */
5661                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5662                                                     &phy_reg);
5663                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5664                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5665                                                      phy_reg);
5666
5667                         /* Set bit enable LPI (EEE) to reset only on
5668                          * power good.
5669                         */
5670                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5671                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5672                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5673
5674                         /* Disable the SMB release on LCD reset. */
5675                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5676                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5677                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5678                 }
5679
5680                 /* Enable MTA to reset for Intel Rapid Start Technology
5681                  * Support
5682                  */
5683                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5684                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5685                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5686
5687 release:
5688                 hw->phy.ops.release(hw);
5689         }
5690 out:
5691         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5692
5693         if (hw->mac.type == e1000_ich8lan)
5694                 e1000_gig_downshift_workaround_ich8lan(hw);
5695
5696         if (hw->mac.type >= e1000_pchlan) {
5697                 e1000_oem_bits_config_ich8lan(hw, false);
5698
5699                 /* Reset PHY to activate OEM bits on 82577/8 */
5700                 if (hw->mac.type == e1000_pchlan)
5701                         e1000_phy_hw_reset_generic(hw);
5702
5703                 ret_val = hw->phy.ops.acquire(hw);
5704                 if (ret_val)
5705                         return;
5706                 e1000_write_smbus_addr(hw);
5707                 hw->phy.ops.release(hw);
5708         }
5709
5710         return;
5711 }
5712
5713 /**
5714  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5715  *  @hw: pointer to the HW structure
5716  *
5717  *  During Sx to S0 transitions on non-managed devices or managed devices
5718  *  on which PHY resets are not blocked, if the PHY registers cannot be
5719  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5720  *  the PHY.
5721  *  On i217, setup Intel Rapid Start Technology.
5722  **/
5723 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5724 {
5725         s32 ret_val;
5726
5727         DEBUGFUNC("e1000_resume_workarounds_pchlan");
5728         if (hw->mac.type < e1000_pch2lan)
5729                 return E1000_SUCCESS;
5730
5731         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5732         if (ret_val) {
5733                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5734                 return ret_val;
5735         }
5736
5737         /* For i217 Intel Rapid Start Technology support when the system
5738          * is transitioning from Sx and no manageability engine is present
5739          * configure SMBus to restore on reset, disable proxy, and enable
5740          * the reset on MTA (Multicast table array).
5741          */
5742         if (hw->phy.type == e1000_phy_i217) {
5743                 u16 phy_reg;
5744
5745                 ret_val = hw->phy.ops.acquire(hw);
5746                 if (ret_val) {
5747                         DEBUGOUT("Failed to setup iRST\n");
5748                         return ret_val;
5749                 }
5750
5751                 /* Clear Auto Enable LPI after link up */
5752                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5753                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5754                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5755
5756                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5757                     E1000_ICH_FWSM_FW_VALID)) {
5758                         /* Restore clear on SMB if no manageability engine
5759                          * is present
5760                          */
5761                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5762                                                               &phy_reg);
5763                         if (ret_val)
5764                                 goto release;
5765                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5766                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5767
5768                         /* Disable Proxy */
5769                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5770                 }
5771                 /* Enable reset on MTA */
5772                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5773                                                       &phy_reg);
5774                 if (ret_val)
5775                         goto release;
5776                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5777                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5778 release:
5779                 if (ret_val)
5780                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5781                 hw->phy.ops.release(hw);
5782                 return ret_val;
5783         }
5784         return E1000_SUCCESS;
5785 }
5786
5787 /**
5788  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5789  *  @hw: pointer to the HW structure
5790  *
5791  *  Return the LED back to the default configuration.
5792  **/
5793 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5794 {
5795         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5796
5797         if (hw->phy.type == e1000_phy_ife)
5798                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5799                                              0);
5800
5801         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5802         return E1000_SUCCESS;
5803 }
5804
5805 /**
5806  *  e1000_led_on_ich8lan - Turn LEDs on
5807  *  @hw: pointer to the HW structure
5808  *
5809  *  Turn on the LEDs.
5810  **/
5811 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5812 {
5813         DEBUGFUNC("e1000_led_on_ich8lan");
5814
5815         if (hw->phy.type == e1000_phy_ife)
5816                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5817                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5818
5819         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5820         return E1000_SUCCESS;
5821 }
5822
5823 /**
5824  *  e1000_led_off_ich8lan - Turn LEDs off
5825  *  @hw: pointer to the HW structure
5826  *
5827  *  Turn off the LEDs.
5828  **/
5829 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5830 {
5831         DEBUGFUNC("e1000_led_off_ich8lan");
5832
5833         if (hw->phy.type == e1000_phy_ife)
5834                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5835                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5836
5837         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5838         return E1000_SUCCESS;
5839 }
5840
5841 /**
5842  *  e1000_setup_led_pchlan - Configures SW controllable LED
5843  *  @hw: pointer to the HW structure
5844  *
5845  *  This prepares the SW controllable LED for use.
5846  **/
5847 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5848 {
5849         DEBUGFUNC("e1000_setup_led_pchlan");
5850
5851         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5852                                      (u16)hw->mac.ledctl_mode1);
5853 }
5854
5855 /**
5856  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5857  *  @hw: pointer to the HW structure
5858  *
5859  *  Return the LED back to the default configuration.
5860  **/
5861 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5862 {
5863         DEBUGFUNC("e1000_cleanup_led_pchlan");
5864
5865         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5866                                      (u16)hw->mac.ledctl_default);
5867 }
5868
5869 /**
5870  *  e1000_led_on_pchlan - Turn LEDs on
5871  *  @hw: pointer to the HW structure
5872  *
5873  *  Turn on the LEDs.
5874  **/
5875 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5876 {
5877         u16 data = (u16)hw->mac.ledctl_mode2;
5878         u32 i, led;
5879
5880         DEBUGFUNC("e1000_led_on_pchlan");
5881
5882         /* If no link, then turn LED on by setting the invert bit
5883          * for each LED that's mode is "link_up" in ledctl_mode2.
5884          */
5885         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5886                 for (i = 0; i < 3; i++) {
5887                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5888                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5889                             E1000_LEDCTL_MODE_LINK_UP)
5890                                 continue;
5891                         if (led & E1000_PHY_LED0_IVRT)
5892                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5893                         else
5894                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5895                 }
5896         }
5897
5898         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5899 }
5900
5901 /**
5902  *  e1000_led_off_pchlan - Turn LEDs off
5903  *  @hw: pointer to the HW structure
5904  *
5905  *  Turn off the LEDs.
5906  **/
5907 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5908 {
5909         u16 data = (u16)hw->mac.ledctl_mode1;
5910         u32 i, led;
5911
5912         DEBUGFUNC("e1000_led_off_pchlan");
5913
5914         /* If no link, then turn LED off by clearing the invert bit
5915          * for each LED that's mode is "link_up" in ledctl_mode1.
5916          */
5917         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5918                 for (i = 0; i < 3; i++) {
5919                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5920                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5921                             E1000_LEDCTL_MODE_LINK_UP)
5922                                 continue;
5923                         if (led & E1000_PHY_LED0_IVRT)
5924                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5925                         else
5926                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5927                 }
5928         }
5929
5930         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5931 }
5932
5933 /**
5934  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5935  *  @hw: pointer to the HW structure
5936  *
5937  *  Read appropriate register for the config done bit for completion status
5938  *  and configure the PHY through s/w for EEPROM-less parts.
5939  *
5940  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5941  *  config done bit, so only an error is logged and continues.  If we were
5942  *  to return with error, EEPROM-less silicon would not be able to be reset
5943  *  or change link.
5944  **/
5945 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5946 {
5947         s32 ret_val = E1000_SUCCESS;
5948         u32 bank = 0;
5949         u32 status;
5950
5951         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5952
5953         e1000_get_cfg_done_generic(hw);
5954
5955         /* Wait for indication from h/w that it has completed basic config */
5956         if (hw->mac.type >= e1000_ich10lan) {
5957                 e1000_lan_init_done_ich8lan(hw);
5958         } else {
5959                 ret_val = e1000_get_auto_rd_done_generic(hw);
5960                 if (ret_val) {
5961                         /* When auto config read does not complete, do not
5962                          * return with an error. This can happen in situations
5963                          * where there is no eeprom and prevents getting link.
5964                          */
5965                         DEBUGOUT("Auto Read Done did not complete\n");
5966                         ret_val = E1000_SUCCESS;
5967                 }
5968         }
5969
5970         /* Clear PHY Reset Asserted bit */
5971         status = E1000_READ_REG(hw, E1000_STATUS);
5972         if (status & E1000_STATUS_PHYRA)
5973                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5974         else
5975                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5976
5977         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5978         if (hw->mac.type <= e1000_ich9lan) {
5979                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5980                     (hw->phy.type == e1000_phy_igp_3)) {
5981                         e1000_phy_init_script_igp3(hw);
5982                 }
5983         } else {
5984                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5985                         /* Maybe we should do a basic PHY config */
5986                         DEBUGOUT("EEPROM not present\n");
5987                         ret_val = -E1000_ERR_CONFIG;
5988                 }
5989         }
5990
5991         return ret_val;
5992 }
5993
5994 /**
5995  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5996  * @hw: pointer to the HW structure
5997  *
5998  * In the case of a PHY power down to save power, or to turn off link during a
5999  * driver unload, or wake on lan is not enabled, remove the link.
6000  **/
6001 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6002 {
6003         /* If the management interface is not enabled, then power down */
6004         if (!(hw->mac.ops.check_mng_mode(hw) ||
6005               hw->phy.ops.check_reset_block(hw)))
6006                 e1000_power_down_phy_copper(hw);
6007
6008         return;
6009 }
6010
6011 /**
6012  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6013  *  @hw: pointer to the HW structure
6014  *
6015  *  Clears hardware counters specific to the silicon family and calls
6016  *  clear_hw_cntrs_generic to clear all general purpose counters.
6017  **/
6018 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6019 {
6020         u16 phy_data;
6021         s32 ret_val;
6022
6023         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6024
6025         e1000_clear_hw_cntrs_base_generic(hw);
6026
6027         E1000_READ_REG(hw, E1000_ALGNERRC);
6028         E1000_READ_REG(hw, E1000_RXERRC);
6029         E1000_READ_REG(hw, E1000_TNCRS);
6030         E1000_READ_REG(hw, E1000_CEXTERR);
6031         E1000_READ_REG(hw, E1000_TSCTC);
6032         E1000_READ_REG(hw, E1000_TSCTFC);
6033
6034         E1000_READ_REG(hw, E1000_MGTPRC);
6035         E1000_READ_REG(hw, E1000_MGTPDC);
6036         E1000_READ_REG(hw, E1000_MGTPTC);
6037
6038         E1000_READ_REG(hw, E1000_IAC);
6039         E1000_READ_REG(hw, E1000_ICRXOC);
6040
6041         /* Clear PHY statistics registers */
6042         if ((hw->phy.type == e1000_phy_82578) ||
6043             (hw->phy.type == e1000_phy_82579) ||
6044             (hw->phy.type == e1000_phy_i217) ||
6045             (hw->phy.type == e1000_phy_82577)) {
6046                 ret_val = hw->phy.ops.acquire(hw);
6047                 if (ret_val)
6048                         return;
6049                 ret_val = hw->phy.ops.set_page(hw,
6050                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
6051                 if (ret_val)
6052                         goto release;
6053                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6054                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6055                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6056                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6057                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6058                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6059                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6060                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6061                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6062                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6063                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6064                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6065                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6066                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6067 release:
6068                 hw->phy.ops.release(hw);
6069         }
6070 }
6071
6072 /**
6073  *  e1000_configure_k0s_lpt - Configure K0s power state
6074  *  @hw: pointer to the HW structure
6075  *  @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6076  *      0 corresponds to 128ns, each value over 0 doubles the duration.
6077  *  @min_time: Minimum Tx idle period allowed  - valid values are 0 to 4.
6078  *      0 corresponds to 128ns, each value over 0 doubles the duration.
6079  *
6080  *  Configure the K1 power state based on the provided parameter.
6081  *  Assumes semaphore already acquired.
6082  *
6083  *  Success returns 0, Failure returns:
6084  *      -E1000_ERR_PHY (-2) in case of access error
6085  *      -E1000_ERR_PARAM (-4) in case of parameters error
6086  **/
6087 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6088 {
6089         s32 ret_val;
6090         u16 kmrn_reg = 0;
6091
6092         DEBUGFUNC("e1000_configure_k0s_lpt");
6093
6094         if (entry_latency > 3 || min_time > 4)
6095                 return -E1000_ERR_PARAM;
6096
6097         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6098                                              &kmrn_reg);
6099         if (ret_val)
6100                 return ret_val;
6101
6102         /* for now don't touch the latency */
6103         kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6104         kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6105
6106         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6107                                               kmrn_reg);
6108         if (ret_val)
6109                 return ret_val;
6110
6111         return E1000_SUCCESS;
6112 }