drivers/net/e1000/base/e1000_ich8lan.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82562G 10/100 Network Connection
  35  * 82562G-2 10/100 Network Connection
  36  * 82562GT 10/100 Network Connection
  37  * 82562GT-2 10/100 Network Connection
  38  * 82562V 10/100 Network Connection
  39  * 82562V-2 10/100 Network Connection
  40  * 82566DC-2 Gigabit Network Connection
  41  * 82566DC Gigabit Network Connection
  42  * 82566DM-2 Gigabit Network Connection
  43  * 82566DM Gigabit Network Connection
  44  * 82566MC Gigabit Network Connection
  45  * 82566MM Gigabit Network Connection
  46  * 82567LM Gigabit Network Connection
  47  * 82567LF Gigabit Network Connection
  48  * 82567V Gigabit Network Connection
  49  * 82567LM-2 Gigabit Network Connection
  50  * 82567LF-2 Gigabit Network Connection
  51  * 82567V-2 Gigabit Network Connection
  52  * 82567LF-3 Gigabit Network Connection
  53  * 82567LM-3 Gigabit Network Connection
  54  * 82567LM-4 Gigabit Network Connection
  55  * 82577LM Gigabit Network Connection
  56  * 82577LC Gigabit Network Connection
  57  * 82578DM Gigabit Network Connection
  58  * 82578DC Gigabit Network Connection
  59  * 82579LM Gigabit Network Connection
  60  * 82579V Gigabit Network Connection
  61  * Ethernet Connection I217-LM
  62  * Ethernet Connection I217-V
  63  * Ethernet Connection I218-V
  64  * Ethernet Connection I218-LM
  65  * Ethernet Connection (2) I218-LM
  66  * Ethernet Connection (2) I218-V
  67  * Ethernet Connection (3) I218-LM
  68  * Ethernet Connection (3) I218-V
  69  */
  70
  71 #include "e1000_api.h"
  72
  73 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  74 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  75 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  76 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  77 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  78 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  79 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  80 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  81 STATIC void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  82 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  83 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  84 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  85                                               u8 *mc_addr_list,
  86                                               u32 mc_addr_count);
  87 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  88 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  90 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  91 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  92                                             bool active);
  93 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  94                                             bool active);
  95 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  96                                    u16 words, u16 *data);
  97 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  98                                     u16 words, u16 *data);
  99 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 100 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
 101 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
 102                                             u16 *data);
 103 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 104 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 105 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 106 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 107 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 108 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 109 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 110 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 111                                            u16 *speed, u16 *duplex);
 112 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 113 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 114 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 115 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 116 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 117 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 118 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 119 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 120 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 121 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 122 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 123 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 124 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 125                                           u32 offset, u8 *data);
 126 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 127                                           u8 size, u16 *data);
 128 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 129                                           u32 offset, u16 *data);
 130 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 131                                                  u32 offset, u8 byte);
 132 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 133 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 134 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 135 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 136 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 137 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 138
 139 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 140 /* Offset 04h HSFSTS */
 141 union ich8_hws_flash_status {
 142         struct ich8_hsfsts {
 143                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 144                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 145                 u16 dael:1; /* bit 2 Direct Access error Log */
 146                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 147                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 148                 u16 reserved1:2; /* bit 13:6 Reserved */
 149                 u16 reserved2:6; /* bit 13:6 Reserved */
 150                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 151                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 152         } hsf_status;
 153         u16 regval;
 154 };
 155
 156 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 157 /* Offset 06h FLCTL */
 158 union ich8_hws_flash_ctrl {
 159         struct ich8_hsflctl {
 160                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 161                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 162                 u16 reserved:5;   /* 7:3 Reserved  */
 163                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 164                 u16 flockdn:6;   /* 15:10 Reserved */
 165         } hsf_ctrl;
 166         u16 regval;
 167 };
 168
 169 /* ICH Flash Region Access Permissions */
 170 union ich8_hws_flash_regacc {
 171         struct ich8_flracc {
 172                 u32 grra:8; /* 0:7 GbE region Read Access */
 173                 u32 grwa:8; /* 8:15 GbE region Write Access */
 174                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 175                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 176         } hsf_flregacc;
 177         u16 regval;
 178 };
 179
 180 /**
 181  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 182  *  @hw: pointer to the HW structure
 183  *
 184  *  Test access to the PHY registers by reading the PHY ID registers.  If
 185  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 186  *  otherwise assume the read PHY ID is correct if it is valid.
 187  *
 188  *  Assumes the sw/fw/hw semaphore is already acquired.
 189  **/
 190 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 191 {
 192         u16 phy_reg = 0;
 193         u32 phy_id = 0;
 194         s32 ret_val = 0;
 195         u16 retry_count;
 196         u32 mac_reg = 0;
 197
 198         for (retry_count = 0; retry_count < 2; retry_count++) {
 199                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 200                 if (ret_val || (phy_reg == 0xFFFF))
 201                         continue;
 202                 phy_id = (u32)(phy_reg << 16);
 203
 204                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 205                 if (ret_val || (phy_reg == 0xFFFF)) {
 206                         phy_id = 0;
 207                         continue;
 208                 }
 209                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 210                 break;
 211         }
 212
 213         if (hw->phy.id) {
 214                 if  (hw->phy.id == phy_id)
 215                         goto out;
 216         } else if (phy_id) {
 217                 hw->phy.id = phy_id;
 218                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 219                 goto out;
 220         }
 221
 222         /* In case the PHY needs to be in mdio slow mode,
 223          * set slow mode and try to get the PHY id again.
 224          */
 225         if (hw->mac.type < e1000_pch_lpt) {
 226                 hw->phy.ops.release(hw);
 227                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 228                 if (!ret_val)
 229                         ret_val = e1000_get_phy_id(hw);
 230                 hw->phy.ops.acquire(hw);
 231         }
 232
 233         if (ret_val)
 234                 return false;
 235 out:
 236         if (hw->mac.type == e1000_pch_lpt) {
 237                 /* Unforce SMBus mode in PHY */
 238                 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 239                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 240                 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 241
 242                 /* Unforce SMBus mode in MAC */
 243                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 244                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 245                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 246         }
 247
 248         return true;
 249 }
 250
 251 /**
 252  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 253  *  @hw: pointer to the HW structure
 254  *
 255  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 256  *  used to reset the PHY to a quiescent state when necessary.
 257  **/
 258 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 259 {
 260         u32 mac_reg;
 261
 262         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 263
 264         /* Set Phy Config Counter to 50msec */
 265         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 266         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 267         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 268         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 269
 270         /* Toggle LANPHYPC Value bit */
 271         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 272         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 273         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 274         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 275         E1000_WRITE_FLUSH(hw);
 276         usec_delay(10);
 277         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 278         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 279         E1000_WRITE_FLUSH(hw);
 280
 281         if (hw->mac.type < e1000_pch_lpt) {
 282                 msec_delay(50);
 283         } else {
 284                 u16 count = 20;
 285
 286                 do {
 287                         msec_delay(5);
 288                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 289                            E1000_CTRL_EXT_LPCD) && count--);
 290
 291                 msec_delay(30);
 292         }
 293 }
 294
 295 /**
 296  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 297  *  @hw: pointer to the HW structure
 298  *
 299  *  Workarounds/flow necessary for PHY initialization during driver load
 300  *  and resume paths.
 301  **/
 302 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 303 {
 304         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 305         s32 ret_val;
 306
 307         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 308
 309         /* Gate automatic PHY configuration by hardware on managed and
 310          * non-managed 82579 and newer adapters.
 311          */
 312         e1000_gate_hw_phy_config_ich8lan(hw, true);
 313
 314 #if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)
 315         /* It is not possible to be certain of the current state of ULP
 316          * so forcibly disable it.
 317          */
 318         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 319
 320 #endif /* NAHUM6LP_HW && ULP_SUPPORT */
 321         ret_val = hw->phy.ops.acquire(hw);
 322         if (ret_val) {
 323                 DEBUGOUT("Failed to initialize PHY flow\n");
 324                 goto out;
 325         }
 326
 327         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 328          * inaccessible and resetting the PHY is not blocked, toggle the
 329          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 330          */
 331         switch (hw->mac.type) {
 332         case e1000_pch_lpt:
 333                 if (e1000_phy_is_accessible_pchlan(hw))
 334                         break;
 335
 336                 /* Before toggling LANPHYPC, see if PHY is accessible by
 337                  * forcing MAC to SMBus mode first.
 338                  */
 339                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 340                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 341                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 342
 343                 /* Wait 50 milliseconds for MAC to finish any retries
 344                  * that it might be trying to perform from previous
 345                  * attempts to acknowledge any phy read requests.
 346                  */
 347                  msec_delay(50);
 348
 349                 /* fall-through */
 350         case e1000_pch2lan:
 351                 if (e1000_phy_is_accessible_pchlan(hw))
 352                         break;
 353
 354                 /* fall-through */
 355         case e1000_pchlan:
 356                 if ((hw->mac.type == e1000_pchlan) &&
 357                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 358                         break;
 359
 360                 if (hw->phy.ops.check_reset_block(hw)) {
 361                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 362                         ret_val = -E1000_ERR_PHY;
 363                         break;
 364                 }
 365
 366                 /* Toggle LANPHYPC Value bit */
 367                 e1000_toggle_lanphypc_pch_lpt(hw);
 368                 if (hw->mac.type >= e1000_pch_lpt) {
 369                         if (e1000_phy_is_accessible_pchlan(hw))
 370                                 break;
 371
 372                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 373                          * so ensure that the MAC is also out of SMBus mode
 374                          */
 375                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 376                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 377                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 378
 379                         if (e1000_phy_is_accessible_pchlan(hw))
 380                                 break;
 381
 382                         ret_val = -E1000_ERR_PHY;
 383                 }
 384                 break;
 385         default:
 386                 break;
 387         }
 388
 389         hw->phy.ops.release(hw);
 390         if (!ret_val) {
 391
 392                 /* Check to see if able to reset PHY.  Print error if not */
 393                 if (hw->phy.ops.check_reset_block(hw)) {
 394                         ERROR_REPORT("Reset blocked by ME\n");
 395                         goto out;
 396                 }
 397
 398                 /* Reset the PHY before any access to it.  Doing so, ensures
 399                  * that the PHY is in a known good state before we read/write
 400                  * PHY registers.  The generic reset is sufficient here,
 401                  * because we haven't determined the PHY type yet.
 402                  */
 403                 ret_val = e1000_phy_hw_reset_generic(hw);
 404                 if (ret_val)
 405                         goto out;
 406
 407                 /* On a successful reset, possibly need to wait for the PHY
 408                  * to quiesce to an accessible state before returning control
 409                  * to the calling function.  If the PHY does not quiesce, then
 410                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 411                  *  the PHY is in.
 412                  */
 413                 ret_val = hw->phy.ops.check_reset_block(hw);
 414                 if (ret_val)
 415                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 416         }
 417
 418 out:
 419         /* Ungate automatic PHY configuration on non-managed 82579 */
 420         if ((hw->mac.type == e1000_pch2lan) &&
 421             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 422                 msec_delay(10);
 423                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 424         }
 425
 426         return ret_val;
 427 }
 428
 429 /**
 430  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 431  *  @hw: pointer to the HW structure
 432  *
 433  *  Initialize family-specific PHY parameters and function pointers.
 434  **/
 435 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 436 {
 437         struct e1000_phy_info *phy = &hw->phy;
 438         s32 ret_val;
 439
 440         DEBUGFUNC("e1000_init_phy_params_pchlan");
 441
 442         phy->addr               = 1;
 443         phy->reset_delay_us     = 100;
 444
 445         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 446         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 447         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 448         phy->ops.set_page       = e1000_set_page_igp;
 449         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 450         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 451         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 452         phy->ops.release        = e1000_release_swflag_ich8lan;
 453         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 454         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 455         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 456         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 457         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 458         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 459         phy->ops.power_up       = e1000_power_up_phy_copper;
 460         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 461         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 462
 463         phy->id = e1000_phy_unknown;
 464
 465         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 466         if (ret_val)
 467                 return ret_val;
 468
 469         if (phy->id == e1000_phy_unknown)
 470                 switch (hw->mac.type) {
 471                 default:
 472                         ret_val = e1000_get_phy_id(hw);
 473                         if (ret_val)
 474                                 return ret_val;
 475                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 476                                 break;
 477                         /* fall-through */
 478                 case e1000_pch2lan:
 479                 case e1000_pch_lpt:
 480                         /* In case the PHY needs to be in mdio slow mode,
 481                          * set slow mode and try to get the PHY id again.
 482                          */
 483                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 484                         if (ret_val)
 485                                 return ret_val;
 486                         ret_val = e1000_get_phy_id(hw);
 487                         if (ret_val)
 488                                 return ret_val;
 489                         break;
 490                 }
 491         phy->type = e1000_get_phy_type_from_id(phy->id);
 492
 493         switch (phy->type) {
 494         case e1000_phy_82577:
 495         case e1000_phy_82579:
 496         case e1000_phy_i217:
 497                 phy->ops.check_polarity = e1000_check_polarity_82577;
 498                 phy->ops.force_speed_duplex =
 499                         e1000_phy_force_speed_duplex_82577;
 500                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 501                 phy->ops.get_info = e1000_get_phy_info_82577;
 502                 phy->ops.commit = e1000_phy_sw_reset_generic;
 503                 break;
 504         case e1000_phy_82578:
 505                 phy->ops.check_polarity = e1000_check_polarity_m88;
 506                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 507                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 508                 phy->ops.get_info = e1000_get_phy_info_m88;
 509                 break;
 510         default:
 511                 ret_val = -E1000_ERR_PHY;
 512                 break;
 513         }
 514
 515         return ret_val;
 516 }
 517
 518 /**
 519  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 520  *  @hw: pointer to the HW structure
 521  *
 522  *  Initialize family-specific PHY parameters and function pointers.
 523  **/
 524 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 525 {
 526         struct e1000_phy_info *phy = &hw->phy;
 527         s32 ret_val;
 528         u16 i = 0;
 529
 530         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 531
 532         phy->addr               = 1;
 533         phy->reset_delay_us     = 100;
 534
 535         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 536         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 537         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 538         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 539         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 540         phy->ops.release        = e1000_release_swflag_ich8lan;
 541         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 542         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 543         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 544         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 545         phy->ops.power_up       = e1000_power_up_phy_copper;
 546         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 547
 548         /* We may need to do this twice - once for IGP and if that fails,
 549          * we'll set BM func pointers and try again
 550          */
 551         ret_val = e1000_determine_phy_address(hw);
 552         if (ret_val) {
 553                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 554                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 555                 ret_val = e1000_determine_phy_address(hw);
 556                 if (ret_val) {
 557                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 558                         return ret_val;
 559                 }
 560         }
 561
 562         phy->id = 0;
 563         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 564                (i++ < 100)) {
 565                 msec_delay(1);
 566                 ret_val = e1000_get_phy_id(hw);
 567                 if (ret_val)
 568                         return ret_val;
 569         }
 570
 571         /* Verify phy id */
 572         switch (phy->id) {
 573         case IGP03E1000_E_PHY_ID:
 574                 phy->type = e1000_phy_igp_3;
 575                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 576                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 577                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 578                 phy->ops.get_info = e1000_get_phy_info_igp;
 579                 phy->ops.check_polarity = e1000_check_polarity_igp;
 580                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 581                 break;
 582         case IFE_E_PHY_ID:
 583         case IFE_PLUS_E_PHY_ID:
 584         case IFE_C_E_PHY_ID:
 585                 phy->type = e1000_phy_ife;
 586                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 587                 phy->ops.get_info = e1000_get_phy_info_ife;
 588                 phy->ops.check_polarity = e1000_check_polarity_ife;
 589                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 590                 break;
 591         case BME1000_E_PHY_ID:
 592                 phy->type = e1000_phy_bm;
 593                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 594                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 595                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 596                 phy->ops.commit = e1000_phy_sw_reset_generic;
 597                 phy->ops.get_info = e1000_get_phy_info_m88;
 598                 phy->ops.check_polarity = e1000_check_polarity_m88;
 599                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 600                 break;
 601         default:
 602                 return -E1000_ERR_PHY;
 603                 break;
 604         }
 605
 606         return E1000_SUCCESS;
 607 }
 608
 609 /**
 610  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 611  *  @hw: pointer to the HW structure
 612  *
 613  *  Initialize family-specific NVM parameters and function
 614  *  pointers.
 615  **/
 616 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 617 {
 618         struct e1000_nvm_info *nvm = &hw->nvm;
 619         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 620         u32 gfpreg, sector_base_addr, sector_end_addr;
 621         u16 i;
 622
 623         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 624
 625         /* Can't read flash registers if the register set isn't mapped. */
 626         nvm->type = e1000_nvm_flash_sw;
 627         if (!hw->flash_address) {
 628                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 629                 return -E1000_ERR_CONFIG;
 630         }
 631
 632         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 633
 634         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 635          * Add 1 to sector_end_addr since this sector is included in
 636          * the overall size.
 637          */
 638         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 639         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 640
 641         /* flash_base_addr is byte-aligned */
 642         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 643
 644         /* find total size of the NVM, then cut in half since the total
 645          * size represents two separate NVM banks.
 646          */
 647         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 648                                 << FLASH_SECTOR_ADDR_SHIFT);
 649         nvm->flash_bank_size /= 2;
 650         /* Adjust to word count */
 651         nvm->flash_bank_size /= sizeof(u16);
 652
 653         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 654
 655         /* Clear shadow ram */
 656         for (i = 0; i < nvm->word_size; i++) {
 657                 dev_spec->shadow_ram[i].modified = false;
 658                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 659         }
 660
 661         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 662         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 663
 664         /* Function Pointers */
 665         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 666         nvm->ops.release        = e1000_release_nvm_ich8lan;
 667         nvm->ops.read           = e1000_read_nvm_ich8lan;
 668         nvm->ops.update         = e1000_update_nvm_checksum_ich8lan;
 669         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 670         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 671         nvm->ops.write          = e1000_write_nvm_ich8lan;
 672
 673         return E1000_SUCCESS;
 674 }
 675
 676 /**
 677  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 678  *  @hw: pointer to the HW structure
 679  *
 680  *  Initialize family-specific MAC parameters and function
 681  *  pointers.
 682  **/
 683 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 684 {
 685         struct e1000_mac_info *mac = &hw->mac;
 686 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 687         u16 pci_cfg;
 688 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 689
 690         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 691
 692         /* Set media type function pointer */
 693         hw->phy.media_type = e1000_media_type_copper;
 694
 695         /* Set mta register count */
 696         mac->mta_reg_count = 32;
 697         /* Set rar entry count */
 698         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 699         if (mac->type == e1000_ich8lan)
 700                 mac->rar_entry_count--;
 701         /* Set if part includes ASF firmware */
 702         mac->asf_firmware_present = true;
 703         /* FWSM register */
 704         mac->has_fwsm = true;
 705         /* ARC subsystem not supported */
 706         mac->arc_subsystem_valid = false;
 707         /* Adaptive IFS supported */
 708         mac->adaptive_ifs = true;
 709
 710         /* Function pointers */
 711
 712         /* bus type/speed/width */
 713         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 714         /* function id */
 715         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 716         /* reset */
 717         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 718         /* hw initialization */
 719         mac->ops.init_hw = e1000_init_hw_ich8lan;
 720         /* link setup */
 721         mac->ops.setup_link = e1000_setup_link_ich8lan;
 722         /* physical interface setup */
 723         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 724         /* check for link */
 725         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 726         /* link info */
 727         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 728         /* multicast address update */
 729         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 730         /* clear hardware counters */
 731         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 732
 733         /* LED and other operations */
 734         switch (mac->type) {
 735         case e1000_ich8lan:
 736         case e1000_ich9lan:
 737         case e1000_ich10lan:
 738                 /* check management mode */
 739                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 740                 /* ID LED init */
 741                 mac->ops.id_led_init = e1000_id_led_init_generic;
 742                 /* blink LED */
 743                 mac->ops.blink_led = e1000_blink_led_generic;
 744                 /* setup LED */
 745                 mac->ops.setup_led = e1000_setup_led_generic;
 746                 /* cleanup LED */
 747                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 748                 /* turn on/off LED */
 749                 mac->ops.led_on = e1000_led_on_ich8lan;
 750                 mac->ops.led_off = e1000_led_off_ich8lan;
 751                 break;
 752         case e1000_pch2lan:
 753                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 754                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 755                 /* fall-through */
 756         case e1000_pch_lpt:
 757 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 758                 /* multicast address update for pch2 */
 759                 mac->ops.update_mc_addr_list =
 760                         e1000_update_mc_addr_list_pch2lan;
 761 #endif
 762         case e1000_pchlan:
 763 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 764                 /* save PCH revision_id */
 765                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 766                 hw->revision_id = (u8)(pci_cfg &= 0x000F);
 767 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 768                 /* check management mode */
 769                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 770                 /* ID LED init */
 771                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 772                 /* setup LED */
 773                 mac->ops.setup_led = e1000_setup_led_pchlan;
 774                 /* cleanup LED */
 775                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 776                 /* turn on/off LED */
 777                 mac->ops.led_on = e1000_led_on_pchlan;
 778                 mac->ops.led_off = e1000_led_off_pchlan;
 779                 break;
 780         default:
 781                 break;
 782         }
 783
 784         if (mac->type == e1000_pch_lpt) {
 785                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 786                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 787                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 788         }
 789
 790         /* Enable PCS Lock-loss workaround for ICH8 */
 791         if (mac->type == e1000_ich8lan)
 792                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 793
 794         return E1000_SUCCESS;
 795 }
 796
 797 /**
 798  *  __e1000_access_emi_reg_locked - Read/write EMI register
 799  *  @hw: pointer to the HW structure
 800  *  @addr: EMI address to program
 801  *  @data: pointer to value to read/write from/to the EMI address
 802  *  @read: boolean flag to indicate read or write
 803  *
 804  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 805  **/
 806 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 807                                          u16 *data, bool read)
 808 {
 809         s32 ret_val;
 810
 811         DEBUGFUNC("__e1000_access_emi_reg_locked");
 812
 813         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 814         if (ret_val)
 815                 return ret_val;
 816
 817         if (read)
 818                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 819                                                       data);
 820         else
 821                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 822                                                        *data);
 823
 824         return ret_val;
 825 }
 826
 827 /**
 828  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 829  *  @hw: pointer to the HW structure
 830  *  @addr: EMI address to program
 831  *  @data: value to be read from the EMI address
 832  *
 833  *  Assumes the SW/FW/HW Semaphore is already acquired.
 834  **/
 835 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 836 {
 837         DEBUGFUNC("e1000_read_emi_reg_locked");
 838
 839         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 840 }
 841
 842 /**
 843  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 844  *  @hw: pointer to the HW structure
 845  *  @addr: EMI address to program
 846  *  @data: value to be written to the EMI address
 847  *
 848  *  Assumes the SW/FW/HW Semaphore is already acquired.
 849  **/
 850 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 851 {
 852         DEBUGFUNC("e1000_read_emi_reg_locked");
 853
 854         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 855 }
 856
 857 /**
 858  *  e1000_set_eee_pchlan - Enable/disable EEE support
 859  *  @hw: pointer to the HW structure
 860  *
 861  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 862  *  the link and the EEE capabilities of the link partner.  The LPI Control
 863  *  register bits will remain set only if/when link is up.
 864  *
 865  *  EEE LPI must not be asserted earlier than one second after link is up.
 866  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 867  *  can be link issues with some switches.  Other devices can have EEE LPI
 868  *  enabled immediately upon link up since they have a timer in hardware which
 869  *  prevents LPI from being asserted too early.
 870  **/
 871 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 872 {
 873         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 874         s32 ret_val;
 875         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 876
 877         DEBUGFUNC("e1000_set_eee_pchlan");
 878
 879         switch (hw->phy.type) {
 880         case e1000_phy_82579:
 881                 lpa = I82579_EEE_LP_ABILITY;
 882                 pcs_status = I82579_EEE_PCS_STATUS;
 883                 adv_addr = I82579_EEE_ADVERTISEMENT;
 884                 break;
 885         case e1000_phy_i217:
 886                 lpa = I217_EEE_LP_ABILITY;
 887                 pcs_status = I217_EEE_PCS_STATUS;
 888                 adv_addr = I217_EEE_ADVERTISEMENT;
 889                 break;
 890         default:
 891                 return E1000_SUCCESS;
 892         }
 893
 894         ret_val = hw->phy.ops.acquire(hw);
 895         if (ret_val)
 896                 return ret_val;
 897
 898         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 899         if (ret_val)
 900                 goto release;
 901
 902         /* Clear bits that enable EEE in various speeds */
 903         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 904
 905         /* Enable EEE if not disabled by user */
 906         if (!dev_spec->eee_disable) {
 907                 /* Save off link partner's EEE ability */
 908                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 909                                                     &dev_spec->eee_lp_ability);
 910                 if (ret_val)
 911                         goto release;
 912
 913                 /* Read EEE advertisement */
 914                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 915                 if (ret_val)
 916                         goto release;
 917
 918                 /* Enable EEE only for speeds in which the link partner is
 919                  * EEE capable and for which we advertise EEE.
 920                  */
 921                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 922                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 923
 924                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 925                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 926                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 927                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 928                         else
 929                                 /* EEE is not supported in 100Half, so ignore
 930                                  * partner's EEE in 100 ability if full-duplex
 931                                  * is not advertised.
 932                                  */
 933                                 dev_spec->eee_lp_ability &=
 934                                     ~I82579_EEE_100_SUPPORTED;
 935                 }
 936         }
 937
 938         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 939         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 940         if (ret_val)
 941                 goto release;
 942
 943         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 944 release:
 945         hw->phy.ops.release(hw);
 946
 947         return ret_val;
 948 }
 949
 950 /**
 951  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 952  *  @hw:   pointer to the HW structure
 953  *  @link: link up bool flag
 954  *
 955  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 956  *  preventing further DMA write requests.  Workaround the issue by disabling
 957  *  the de-assertion of the clock request when in 1Gpbs mode.
 958  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 959  *  speeds in order to avoid Tx hangs.
 960  **/
 961 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 962 {
 963         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
 964         u32 status = E1000_READ_REG(hw, E1000_STATUS);
 965         s32 ret_val = E1000_SUCCESS;
 966         u16 reg;
 967
 968         if (link && (status & E1000_STATUS_SPEED_1000)) {
 969                 ret_val = hw->phy.ops.acquire(hw);
 970                 if (ret_val)
 971                         return ret_val;
 972
 973                 ret_val =
 974                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 975                                                &reg);
 976                 if (ret_val)
 977                         goto release;
 978
 979                 ret_val =
 980                     e1000_write_kmrn_reg_locked(hw,
 981                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 982                                                 reg &
 983                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
 984                 if (ret_val)
 985                         goto release;
 986
 987                 usec_delay(10);
 988
 989                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
 990                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 991
 992                 ret_val =
 993                     e1000_write_kmrn_reg_locked(hw,
 994                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 995                                                 reg);
 996 release:
 997                 hw->phy.ops.release(hw);
 998         } else {
 999                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1000                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1001
1002                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1003                               (status & E1000_STATUS_FD)))
1004                         goto update_fextnvm6;
1005
1006                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1007                 if (ret_val)
1008                         return ret_val;
1009
1010                 /* Clear link status transmit timeout */
1011                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1012
1013                 if (status & E1000_STATUS_SPEED_100) {
1014                         /* Set inband Tx timeout to 5x10us for 100Half */
1015                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1016
1017                         /* Do not extend the K1 entry latency for 100Half */
1018                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1019                 } else {
1020                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1021                         reg |= 50 <<
1022                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1023
1024                         /* Extend the K1 entry latency for 10 Mbps */
1025                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1026                 }
1027
1028                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1029                 if (ret_val)
1030                         return ret_val;
1031
1032 update_fextnvm6:
1033                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1034         }
1035
1036         return ret_val;
1037 }
1038
1039 #if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)
1040 /**
1041  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1042  *  @hw: pointer to the HW structure
1043  *  @to_sx: boolean indicating a system power state transition to Sx
1044  *
1045  *  When link is down, configure ULP mode to significantly reduce the power
1046  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1047  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1048  *  system, configure the ULP mode by software.
1049  */
1050 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1051 {
1052         u32 mac_reg;
1053         s32 ret_val = E1000_SUCCESS;
1054         u16 phy_reg;
1055
1056         if ((hw->mac.type < e1000_pch_lpt) ||
1057             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1058             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1059             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1060             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1061             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1062                 return 0;
1063
1064         if (!to_sx) {
1065                 int i = 0;
1066                 /* Poll up to 5 seconds for Cable Disconnected indication */
1067                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1068                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1069                         /* Bail if link is re-acquired */
1070                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1071                                 return -E1000_ERR_PHY;
1072                         if (i++ == 100)
1073                                 break;
1074
1075                         msec_delay(50);
1076                 }
1077                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1078                           (E1000_READ_REG(hw, E1000_FEXT) &
1079                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1080                           i * 50);
1081         }
1082
1083         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1084                 /* Request ME configure ULP mode in the PHY */
1085                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1086                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1087                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1088
1089                 goto out;
1090         }
1091
1092         ret_val = hw->phy.ops.acquire(hw);
1093         if (ret_val)
1094                 goto out;
1095
1096         /* During S0 Idle keep the phy in PCI-E mode */
1097         if (hw->dev_spec.ich8lan.smbus_disable)
1098                 goto skip_smbus;
1099
1100         /* Force SMBus mode in PHY */
1101         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1102         if (ret_val)
1103                 goto release;
1104         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1105         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1106
1107         /* Force SMBus mode in MAC */
1108         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1109         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1110         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1111
1112 skip_smbus:
1113         if (!to_sx) {
1114                 /* Change the 'Link Status Change' interrupt to trigger
1115                  * on 'Cable Status Change'
1116                  */
1117                 ret_val = e1000_read_kmrn_reg_locked(hw,
1118                                                      E1000_KMRNCTRLSTA_OP_MODES,
1119                                                      &phy_reg);
1120                 if (ret_val)
1121                         goto release;
1122                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1123                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1124                                             phy_reg);
1125         }
1126
1127         /* Set Inband ULP Exit, Reset to SMBus mode and
1128          * Disable SMBus Release on PERST# in PHY
1129          */
1130         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1131         if (ret_val)
1132                 goto release;
1133         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1134                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1135         if (to_sx) {
1136                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1137                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1138
1139                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1140         } else {
1141                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1142         }
1143         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1144
1145         /* Set Disable SMBus Release on PERST# in MAC */
1146         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1147         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1148         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1149
1150         /* Commit ULP changes in PHY by starting auto ULP configuration */
1151         phy_reg |= I218_ULP_CONFIG1_START;
1152         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1153
1154         if (!to_sx) {
1155                 /* Disable Tx so that the MAC doesn't send any (buffered)
1156                  * packets to the PHY.
1157                  */
1158                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1159                 mac_reg &= ~E1000_TCTL_EN;
1160                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1161         }
1162 release:
1163         hw->phy.ops.release(hw);
1164 out:
1165         if (ret_val)
1166                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1167         else
1168                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1169
1170         return ret_val;
1171 }
1172
1173 /**
1174  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1175  *  @hw: pointer to the HW structure
1176  *  @force: boolean indicating whether or not to force disabling ULP
1177  *
1178  *  Un-configure ULP mode when link is up, the system is transitioned from
1179  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1180  *  system, poll for an indication from ME that ULP has been un-configured.
1181  *  If not on an ME enabled system, un-configure the ULP mode by software.
1182  *
1183  *  During nominal operation, this function is called when link is acquired
1184  *  to disable ULP mode (force=false); otherwise, for example when unloading
1185  *  the driver or during Sx->S0 transitions, this is called with force=true
1186  *  to forcibly disable ULP.
1187
1188  *  When the cable is plugged in while the device is in D0, a Cable Status
1189  *  Change interrupt is generated which causes this function to be called
1190  *  to partially disable ULP mode and restart autonegotiation.  This function
1191  *  is then called again due to the resulting Link Status Change interrupt
1192  *  to finish cleaning up after the ULP flow.
1193  */
1194 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1195 {
1196         s32 ret_val = E1000_SUCCESS;
1197         u32 mac_reg;
1198         u16 phy_reg;
1199         int i = 0;
1200
1201         if ((hw->mac.type < e1000_pch_lpt) ||
1202             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1203             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1204             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1205             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1206             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1207                 return 0;
1208
1209         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1210                 if (force) {
1211                         /* Request ME un-configure ULP mode in the PHY */
1212                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1213                         mac_reg &= ~E1000_H2ME_ULP;
1214                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1215                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1216                 }
1217
1218                 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1219                 while (E1000_READ_REG(hw, E1000_FWSM) &
1220                        E1000_FWSM_ULP_CFG_DONE) {
1221                         if (i++ == 10) {
1222                                 ret_val = -E1000_ERR_PHY;
1223                                 goto out;
1224                         }
1225
1226                         msec_delay(10);
1227                 }
1228                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1229
1230                 if (force) {
1231                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1232                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1233                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1234                 } else {
1235                         /* Clear H2ME.ULP after ME ULP configuration */
1236                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1237                         mac_reg &= ~E1000_H2ME_ULP;
1238                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1239
1240                         /* Restore link speed advertisements and restart
1241                          * Auto-negotiation
1242                          */
1243                         ret_val = e1000_phy_setup_autoneg(hw);
1244                         if (ret_val)
1245                                 goto out;
1246
1247                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1248                 }
1249
1250                 goto out;
1251         }
1252
1253         ret_val = hw->phy.ops.acquire(hw);
1254         if (ret_val)
1255                 goto out;
1256
1257         /* Revert the change to the 'Link Status Change'
1258          * interrupt to trigger on 'Cable Status Change'
1259          */
1260         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1261                                              &phy_reg);
1262         if (ret_val)
1263                 goto release;
1264         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1265         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1266
1267         if (force)
1268                 /* Toggle LANPHYPC Value bit */
1269                 e1000_toggle_lanphypc_pch_lpt(hw);
1270
1271         /* Unforce SMBus mode in PHY */
1272         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1273         if (ret_val) {
1274                 /* The MAC might be in PCIe mode, so temporarily force to
1275                  * SMBus mode in order to access the PHY.
1276                  */
1277                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1278                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1279                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1280
1281                 msec_delay(50);
1282
1283                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1284                                                        &phy_reg);
1285                 if (ret_val)
1286                         goto release;
1287         }
1288         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1289         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1290
1291         /* Unforce SMBus mode in MAC */
1292         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1293         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1294         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1295
1296         /* When ULP mode was previously entered, K1 was disabled by the
1297          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1298          */
1299         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1300         if (ret_val)
1301                 goto release;
1302         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1303         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1304
1305         /* Clear ULP enabled configuration */
1306         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1307         if (ret_val)
1308                 goto release;
1309         /* CSC interrupt received due to ULP Indication */
1310         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1311                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1312                              I218_ULP_CONFIG1_STICKY_ULP |
1313                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1314                              I218_ULP_CONFIG1_WOL_HOST |
1315                              I218_ULP_CONFIG1_INBAND_EXIT |
1316                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1317                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1318
1319                 /* Commit ULP changes by starting auto ULP configuration */
1320                 phy_reg |= I218_ULP_CONFIG1_START;
1321                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1322
1323                 /* Clear Disable SMBus Release on PERST# in MAC */
1324                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1325                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1326                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1327
1328                 if (!force) {
1329                         hw->phy.ops.release(hw);
1330
1331                         if (hw->mac.autoneg)
1332                                 e1000_phy_setup_autoneg(hw);
1333
1334                         e1000_sw_lcd_config_ich8lan(hw);
1335
1336                         e1000_oem_bits_config_ich8lan(hw, true);
1337
1338                         /* Set ULP state to unknown and return non-zero to
1339                          * indicate no link (yet) and re-enter on the next LSC
1340                          * to finish disabling ULP flow.
1341                          */
1342                         hw->dev_spec.ich8lan.ulp_state =
1343                             e1000_ulp_state_unknown;
1344
1345                         return 1;
1346                 }
1347         }
1348
1349         /* Re-enable Tx */
1350         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1351         mac_reg |= E1000_TCTL_EN;
1352         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1353
1354 release:
1355         hw->phy.ops.release(hw);
1356         if (force) {
1357                 hw->phy.ops.reset(hw);
1358                 msec_delay(50);
1359         }
1360 out:
1361         if (ret_val)
1362                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1363         else
1364                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1365
1366         return ret_val;
1367 }
1368
1369 #endif /* NAHUM6LP_HW && ULP_SUPPORT */
1370 /**
1371  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1372  *  @hw: pointer to the HW structure
1373  *
1374  *  Checks to see of the link status of the hardware has changed.  If a
1375  *  change in link status has been detected, then we read the PHY registers
1376  *  to get the current speed/duplex if link exists.
1377  **/
1378 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1379 {
1380         struct e1000_mac_info *mac = &hw->mac;
1381         s32 ret_val;
1382         bool link = false;
1383         u16 phy_reg;
1384
1385         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1386
1387         /* We only want to go out to the PHY registers to see if Auto-Neg
1388          * has completed and/or if our link status has changed.  The
1389          * get_link_status flag is set upon receiving a Link Status
1390          * Change or Rx Sequence Error interrupt.
1391          */
1392         if (!mac->get_link_status)
1393                 return E1000_SUCCESS;
1394
1395         if ((hw->mac.type < e1000_pch_lpt) ||
1396             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1397             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1398                 /* First we want to see if the MII Status Register reports
1399                  * link.  If so, then we want to get the current speed/duplex
1400                  * of the PHY.
1401                  */
1402                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1403                 if (ret_val)
1404                         return ret_val;
1405         } else {
1406                 /* Check the MAC's STATUS register to determine link state
1407                  * since the PHY could be inaccessible while in ULP mode.
1408                  */
1409                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1410                 if (link)
1411                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1412                 else
1413                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1414
1415                 if (ret_val)
1416                         return ret_val;
1417         }
1418
1419         if (hw->mac.type == e1000_pchlan) {
1420                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1421                 if (ret_val)
1422                         return ret_val;
1423         }
1424
1425         /* When connected at 10Mbps half-duplex, some parts are excessively
1426          * aggressive resulting in many collisions. To avoid this, increase
1427          * the IPG and reduce Rx latency in the PHY.
1428          */
1429         if (((hw->mac.type == e1000_pch2lan) ||
1430              (hw->mac.type == e1000_pch_lpt)) && link) {
1431                 u32 reg;
1432                 reg = E1000_READ_REG(hw, E1000_STATUS);
1433                 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1434                         u16 emi_addr;
1435
1436                         reg = E1000_READ_REG(hw, E1000_TIPG);
1437                         reg &= ~E1000_TIPG_IPGT_MASK;
1438                         reg |= 0xFF;
1439                         E1000_WRITE_REG(hw, E1000_TIPG, reg);
1440
1441                         /* Reduce Rx latency in analog PHY */
1442                         ret_val = hw->phy.ops.acquire(hw);
1443                         if (ret_val)
1444                                 return ret_val;
1445
1446                         if (hw->mac.type == e1000_pch2lan)
1447                                 emi_addr = I82579_RX_CONFIG;
1448                         else
1449                                 emi_addr = I217_RX_CONFIG;
1450                         ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1451
1452                         hw->phy.ops.release(hw);
1453
1454                         if (ret_val)
1455                                 return ret_val;
1456                 }
1457         }
1458
1459         /* Work-around I218 hang issue */
1460         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1461             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1462             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1463             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1464                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1465                 if (ret_val)
1466                         return ret_val;
1467         }
1468
1469         /* Clear link partner's EEE ability */
1470         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1471
1472         if (!link)
1473                 return E1000_SUCCESS; /* No link detected */
1474
1475         mac->get_link_status = false;
1476
1477         switch (hw->mac.type) {
1478         case e1000_pch2lan:
1479                 ret_val = e1000_k1_workaround_lv(hw);
1480                 if (ret_val)
1481                         return ret_val;
1482                 /* fall-thru */
1483         case e1000_pchlan:
1484                 if (hw->phy.type == e1000_phy_82578) {
1485                         ret_val = e1000_link_stall_workaround_hv(hw);
1486                         if (ret_val)
1487                                 return ret_val;
1488                 }
1489
1490                 /* Workaround for PCHx parts in half-duplex:
1491                  * Set the number of preambles removed from the packet
1492                  * when it is passed from the PHY to the MAC to prevent
1493                  * the MAC from misinterpreting the packet type.
1494                  */
1495                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1496                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1497
1498                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1499                     E1000_STATUS_FD)
1500                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1501
1502                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1503                 break;
1504         default:
1505                 break;
1506         }
1507
1508         /* Check if there was DownShift, must be checked
1509          * immediately after link-up
1510          */
1511         e1000_check_downshift_generic(hw);
1512
1513         /* Enable/Disable EEE after link up */
1514         if (hw->phy.type > e1000_phy_82579) {
1515                 ret_val = e1000_set_eee_pchlan(hw);
1516                 if (ret_val)
1517                         return ret_val;
1518         }
1519
1520         /* If we are forcing speed/duplex, then we simply return since
1521          * we have already determined whether we have link or not.
1522          */
1523         if (!mac->autoneg)
1524                 return -E1000_ERR_CONFIG;
1525
1526         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1527          * of MAC speed/duplex configuration.  So we only need to
1528          * configure Collision Distance in the MAC.
1529          */
1530         mac->ops.config_collision_dist(hw);
1531
1532         /* Configure Flow Control now that Auto-Neg has completed.
1533          * First, we need to restore the desired flow control
1534          * settings because we may have had to re-autoneg with a
1535          * different link partner.
1536          */
1537         ret_val = e1000_config_fc_after_link_up_generic(hw);
1538         if (ret_val)
1539                 DEBUGOUT("Error configuring flow control\n");
1540
1541         return ret_val;
1542 }
1543
1544 /**
1545  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1546  *  @hw: pointer to the HW structure
1547  *
1548  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1549  **/
1550 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1551 {
1552         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1553
1554         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1555         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1556         switch (hw->mac.type) {
1557         case e1000_ich8lan:
1558         case e1000_ich9lan:
1559         case e1000_ich10lan:
1560                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1561                 break;
1562         case e1000_pchlan:
1563         case e1000_pch2lan:
1564         case e1000_pch_lpt:
1565                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1566                 break;
1567         default:
1568                 break;
1569         }
1570 }
1571
1572 /**
1573  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1574  *  @hw: pointer to the HW structure
1575  *
1576  *  Acquires the mutex for performing NVM operations.
1577  **/
1578 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1579 {
1580         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1581
1582         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1583
1584         return E1000_SUCCESS;
1585 }
1586
1587 /**
1588  *  e1000_release_nvm_ich8lan - Release NVM mutex
1589  *  @hw: pointer to the HW structure
1590  *
1591  *  Releases the mutex used while performing NVM operations.
1592  **/
1593 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1594 {
1595         DEBUGFUNC("e1000_release_nvm_ich8lan");
1596
1597         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1598
1599         return;
1600 }
1601
1602 /**
1603  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1604  *  @hw: pointer to the HW structure
1605  *
1606  *  Acquires the software control flag for performing PHY and select
1607  *  MAC CSR accesses.
1608  **/
1609 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1610 {
1611         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1612         s32 ret_val = E1000_SUCCESS;
1613
1614         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1615
1616         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1617
1618         while (timeout) {
1619                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1620                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1621                         break;
1622
1623                 msec_delay_irq(1);
1624                 timeout--;
1625         }
1626
1627         if (!timeout) {
1628                 DEBUGOUT("SW has already locked the resource.\n");
1629                 ret_val = -E1000_ERR_CONFIG;
1630                 goto out;
1631         }
1632
1633         timeout = SW_FLAG_TIMEOUT;
1634
1635         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1636         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1637
1638         while (timeout) {
1639                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1640                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1641                         break;
1642
1643                 msec_delay_irq(1);
1644                 timeout--;
1645         }
1646
1647         if (!timeout) {
1648                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1649                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1650                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1651                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1652                 ret_val = -E1000_ERR_CONFIG;
1653                 goto out;
1654         }
1655
1656 out:
1657         if (ret_val)
1658                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1659
1660         return ret_val;
1661 }
1662
1663 /**
1664  *  e1000_release_swflag_ich8lan - Release software control flag
1665  *  @hw: pointer to the HW structure
1666  *
1667  *  Releases the software control flag for performing PHY and select
1668  *  MAC CSR accesses.
1669  **/
1670 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1671 {
1672         u32 extcnf_ctrl;
1673
1674         DEBUGFUNC("e1000_release_swflag_ich8lan");
1675
1676         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1677
1678         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1679                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1680                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1681         } else {
1682                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1683         }
1684
1685         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1686
1687         return;
1688 }
1689
1690 /**
1691  *  e1000_check_mng_mode_ich8lan - Checks management mode
1692  *  @hw: pointer to the HW structure
1693  *
1694  *  This checks if the adapter has any manageability enabled.
1695  *  This is a function pointer entry point only called by read/write
1696  *  routines for the PHY and NVM parts.
1697  **/
1698 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1699 {
1700         u32 fwsm;
1701
1702         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1703
1704         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1705
1706         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1707                ((fwsm & E1000_FWSM_MODE_MASK) ==
1708                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1709 }
1710
1711 /**
1712  *  e1000_check_mng_mode_pchlan - Checks management mode
1713  *  @hw: pointer to the HW structure
1714  *
1715  *  This checks if the adapter has iAMT enabled.
1716  *  This is a function pointer entry point only called by read/write
1717  *  routines for the PHY and NVM parts.
1718  **/
1719 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1720 {
1721         u32 fwsm;
1722
1723         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1724
1725         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1726
1727         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1728                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1729 }
1730
1731 /**
1732  *  e1000_rar_set_pch2lan - Set receive address register
1733  *  @hw: pointer to the HW structure
1734  *  @addr: pointer to the receive address
1735  *  @index: receive address array register
1736  *
1737  *  Sets the receive address array register at index to the address passed
1738  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1739  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1740  *  Use SHRA[0-3] in place of those reserved for ME.
1741  **/
1742 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1743 {
1744         u32 rar_low, rar_high;
1745
1746         DEBUGFUNC("e1000_rar_set_pch2lan");
1747
1748         /* HW expects these in little endian so we reverse the byte order
1749          * from network order (big endian) to little endian
1750          */
1751         rar_low = ((u32) addr[0] |
1752                    ((u32) addr[1] << 8) |
1753                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1754
1755         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1756
1757         /* If MAC address zero, no need to set the AV bit */
1758         if (rar_low || rar_high)
1759                 rar_high |= E1000_RAH_AV;
1760
1761         if (index == 0) {
1762                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1763                 E1000_WRITE_FLUSH(hw);
1764                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1765                 E1000_WRITE_FLUSH(hw);
1766                 return;
1767         }
1768
1769         /* RAR[1-6] are owned by manageability.  Skip those and program the
1770          * next address into the SHRA register array.
1771          */
1772         if (index < (u32) (hw->mac.rar_entry_count)) {
1773                 s32 ret_val;
1774
1775                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1776                 if (ret_val)
1777                         goto out;
1778
1779                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1780                 E1000_WRITE_FLUSH(hw);
1781                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1782                 E1000_WRITE_FLUSH(hw);
1783
1784                 e1000_release_swflag_ich8lan(hw);
1785
1786                 /* verify the register updates */
1787                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1788                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1789                         return;
1790
1791                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1792                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1793         }
1794
1795 out:
1796         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1797 }
1798
1799 /**
1800  *  e1000_rar_set_pch_lpt - Set receive address registers
1801  *  @hw: pointer to the HW structure
1802  *  @addr: pointer to the receive address
1803  *  @index: receive address array register
1804  *
1805  *  Sets the receive address register array at index to the address passed
1806  *  in by addr. For LPT, RAR[0] is the base address register that is to
1807  *  contain the MAC address. SHRA[0-10] are the shared receive address
1808  *  registers that are shared between the Host and manageability engine (ME).
1809  **/
1810 STATIC void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1811 {
1812         u32 rar_low, rar_high;
1813         u32 wlock_mac;
1814
1815         DEBUGFUNC("e1000_rar_set_pch_lpt");
1816
1817         /* HW expects these in little endian so we reverse the byte order
1818          * from network order (big endian) to little endian
1819          */
1820         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1821                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1822
1823         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1824
1825         /* If MAC address zero, no need to set the AV bit */
1826         if (rar_low || rar_high)
1827                 rar_high |= E1000_RAH_AV;
1828
1829         if (index == 0) {
1830                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1831                 E1000_WRITE_FLUSH(hw);
1832                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1833                 E1000_WRITE_FLUSH(hw);
1834                 return;
1835         }
1836
1837         /* The manageability engine (ME) can lock certain SHRAR registers that
1838          * it is using - those registers are unavailable for use.
1839          */
1840         if (index < hw->mac.rar_entry_count) {
1841                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1842                             E1000_FWSM_WLOCK_MAC_MASK;
1843                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1844
1845                 /* Check if all SHRAR registers are locked */
1846                 if (wlock_mac == 1)
1847                         goto out;
1848
1849                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1850                         s32 ret_val;
1851
1852                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1853
1854                         if (ret_val)
1855                                 goto out;
1856
1857                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1858                                         rar_low);
1859                         E1000_WRITE_FLUSH(hw);
1860                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1861                                         rar_high);
1862                         E1000_WRITE_FLUSH(hw);
1863
1864                         e1000_release_swflag_ich8lan(hw);
1865
1866                         /* verify the register updates */
1867                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1868                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1869                                 return;
1870                 }
1871         }
1872
1873 out:
1874         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1875 }
1876
1877 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1878 /**
1879  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1880  *  @hw: pointer to the HW structure
1881  *  @mc_addr_list: array of multicast addresses to program
1882  *  @mc_addr_count: number of multicast addresses to program
1883  *
1884  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1885  *  The caller must have a packed mc_addr_list of multicast addresses.
1886  **/
1887 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1888                                               u8 *mc_addr_list,
1889                                               u32 mc_addr_count)
1890 {
1891         u16 phy_reg = 0;
1892         int i;
1893         s32 ret_val;
1894
1895         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1896
1897         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1898
1899         ret_val = hw->phy.ops.acquire(hw);
1900         if (ret_val)
1901                 return;
1902
1903         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1904         if (ret_val)
1905                 goto release;
1906
1907         for (i = 0; i < hw->mac.mta_reg_count; i++) {
1908                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1909                                            (u16)(hw->mac.mta_shadow[i] &
1910                                                  0xFFFF));
1911                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1912                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
1913                                                  0xFFFF));
1914         }
1915
1916         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1917
1918 release:
1919         hw->phy.ops.release(hw);
1920 }
1921
1922 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1923 /**
1924  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1925  *  @hw: pointer to the HW structure
1926  *
1927  *  Checks if firmware is blocking the reset of the PHY.
1928  *  This is a function pointer entry point only called by
1929  *  reset routines.
1930  **/
1931 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1932 {
1933         u32 fwsm;
1934         bool blocked = false;
1935         int i = 0;
1936
1937         DEBUGFUNC("e1000_check_reset_block_ich8lan");
1938
1939         do {
1940                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1941                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
1942                         blocked = true;
1943                         msec_delay(10);
1944                         continue;
1945                 }
1946                 blocked = false;
1947         } while (blocked && (i++ < 10));
1948         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
1949 }
1950
1951 /**
1952  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1953  *  @hw: pointer to the HW structure
1954  *
1955  *  Assumes semaphore already acquired.
1956  *
1957  **/
1958 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1959 {
1960         u16 phy_data;
1961         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
1962         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1963                 E1000_STRAP_SMT_FREQ_SHIFT;
1964         s32 ret_val;
1965
1966         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1967
1968         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1969         if (ret_val)
1970                 return ret_val;
1971
1972         phy_data &= ~HV_SMB_ADDR_MASK;
1973         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1974         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1975
1976         if (hw->phy.type == e1000_phy_i217) {
1977                 /* Restore SMBus frequency */
1978                 if (freq--) {
1979                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1980                         phy_data |= (freq & (1 << 0)) <<
1981                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1982                         phy_data |= (freq & (1 << 1)) <<
1983                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1984                 } else {
1985                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
1986                 }
1987         }
1988
1989         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1990 }
1991
1992 /**
1993  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1994  *  @hw:   pointer to the HW structure
1995  *
1996  *  SW should configure the LCD from the NVM extended configuration region
1997  *  as a workaround for certain parts.
1998  **/
1999 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2000 {
2001         struct e1000_phy_info *phy = &hw->phy;
2002         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2003         s32 ret_val = E1000_SUCCESS;
2004         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2005
2006         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2007
2008         /* Initialize the PHY from the NVM on ICH platforms.  This
2009          * is needed due to an issue where the NVM configuration is
2010          * not properly autoloaded after power transitions.
2011          * Therefore, after each PHY reset, we will load the
2012          * configuration data out of the NVM manually.
2013          */
2014         switch (hw->mac.type) {
2015         case e1000_ich8lan:
2016                 if (phy->type != e1000_phy_igp_3)
2017                         return ret_val;
2018
2019                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2020                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2021                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2022                         break;
2023                 }
2024                 /* Fall-thru */
2025         case e1000_pchlan:
2026         case e1000_pch2lan:
2027         case e1000_pch_lpt:
2028                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2029                 break;
2030         default:
2031                 return ret_val;
2032         }
2033
2034         ret_val = hw->phy.ops.acquire(hw);
2035         if (ret_val)
2036                 return ret_val;
2037
2038         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2039         if (!(data & sw_cfg_mask))
2040                 goto release;
2041
2042         /* Make sure HW does not configure LCD from PHY
2043          * extended configuration before SW configuration
2044          */
2045         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2046         if ((hw->mac.type < e1000_pch2lan) &&
2047             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2048                         goto release;
2049
2050         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2051         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2052         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2053         if (!cnf_size)
2054                 goto release;
2055
2056         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2057         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2058
2059         if (((hw->mac.type == e1000_pchlan) &&
2060              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2061             (hw->mac.type > e1000_pchlan)) {
2062                 /* HW configures the SMBus address and LEDs when the
2063                  * OEM and LCD Write Enable bits are set in the NVM.
2064                  * When both NVM bits are cleared, SW will configure
2065                  * them instead.
2066                  */
2067                 ret_val = e1000_write_smbus_addr(hw);
2068                 if (ret_val)
2069                         goto release;
2070
2071                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2072                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2073                                                         (u16)data);
2074                 if (ret_val)
2075                         goto release;
2076         }
2077
2078         /* Configure LCD from extended configuration region. */
2079
2080         /* cnf_base_addr is in DWORD */
2081         word_addr = (u16)(cnf_base_addr << 1);
2082
2083         for (i = 0; i < cnf_size; i++) {
2084                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2085                                            &reg_data);
2086                 if (ret_val)
2087                         goto release;
2088
2089                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2090                                            1, &reg_addr);
2091                 if (ret_val)
2092                         goto release;
2093
2094                 /* Save off the PHY page for future writes. */
2095                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2096                         phy_page = reg_data;
2097                         continue;
2098                 }
2099
2100                 reg_addr &= PHY_REG_MASK;
2101                 reg_addr |= phy_page;
2102
2103                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2104                                                     reg_data);
2105                 if (ret_val)
2106                         goto release;
2107         }
2108
2109 release:
2110         hw->phy.ops.release(hw);
2111         return ret_val;
2112 }
2113
2114 /**
2115  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2116  *  @hw:   pointer to the HW structure
2117  *  @link: link up bool flag
2118  *
2119  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2120  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2121  *  If link is down, the function will restore the default K1 setting located
2122  *  in the NVM.
2123  **/
2124 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2125 {
2126         s32 ret_val = E1000_SUCCESS;
2127         u16 status_reg = 0;
2128         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2129
2130         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2131
2132         if (hw->mac.type != e1000_pchlan)
2133                 return E1000_SUCCESS;
2134
2135         /* Wrap the whole flow with the sw flag */
2136         ret_val = hw->phy.ops.acquire(hw);
2137         if (ret_val)
2138                 return ret_val;
2139
2140         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2141         if (link) {
2142                 if (hw->phy.type == e1000_phy_82578) {
2143                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2144                                                               &status_reg);
2145                         if (ret_val)
2146                                 goto release;
2147
2148                         status_reg &= (BM_CS_STATUS_LINK_UP |
2149                                        BM_CS_STATUS_RESOLVED |
2150                                        BM_CS_STATUS_SPEED_MASK);
2151
2152                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2153                                            BM_CS_STATUS_RESOLVED |
2154                                            BM_CS_STATUS_SPEED_1000))
2155                                 k1_enable = false;
2156                 }
2157
2158                 if (hw->phy.type == e1000_phy_82577) {
2159                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2160                                                               &status_reg);
2161                         if (ret_val)
2162                                 goto release;
2163
2164                         status_reg &= (HV_M_STATUS_LINK_UP |
2165                                        HV_M_STATUS_AUTONEG_COMPLETE |
2166                                        HV_M_STATUS_SPEED_MASK);
2167
2168                         if (status_reg == (HV_M_STATUS_LINK_UP |
2169                                            HV_M_STATUS_AUTONEG_COMPLETE |
2170                                            HV_M_STATUS_SPEED_1000))
2171                                 k1_enable = false;
2172                 }
2173
2174                 /* Link stall fix for link up */
2175                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2176                                                        0x0100);
2177                 if (ret_val)
2178                         goto release;
2179
2180         } else {
2181                 /* Link stall fix for link down */
2182                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2183                                                        0x4100);
2184                 if (ret_val)
2185                         goto release;
2186         }
2187
2188         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2189
2190 release:
2191         hw->phy.ops.release(hw);
2192
2193         return ret_val;
2194 }
2195
2196 /**
2197  *  e1000_configure_k1_ich8lan - Configure K1 power state
2198  *  @hw: pointer to the HW structure
2199  *  @enable: K1 state to configure
2200  *
2201  *  Configure the K1 power state based on the provided parameter.
2202  *  Assumes semaphore already acquired.
2203  *
2204  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2205  **/
2206 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2207 {
2208         s32 ret_val;
2209         u32 ctrl_reg = 0;
2210         u32 ctrl_ext = 0;
2211         u32 reg = 0;
2212         u16 kmrn_reg = 0;
2213
2214         DEBUGFUNC("e1000_configure_k1_ich8lan");
2215
2216         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2217                                              &kmrn_reg);
2218         if (ret_val)
2219                 return ret_val;
2220
2221         if (k1_enable)
2222                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2223         else
2224                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2225
2226         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2227                                               kmrn_reg);
2228         if (ret_val)
2229                 return ret_val;
2230
2231         usec_delay(20);
2232         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2233         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2234
2235         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2236         reg |= E1000_CTRL_FRCSPD;
2237         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2238
2239         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2240         E1000_WRITE_FLUSH(hw);
2241         usec_delay(20);
2242         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2243         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2244         E1000_WRITE_FLUSH(hw);
2245         usec_delay(20);
2246
2247         return E1000_SUCCESS;
2248 }
2249
2250 /**
2251  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2252  *  @hw:       pointer to the HW structure
2253  *  @d0_state: boolean if entering d0 or d3 device state
2254  *
2255  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2256  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2257  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2258  **/
2259 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2260 {
2261         s32 ret_val = 0;
2262         u32 mac_reg;
2263         u16 oem_reg;
2264
2265         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2266
2267         if (hw->mac.type < e1000_pchlan)
2268                 return ret_val;
2269
2270         ret_val = hw->phy.ops.acquire(hw);
2271         if (ret_val)
2272                 return ret_val;
2273
2274         if (hw->mac.type == e1000_pchlan) {
2275                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2276                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2277                         goto release;
2278         }
2279
2280         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2281         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2282                 goto release;
2283
2284         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2285
2286         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2287         if (ret_val)
2288                 goto release;
2289
2290         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2291
2292         if (d0_state) {
2293                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2294                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2295
2296                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2297                         oem_reg |= HV_OEM_BITS_LPLU;
2298         } else {
2299                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2300                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2301                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2302
2303                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2304                     E1000_PHY_CTRL_NOND0A_LPLU))
2305                         oem_reg |= HV_OEM_BITS_LPLU;
2306         }
2307
2308         /* Set Restart auto-neg to activate the bits */
2309         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2310             !hw->phy.ops.check_reset_block(hw))
2311                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2312
2313         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2314
2315 release:
2316         hw->phy.ops.release(hw);
2317
2318         return ret_val;
2319 }
2320
2321
2322 /**
2323  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2324  *  @hw:   pointer to the HW structure
2325  **/
2326 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2327 {
2328         s32 ret_val;
2329         u16 data;
2330
2331         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2332
2333         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2334         if (ret_val)
2335                 return ret_val;
2336
2337         data |= HV_KMRN_MDIO_SLOW;
2338
2339         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2340
2341         return ret_val;
2342 }
2343
2344 /**
2345  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2346  *  done after every PHY reset.
2347  **/
2348 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2349 {
2350         s32 ret_val = E1000_SUCCESS;
2351         u16 phy_data;
2352
2353         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2354
2355         if (hw->mac.type != e1000_pchlan)
2356                 return E1000_SUCCESS;
2357
2358         /* Set MDIO slow mode before any other MDIO access */
2359         if (hw->phy.type == e1000_phy_82577) {
2360                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2361                 if (ret_val)
2362                         return ret_val;
2363         }
2364
2365         if (((hw->phy.type == e1000_phy_82577) &&
2366              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2367             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2368                 /* Disable generation of early preamble */
2369                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2370                 if (ret_val)
2371                         return ret_val;
2372
2373                 /* Preamble tuning for SSC */
2374                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2375                                                 0xA204);
2376                 if (ret_val)
2377                         return ret_val;
2378         }
2379
2380         if (hw->phy.type == e1000_phy_82578) {
2381                 /* Return registers to default by doing a soft reset then
2382                  * writing 0x3140 to the control register.
2383                  */
2384                 if (hw->phy.revision < 2) {
2385                         e1000_phy_sw_reset_generic(hw);
2386                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2387                                                         0x3140);
2388                 }
2389         }
2390
2391         /* Select page 0 */
2392         ret_val = hw->phy.ops.acquire(hw);
2393         if (ret_val)
2394                 return ret_val;
2395
2396         hw->phy.addr = 1;
2397         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2398         hw->phy.ops.release(hw);
2399         if (ret_val)
2400                 return ret_val;
2401
2402         /* Configure the K1 Si workaround during phy reset assuming there is
2403          * link so that it disables K1 if link is in 1Gbps.
2404          */
2405         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2406         if (ret_val)
2407                 return ret_val;
2408
2409         /* Workaround for link disconnects on a busy hub in half duplex */
2410         ret_val = hw->phy.ops.acquire(hw);
2411         if (ret_val)
2412                 return ret_val;
2413         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2414         if (ret_val)
2415                 goto release;
2416         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2417                                                phy_data & 0x00FF);
2418         if (ret_val)
2419                 goto release;
2420
2421         /* set MSE higher to enable link to stay up when noise is high */
2422         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2423 release:
2424         hw->phy.ops.release(hw);
2425
2426         return ret_val;
2427 }
2428
2429 /**
2430  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2431  *  @hw:   pointer to the HW structure
2432  **/
2433 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2434 {
2435         u32 mac_reg;
2436         u16 i, phy_reg = 0;
2437         s32 ret_val;
2438
2439         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2440
2441         ret_val = hw->phy.ops.acquire(hw);
2442         if (ret_val)
2443                 return;
2444         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2445         if (ret_val)
2446                 goto release;
2447
2448         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2449         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2450                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2451                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2452                                            (u16)(mac_reg & 0xFFFF));
2453                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2454                                            (u16)((mac_reg >> 16) & 0xFFFF));
2455
2456                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2457                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2458                                            (u16)(mac_reg & 0xFFFF));
2459                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2460                                            (u16)((mac_reg & E1000_RAH_AV)
2461                                                  >> 16));
2462         }
2463
2464         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2465
2466 release:
2467         hw->phy.ops.release(hw);
2468 }
2469
2470 #ifndef CRC32_OS_SUPPORT
2471 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2472 {
2473         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2474         u32 i, j, mask, crc;
2475
2476         DEBUGFUNC("e1000_calc_rx_da_crc");
2477
2478         crc = 0xffffffff;
2479         for (i = 0; i < 6; i++) {
2480                 crc = crc ^ mac[i];
2481                 for (j = 8; j > 0; j--) {
2482                         mask = (crc & 1) * (-1);
2483                         crc = (crc >> 1) ^ (poly & mask);
2484                 }
2485         }
2486         return ~crc;
2487 }
2488
2489 #endif /* CRC32_OS_SUPPORT */
2490 /**
2491  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2492  *  with 82579 PHY
2493  *  @hw: pointer to the HW structure
2494  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2495  **/
2496 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2497 {
2498         s32 ret_val = E1000_SUCCESS;
2499         u16 phy_reg, data;
2500         u32 mac_reg;
2501         u16 i;
2502
2503         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2504
2505         if (hw->mac.type < e1000_pch2lan)
2506                 return E1000_SUCCESS;
2507
2508         /* disable Rx path while enabling/disabling workaround */
2509         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2510         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2511                                         phy_reg | (1 << 14));
2512         if (ret_val)
2513                 return ret_val;
2514
2515         if (enable) {
2516                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2517                  * SHRAL/H) and initial CRC values to the MAC
2518                  */
2519                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2520                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2521                         u32 addr_high, addr_low;
2522
2523                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2524                         if (!(addr_high & E1000_RAH_AV))
2525                                 continue;
2526                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2527                         mac_addr[0] = (addr_low & 0xFF);
2528                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2529                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2530                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2531                         mac_addr[4] = (addr_high & 0xFF);
2532                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2533
2534 #ifndef CRC32_OS_SUPPORT
2535                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2536                                         e1000_calc_rx_da_crc(mac_addr));
2537 #else /* CRC32_OS_SUPPORT */
2538                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2539                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2540 #endif /* CRC32_OS_SUPPORT */
2541                 }
2542
2543                 /* Write Rx addresses to the PHY */
2544                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2545
2546                 /* Enable jumbo frame workaround in the MAC */
2547                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2548                 mac_reg &= ~(1 << 14);
2549                 mac_reg |= (7 << 15);
2550                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2551
2552                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2553                 mac_reg |= E1000_RCTL_SECRC;
2554                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2555
2556                 ret_val = e1000_read_kmrn_reg_generic(hw,
2557                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2558                                                 &data);
2559                 if (ret_val)
2560                         return ret_val;
2561                 ret_val = e1000_write_kmrn_reg_generic(hw,
2562                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2563                                                 data | (1 << 0));
2564                 if (ret_val)
2565                         return ret_val;
2566                 ret_val = e1000_read_kmrn_reg_generic(hw,
2567                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2568                                                 &data);
2569                 if (ret_val)
2570                         return ret_val;
2571                 data &= ~(0xF << 8);
2572                 data |= (0xB << 8);
2573                 ret_val = e1000_write_kmrn_reg_generic(hw,
2574                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2575                                                 data);
2576                 if (ret_val)
2577                         return ret_val;
2578
2579                 /* Enable jumbo frame workaround in the PHY */
2580                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2581                 data &= ~(0x7F << 5);
2582                 data |= (0x37 << 5);
2583                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2584                 if (ret_val)
2585                         return ret_val;
2586                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2587                 data &= ~(1 << 13);
2588                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2589                 if (ret_val)
2590                         return ret_val;
2591                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2592                 data &= ~(0x3FF << 2);
2593                 data |= (0x1A << 2);
2594                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2595                 if (ret_val)
2596                         return ret_val;
2597                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2598                 if (ret_val)
2599                         return ret_val;
2600                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2601                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2602                                                 (1 << 10));
2603                 if (ret_val)
2604                         return ret_val;
2605         } else {
2606                 /* Write MAC register values back to h/w defaults */
2607                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2608                 mac_reg &= ~(0xF << 14);
2609                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2610
2611                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2612                 mac_reg &= ~E1000_RCTL_SECRC;
2613                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2614
2615                 ret_val = e1000_read_kmrn_reg_generic(hw,
2616                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2617                                                 &data);
2618                 if (ret_val)
2619                         return ret_val;
2620                 ret_val = e1000_write_kmrn_reg_generic(hw,
2621                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2622                                                 data & ~(1 << 0));
2623                 if (ret_val)
2624                         return ret_val;
2625                 ret_val = e1000_read_kmrn_reg_generic(hw,
2626                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2627                                                 &data);
2628                 if (ret_val)
2629                         return ret_val;
2630                 data &= ~(0xF << 8);
2631                 data |= (0xB << 8);
2632                 ret_val = e1000_write_kmrn_reg_generic(hw,
2633                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2634                                                 data);
2635                 if (ret_val)
2636                         return ret_val;
2637
2638                 /* Write PHY register values back to h/w defaults */
2639                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2640                 data &= ~(0x7F << 5);
2641                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2642                 if (ret_val)
2643                         return ret_val;
2644                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2645                 data |= (1 << 13);
2646                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2647                 if (ret_val)
2648                         return ret_val;
2649                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2650                 data &= ~(0x3FF << 2);
2651                 data |= (0x8 << 2);
2652                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2653                 if (ret_val)
2654                         return ret_val;
2655                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2656                 if (ret_val)
2657                         return ret_val;
2658                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2659                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2660                                                 ~(1 << 10));
2661                 if (ret_val)
2662                         return ret_val;
2663         }
2664
2665         /* re-enable Rx path after enabling/disabling workaround */
2666         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2667                                      ~(1 << 14));
2668 }
2669
2670 /**
2671  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2672  *  done after every PHY reset.
2673  **/
2674 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2675 {
2676         s32 ret_val = E1000_SUCCESS;
2677
2678         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2679
2680         if (hw->mac.type != e1000_pch2lan)
2681                 return E1000_SUCCESS;
2682
2683         /* Set MDIO slow mode before any other MDIO access */
2684         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2685         if (ret_val)
2686                 return ret_val;
2687
2688         ret_val = hw->phy.ops.acquire(hw);
2689         if (ret_val)
2690                 return ret_val;
2691         /* set MSE higher to enable link to stay up when noise is high */
2692         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2693         if (ret_val)
2694                 goto release;
2695         /* drop link after 5 times MSE threshold was reached */
2696         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2697 release:
2698         hw->phy.ops.release(hw);
2699
2700         return ret_val;
2701 }
2702
2703 /**
2704  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2705  *  @hw:   pointer to the HW structure
2706  *
2707  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2708  *  Disable K1 for 1000 and 100 speeds
2709  **/
2710 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2711 {
2712         s32 ret_val = E1000_SUCCESS;
2713         u16 status_reg = 0;
2714
2715         DEBUGFUNC("e1000_k1_workaround_lv");
2716
2717         if (hw->mac.type != e1000_pch2lan)
2718                 return E1000_SUCCESS;
2719
2720         /* Set K1 beacon duration based on 10Mbs speed */
2721         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2722         if (ret_val)
2723                 return ret_val;
2724
2725         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2726             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2727                 if (status_reg &
2728                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2729                         u16 pm_phy_reg;
2730
2731                         /* LV 1G/100 Packet drop issue wa  */
2732                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2733                                                        &pm_phy_reg);
2734                         if (ret_val)
2735                                 return ret_val;
2736                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2737                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2738                                                         pm_phy_reg);
2739                         if (ret_val)
2740                                 return ret_val;
2741                 } else {
2742                         u32 mac_reg;
2743                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2744                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2745                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2746                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2747                 }
2748         }
2749
2750         return ret_val;
2751 }
2752
2753 /**
2754  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2755  *  @hw:   pointer to the HW structure
2756  *  @gate: boolean set to true to gate, false to ungate
2757  *
2758  *  Gate/ungate the automatic PHY configuration via hardware; perform
2759  *  the configuration via software instead.
2760  **/
2761 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2762 {
2763         u32 extcnf_ctrl;
2764
2765         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2766
2767         if (hw->mac.type < e1000_pch2lan)
2768                 return;
2769
2770         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2771
2772         if (gate)
2773                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2774         else
2775                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2776
2777         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2778 }
2779
2780 /**
2781  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2782  *  @hw: pointer to the HW structure
2783  *
2784  *  Check the appropriate indication the MAC has finished configuring the
2785  *  PHY after a software reset.
2786  **/
2787 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2788 {
2789         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2790
2791         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2792
2793         /* Wait for basic configuration completes before proceeding */
2794         do {
2795                 data = E1000_READ_REG(hw, E1000_STATUS);
2796                 data &= E1000_STATUS_LAN_INIT_DONE;
2797                 usec_delay(100);
2798         } while ((!data) && --loop);
2799
2800         /* If basic configuration is incomplete before the above loop
2801          * count reaches 0, loading the configuration from NVM will
2802          * leave the PHY in a bad state possibly resulting in no link.
2803          */
2804         if (loop == 0)
2805                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2806
2807         /* Clear the Init Done bit for the next init event */
2808         data = E1000_READ_REG(hw, E1000_STATUS);
2809         data &= ~E1000_STATUS_LAN_INIT_DONE;
2810         E1000_WRITE_REG(hw, E1000_STATUS, data);
2811 }
2812
2813 /**
2814  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2815  *  @hw: pointer to the HW structure
2816  **/
2817 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2818 {
2819         s32 ret_val = E1000_SUCCESS;
2820         u16 reg;
2821
2822         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2823
2824         if (hw->phy.ops.check_reset_block(hw))
2825                 return E1000_SUCCESS;
2826
2827         /* Allow time for h/w to get to quiescent state after reset */
2828         msec_delay(10);
2829
2830         /* Perform any necessary post-reset workarounds */
2831         switch (hw->mac.type) {
2832         case e1000_pchlan:
2833                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2834                 if (ret_val)
2835                         return ret_val;
2836                 break;
2837         case e1000_pch2lan:
2838                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2839                 if (ret_val)
2840                         return ret_val;
2841                 break;
2842         default:
2843                 break;
2844         }
2845
2846         /* Clear the host wakeup bit after lcd reset */
2847         if (hw->mac.type >= e1000_pchlan) {
2848                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2849                 reg &= ~BM_WUC_HOST_WU_BIT;
2850                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2851         }
2852
2853         /* Configure the LCD with the extended configuration region in NVM */
2854         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2855         if (ret_val)
2856                 return ret_val;
2857
2858         /* Configure the LCD with the OEM bits in NVM */
2859         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2860
2861         if (hw->mac.type == e1000_pch2lan) {
2862                 /* Ungate automatic PHY configuration on non-managed 82579 */
2863                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2864                     E1000_ICH_FWSM_FW_VALID)) {
2865                         msec_delay(10);
2866                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2867                 }
2868
2869                 /* Set EEE LPI Update Timer to 200usec */
2870                 ret_val = hw->phy.ops.acquire(hw);
2871                 if (ret_val)
2872                         return ret_val;
2873                 ret_val = e1000_write_emi_reg_locked(hw,
2874                                                      I82579_LPI_UPDATE_TIMER,
2875                                                      0x1387);
2876                 hw->phy.ops.release(hw);
2877         }
2878
2879         return ret_val;
2880 }
2881
2882 /**
2883  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2884  *  @hw: pointer to the HW structure
2885  *
2886  *  Resets the PHY
2887  *  This is a function pointer entry point called by drivers
2888  *  or other shared routines.
2889  **/
2890 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2891 {
2892         s32 ret_val = E1000_SUCCESS;
2893
2894         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2895
2896         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2897         if ((hw->mac.type == e1000_pch2lan) &&
2898             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2899                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2900
2901         ret_val = e1000_phy_hw_reset_generic(hw);
2902         if (ret_val)
2903                 return ret_val;
2904
2905         return e1000_post_phy_reset_ich8lan(hw);
2906 }
2907
2908 /**
2909  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2910  *  @hw: pointer to the HW structure
2911  *  @active: true to enable LPLU, false to disable
2912  *
2913  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2914  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2915  *  the phy speed. This function will manually set the LPLU bit and restart
2916  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2917  *  since it configures the same bit.
2918  **/
2919 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2920 {
2921         s32 ret_val;
2922         u16 oem_reg;
2923
2924         DEBUGFUNC("e1000_set_lplu_state_pchlan");
2925
2926         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2927         if (ret_val)
2928                 return ret_val;
2929
2930         if (active)
2931                 oem_reg |= HV_OEM_BITS_LPLU;
2932         else
2933                 oem_reg &= ~HV_OEM_BITS_LPLU;
2934
2935         if (!hw->phy.ops.check_reset_block(hw))
2936                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2937
2938         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2939 }
2940
2941 /**
2942  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2943  *  @hw: pointer to the HW structure
2944  *  @active: true to enable LPLU, false to disable
2945  *
2946  *  Sets the LPLU D0 state according to the active flag.  When
2947  *  activating LPLU this function also disables smart speed
2948  *  and vice versa.  LPLU will not be activated unless the
2949  *  device autonegotiation advertisement meets standards of
2950  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2951  *  This is a function pointer entry point only called by
2952  *  PHY setup routines.
2953  **/
2954 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2955 {
2956         struct e1000_phy_info *phy = &hw->phy;
2957         u32 phy_ctrl;
2958         s32 ret_val = E1000_SUCCESS;
2959         u16 data;
2960
2961         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
2962
2963         if (phy->type == e1000_phy_ife)
2964                 return E1000_SUCCESS;
2965
2966         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2967
2968         if (active) {
2969                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2970                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2971
2972                 if (phy->type != e1000_phy_igp_3)
2973                         return E1000_SUCCESS;
2974
2975                 /* Call gig speed drop workaround on LPLU before accessing
2976                  * any PHY registers
2977                  */
2978                 if (hw->mac.type == e1000_ich8lan)
2979                         e1000_gig_downshift_workaround_ich8lan(hw);
2980
2981                 /* When LPLU is enabled, we should disable SmartSpeed */
2982                 ret_val = phy->ops.read_reg(hw,
2983                                             IGP01E1000_PHY_PORT_CONFIG,
2984                                             &data);
2985                 if (ret_val)
2986                         return ret_val;
2987                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2988                 ret_val = phy->ops.write_reg(hw,
2989                                              IGP01E1000_PHY_PORT_CONFIG,
2990                                              data);
2991                 if (ret_val)
2992                         return ret_val;
2993         } else {
2994                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2995                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2996
2997                 if (phy->type != e1000_phy_igp_3)
2998                         return E1000_SUCCESS;
2999
3000                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3001                  * during Dx states where the power conservation is most
3002                  * important.  During driver activity we should enable
3003                  * SmartSpeed, so performance is maintained.
3004                  */
3005                 if (phy->smart_speed == e1000_smart_speed_on) {
3006                         ret_val = phy->ops.read_reg(hw,
3007                                                     IGP01E1000_PHY_PORT_CONFIG,
3008                                                     &data);
3009                         if (ret_val)
3010                                 return ret_val;
3011
3012                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3013                         ret_val = phy->ops.write_reg(hw,
3014                                                      IGP01E1000_PHY_PORT_CONFIG,
3015                                                      data);
3016                         if (ret_val)
3017                                 return ret_val;
3018                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3019                         ret_val = phy->ops.read_reg(hw,
3020                                                     IGP01E1000_PHY_PORT_CONFIG,
3021                                                     &data);
3022                         if (ret_val)
3023                                 return ret_val;
3024
3025                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3026                         ret_val = phy->ops.write_reg(hw,
3027                                                      IGP01E1000_PHY_PORT_CONFIG,
3028                                                      data);
3029                         if (ret_val)
3030                                 return ret_val;
3031                 }
3032         }
3033
3034         return E1000_SUCCESS;
3035 }
3036
3037 /**
3038  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3039  *  @hw: pointer to the HW structure
3040  *  @active: true to enable LPLU, false to disable
3041  *
3042  *  Sets the LPLU D3 state according to the active flag.  When
3043  *  activating LPLU this function also disables smart speed
3044  *  and vice versa.  LPLU will not be activated unless the
3045  *  device autonegotiation advertisement meets standards of
3046  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3047  *  This is a function pointer entry point only called by
3048  *  PHY setup routines.
3049  **/
3050 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3051 {
3052         struct e1000_phy_info *phy = &hw->phy;
3053         u32 phy_ctrl;
3054         s32 ret_val = E1000_SUCCESS;
3055         u16 data;
3056
3057         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3058
3059         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3060
3061         if (!active) {
3062                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3063                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3064
3065                 if (phy->type != e1000_phy_igp_3)
3066                         return E1000_SUCCESS;
3067
3068                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3069                  * during Dx states where the power conservation is most
3070                  * important.  During driver activity we should enable
3071                  * SmartSpeed, so performance is maintained.
3072                  */
3073                 if (phy->smart_speed == e1000_smart_speed_on) {
3074                         ret_val = phy->ops.read_reg(hw,
3075                                                     IGP01E1000_PHY_PORT_CONFIG,
3076                                                     &data);
3077                         if (ret_val)
3078                                 return ret_val;
3079
3080                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3081                         ret_val = phy->ops.write_reg(hw,
3082                                                      IGP01E1000_PHY_PORT_CONFIG,
3083                                                      data);
3084                         if (ret_val)
3085                                 return ret_val;
3086                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3087                         ret_val = phy->ops.read_reg(hw,
3088                                                     IGP01E1000_PHY_PORT_CONFIG,
3089                                                     &data);
3090                         if (ret_val)
3091                                 return ret_val;
3092
3093                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3094                         ret_val = phy->ops.write_reg(hw,
3095                                                      IGP01E1000_PHY_PORT_CONFIG,
3096                                                      data);
3097                         if (ret_val)
3098                                 return ret_val;
3099                 }
3100         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3101                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3102                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3103                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3104                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3105
3106                 if (phy->type != e1000_phy_igp_3)
3107                         return E1000_SUCCESS;
3108
3109                 /* Call gig speed drop workaround on LPLU before accessing
3110                  * any PHY registers
3111                  */
3112                 if (hw->mac.type == e1000_ich8lan)
3113                         e1000_gig_downshift_workaround_ich8lan(hw);
3114
3115                 /* When LPLU is enabled, we should disable SmartSpeed */
3116                 ret_val = phy->ops.read_reg(hw,
3117                                             IGP01E1000_PHY_PORT_CONFIG,
3118                                             &data);
3119                 if (ret_val)
3120                         return ret_val;
3121
3122                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3123                 ret_val = phy->ops.write_reg(hw,
3124                                              IGP01E1000_PHY_PORT_CONFIG,
3125                                              data);
3126         }
3127
3128         return ret_val;
3129 }
3130
3131 /**
3132  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3133  *  @hw: pointer to the HW structure
3134  *  @bank:  pointer to the variable that returns the active bank
3135  *
3136  *  Reads signature byte from the NVM using the flash access registers.
3137  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3138  **/
3139 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3140 {
3141         u32 eecd;
3142         struct e1000_nvm_info *nvm = &hw->nvm;
3143         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3144         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3145         u8 sig_byte = 0;
3146         s32 ret_val;
3147
3148         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3149
3150         switch (hw->mac.type) {
3151         case e1000_ich8lan:
3152         case e1000_ich9lan:
3153                 eecd = E1000_READ_REG(hw, E1000_EECD);
3154                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3155                     E1000_EECD_SEC1VAL_VALID_MASK) {
3156                         if (eecd & E1000_EECD_SEC1VAL)
3157                                 *bank = 1;
3158                         else
3159                                 *bank = 0;
3160
3161                         return E1000_SUCCESS;
3162                 }
3163                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3164                 /* fall-thru */
3165         default:
3166                 /* set bank to 0 in case flash read fails */
3167                 *bank = 0;
3168
3169                 /* Check bank 0 */
3170                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3171                                                         &sig_byte);
3172                 if (ret_val)
3173                         return ret_val;
3174                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3175                     E1000_ICH_NVM_SIG_VALUE) {
3176                         *bank = 0;
3177                         return E1000_SUCCESS;
3178                 }
3179
3180                 /* Check bank 1 */
3181                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3182                                                         bank1_offset,
3183                                                         &sig_byte);
3184                 if (ret_val)
3185                         return ret_val;
3186                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3187                     E1000_ICH_NVM_SIG_VALUE) {
3188                         *bank = 1;
3189                         return E1000_SUCCESS;
3190                 }
3191
3192                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3193                 return -E1000_ERR_NVM;
3194         }
3195 }
3196
3197 /**
3198  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3199  *  @hw: pointer to the HW structure
3200  *  @offset: The offset (in bytes) of the word(s) to read.
3201  *  @words: Size of data to read in words
3202  *  @data: Pointer to the word(s) to read at offset.
3203  *
3204  *  Reads a word(s) from the NVM using the flash access registers.
3205  **/
3206 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3207                                   u16 *data)
3208 {
3209         struct e1000_nvm_info *nvm = &hw->nvm;
3210         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3211         u32 act_offset;
3212         s32 ret_val = E1000_SUCCESS;
3213         u32 bank = 0;
3214         u16 i, word;
3215
3216         DEBUGFUNC("e1000_read_nvm_ich8lan");
3217
3218         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3219             (words == 0)) {
3220                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3221                 ret_val = -E1000_ERR_NVM;
3222                 goto out;
3223         }
3224
3225         nvm->ops.acquire(hw);
3226
3227         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3228         if (ret_val != E1000_SUCCESS) {
3229                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3230                 bank = 0;
3231         }
3232
3233         act_offset = (bank) ? nvm->flash_bank_size : 0;
3234         act_offset += offset;
3235
3236         ret_val = E1000_SUCCESS;
3237         for (i = 0; i < words; i++) {
3238                 if (dev_spec->shadow_ram[offset+i].modified) {
3239                         data[i] = dev_spec->shadow_ram[offset+i].value;
3240                 } else {
3241                         ret_val = e1000_read_flash_word_ich8lan(hw,
3242                                                                 act_offset + i,
3243                                                                 &word);
3244                         if (ret_val)
3245                                 break;
3246                         data[i] = word;
3247                 }
3248         }
3249
3250         nvm->ops.release(hw);
3251
3252 out:
3253         if (ret_val)
3254                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3255
3256         return ret_val;
3257 }
3258
3259 /**
3260  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3261  *  @hw: pointer to the HW structure
3262  *
3263  *  This function does initial flash setup so that a new read/write/erase cycle
3264  *  can be started.
3265  **/
3266 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3267 {
3268         union ich8_hws_flash_status hsfsts;
3269         s32 ret_val = -E1000_ERR_NVM;
3270
3271         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3272
3273         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3274
3275         /* Check if the flash descriptor is valid */
3276         if (!hsfsts.hsf_status.fldesvalid) {
3277                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3278                 return -E1000_ERR_NVM;
3279         }
3280
3281         /* Clear FCERR and DAEL in hw status by writing 1 */
3282         hsfsts.hsf_status.flcerr = 1;
3283         hsfsts.hsf_status.dael = 1;
3284         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3285
3286         /* Either we should have a hardware SPI cycle in progress
3287          * bit to check against, in order to start a new cycle or
3288          * FDONE bit should be changed in the hardware so that it
3289          * is 1 after hardware reset, which can then be used as an
3290          * indication whether a cycle is in progress or has been
3291          * completed.
3292          */
3293
3294         if (!hsfsts.hsf_status.flcinprog) {
3295                 /* There is no cycle running at present,
3296                  * so we can start a cycle.
3297                  * Begin by setting Flash Cycle Done.
3298                  */
3299                 hsfsts.hsf_status.flcdone = 1;
3300                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3301                 ret_val = E1000_SUCCESS;
3302         } else {
3303                 s32 i;
3304
3305                 /* Otherwise poll for sometime so the current
3306                  * cycle has a chance to end before giving up.
3307                  */
3308                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3309                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3310                                                               ICH_FLASH_HSFSTS);
3311                         if (!hsfsts.hsf_status.flcinprog) {
3312                                 ret_val = E1000_SUCCESS;
3313                                 break;
3314                         }
3315                         usec_delay(1);
3316                 }
3317                 if (ret_val == E1000_SUCCESS) {
3318                         /* Successful in waiting for previous cycle to timeout,
3319                          * now set the Flash Cycle Done.
3320                          */
3321                         hsfsts.hsf_status.flcdone = 1;
3322                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3323                                                 hsfsts.regval);
3324                 } else {
3325                         DEBUGOUT("Flash controller busy, cannot get access\n");
3326                 }
3327         }
3328
3329         return ret_val;
3330 }
3331
3332 /**
3333  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3334  *  @hw: pointer to the HW structure
3335  *  @timeout: maximum time to wait for completion
3336  *
3337  *  This function starts a flash cycle and waits for its completion.
3338  **/
3339 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3340 {
3341         union ich8_hws_flash_ctrl hsflctl;
3342         union ich8_hws_flash_status hsfsts;
3343         u32 i = 0;
3344
3345         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3346
3347         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3348         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3349         hsflctl.hsf_ctrl.flcgo = 1;
3350
3351         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3352
3353         /* wait till FDONE bit is set to 1 */
3354         do {
3355                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3356                 if (hsfsts.hsf_status.flcdone)
3357                         break;
3358                 usec_delay(1);
3359         } while (i++ < timeout);
3360
3361         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3362                 return E1000_SUCCESS;
3363
3364         return -E1000_ERR_NVM;
3365 }
3366
3367 /**
3368  *  e1000_read_flash_word_ich8lan - Read word from flash
3369  *  @hw: pointer to the HW structure
3370  *  @offset: offset to data location
3371  *  @data: pointer to the location for storing the data
3372  *
3373  *  Reads the flash word at offset into data.  Offset is converted
3374  *  to bytes before read.
3375  **/
3376 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3377                                          u16 *data)
3378 {
3379         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3380
3381         if (!data)
3382                 return -E1000_ERR_NVM;
3383
3384         /* Must convert offset into bytes. */
3385         offset <<= 1;
3386
3387         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3388 }
3389
3390 /**
3391  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3392  *  @hw: pointer to the HW structure
3393  *  @offset: The offset of the byte to read.
3394  *  @data: Pointer to a byte to store the value read.
3395  *
3396  *  Reads a single byte from the NVM using the flash access registers.
3397  **/
3398 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3399                                          u8 *data)
3400 {
3401         s32 ret_val;
3402         u16 word = 0;
3403
3404         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3405
3406         if (ret_val)
3407                 return ret_val;
3408
3409         *data = (u8)word;
3410
3411         return E1000_SUCCESS;
3412 }
3413
3414 /**
3415  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3416  *  @hw: pointer to the HW structure
3417  *  @offset: The offset (in bytes) of the byte or word to read.
3418  *  @size: Size of data to read, 1=byte 2=word
3419  *  @data: Pointer to the word to store the value read.
3420  *
3421  *  Reads a byte or word from the NVM using the flash access registers.
3422  **/
3423 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3424                                          u8 size, u16 *data)
3425 {
3426         union ich8_hws_flash_status hsfsts;
3427         union ich8_hws_flash_ctrl hsflctl;
3428         u32 flash_linear_addr;
3429         u32 flash_data = 0;
3430         s32 ret_val = -E1000_ERR_NVM;
3431         u8 count = 0;
3432
3433         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3434
3435         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3436                 return -E1000_ERR_NVM;
3437         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3438                              hw->nvm.flash_base_addr);
3439
3440         do {
3441                 usec_delay(1);
3442                 /* Steps */
3443                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3444                 if (ret_val != E1000_SUCCESS)
3445                         break;
3446                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3447
3448                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3449                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3450                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3451                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3452
3453                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3454
3455                 ret_val =
3456                     e1000_flash_cycle_ich8lan(hw,
3457                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3458
3459                 /* Check if FCERR is set to 1, if set to 1, clear it
3460                  * and try the whole sequence a few more times, else
3461                  * read in (shift in) the Flash Data0, the order is
3462                  * least significant byte first msb to lsb
3463                  */
3464                 if (ret_val == E1000_SUCCESS) {
3465                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3466                         if (size == 1)
3467                                 *data = (u8)(flash_data & 0x000000FF);
3468                         else if (size == 2)
3469                                 *data = (u16)(flash_data & 0x0000FFFF);
3470                         break;
3471                 } else {
3472                         /* If we've gotten here, then things are probably
3473                          * completely hosed, but if the error condition is
3474                          * detected, it won't hurt to give it another try...
3475                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3476                          */
3477                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3478                                                               ICH_FLASH_HSFSTS);
3479                         if (hsfsts.hsf_status.flcerr) {
3480                                 /* Repeat for some time before giving up. */
3481                                 continue;
3482                         } else if (!hsfsts.hsf_status.flcdone) {
3483                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3484                                 break;
3485                         }
3486                 }
3487         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3488
3489         return ret_val;
3490 }
3491
3492 /**
3493  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3494  *  @hw: pointer to the HW structure
3495  *  @offset: The offset (in bytes) of the word(s) to write.
3496  *  @words: Size of data to write in words
3497  *  @data: Pointer to the word(s) to write at offset.
3498  *
3499  *  Writes a byte or word to the NVM using the flash access registers.
3500  **/
3501 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3502                                    u16 *data)
3503 {
3504         struct e1000_nvm_info *nvm = &hw->nvm;
3505         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3506         u16 i;
3507
3508         DEBUGFUNC("e1000_write_nvm_ich8lan");
3509
3510         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3511             (words == 0)) {
3512                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3513                 return -E1000_ERR_NVM;
3514         }
3515
3516         nvm->ops.acquire(hw);
3517
3518         for (i = 0; i < words; i++) {
3519                 dev_spec->shadow_ram[offset+i].modified = true;
3520                 dev_spec->shadow_ram[offset+i].value = data[i];
3521         }
3522
3523         nvm->ops.release(hw);
3524
3525         return E1000_SUCCESS;
3526 }
3527
3528 /**
3529  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3530  *  @hw: pointer to the HW structure
3531  *
3532  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3533  *  which writes the checksum to the shadow ram.  The changes in the shadow
3534  *  ram are then committed to the EEPROM by processing each bank at a time
3535  *  checking for the modified bit and writing only the pending changes.
3536  *  After a successful commit, the shadow ram is cleared and is ready for
3537  *  future writes.
3538  **/
3539 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3540 {
3541         struct e1000_nvm_info *nvm = &hw->nvm;
3542         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3543         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3544         s32 ret_val;
3545         u16 data;
3546
3547         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3548
3549         ret_val = e1000_update_nvm_checksum_generic(hw);
3550         if (ret_val)
3551                 goto out;
3552
3553         if (nvm->type != e1000_nvm_flash_sw)
3554                 goto out;
3555
3556         nvm->ops.acquire(hw);
3557
3558         /* We're writing to the opposite bank so if we're on bank 1,
3559          * write to bank 0 etc.  We also need to erase the segment that
3560          * is going to be written
3561          */
3562         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3563         if (ret_val != E1000_SUCCESS) {
3564                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3565                 bank = 0;
3566         }
3567
3568         if (bank == 0) {
3569                 new_bank_offset = nvm->flash_bank_size;
3570                 old_bank_offset = 0;
3571                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3572                 if (ret_val)
3573                         goto release;
3574         } else {
3575                 old_bank_offset = nvm->flash_bank_size;
3576                 new_bank_offset = 0;
3577                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3578                 if (ret_val)
3579                         goto release;
3580         }
3581
3582         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3583                 /* Determine whether to write the value stored
3584                  * in the other NVM bank or a modified value stored
3585                  * in the shadow RAM
3586                  */
3587                 if (dev_spec->shadow_ram[i].modified) {
3588                         data = dev_spec->shadow_ram[i].value;
3589                 } else {
3590                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3591                                                                 old_bank_offset,
3592                                                                 &data);
3593                         if (ret_val)
3594                                 break;
3595                 }
3596
3597                 /* If the word is 0x13, then make sure the signature bits
3598                  * (15:14) are 11b until the commit has completed.
3599                  * This will allow us to write 10b which indicates the
3600                  * signature is valid.  We want to do this after the write
3601                  * has completed so that we don't mark the segment valid
3602                  * while the write is still in progress
3603                  */
3604                 if (i == E1000_ICH_NVM_SIG_WORD)
3605                         data |= E1000_ICH_NVM_SIG_MASK;
3606
3607                 /* Convert offset to bytes. */
3608                 act_offset = (i + new_bank_offset) << 1;
3609
3610                 usec_delay(100);
3611                 /* Write the bytes to the new bank. */
3612                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3613                                                                act_offset,
3614                                                                (u8)data);
3615                 if (ret_val)
3616                         break;
3617
3618                 usec_delay(100);
3619                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3620                                                           act_offset + 1,
3621                                                           (u8)(data >> 8));
3622                 if (ret_val)
3623                         break;
3624         }
3625
3626         /* Don't bother writing the segment valid bits if sector
3627          * programming failed.
3628          */
3629         if (ret_val) {
3630                 DEBUGOUT("Flash commit failed.\n");
3631                 goto release;
3632         }
3633
3634         /* Finally validate the new segment by setting bit 15:14
3635          * to 10b in word 0x13 , this can be done without an
3636          * erase as well since these bits are 11 to start with
3637          * and we need to change bit 14 to 0b
3638          */
3639         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3640         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3641         if (ret_val)
3642                 goto release;
3643
3644         data &= 0xBFFF;
3645         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3646                                                        act_offset * 2 + 1,
3647                                                        (u8)(data >> 8));
3648         if (ret_val)
3649                 goto release;
3650
3651         /* And invalidate the previously valid segment by setting
3652          * its signature word (0x13) high_byte to 0b. This can be
3653          * done without an erase because flash erase sets all bits
3654          * to 1's. We can write 1's to 0's without an erase
3655          */
3656         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3657         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3658         if (ret_val)
3659                 goto release;
3660
3661         /* Great!  Everything worked, we can now clear the cached entries. */
3662         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3663                 dev_spec->shadow_ram[i].modified = false;
3664                 dev_spec->shadow_ram[i].value = 0xFFFF;
3665         }
3666
3667 release:
3668         nvm->ops.release(hw);
3669
3670         /* Reload the EEPROM, or else modifications will not appear
3671          * until after the next adapter reset.
3672          */
3673         if (!ret_val) {
3674                 nvm->ops.reload(hw);
3675                 msec_delay(10);
3676         }
3677
3678 out:
3679         if (ret_val)
3680                 DEBUGOUT1("NVM update error: %d\n", ret_val);
3681
3682         return ret_val;
3683 }
3684
3685 /**
3686  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3687  *  @hw: pointer to the HW structure
3688  *
3689  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3690  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3691  *  calculated, in which case we need to calculate the checksum and set bit 6.
3692  **/
3693 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3694 {
3695         s32 ret_val;
3696         u16 data;
3697         u16 word;
3698         u16 valid_csum_mask;
3699
3700         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3701
3702         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3703          * the checksum needs to be fixed.  This bit is an indication that
3704          * the NVM was prepared by OEM software and did not calculate
3705          * the checksum...a likely scenario.
3706          */
3707         switch (hw->mac.type) {
3708         case e1000_pch_lpt:
3709                 word = NVM_COMPAT;
3710                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3711                 break;
3712         default:
3713                 word = NVM_FUTURE_INIT_WORD1;
3714                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3715                 break;
3716         }
3717
3718         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3719         if (ret_val)
3720                 return ret_val;
3721
3722         if (!(data & valid_csum_mask)) {
3723                 data |= valid_csum_mask;
3724                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3725                 if (ret_val)
3726                         return ret_val;
3727                 ret_val = hw->nvm.ops.update(hw);
3728                 if (ret_val)
3729                         return ret_val;
3730         }
3731
3732         return e1000_validate_nvm_checksum_generic(hw);
3733 }
3734
3735 /**
3736  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3737  *  @hw: pointer to the HW structure
3738  *  @offset: The offset (in bytes) of the byte/word to read.
3739  *  @size: Size of data to read, 1=byte 2=word
3740  *  @data: The byte(s) to write to the NVM.
3741  *
3742  *  Writes one/two bytes to the NVM using the flash access registers.
3743  **/
3744 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3745                                           u8 size, u16 data)
3746 {
3747         union ich8_hws_flash_status hsfsts;
3748         union ich8_hws_flash_ctrl hsflctl;
3749         u32 flash_linear_addr;
3750         u32 flash_data = 0;
3751         s32 ret_val;
3752         u8 count = 0;
3753
3754         DEBUGFUNC("e1000_write_ich8_data");
3755
3756         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3757                 return -E1000_ERR_NVM;
3758
3759         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3760                              hw->nvm.flash_base_addr);
3761
3762         do {
3763                 usec_delay(1);
3764                 /* Steps */
3765                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3766                 if (ret_val != E1000_SUCCESS)
3767                         break;
3768                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3769
3770                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3771                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3772                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3773                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3774
3775                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3776
3777                 if (size == 1)
3778                         flash_data = (u32)data & 0x00FF;
3779                 else
3780                         flash_data = (u32)data;
3781
3782                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3783
3784                 /* check if FCERR is set to 1 , if set to 1, clear it
3785                  * and try the whole sequence a few more times else done
3786                  */
3787                 ret_val =
3788                     e1000_flash_cycle_ich8lan(hw,
3789                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3790                 if (ret_val == E1000_SUCCESS)
3791                         break;
3792
3793                 /* If we're here, then things are most likely
3794                  * completely hosed, but if the error condition
3795                  * is detected, it won't hurt to give it another
3796                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3797                  */
3798                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3799                 if (hsfsts.hsf_status.flcerr)
3800                         /* Repeat for some time before giving up. */
3801                         continue;
3802                 if (!hsfsts.hsf_status.flcdone) {
3803                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3804                         break;
3805                 }
3806         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3807
3808         return ret_val;
3809 }
3810
3811 /**
3812  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3813  *  @hw: pointer to the HW structure
3814  *  @offset: The index of the byte to read.
3815  *  @data: The byte to write to the NVM.
3816  *
3817  *  Writes a single byte to the NVM using the flash access registers.
3818  **/
3819 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3820                                           u8 data)
3821 {
3822         u16 word = (u16)data;
3823
3824         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3825
3826         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3827 }
3828
3829 /**
3830  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3831  *  @hw: pointer to the HW structure
3832  *  @offset: The offset of the byte to write.
3833  *  @byte: The byte to write to the NVM.
3834  *
3835  *  Writes a single byte to the NVM using the flash access registers.
3836  *  Goes through a retry algorithm before giving up.
3837  **/
3838 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3839                                                 u32 offset, u8 byte)
3840 {
3841         s32 ret_val;
3842         u16 program_retries;
3843
3844         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3845
3846         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3847         if (!ret_val)
3848                 return ret_val;
3849
3850         for (program_retries = 0; program_retries < 100; program_retries++) {
3851                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3852                 usec_delay(100);
3853                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3854                 if (ret_val == E1000_SUCCESS)
3855                         break;
3856         }
3857         if (program_retries == 100)
3858                 return -E1000_ERR_NVM;
3859
3860         return E1000_SUCCESS;
3861 }
3862
3863 /**
3864  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3865  *  @hw: pointer to the HW structure
3866  *  @bank: 0 for first bank, 1 for second bank, etc.
3867  *
3868  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3869  *  bank N is 4096 * N + flash_reg_addr.
3870  **/
3871 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3872 {
3873         struct e1000_nvm_info *nvm = &hw->nvm;
3874         union ich8_hws_flash_status hsfsts;
3875         union ich8_hws_flash_ctrl hsflctl;
3876         u32 flash_linear_addr;
3877         /* bank size is in 16bit words - adjust to bytes */
3878         u32 flash_bank_size = nvm->flash_bank_size * 2;
3879         s32 ret_val;
3880         s32 count = 0;
3881         s32 j, iteration, sector_size;
3882
3883         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3884
3885         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3886
3887         /* Determine HW Sector size: Read BERASE bits of hw flash status
3888          * register
3889          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3890          *     consecutive sectors.  The start index for the nth Hw sector
3891          *     can be calculated as = bank * 4096 + n * 256
3892          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3893          *     The start index for the nth Hw sector can be calculated
3894          *     as = bank * 4096
3895          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3896          *     (ich9 only, otherwise error condition)
3897          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3898          */
3899         switch (hsfsts.hsf_status.berasesz) {
3900         case 0:
3901                 /* Hw sector size 256 */
3902                 sector_size = ICH_FLASH_SEG_SIZE_256;
3903                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3904                 break;
3905         case 1:
3906                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3907                 iteration = 1;
3908                 break;
3909         case 2:
3910                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3911                 iteration = 1;
3912                 break;
3913         case 3:
3914                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3915                 iteration = 1;
3916                 break;
3917         default:
3918                 return -E1000_ERR_NVM;
3919         }
3920
3921         /* Start with the base address, then add the sector offset. */
3922         flash_linear_addr = hw->nvm.flash_base_addr;
3923         flash_linear_addr += (bank) ? flash_bank_size : 0;
3924
3925         for (j = 0; j < iteration; j++) {
3926                 do {
3927                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3928
3929                         /* Steps */
3930                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3931                         if (ret_val)
3932                                 return ret_val;
3933
3934                         /* Write a value 11 (block Erase) in Flash
3935                          * Cycle field in hw flash control
3936                          */
3937                         hsflctl.regval =
3938                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3939
3940                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3941                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3942                                                 hsflctl.regval);
3943
3944                         /* Write the last 24 bits of an index within the
3945                          * block into Flash Linear address field in Flash
3946                          * Address.
3947                          */
3948                         flash_linear_addr += (j * sector_size);
3949                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
3950                                               flash_linear_addr);
3951
3952                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3953                         if (ret_val == E1000_SUCCESS)
3954                                 break;
3955
3956                         /* Check if FCERR is set to 1.  If 1,
3957                          * clear it and try the whole sequence
3958                          * a few more times else Done
3959                          */
3960                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3961                                                       ICH_FLASH_HSFSTS);
3962                         if (hsfsts.hsf_status.flcerr)
3963                                 /* repeat for some time before giving up */
3964                                 continue;
3965                         else if (!hsfsts.hsf_status.flcdone)
3966                                 return ret_val;
3967                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3968         }
3969
3970         return E1000_SUCCESS;
3971 }
3972
3973 /**
3974  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3975  *  @hw: pointer to the HW structure
3976  *  @data: Pointer to the LED settings
3977  *
3978  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3979  *  settings is all 0's or F's, set the LED default to a valid LED default
3980  *  setting.
3981  **/
3982 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3983 {
3984         s32 ret_val;
3985
3986         DEBUGFUNC("e1000_valid_led_default_ich8lan");
3987
3988         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
3989         if (ret_val) {
3990                 DEBUGOUT("NVM Read Error\n");
3991                 return ret_val;
3992         }
3993
3994         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3995                 *data = ID_LED_DEFAULT_ICH8LAN;
3996
3997         return E1000_SUCCESS;
3998 }
3999
4000 /**
4001  *  e1000_id_led_init_pchlan - store LED configurations
4002  *  @hw: pointer to the HW structure
4003  *
4004  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4005  *  the PHY LED configuration register.
4006  *
4007  *  PCH also does not have an "always on" or "always off" mode which
4008  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4009  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4010  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4011  *  link based on logic in e1000_led_[on|off]_pchlan().
4012  **/
4013 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4014 {
4015         struct e1000_mac_info *mac = &hw->mac;
4016         s32 ret_val;
4017         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4018         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4019         u16 data, i, temp, shift;
4020
4021         DEBUGFUNC("e1000_id_led_init_pchlan");
4022
4023         /* Get default ID LED modes */
4024         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4025         if (ret_val)
4026                 return ret_val;
4027
4028         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4029         mac->ledctl_mode1 = mac->ledctl_default;
4030         mac->ledctl_mode2 = mac->ledctl_default;
4031
4032         for (i = 0; i < 4; i++) {
4033                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4034                 shift = (i * 5);
4035                 switch (temp) {
4036                 case ID_LED_ON1_DEF2:
4037                 case ID_LED_ON1_ON2:
4038                 case ID_LED_ON1_OFF2:
4039                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4040                         mac->ledctl_mode1 |= (ledctl_on << shift);
4041                         break;
4042                 case ID_LED_OFF1_DEF2:
4043                 case ID_LED_OFF1_ON2:
4044                 case ID_LED_OFF1_OFF2:
4045                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4046                         mac->ledctl_mode1 |= (ledctl_off << shift);
4047                         break;
4048                 default:
4049                         /* Do nothing */
4050                         break;
4051                 }
4052                 switch (temp) {
4053                 case ID_LED_DEF1_ON2:
4054                 case ID_LED_ON1_ON2:
4055                 case ID_LED_OFF1_ON2:
4056                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4057                         mac->ledctl_mode2 |= (ledctl_on << shift);
4058                         break;
4059                 case ID_LED_DEF1_OFF2:
4060                 case ID_LED_ON1_OFF2:
4061                 case ID_LED_OFF1_OFF2:
4062                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4063                         mac->ledctl_mode2 |= (ledctl_off << shift);
4064                         break;
4065                 default:
4066                         /* Do nothing */
4067                         break;
4068                 }
4069         }
4070
4071         return E1000_SUCCESS;
4072 }
4073
4074 /**
4075  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4076  *  @hw: pointer to the HW structure
4077  *
4078  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4079  *  register, so the the bus width is hard coded.
4080  **/
4081 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4082 {
4083         struct e1000_bus_info *bus = &hw->bus;
4084         s32 ret_val;
4085
4086         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4087
4088         ret_val = e1000_get_bus_info_pcie_generic(hw);
4089
4090         /* ICH devices are "PCI Express"-ish.  They have
4091          * a configuration space, but do not contain
4092          * PCI Express Capability registers, so bus width
4093          * must be hardcoded.
4094          */
4095         if (bus->width == e1000_bus_width_unknown)
4096                 bus->width = e1000_bus_width_pcie_x1;
4097
4098         return ret_val;
4099 }
4100
4101 /**
4102  *  e1000_reset_hw_ich8lan - Reset the hardware
4103  *  @hw: pointer to the HW structure
4104  *
4105  *  Does a full reset of the hardware which includes a reset of the PHY and
4106  *  MAC.
4107  **/
4108 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4109 {
4110         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4111         u16 kum_cfg;
4112         u32 ctrl, reg;
4113         s32 ret_val;
4114
4115         DEBUGFUNC("e1000_reset_hw_ich8lan");
4116
4117         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4118          * on the last TLP read/write transaction when MAC is reset.
4119          */
4120         ret_val = e1000_disable_pcie_master_generic(hw);
4121         if (ret_val)
4122                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4123
4124         DEBUGOUT("Masking off all interrupts\n");
4125         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4126
4127         /* Disable the Transmit and Receive units.  Then delay to allow
4128          * any pending transactions to complete before we hit the MAC
4129          * with the global reset.
4130          */
4131         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4132         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4133         E1000_WRITE_FLUSH(hw);
4134
4135         msec_delay(10);
4136
4137         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4138         if (hw->mac.type == e1000_ich8lan) {
4139                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4140                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4141                 /* Set Packet Buffer Size to 16k. */
4142                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4143         }
4144
4145         if (hw->mac.type == e1000_pchlan) {
4146                 /* Save the NVM K1 bit setting*/
4147                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4148                 if (ret_val)
4149                         return ret_val;
4150
4151                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4152                         dev_spec->nvm_k1_enabled = true;
4153                 else
4154                         dev_spec->nvm_k1_enabled = false;
4155         }
4156
4157         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4158
4159         if (!hw->phy.ops.check_reset_block(hw)) {
4160                 /* Full-chip reset requires MAC and PHY reset at the same
4161                  * time to make sure the interface between MAC and the
4162                  * external PHY is reset.
4163                  */
4164                 ctrl |= E1000_CTRL_PHY_RST;
4165
4166                 /* Gate automatic PHY configuration by hardware on
4167                  * non-managed 82579
4168                  */
4169                 if ((hw->mac.type == e1000_pch2lan) &&
4170                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4171                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4172         }
4173         ret_val = e1000_acquire_swflag_ich8lan(hw);
4174         DEBUGOUT("Issuing a global reset to ich8lan\n");
4175         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4176         /* cannot issue a flush here because it hangs the hardware */
4177         msec_delay(20);
4178
4179         /* Set Phy Config Counter to 50msec */
4180         if (hw->mac.type == e1000_pch2lan) {
4181                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4182                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4183                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4184                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4185         }
4186
4187         if (!ret_val)
4188                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4189
4190         if (ctrl & E1000_CTRL_PHY_RST) {
4191                 ret_val = hw->phy.ops.get_cfg_done(hw);
4192                 if (ret_val)
4193                         return ret_val;
4194
4195                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4196                 if (ret_val)
4197                         return ret_val;
4198         }
4199
4200         /* For PCH, this write will make sure that any noise
4201          * will be detected as a CRC error and be dropped rather than show up
4202          * as a bad packet to the DMA engine.
4203          */
4204         if (hw->mac.type == e1000_pchlan)
4205                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4206
4207         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4208         E1000_READ_REG(hw, E1000_ICR);
4209
4210         reg = E1000_READ_REG(hw, E1000_KABGTXD);
4211         reg |= E1000_KABGTXD_BGSQLBIAS;
4212         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4213
4214         return E1000_SUCCESS;
4215 }
4216
4217 /**
4218  *  e1000_init_hw_ich8lan - Initialize the hardware
4219  *  @hw: pointer to the HW structure
4220  *
4221  *  Prepares the hardware for transmit and receive by doing the following:
4222  *   - initialize hardware bits
4223  *   - initialize LED identification
4224  *   - setup receive address registers
4225  *   - setup flow control
4226  *   - setup transmit descriptors
4227  *   - clear statistics
4228  **/
4229 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4230 {
4231         struct e1000_mac_info *mac = &hw->mac;
4232         u32 ctrl_ext, txdctl, snoop;
4233         s32 ret_val;
4234         u16 i;
4235
4236         DEBUGFUNC("e1000_init_hw_ich8lan");
4237
4238         e1000_initialize_hw_bits_ich8lan(hw);
4239
4240         /* Initialize identification LED */
4241         ret_val = mac->ops.id_led_init(hw);
4242         /* An error is not fatal and we should not stop init due to this */
4243         if (ret_val)
4244                 DEBUGOUT("Error initializing identification LED\n");
4245
4246         /* Setup the receive address. */
4247         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4248
4249         /* Zero out the Multicast HASH table */
4250         DEBUGOUT("Zeroing the MTA\n");
4251         for (i = 0; i < mac->mta_reg_count; i++)
4252                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4253
4254         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4255          * the ME.  Disable wakeup by clearing the host wakeup bit.
4256          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4257          */
4258         if (hw->phy.type == e1000_phy_82578) {
4259                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4260                 i &= ~BM_WUC_HOST_WU_BIT;
4261                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4262                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4263                 if (ret_val)
4264                         return ret_val;
4265         }
4266
4267         /* Setup link and flow control */
4268         ret_val = mac->ops.setup_link(hw);
4269
4270         /* Set the transmit descriptor write-back policy for both queues */
4271         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4272         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4273                   E1000_TXDCTL_FULL_TX_DESC_WB);
4274         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4275                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4276         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4277         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4278         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4279                   E1000_TXDCTL_FULL_TX_DESC_WB);
4280         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4281                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4282         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4283
4284         /* ICH8 has opposite polarity of no_snoop bits.
4285          * By default, we should use snoop behavior.
4286          */
4287         if (mac->type == e1000_ich8lan)
4288                 snoop = PCIE_ICH8_SNOOP_ALL;
4289         else
4290                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4291         e1000_set_pcie_no_snoop_generic(hw, snoop);
4292
4293         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4294         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4295         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4296
4297         /* Clear all of the statistics registers (clear on read).  It is
4298          * important that we do this after we have tried to establish link
4299          * because the symbol error count will increment wildly if there
4300          * is no link.
4301          */
4302         e1000_clear_hw_cntrs_ich8lan(hw);
4303
4304         return ret_val;
4305 }
4306
4307 /**
4308  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4309  *  @hw: pointer to the HW structure
4310  *
4311  *  Sets/Clears required hardware bits necessary for correctly setting up the
4312  *  hardware for transmit and receive.
4313  **/
4314 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4315 {
4316         u32 reg;
4317
4318         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4319
4320         /* Extended Device Control */
4321         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4322         reg |= (1 << 22);
4323         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4324         if (hw->mac.type >= e1000_pchlan)
4325                 reg |= E1000_CTRL_EXT_PHYPDEN;
4326         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4327
4328         /* Transmit Descriptor Control 0 */
4329         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4330         reg |= (1 << 22);
4331         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4332
4333         /* Transmit Descriptor Control 1 */
4334         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4335         reg |= (1 << 22);
4336         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4337
4338         /* Transmit Arbitration Control 0 */
4339         reg = E1000_READ_REG(hw, E1000_TARC(0));
4340         if (hw->mac.type == e1000_ich8lan)
4341                 reg |= (1 << 28) | (1 << 29);
4342         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4343         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4344
4345         /* Transmit Arbitration Control 1 */
4346         reg = E1000_READ_REG(hw, E1000_TARC(1));
4347         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4348                 reg &= ~(1 << 28);
4349         else
4350                 reg |= (1 << 28);
4351         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4352         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4353
4354         /* Device Status */
4355         if (hw->mac.type == e1000_ich8lan) {
4356                 reg = E1000_READ_REG(hw, E1000_STATUS);
4357                 reg &= ~(1 << 31);
4358                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4359         }
4360
4361         /* work-around descriptor data corruption issue during nfs v2 udp
4362          * traffic, just disable the nfs filtering capability
4363          */
4364         reg = E1000_READ_REG(hw, E1000_RFCTL);
4365         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4366
4367         /* Disable IPv6 extension header parsing because some malformed
4368          * IPv6 headers can hang the Rx.
4369          */
4370         if (hw->mac.type == e1000_ich8lan)
4371                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4372         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4373
4374         /* Enable ECC on Lynxpoint */
4375         if (hw->mac.type == e1000_pch_lpt) {
4376                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4377                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4378                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4379
4380                 reg = E1000_READ_REG(hw, E1000_CTRL);
4381                 reg |= E1000_CTRL_MEHE;
4382                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4383         }
4384
4385         return;
4386 }
4387
4388 /**
4389  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4390  *  @hw: pointer to the HW structure
4391  *
4392  *  Determines which flow control settings to use, then configures flow
4393  *  control.  Calls the appropriate media-specific link configuration
4394  *  function.  Assuming the adapter has a valid link partner, a valid link
4395  *  should be established.  Assumes the hardware has previously been reset
4396  *  and the transmitter and receiver are not enabled.
4397  **/
4398 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4399 {
4400         s32 ret_val;
4401
4402         DEBUGFUNC("e1000_setup_link_ich8lan");
4403
4404         if (hw->phy.ops.check_reset_block(hw))
4405                 return E1000_SUCCESS;
4406
4407         /* ICH parts do not have a word in the NVM to determine
4408          * the default flow control setting, so we explicitly
4409          * set it to full.
4410          */
4411         if (hw->fc.requested_mode == e1000_fc_default)
4412                 hw->fc.requested_mode = e1000_fc_full;
4413
4414         /* Save off the requested flow control mode for use later.  Depending
4415          * on the link partner's capabilities, we may or may not use this mode.
4416          */
4417         hw->fc.current_mode = hw->fc.requested_mode;
4418
4419         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4420                 hw->fc.current_mode);
4421
4422         /* Continue to configure the copper link. */
4423         ret_val = hw->mac.ops.setup_physical_interface(hw);
4424         if (ret_val)
4425                 return ret_val;
4426
4427         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4428         if ((hw->phy.type == e1000_phy_82578) ||
4429             (hw->phy.type == e1000_phy_82579) ||
4430             (hw->phy.type == e1000_phy_i217) ||
4431             (hw->phy.type == e1000_phy_82577)) {
4432                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4433
4434                 ret_val = hw->phy.ops.write_reg(hw,
4435                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
4436                                              hw->fc.pause_time);
4437                 if (ret_val)
4438                         return ret_val;
4439         }
4440
4441         return e1000_set_fc_watermarks_generic(hw);
4442 }
4443
4444 /**
4445  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4446  *  @hw: pointer to the HW structure
4447  *
4448  *  Configures the kumeran interface to the PHY to wait the appropriate time
4449  *  when polling the PHY, then call the generic setup_copper_link to finish
4450  *  configuring the copper link.
4451  **/
4452 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4453 {
4454         u32 ctrl;
4455         s32 ret_val;
4456         u16 reg_data;
4457
4458         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4459
4460         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4461         ctrl |= E1000_CTRL_SLU;
4462         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4463         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4464
4465         /* Set the mac to wait the maximum time between each iteration
4466          * and increase the max iterations when polling the phy;
4467          * this fixes erroneous timeouts at 10Mbps.
4468          */
4469         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4470                                                0xFFFF);
4471         if (ret_val)
4472                 return ret_val;
4473         ret_val = e1000_read_kmrn_reg_generic(hw,
4474                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
4475                                               &reg_data);
4476         if (ret_val)
4477                 return ret_val;
4478         reg_data |= 0x3F;
4479         ret_val = e1000_write_kmrn_reg_generic(hw,
4480                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
4481                                                reg_data);
4482         if (ret_val)
4483                 return ret_val;
4484
4485         switch (hw->phy.type) {
4486         case e1000_phy_igp_3:
4487                 ret_val = e1000_copper_link_setup_igp(hw);
4488                 if (ret_val)
4489                         return ret_val;
4490                 break;
4491         case e1000_phy_bm:
4492         case e1000_phy_82578:
4493                 ret_val = e1000_copper_link_setup_m88(hw);
4494                 if (ret_val)
4495                         return ret_val;
4496                 break;
4497         case e1000_phy_82577:
4498         case e1000_phy_82579:
4499                 ret_val = e1000_copper_link_setup_82577(hw);
4500                 if (ret_val)
4501                         return ret_val;
4502                 break;
4503         case e1000_phy_ife:
4504                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4505                                                &reg_data);
4506                 if (ret_val)
4507                         return ret_val;
4508
4509                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4510
4511                 switch (hw->phy.mdix) {
4512                 case 1:
4513                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4514                         break;
4515                 case 2:
4516                         reg_data |= IFE_PMC_FORCE_MDIX;
4517                         break;
4518                 case 0:
4519                 default:
4520                         reg_data |= IFE_PMC_AUTO_MDIX;
4521                         break;
4522                 }
4523                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4524                                                 reg_data);
4525                 if (ret_val)
4526                         return ret_val;
4527                 break;
4528         default:
4529                 break;
4530         }
4531
4532         return e1000_setup_copper_link_generic(hw);
4533 }
4534
4535 /**
4536  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4537  *  @hw: pointer to the HW structure
4538  *
4539  *  Calls the PHY specific link setup function and then calls the
4540  *  generic setup_copper_link to finish configuring the link for
4541  *  Lynxpoint PCH devices
4542  **/
4543 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4544 {
4545         u32 ctrl;
4546         s32 ret_val;
4547
4548         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4549
4550         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4551         ctrl |= E1000_CTRL_SLU;
4552         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4553         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4554
4555         ret_val = e1000_copper_link_setup_82577(hw);
4556         if (ret_val)
4557                 return ret_val;
4558
4559         return e1000_setup_copper_link_generic(hw);
4560 }
4561
4562 /**
4563  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4564  *  @hw: pointer to the HW structure
4565  *  @speed: pointer to store current link speed
4566  *  @duplex: pointer to store the current link duplex
4567  *
4568  *  Calls the generic get_speed_and_duplex to retrieve the current link
4569  *  information and then calls the Kumeran lock loss workaround for links at
4570  *  gigabit speeds.
4571  **/
4572 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4573                                           u16 *duplex)
4574 {
4575         s32 ret_val;
4576
4577         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4578
4579         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4580         if (ret_val)
4581                 return ret_val;
4582
4583         if ((hw->mac.type == e1000_ich8lan) &&
4584             (hw->phy.type == e1000_phy_igp_3) &&
4585             (*speed == SPEED_1000)) {
4586                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4587         }
4588
4589         return ret_val;
4590 }
4591
4592 /**
4593  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4594  *  @hw: pointer to the HW structure
4595  *
4596  *  Work-around for 82566 Kumeran PCS lock loss:
4597  *  On link status change (i.e. PCI reset, speed change) and link is up and
4598  *  speed is gigabit-
4599  *    0) if workaround is optionally disabled do nothing
4600  *    1) wait 1ms for Kumeran link to come up
4601  *    2) check Kumeran Diagnostic register PCS lock loss bit
4602  *    3) if not set the link is locked (all is good), otherwise...
4603  *    4) reset the PHY
4604  *    5) repeat up to 10 times
4605  *  Note: this is only called for IGP3 copper when speed is 1gb.
4606  **/
4607 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4608 {
4609         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4610         u32 phy_ctrl;
4611         s32 ret_val;
4612         u16 i, data;
4613         bool link;
4614
4615         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4616
4617         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4618                 return E1000_SUCCESS;
4619
4620         /* Make sure link is up before proceeding.  If not just return.
4621          * Attempting this while link is negotiating fouled up link
4622          * stability
4623          */
4624         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4625         if (!link)
4626                 return E1000_SUCCESS;
4627
4628         for (i = 0; i < 10; i++) {
4629                 /* read once to clear */
4630                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4631                 if (ret_val)
4632                         return ret_val;
4633                 /* and again to get new status */
4634                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4635                 if (ret_val)
4636                         return ret_val;
4637
4638                 /* check for PCS lock */
4639                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4640                         return E1000_SUCCESS;
4641
4642                 /* Issue PHY reset */
4643                 hw->phy.ops.reset(hw);
4644                 msec_delay_irq(5);
4645         }
4646         /* Disable GigE link negotiation */
4647         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4648         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4649                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4650         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4651
4652         /* Call gig speed drop workaround on Gig disable before accessing
4653          * any PHY registers
4654          */
4655         e1000_gig_downshift_workaround_ich8lan(hw);
4656
4657         /* unable to acquire PCS lock */
4658         return -E1000_ERR_PHY;
4659 }
4660
4661 /**
4662  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4663  *  @hw: pointer to the HW structure
4664  *  @state: boolean value used to set the current Kumeran workaround state
4665  *
4666  *  If ICH8, set the current Kumeran workaround state (enabled - true
4667  *  /disabled - false).
4668  **/
4669 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4670                                                  bool state)
4671 {
4672         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4673
4674         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4675
4676         if (hw->mac.type != e1000_ich8lan) {
4677                 DEBUGOUT("Workaround applies to ICH8 only.\n");
4678                 return;
4679         }
4680
4681         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4682
4683         return;
4684 }
4685
4686 /**
4687  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4688  *  @hw: pointer to the HW structure
4689  *
4690  *  Workaround for 82566 power-down on D3 entry:
4691  *    1) disable gigabit link
4692  *    2) write VR power-down enable
4693  *    3) read it back
4694  *  Continue if successful, else issue LCD reset and repeat
4695  **/
4696 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4697 {
4698         u32 reg;
4699         u16 data;
4700         u8  retry = 0;
4701
4702         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4703
4704         if (hw->phy.type != e1000_phy_igp_3)
4705                 return;
4706
4707         /* Try the workaround twice (if needed) */
4708         do {
4709                 /* Disable link */
4710                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4711                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4712                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4713                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4714
4715                 /* Call gig speed drop workaround on Gig disable before
4716                  * accessing any PHY registers
4717                  */
4718                 if (hw->mac.type == e1000_ich8lan)
4719                         e1000_gig_downshift_workaround_ich8lan(hw);
4720
4721                 /* Write VR power-down enable */
4722                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4723                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4724                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4725                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4726
4727                 /* Read it back and test */
4728                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4729                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4730                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4731                         break;
4732
4733                 /* Issue PHY reset and repeat at most one more time */
4734                 reg = E1000_READ_REG(hw, E1000_CTRL);
4735                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4736                 retry++;
4737         } while (retry);
4738 }
4739
4740 /**
4741  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4742  *  @hw: pointer to the HW structure
4743  *
4744  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4745  *  LPLU, Gig disable, MDIC PHY reset):
4746  *    1) Set Kumeran Near-end loopback
4747  *    2) Clear Kumeran Near-end loopback
4748  *  Should only be called for ICH8[m] devices with any 1G Phy.
4749  **/
4750 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4751 {
4752         s32 ret_val;
4753         u16 reg_data;
4754
4755         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4756
4757         if ((hw->mac.type != e1000_ich8lan) ||
4758             (hw->phy.type == e1000_phy_ife))
4759                 return;
4760
4761         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4762                                               &reg_data);
4763         if (ret_val)
4764                 return;
4765         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4766         ret_val = e1000_write_kmrn_reg_generic(hw,
4767                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
4768                                                reg_data);
4769         if (ret_val)
4770                 return;
4771         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4772         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4773                                      reg_data);
4774 }
4775
4776 /**
4777  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4778  *  @hw: pointer to the HW structure
4779  *
4780  *  During S0 to Sx transition, it is possible the link remains at gig
4781  *  instead of negotiating to a lower speed.  Before going to Sx, set
4782  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4783  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4784  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4785  *  needs to be written.
4786  *  Parts that support (and are linked to a partner which support) EEE in
4787  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4788  *  than 10Mbps w/o EEE.
4789  **/
4790 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4791 {
4792         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4793         u32 phy_ctrl;
4794         s32 ret_val;
4795
4796         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4797
4798         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4799         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4800
4801         if (hw->phy.type == e1000_phy_i217) {
4802                 u16 phy_reg, device_id = hw->device_id;
4803
4804                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4805                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4806                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4807                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4808                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4809
4810                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4811                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4812                 }
4813
4814                 ret_val = hw->phy.ops.acquire(hw);
4815                 if (ret_val)
4816                         goto out;
4817
4818                 if (!dev_spec->eee_disable) {
4819                         u16 eee_advert;
4820
4821                         ret_val =
4822                             e1000_read_emi_reg_locked(hw,
4823                                                       I217_EEE_ADVERTISEMENT,
4824                                                       &eee_advert);
4825                         if (ret_val)
4826                                 goto release;
4827
4828                         /* Disable LPLU if both link partners support 100BaseT
4829                          * EEE and 100Full is advertised on both ends of the
4830                          * link, and enable Auto Enable LPI since there will
4831                          * be no driver to enable LPI while in Sx.
4832                          */
4833                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4834                             (dev_spec->eee_lp_ability &
4835                              I82579_EEE_100_SUPPORTED) &&
4836                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4837                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4838                                               E1000_PHY_CTRL_NOND0A_LPLU);
4839
4840                                 /* Set Auto Enable LPI after link up */
4841                                 hw->phy.ops.read_reg_locked(hw,
4842                                                             I217_LPI_GPIO_CTRL,
4843                                                             &phy_reg);
4844                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4845                                 hw->phy.ops.write_reg_locked(hw,
4846                                                              I217_LPI_GPIO_CTRL,
4847                                                              phy_reg);
4848                         }
4849                 }
4850
4851                 /* For i217 Intel Rapid Start Technology support,
4852                  * when the system is going into Sx and no manageability engine
4853                  * is present, the driver must configure proxy to reset only on
4854                  * power good.  LPI (Low Power Idle) state must also reset only
4855                  * on power good, as well as the MTA (Multicast table array).
4856                  * The SMBus release must also be disabled on LCD reset.
4857                  */
4858                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4859                       E1000_ICH_FWSM_FW_VALID)) {
4860                         /* Enable proxy to reset only on power good. */
4861                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4862                                                     &phy_reg);
4863                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4864                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4865                                                      phy_reg);
4866
4867                         /* Set bit enable LPI (EEE) to reset only on
4868                          * power good.
4869                         */
4870                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4871                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4872                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4873
4874                         /* Disable the SMB release on LCD reset. */
4875                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4876                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4877                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4878                 }
4879
4880                 /* Enable MTA to reset for Intel Rapid Start Technology
4881                  * Support
4882                  */
4883                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4884                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4885                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4886
4887 release:
4888                 hw->phy.ops.release(hw);
4889         }
4890 out:
4891         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4892
4893         if (hw->mac.type == e1000_ich8lan)
4894                 e1000_gig_downshift_workaround_ich8lan(hw);
4895
4896         if (hw->mac.type >= e1000_pchlan) {
4897                 e1000_oem_bits_config_ich8lan(hw, false);
4898
4899                 /* Reset PHY to activate OEM bits on 82577/8 */
4900                 if (hw->mac.type == e1000_pchlan)
4901                         e1000_phy_hw_reset_generic(hw);
4902
4903                 ret_val = hw->phy.ops.acquire(hw);
4904                 if (ret_val)
4905                         return;
4906                 e1000_write_smbus_addr(hw);
4907                 hw->phy.ops.release(hw);
4908         }
4909
4910         return;
4911 }
4912
4913 /**
4914  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4915  *  @hw: pointer to the HW structure
4916  *
4917  *  During Sx to S0 transitions on non-managed devices or managed devices
4918  *  on which PHY resets are not blocked, if the PHY registers cannot be
4919  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4920  *  the PHY.
4921  *  On i217, setup Intel Rapid Start Technology.
4922  **/
4923 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4924 {
4925         s32 ret_val;
4926
4927         DEBUGFUNC("e1000_resume_workarounds_pchlan");
4928
4929         if (hw->mac.type < e1000_pch2lan)
4930                 return;
4931
4932         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4933         if (ret_val) {
4934                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4935                 return;
4936         }
4937
4938         /* For i217 Intel Rapid Start Technology support when the system
4939          * is transitioning from Sx and no manageability engine is present
4940          * configure SMBus to restore on reset, disable proxy, and enable
4941          * the reset on MTA (Multicast table array).
4942          */
4943         if (hw->phy.type == e1000_phy_i217) {
4944                 u16 phy_reg;
4945
4946                 ret_val = hw->phy.ops.acquire(hw);
4947                 if (ret_val) {
4948                         DEBUGOUT("Failed to setup iRST\n");
4949                         return;
4950                 }
4951
4952                 /* Clear Auto Enable LPI after link up */
4953                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
4954                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4955                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
4956
4957                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4958                     E1000_ICH_FWSM_FW_VALID)) {
4959                         /* Restore clear on SMB if no manageability engine
4960                          * is present
4961                          */
4962                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
4963                                                               &phy_reg);
4964                         if (ret_val)
4965                                 goto release;
4966                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4967                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4968
4969                         /* Disable Proxy */
4970                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
4971                 }
4972                 /* Enable reset on MTA */
4973                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
4974                                                       &phy_reg);
4975                 if (ret_val)
4976                         goto release;
4977                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4978                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4979 release:
4980                 if (ret_val)
4981                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
4982                 hw->phy.ops.release(hw);
4983         }
4984 }
4985
4986 /**
4987  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4988  *  @hw: pointer to the HW structure
4989  *
4990  *  Return the LED back to the default configuration.
4991  **/
4992 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4993 {
4994         DEBUGFUNC("e1000_cleanup_led_ich8lan");
4995
4996         if (hw->phy.type == e1000_phy_ife)
4997                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4998                                              0);
4999
5000         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5001         return E1000_SUCCESS;
5002 }
5003
5004 /**
5005  *  e1000_led_on_ich8lan - Turn LEDs on
5006  *  @hw: pointer to the HW structure
5007  *
5008  *  Turn on the LEDs.
5009  **/
5010 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5011 {
5012         DEBUGFUNC("e1000_led_on_ich8lan");
5013
5014         if (hw->phy.type == e1000_phy_ife)
5015                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5016                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5017
5018         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5019         return E1000_SUCCESS;
5020 }
5021
5022 /**
5023  *  e1000_led_off_ich8lan - Turn LEDs off
5024  *  @hw: pointer to the HW structure
5025  *
5026  *  Turn off the LEDs.
5027  **/
5028 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5029 {
5030         DEBUGFUNC("e1000_led_off_ich8lan");
5031
5032         if (hw->phy.type == e1000_phy_ife)
5033                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5034                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5035
5036         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5037         return E1000_SUCCESS;
5038 }
5039
5040 /**
5041  *  e1000_setup_led_pchlan - Configures SW controllable LED
5042  *  @hw: pointer to the HW structure
5043  *
5044  *  This prepares the SW controllable LED for use.
5045  **/
5046 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5047 {
5048         DEBUGFUNC("e1000_setup_led_pchlan");
5049
5050         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5051                                      (u16)hw->mac.ledctl_mode1);
5052 }
5053
5054 /**
5055  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5056  *  @hw: pointer to the HW structure
5057  *
5058  *  Return the LED back to the default configuration.
5059  **/
5060 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5061 {
5062         DEBUGFUNC("e1000_cleanup_led_pchlan");
5063
5064         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5065                                      (u16)hw->mac.ledctl_default);
5066 }
5067
5068 /**
5069  *  e1000_led_on_pchlan - Turn LEDs on
5070  *  @hw: pointer to the HW structure
5071  *
5072  *  Turn on the LEDs.
5073  **/
5074 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5075 {
5076         u16 data = (u16)hw->mac.ledctl_mode2;
5077         u32 i, led;
5078
5079         DEBUGFUNC("e1000_led_on_pchlan");
5080
5081         /* If no link, then turn LED on by setting the invert bit
5082          * for each LED that's mode is "link_up" in ledctl_mode2.
5083          */
5084         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5085                 for (i = 0; i < 3; i++) {
5086                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5087                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5088                             E1000_LEDCTL_MODE_LINK_UP)
5089                                 continue;
5090                         if (led & E1000_PHY_LED0_IVRT)
5091                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5092                         else
5093                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5094                 }
5095         }
5096
5097         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5098 }
5099
5100 /**
5101  *  e1000_led_off_pchlan - Turn LEDs off
5102  *  @hw: pointer to the HW structure
5103  *
5104  *  Turn off the LEDs.
5105  **/
5106 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5107 {
5108         u16 data = (u16)hw->mac.ledctl_mode1;
5109         u32 i, led;
5110
5111         DEBUGFUNC("e1000_led_off_pchlan");
5112
5113         /* If no link, then turn LED off by clearing the invert bit
5114          * for each LED that's mode is "link_up" in ledctl_mode1.
5115          */
5116         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5117                 for (i = 0; i < 3; i++) {
5118                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5119                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5120                             E1000_LEDCTL_MODE_LINK_UP)
5121                                 continue;
5122                         if (led & E1000_PHY_LED0_IVRT)
5123                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5124                         else
5125                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5126                 }
5127         }
5128
5129         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5130 }
5131
5132 /**
5133  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5134  *  @hw: pointer to the HW structure
5135  *
5136  *  Read appropriate register for the config done bit for completion status
5137  *  and configure the PHY through s/w for EEPROM-less parts.
5138  *
5139  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5140  *  config done bit, so only an error is logged and continues.  If we were
5141  *  to return with error, EEPROM-less silicon would not be able to be reset
5142  *  or change link.
5143  **/
5144 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5145 {
5146         s32 ret_val = E1000_SUCCESS;
5147         u32 bank = 0;
5148         u32 status;
5149
5150         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5151
5152         e1000_get_cfg_done_generic(hw);
5153
5154         /* Wait for indication from h/w that it has completed basic config */
5155         if (hw->mac.type >= e1000_ich10lan) {
5156                 e1000_lan_init_done_ich8lan(hw);
5157         } else {
5158                 ret_val = e1000_get_auto_rd_done_generic(hw);
5159                 if (ret_val) {
5160                         /* When auto config read does not complete, do not
5161                          * return with an error. This can happen in situations
5162                          * where there is no eeprom and prevents getting link.
5163                          */
5164                         DEBUGOUT("Auto Read Done did not complete\n");
5165                         ret_val = E1000_SUCCESS;
5166                 }
5167         }
5168
5169         /* Clear PHY Reset Asserted bit */
5170         status = E1000_READ_REG(hw, E1000_STATUS);
5171         if (status & E1000_STATUS_PHYRA)
5172                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5173         else
5174                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5175
5176         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5177         if (hw->mac.type <= e1000_ich9lan) {
5178                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5179                     (hw->phy.type == e1000_phy_igp_3)) {
5180                         e1000_phy_init_script_igp3(hw);
5181                 }
5182         } else {
5183                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5184                         /* Maybe we should do a basic PHY config */
5185                         DEBUGOUT("EEPROM not present\n");
5186                         ret_val = -E1000_ERR_CONFIG;
5187                 }
5188         }
5189
5190         return ret_val;
5191 }
5192
5193 /**
5194  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5195  * @hw: pointer to the HW structure
5196  *
5197  * In the case of a PHY power down to save power, or to turn off link during a
5198  * driver unload, or wake on lan is not enabled, remove the link.
5199  **/
5200 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5201 {
5202         /* If the management interface is not enabled, then power down */
5203         if (!(hw->mac.ops.check_mng_mode(hw) ||
5204               hw->phy.ops.check_reset_block(hw)))
5205                 e1000_power_down_phy_copper(hw);
5206
5207         return;
5208 }
5209
5210 /**
5211  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5212  *  @hw: pointer to the HW structure
5213  *
5214  *  Clears hardware counters specific to the silicon family and calls
5215  *  clear_hw_cntrs_generic to clear all general purpose counters.
5216  **/
5217 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5218 {
5219         u16 phy_data;
5220         s32 ret_val;
5221
5222         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5223
5224         e1000_clear_hw_cntrs_base_generic(hw);
5225
5226         E1000_READ_REG(hw, E1000_ALGNERRC);
5227         E1000_READ_REG(hw, E1000_RXERRC);
5228         E1000_READ_REG(hw, E1000_TNCRS);
5229         E1000_READ_REG(hw, E1000_CEXTERR);
5230         E1000_READ_REG(hw, E1000_TSCTC);
5231         E1000_READ_REG(hw, E1000_TSCTFC);
5232
5233         E1000_READ_REG(hw, E1000_MGTPRC);
5234         E1000_READ_REG(hw, E1000_MGTPDC);
5235         E1000_READ_REG(hw, E1000_MGTPTC);
5236
5237         E1000_READ_REG(hw, E1000_IAC);
5238         E1000_READ_REG(hw, E1000_ICRXOC);
5239
5240         /* Clear PHY statistics registers */
5241         if ((hw->phy.type == e1000_phy_82578) ||
5242             (hw->phy.type == e1000_phy_82579) ||
5243             (hw->phy.type == e1000_phy_i217) ||
5244             (hw->phy.type == e1000_phy_82577)) {
5245                 ret_val = hw->phy.ops.acquire(hw);
5246                 if (ret_val)
5247                         return;
5248                 ret_val = hw->phy.ops.set_page(hw,
5249                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5250                 if (ret_val)
5251                         goto release;
5252                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5253                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5254                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5255                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5256                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5257                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5258                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5259                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5260                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5261                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5262                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5263                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5264                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5265                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5266 release:
5267                 hw->phy.ops.release(hw);
5268         }
5269 }
5270