1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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32 ***************************************************************************/
34 /* 82562G 10/100 Network Connection
35 * 82562G-2 10/100 Network Connection
36 * 82562GT 10/100 Network Connection
37 * 82562GT-2 10/100 Network Connection
38 * 82562V 10/100 Network Connection
39 * 82562V-2 10/100 Network Connection
40 * 82566DC-2 Gigabit Network Connection
41 * 82566DC Gigabit Network Connection
42 * 82566DM-2 Gigabit Network Connection
43 * 82566DM Gigabit Network Connection
44 * 82566MC Gigabit Network Connection
45 * 82566MM Gigabit Network Connection
46 * 82567LM Gigabit Network Connection
47 * 82567LF Gigabit Network Connection
48 * 82567V Gigabit Network Connection
49 * 82567LM-2 Gigabit Network Connection
50 * 82567LF-2 Gigabit Network Connection
51 * 82567V-2 Gigabit Network Connection
52 * 82567LF-3 Gigabit Network Connection
53 * 82567LM-3 Gigabit Network Connection
54 * 82567LM-4 Gigabit Network Connection
55 * 82577LM Gigabit Network Connection
56 * 82577LC Gigabit Network Connection
57 * 82578DM Gigabit Network Connection
58 * 82578DC Gigabit Network Connection
59 * 82579LM Gigabit Network Connection
60 * 82579V Gigabit Network Connection
61 * Ethernet Connection I217-LM
62 * Ethernet Connection I217-V
63 * Ethernet Connection I218-V
64 * Ethernet Connection I218-LM
65 * Ethernet Connection (2) I218-LM
66 * Ethernet Connection (2) I218-V
67 * Ethernet Connection (3) I218-LM
68 * Ethernet Connection (3) I218-V
71 #include "e1000_api.h"
73 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
74 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
84 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
87 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
88 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
89 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
90 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
91 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
93 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
95 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
98 u16 words, u16 *data);
99 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
100 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
103 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
104 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
105 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
106 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
107 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
108 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
109 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
110 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
111 u16 *speed, u16 *duplex);
112 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
113 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
114 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
115 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
116 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
117 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
118 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
119 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
120 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
121 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
122 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
123 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
124 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
125 u32 offset, u8 *data);
126 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
128 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
129 u32 offset, u16 *data);
130 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
131 u32 offset, u8 byte);
132 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
133 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
134 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
135 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
136 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
137 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
139 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
140 /* Offset 04h HSFSTS */
141 union ich8_hws_flash_status {
143 u16 flcdone:1; /* bit 0 Flash Cycle Done */
144 u16 flcerr:1; /* bit 1 Flash Cycle Error */
145 u16 dael:1; /* bit 2 Direct Access error Log */
146 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
147 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
148 u16 reserved1:2; /* bit 13:6 Reserved */
149 u16 reserved2:6; /* bit 13:6 Reserved */
150 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
151 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
156 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
157 /* Offset 06h FLCTL */
158 union ich8_hws_flash_ctrl {
159 struct ich8_hsflctl {
160 u16 flcgo:1; /* 0 Flash Cycle Go */
161 u16 flcycle:2; /* 2:1 Flash Cycle */
162 u16 reserved:5; /* 7:3 Reserved */
163 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
164 u16 flockdn:6; /* 15:10 Reserved */
169 /* ICH Flash Region Access Permissions */
170 union ich8_hws_flash_regacc {
172 u32 grra:8; /* 0:7 GbE region Read Access */
173 u32 grwa:8; /* 8:15 GbE region Write Access */
174 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
175 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
181 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
182 * @hw: pointer to the HW structure
184 * Test access to the PHY registers by reading the PHY ID registers. If
185 * the PHY ID is already known (e.g. resume path) compare it with known ID,
186 * otherwise assume the read PHY ID is correct if it is valid.
188 * Assumes the sw/fw/hw semaphore is already acquired.
190 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
198 for (retry_count = 0; retry_count < 2; retry_count++) {
199 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
200 if (ret_val || (phy_reg == 0xFFFF))
202 phy_id = (u32)(phy_reg << 16);
204 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
205 if (ret_val || (phy_reg == 0xFFFF)) {
209 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
214 if (hw->phy.id == phy_id)
218 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
222 /* In case the PHY needs to be in mdio slow mode,
223 * set slow mode and try to get the PHY id again.
225 if (hw->mac.type < e1000_pch_lpt) {
226 hw->phy.ops.release(hw);
227 ret_val = e1000_set_mdio_slow_mode_hv(hw);
229 ret_val = e1000_get_phy_id(hw);
230 hw->phy.ops.acquire(hw);
236 if (hw->mac.type == e1000_pch_lpt) {
237 /* Only unforce SMBus if ME is not active */
238 if (!(E1000_READ_REG(hw, E1000_FWSM) &
239 E1000_ICH_FWSM_FW_VALID)) {
240 /* Unforce SMBus mode in PHY */
241 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
242 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
243 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
245 /* Unforce SMBus mode in MAC */
246 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
247 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
248 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
256 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
257 * @hw: pointer to the HW structure
259 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
260 * used to reset the PHY to a quiescent state when necessary.
262 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
266 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
268 /* Set Phy Config Counter to 50msec */
269 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
270 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
271 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
272 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
274 /* Toggle LANPHYPC Value bit */
275 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
276 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
277 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
278 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
279 E1000_WRITE_FLUSH(hw);
281 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
282 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
283 E1000_WRITE_FLUSH(hw);
285 if (hw->mac.type < e1000_pch_lpt) {
292 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
293 E1000_CTRL_EXT_LPCD) && count--);
300 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
301 * @hw: pointer to the HW structure
303 * Workarounds/flow necessary for PHY initialization during driver load
306 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
308 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
311 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
313 /* Gate automatic PHY configuration by hardware on managed and
314 * non-managed 82579 and newer adapters.
316 e1000_gate_hw_phy_config_ich8lan(hw, true);
319 /* It is not possible to be certain of the current state of ULP
320 * so forcibly disable it.
322 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
324 #endif /* ULP_SUPPORT */
325 ret_val = hw->phy.ops.acquire(hw);
327 DEBUGOUT("Failed to initialize PHY flow\n");
331 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
332 * inaccessible and resetting the PHY is not blocked, toggle the
333 * LANPHYPC Value bit to force the interconnect to PCIe mode.
335 switch (hw->mac.type) {
337 if (e1000_phy_is_accessible_pchlan(hw))
340 /* Before toggling LANPHYPC, see if PHY is accessible by
341 * forcing MAC to SMBus mode first.
343 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
344 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
345 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
347 /* Wait 50 milliseconds for MAC to finish any retries
348 * that it might be trying to perform from previous
349 * attempts to acknowledge any phy read requests.
355 if (e1000_phy_is_accessible_pchlan(hw))
360 if ((hw->mac.type == e1000_pchlan) &&
361 (fwsm & E1000_ICH_FWSM_FW_VALID))
364 if (hw->phy.ops.check_reset_block(hw)) {
365 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
366 ret_val = -E1000_ERR_PHY;
370 /* Toggle LANPHYPC Value bit */
371 e1000_toggle_lanphypc_pch_lpt(hw);
372 if (hw->mac.type >= e1000_pch_lpt) {
373 if (e1000_phy_is_accessible_pchlan(hw))
376 /* Toggling LANPHYPC brings the PHY out of SMBus mode
377 * so ensure that the MAC is also out of SMBus mode
379 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
380 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
381 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
383 if (e1000_phy_is_accessible_pchlan(hw))
386 ret_val = -E1000_ERR_PHY;
393 hw->phy.ops.release(hw);
396 /* Check to see if able to reset PHY. Print error if not */
397 if (hw->phy.ops.check_reset_block(hw)) {
398 ERROR_REPORT("Reset blocked by ME\n");
402 /* Reset the PHY before any access to it. Doing so, ensures
403 * that the PHY is in a known good state before we read/write
404 * PHY registers. The generic reset is sufficient here,
405 * because we haven't determined the PHY type yet.
407 ret_val = e1000_phy_hw_reset_generic(hw);
411 /* On a successful reset, possibly need to wait for the PHY
412 * to quiesce to an accessible state before returning control
413 * to the calling function. If the PHY does not quiesce, then
414 * return E1000E_BLK_PHY_RESET, as this is the condition that
417 ret_val = hw->phy.ops.check_reset_block(hw);
419 ERROR_REPORT("ME blocked access to PHY after reset\n");
423 /* Ungate automatic PHY configuration on non-managed 82579 */
424 if ((hw->mac.type == e1000_pch2lan) &&
425 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
427 e1000_gate_hw_phy_config_ich8lan(hw, false);
434 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
435 * @hw: pointer to the HW structure
437 * Initialize family-specific PHY parameters and function pointers.
439 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
441 struct e1000_phy_info *phy = &hw->phy;
444 DEBUGFUNC("e1000_init_phy_params_pchlan");
447 phy->reset_delay_us = 100;
449 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
450 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
451 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
452 phy->ops.set_page = e1000_set_page_igp;
453 phy->ops.read_reg = e1000_read_phy_reg_hv;
454 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
455 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
456 phy->ops.release = e1000_release_swflag_ich8lan;
457 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
458 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
459 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
460 phy->ops.write_reg = e1000_write_phy_reg_hv;
461 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
462 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
463 phy->ops.power_up = e1000_power_up_phy_copper;
464 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
465 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
467 phy->id = e1000_phy_unknown;
469 ret_val = e1000_init_phy_workarounds_pchlan(hw);
473 if (phy->id == e1000_phy_unknown)
474 switch (hw->mac.type) {
476 ret_val = e1000_get_phy_id(hw);
479 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
484 /* In case the PHY needs to be in mdio slow mode,
485 * set slow mode and try to get the PHY id again.
487 ret_val = e1000_set_mdio_slow_mode_hv(hw);
490 ret_val = e1000_get_phy_id(hw);
495 phy->type = e1000_get_phy_type_from_id(phy->id);
498 case e1000_phy_82577:
499 case e1000_phy_82579:
501 phy->ops.check_polarity = e1000_check_polarity_82577;
502 phy->ops.force_speed_duplex =
503 e1000_phy_force_speed_duplex_82577;
504 phy->ops.get_cable_length = e1000_get_cable_length_82577;
505 phy->ops.get_info = e1000_get_phy_info_82577;
506 phy->ops.commit = e1000_phy_sw_reset_generic;
508 case e1000_phy_82578:
509 phy->ops.check_polarity = e1000_check_polarity_m88;
510 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
511 phy->ops.get_cable_length = e1000_get_cable_length_m88;
512 phy->ops.get_info = e1000_get_phy_info_m88;
515 ret_val = -E1000_ERR_PHY;
523 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
524 * @hw: pointer to the HW structure
526 * Initialize family-specific PHY parameters and function pointers.
528 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
530 struct e1000_phy_info *phy = &hw->phy;
534 DEBUGFUNC("e1000_init_phy_params_ich8lan");
537 phy->reset_delay_us = 100;
539 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
540 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
541 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
542 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
543 phy->ops.read_reg = e1000_read_phy_reg_igp;
544 phy->ops.release = e1000_release_swflag_ich8lan;
545 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
546 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
547 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
548 phy->ops.write_reg = e1000_write_phy_reg_igp;
549 phy->ops.power_up = e1000_power_up_phy_copper;
550 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
552 /* We may need to do this twice - once for IGP and if that fails,
553 * we'll set BM func pointers and try again
555 ret_val = e1000_determine_phy_address(hw);
557 phy->ops.write_reg = e1000_write_phy_reg_bm;
558 phy->ops.read_reg = e1000_read_phy_reg_bm;
559 ret_val = e1000_determine_phy_address(hw);
561 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
567 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
570 ret_val = e1000_get_phy_id(hw);
577 case IGP03E1000_E_PHY_ID:
578 phy->type = e1000_phy_igp_3;
579 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
580 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
581 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
582 phy->ops.get_info = e1000_get_phy_info_igp;
583 phy->ops.check_polarity = e1000_check_polarity_igp;
584 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
587 case IFE_PLUS_E_PHY_ID:
589 phy->type = e1000_phy_ife;
590 phy->autoneg_mask = E1000_ALL_NOT_GIG;
591 phy->ops.get_info = e1000_get_phy_info_ife;
592 phy->ops.check_polarity = e1000_check_polarity_ife;
593 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
595 case BME1000_E_PHY_ID:
596 phy->type = e1000_phy_bm;
597 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
598 phy->ops.read_reg = e1000_read_phy_reg_bm;
599 phy->ops.write_reg = e1000_write_phy_reg_bm;
600 phy->ops.commit = e1000_phy_sw_reset_generic;
601 phy->ops.get_info = e1000_get_phy_info_m88;
602 phy->ops.check_polarity = e1000_check_polarity_m88;
603 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
606 return -E1000_ERR_PHY;
610 return E1000_SUCCESS;
614 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
615 * @hw: pointer to the HW structure
617 * Initialize family-specific NVM parameters and function
620 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
622 struct e1000_nvm_info *nvm = &hw->nvm;
623 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
624 u32 gfpreg, sector_base_addr, sector_end_addr;
627 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
629 /* Can't read flash registers if the register set isn't mapped. */
630 nvm->type = e1000_nvm_flash_sw;
631 if (!hw->flash_address) {
632 DEBUGOUT("ERROR: Flash registers not mapped\n");
633 return -E1000_ERR_CONFIG;
636 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
638 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
639 * Add 1 to sector_end_addr since this sector is included in
642 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
643 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
645 /* flash_base_addr is byte-aligned */
646 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
648 /* find total size of the NVM, then cut in half since the total
649 * size represents two separate NVM banks.
651 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
652 << FLASH_SECTOR_ADDR_SHIFT);
653 nvm->flash_bank_size /= 2;
654 /* Adjust to word count */
655 nvm->flash_bank_size /= sizeof(u16);
657 nvm->word_size = E1000_SHADOW_RAM_WORDS;
659 /* Clear shadow ram */
660 for (i = 0; i < nvm->word_size; i++) {
661 dev_spec->shadow_ram[i].modified = false;
662 dev_spec->shadow_ram[i].value = 0xFFFF;
665 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
666 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
668 /* Function Pointers */
669 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
670 nvm->ops.release = e1000_release_nvm_ich8lan;
671 nvm->ops.read = e1000_read_nvm_ich8lan;
672 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
673 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
674 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
675 nvm->ops.write = e1000_write_nvm_ich8lan;
677 return E1000_SUCCESS;
681 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
682 * @hw: pointer to the HW structure
684 * Initialize family-specific MAC parameters and function
687 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
689 struct e1000_mac_info *mac = &hw->mac;
690 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
692 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
694 DEBUGFUNC("e1000_init_mac_params_ich8lan");
696 /* Set media type function pointer */
697 hw->phy.media_type = e1000_media_type_copper;
699 /* Set mta register count */
700 mac->mta_reg_count = 32;
701 /* Set rar entry count */
702 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
703 if (mac->type == e1000_ich8lan)
704 mac->rar_entry_count--;
705 /* Set if part includes ASF firmware */
706 mac->asf_firmware_present = true;
708 mac->has_fwsm = true;
709 /* ARC subsystem not supported */
710 mac->arc_subsystem_valid = false;
711 /* Adaptive IFS supported */
712 mac->adaptive_ifs = true;
714 /* Function pointers */
716 /* bus type/speed/width */
717 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
719 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
721 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
722 /* hw initialization */
723 mac->ops.init_hw = e1000_init_hw_ich8lan;
725 mac->ops.setup_link = e1000_setup_link_ich8lan;
726 /* physical interface setup */
727 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
729 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
731 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
732 /* multicast address update */
733 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
734 /* clear hardware counters */
735 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
737 /* LED and other operations */
742 /* check management mode */
743 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
745 mac->ops.id_led_init = e1000_id_led_init_generic;
747 mac->ops.blink_led = e1000_blink_led_generic;
749 mac->ops.setup_led = e1000_setup_led_generic;
751 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
752 /* turn on/off LED */
753 mac->ops.led_on = e1000_led_on_ich8lan;
754 mac->ops.led_off = e1000_led_off_ich8lan;
757 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
758 mac->ops.rar_set = e1000_rar_set_pch2lan;
761 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
762 /* multicast address update for pch2 */
763 mac->ops.update_mc_addr_list =
764 e1000_update_mc_addr_list_pch2lan;
768 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
769 /* save PCH revision_id */
770 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
771 hw->revision_id = (u8)(pci_cfg &= 0x000F);
772 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
773 /* check management mode */
774 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
776 mac->ops.id_led_init = e1000_id_led_init_pchlan;
778 mac->ops.setup_led = e1000_setup_led_pchlan;
780 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
781 /* turn on/off LED */
782 mac->ops.led_on = e1000_led_on_pchlan;
783 mac->ops.led_off = e1000_led_off_pchlan;
789 if (mac->type == e1000_pch_lpt) {
790 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
791 mac->ops.rar_set = e1000_rar_set_pch_lpt;
792 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
795 /* Enable PCS Lock-loss workaround for ICH8 */
796 if (mac->type == e1000_ich8lan)
797 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
799 return E1000_SUCCESS;
803 * __e1000_access_emi_reg_locked - Read/write EMI register
804 * @hw: pointer to the HW structure
805 * @addr: EMI address to program
806 * @data: pointer to value to read/write from/to the EMI address
807 * @read: boolean flag to indicate read or write
809 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
811 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
812 u16 *data, bool read)
816 DEBUGFUNC("__e1000_access_emi_reg_locked");
818 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
823 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
826 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
833 * e1000_read_emi_reg_locked - Read Extended Management Interface register
834 * @hw: pointer to the HW structure
835 * @addr: EMI address to program
836 * @data: value to be read from the EMI address
838 * Assumes the SW/FW/HW Semaphore is already acquired.
840 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
842 DEBUGFUNC("e1000_read_emi_reg_locked");
844 return __e1000_access_emi_reg_locked(hw, addr, data, true);
848 * e1000_write_emi_reg_locked - Write Extended Management Interface register
849 * @hw: pointer to the HW structure
850 * @addr: EMI address to program
851 * @data: value to be written to the EMI address
853 * Assumes the SW/FW/HW Semaphore is already acquired.
855 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
857 DEBUGFUNC("e1000_read_emi_reg_locked");
859 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
863 * e1000_set_eee_pchlan - Enable/disable EEE support
864 * @hw: pointer to the HW structure
866 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
867 * the link and the EEE capabilities of the link partner. The LPI Control
868 * register bits will remain set only if/when link is up.
870 * EEE LPI must not be asserted earlier than one second after link is up.
871 * On 82579, EEE LPI should not be enabled until such time otherwise there
872 * can be link issues with some switches. Other devices can have EEE LPI
873 * enabled immediately upon link up since they have a timer in hardware which
874 * prevents LPI from being asserted too early.
876 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
878 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
880 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
882 DEBUGFUNC("e1000_set_eee_pchlan");
884 switch (hw->phy.type) {
885 case e1000_phy_82579:
886 lpa = I82579_EEE_LP_ABILITY;
887 pcs_status = I82579_EEE_PCS_STATUS;
888 adv_addr = I82579_EEE_ADVERTISEMENT;
891 lpa = I217_EEE_LP_ABILITY;
892 pcs_status = I217_EEE_PCS_STATUS;
893 adv_addr = I217_EEE_ADVERTISEMENT;
896 return E1000_SUCCESS;
899 ret_val = hw->phy.ops.acquire(hw);
903 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
907 /* Clear bits that enable EEE in various speeds */
908 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
910 /* Enable EEE if not disabled by user */
911 if (!dev_spec->eee_disable) {
912 /* Save off link partner's EEE ability */
913 ret_val = e1000_read_emi_reg_locked(hw, lpa,
914 &dev_spec->eee_lp_ability);
918 /* Read EEE advertisement */
919 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
923 /* Enable EEE only for speeds in which the link partner is
924 * EEE capable and for which we advertise EEE.
926 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
927 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
929 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
930 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
931 if (data & NWAY_LPAR_100TX_FD_CAPS)
932 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
934 /* EEE is not supported in 100Half, so ignore
935 * partner's EEE in 100 ability if full-duplex
938 dev_spec->eee_lp_ability &=
939 ~I82579_EEE_100_SUPPORTED;
943 if (hw->phy.type == e1000_phy_82579) {
944 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
949 data &= ~I82579_LPI_100_PLL_SHUT;
950 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
954 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
955 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
959 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
961 hw->phy.ops.release(hw);
967 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
968 * @hw: pointer to the HW structure
969 * @link: link up bool flag
971 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
972 * preventing further DMA write requests. Workaround the issue by disabling
973 * the de-assertion of the clock request when in 1Gpbs mode.
974 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
975 * speeds in order to avoid Tx hangs.
977 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
979 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
980 u32 status = E1000_READ_REG(hw, E1000_STATUS);
981 s32 ret_val = E1000_SUCCESS;
984 if (link && (status & E1000_STATUS_SPEED_1000)) {
985 ret_val = hw->phy.ops.acquire(hw);
990 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
996 e1000_write_kmrn_reg_locked(hw,
997 E1000_KMRNCTRLSTA_K1_CONFIG,
999 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1005 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1006 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1009 e1000_write_kmrn_reg_locked(hw,
1010 E1000_KMRNCTRLSTA_K1_CONFIG,
1013 hw->phy.ops.release(hw);
1015 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1016 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1018 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1019 (status & E1000_STATUS_FD)))
1020 goto update_fextnvm6;
1022 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1026 /* Clear link status transmit timeout */
1027 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1029 if (status & E1000_STATUS_SPEED_100) {
1030 /* Set inband Tx timeout to 5x10us for 100Half */
1031 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1033 /* Do not extend the K1 entry latency for 100Half */
1034 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1036 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1038 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1040 /* Extend the K1 entry latency for 10 Mbps */
1041 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1044 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1049 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1057 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1058 * @hw: pointer to the HW structure
1059 * @to_sx: boolean indicating a system power state transition to Sx
1061 * When link is down, configure ULP mode to significantly reduce the power
1062 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1063 * ME firmware to start the ULP configuration. If not on an ME enabled
1064 * system, configure the ULP mode by software.
1066 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1069 s32 ret_val = E1000_SUCCESS;
1072 if ((hw->mac.type < e1000_pch_lpt) ||
1073 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1074 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1075 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1076 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1077 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1082 /* Poll up to 5 seconds for Cable Disconnected indication */
1083 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1084 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1085 /* Bail if link is re-acquired */
1086 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1087 return -E1000_ERR_PHY;
1093 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1094 (E1000_READ_REG(hw, E1000_FEXT) &
1095 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1097 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1098 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1102 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103 /* Request ME configure ULP mode in the PHY */
1104 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1105 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1111 ret_val = hw->phy.ops.acquire(hw);
1115 /* During S0 Idle keep the phy in PCI-E mode */
1116 if (hw->dev_spec.ich8lan.smbus_disable)
1119 /* Force SMBus mode in PHY */
1120 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1123 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1124 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1126 /* Force SMBus mode in MAC */
1127 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1128 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1129 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1133 /* Change the 'Link Status Change' interrupt to trigger
1134 * on 'Cable Status Change'
1136 ret_val = e1000_read_kmrn_reg_locked(hw,
1137 E1000_KMRNCTRLSTA_OP_MODES,
1141 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1142 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1146 /* Set Inband ULP Exit, Reset to SMBus mode and
1147 * Disable SMBus Release on PERST# in PHY
1149 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1152 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1153 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1155 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1156 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1158 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1160 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1161 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1163 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1164 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1165 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1167 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1169 /* Set Disable SMBus Release on PERST# in MAC */
1170 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1171 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1172 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1174 /* Commit ULP changes in PHY by starting auto ULP configuration */
1175 phy_reg |= I218_ULP_CONFIG1_START;
1176 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1179 /* Disable Tx so that the MAC doesn't send any (buffered)
1180 * packets to the PHY.
1182 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1183 mac_reg &= ~E1000_TCTL_EN;
1184 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1188 hw->phy.ops.release(hw);
1191 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1193 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1199 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1200 * @hw: pointer to the HW structure
1201 * @force: boolean indicating whether or not to force disabling ULP
1203 * Un-configure ULP mode when link is up, the system is transitioned from
1204 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1205 * system, poll for an indication from ME that ULP has been un-configured.
1206 * If not on an ME enabled system, un-configure the ULP mode by software.
1208 * During nominal operation, this function is called when link is acquired
1209 * to disable ULP mode (force=false); otherwise, for example when unloading
1210 * the driver or during Sx->S0 transitions, this is called with force=true
1211 * to forcibly disable ULP.
1213 * When the cable is plugged in while the device is in D0, a Cable Status
1214 * Change interrupt is generated which causes this function to be called
1215 * to partially disable ULP mode and restart autonegotiation. This function
1216 * is then called again due to the resulting Link Status Change interrupt
1217 * to finish cleaning up after the ULP flow.
1219 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1221 s32 ret_val = E1000_SUCCESS;
1226 if ((hw->mac.type < e1000_pch_lpt) ||
1227 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1228 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1229 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1230 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1231 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1234 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1236 /* Request ME un-configure ULP mode in the PHY */
1237 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1238 mac_reg &= ~E1000_H2ME_ULP;
1239 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1240 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1243 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1244 while (E1000_READ_REG(hw, E1000_FWSM) &
1245 E1000_FWSM_ULP_CFG_DONE) {
1247 ret_val = -E1000_ERR_PHY;
1253 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1256 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1257 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1258 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1260 /* Clear H2ME.ULP after ME ULP configuration */
1261 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1262 mac_reg &= ~E1000_H2ME_ULP;
1263 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1265 /* Restore link speed advertisements and restart
1268 if (hw->mac.autoneg) {
1269 ret_val = e1000_phy_setup_autoneg(hw);
1273 ret_val = e1000_setup_copper_link_generic(hw);
1277 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1283 ret_val = hw->phy.ops.acquire(hw);
1287 /* Revert the change to the 'Link Status Change'
1288 * interrupt to trigger on 'Cable Status Change'
1290 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1294 phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1295 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1298 /* Toggle LANPHYPC Value bit */
1299 e1000_toggle_lanphypc_pch_lpt(hw);
1301 /* Unforce SMBus mode in PHY */
1302 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1304 /* The MAC might be in PCIe mode, so temporarily force to
1305 * SMBus mode in order to access the PHY.
1307 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1308 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1309 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1313 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1318 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1319 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1321 /* Unforce SMBus mode in MAC */
1322 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1323 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1324 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1326 /* When ULP mode was previously entered, K1 was disabled by the
1327 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1329 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1332 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1333 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1335 /* Clear ULP enabled configuration */
1336 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1339 /* CSC interrupt received due to ULP Indication */
1340 if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1341 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1342 I218_ULP_CONFIG1_STICKY_ULP |
1343 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1344 I218_ULP_CONFIG1_WOL_HOST |
1345 I218_ULP_CONFIG1_INBAND_EXIT |
1346 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1347 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1348 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1349 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1351 /* Commit ULP changes by starting auto ULP configuration */
1352 phy_reg |= I218_ULP_CONFIG1_START;
1353 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1355 /* Clear Disable SMBus Release on PERST# in MAC */
1356 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1357 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1358 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1361 hw->phy.ops.release(hw);
1363 if (hw->mac.autoneg)
1364 e1000_phy_setup_autoneg(hw);
1366 e1000_setup_copper_link_generic(hw);
1368 e1000_sw_lcd_config_ich8lan(hw);
1370 e1000_oem_bits_config_ich8lan(hw, true);
1372 /* Set ULP state to unknown and return non-zero to
1373 * indicate no link (yet) and re-enter on the next LSC
1374 * to finish disabling ULP flow.
1376 hw->dev_spec.ich8lan.ulp_state =
1377 e1000_ulp_state_unknown;
1384 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1385 mac_reg |= E1000_TCTL_EN;
1386 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1389 hw->phy.ops.release(hw);
1391 hw->phy.ops.reset(hw);
1396 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1398 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1403 #endif /* ULP_SUPPORT */
1405 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1406 * @hw: pointer to the HW structure
1408 * Checks to see of the link status of the hardware has changed. If a
1409 * change in link status has been detected, then we read the PHY registers
1410 * to get the current speed/duplex if link exists.
1412 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1414 struct e1000_mac_info *mac = &hw->mac;
1415 s32 ret_val, tipg_reg = 0;
1416 u16 emi_addr, emi_val = 0;
1420 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1422 /* We only want to go out to the PHY registers to see if Auto-Neg
1423 * has completed and/or if our link status has changed. The
1424 * get_link_status flag is set upon receiving a Link Status
1425 * Change or Rx Sequence Error interrupt.
1427 if (!mac->get_link_status)
1428 return E1000_SUCCESS;
1430 if ((hw->mac.type < e1000_pch_lpt) ||
1431 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1432 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1433 /* First we want to see if the MII Status Register reports
1434 * link. If so, then we want to get the current speed/duplex
1437 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1441 /* Check the MAC's STATUS register to determine link state
1442 * since the PHY could be inaccessible while in ULP mode.
1444 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1446 ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1448 ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1453 if (hw->mac.type == e1000_pchlan) {
1454 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1459 /* When connected at 10Mbps half-duplex, some parts are excessively
1460 * aggressive resulting in many collisions. To avoid this, increase
1461 * the IPG and reduce Rx latency in the PHY.
1463 if (((hw->mac.type == e1000_pch2lan) ||
1464 (hw->mac.type == e1000_pch_lpt)) && link) {
1467 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1468 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1469 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1471 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1473 /* Reduce Rx latency in analog PHY */
1476 /* Roll back the default values */
1481 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1483 ret_val = hw->phy.ops.acquire(hw);
1487 if (hw->mac.type == e1000_pch2lan)
1488 emi_addr = I82579_RX_CONFIG;
1490 emi_addr = I217_RX_CONFIG;
1491 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1494 if (hw->mac.type >= e1000_pch_lpt) {
1497 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1499 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1500 if (speed == SPEED_100 || speed == SPEED_10)
1504 hw->phy.ops.write_reg_locked(hw,
1505 I217_PLL_CLOCK_GATE_REG,
1508 hw->phy.ops.release(hw);
1514 /* I217 Packet Loss issue:
1515 * ensure that FEXTNVM4 Beacon Duration is set correctly
1517 * Set the Beacon Duration for I217 to 8 usec
1519 if (hw->mac.type == e1000_pch_lpt) {
1522 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1523 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1524 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1525 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1528 /* Work-around I218 hang issue */
1529 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1530 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1531 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1532 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1533 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1537 /* Clear link partner's EEE ability */
1538 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1540 /* Configure K0s minimum time */
1541 if (hw->mac.type == e1000_pch_lpt) {
1542 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1546 return E1000_SUCCESS; /* No link detected */
1548 mac->get_link_status = false;
1550 switch (hw->mac.type) {
1552 ret_val = e1000_k1_workaround_lv(hw);
1557 if (hw->phy.type == e1000_phy_82578) {
1558 ret_val = e1000_link_stall_workaround_hv(hw);
1563 /* Workaround for PCHx parts in half-duplex:
1564 * Set the number of preambles removed from the packet
1565 * when it is passed from the PHY to the MAC to prevent
1566 * the MAC from misinterpreting the packet type.
1568 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1569 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1571 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1573 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1575 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1581 /* Check if there was DownShift, must be checked
1582 * immediately after link-up
1584 e1000_check_downshift_generic(hw);
1586 /* Enable/Disable EEE after link up */
1587 if (hw->phy.type > e1000_phy_82579) {
1588 ret_val = e1000_set_eee_pchlan(hw);
1593 /* If we are forcing speed/duplex, then we simply return since
1594 * we have already determined whether we have link or not.
1597 return -E1000_ERR_CONFIG;
1599 /* Auto-Neg is enabled. Auto Speed Detection takes care
1600 * of MAC speed/duplex configuration. So we only need to
1601 * configure Collision Distance in the MAC.
1603 mac->ops.config_collision_dist(hw);
1605 /* Configure Flow Control now that Auto-Neg has completed.
1606 * First, we need to restore the desired flow control
1607 * settings because we may have had to re-autoneg with a
1608 * different link partner.
1610 ret_val = e1000_config_fc_after_link_up_generic(hw);
1612 DEBUGOUT("Error configuring flow control\n");
1618 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1619 * @hw: pointer to the HW structure
1621 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1623 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1625 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1627 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1628 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1629 switch (hw->mac.type) {
1632 case e1000_ich10lan:
1633 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1638 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1646 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1647 * @hw: pointer to the HW structure
1649 * Acquires the mutex for performing NVM operations.
1651 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1653 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1655 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1657 return E1000_SUCCESS;
1661 * e1000_release_nvm_ich8lan - Release NVM mutex
1662 * @hw: pointer to the HW structure
1664 * Releases the mutex used while performing NVM operations.
1666 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1668 DEBUGFUNC("e1000_release_nvm_ich8lan");
1670 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1676 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1677 * @hw: pointer to the HW structure
1679 * Acquires the software control flag for performing PHY and select
1682 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1684 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1685 s32 ret_val = E1000_SUCCESS;
1687 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1689 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1692 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1693 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1701 DEBUGOUT("SW has already locked the resource.\n");
1702 ret_val = -E1000_ERR_CONFIG;
1706 timeout = SW_FLAG_TIMEOUT;
1708 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1709 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1712 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1713 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1721 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1722 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1723 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1724 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1725 ret_val = -E1000_ERR_CONFIG;
1731 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1737 * e1000_release_swflag_ich8lan - Release software control flag
1738 * @hw: pointer to the HW structure
1740 * Releases the software control flag for performing PHY and select
1743 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1747 DEBUGFUNC("e1000_release_swflag_ich8lan");
1749 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1751 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1752 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1753 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1755 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1758 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1764 * e1000_check_mng_mode_ich8lan - Checks management mode
1765 * @hw: pointer to the HW structure
1767 * This checks if the adapter has any manageability enabled.
1768 * This is a function pointer entry point only called by read/write
1769 * routines for the PHY and NVM parts.
1771 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1775 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1777 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1779 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1780 ((fwsm & E1000_FWSM_MODE_MASK) ==
1781 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1785 * e1000_check_mng_mode_pchlan - Checks management mode
1786 * @hw: pointer to the HW structure
1788 * This checks if the adapter has iAMT enabled.
1789 * This is a function pointer entry point only called by read/write
1790 * routines for the PHY and NVM parts.
1792 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1796 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1798 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1800 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1801 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1805 * e1000_rar_set_pch2lan - Set receive address register
1806 * @hw: pointer to the HW structure
1807 * @addr: pointer to the receive address
1808 * @index: receive address array register
1810 * Sets the receive address array register at index to the address passed
1811 * in by addr. For 82579, RAR[0] is the base address register that is to
1812 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1813 * Use SHRA[0-3] in place of those reserved for ME.
1815 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1817 u32 rar_low, rar_high;
1819 DEBUGFUNC("e1000_rar_set_pch2lan");
1821 /* HW expects these in little endian so we reverse the byte order
1822 * from network order (big endian) to little endian
1824 rar_low = ((u32) addr[0] |
1825 ((u32) addr[1] << 8) |
1826 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1828 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1830 /* If MAC address zero, no need to set the AV bit */
1831 if (rar_low || rar_high)
1832 rar_high |= E1000_RAH_AV;
1835 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1836 E1000_WRITE_FLUSH(hw);
1837 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1838 E1000_WRITE_FLUSH(hw);
1839 return E1000_SUCCESS;
1842 /* RAR[1-6] are owned by manageability. Skip those and program the
1843 * next address into the SHRA register array.
1845 if (index < (u32) (hw->mac.rar_entry_count)) {
1848 ret_val = e1000_acquire_swflag_ich8lan(hw);
1852 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1853 E1000_WRITE_FLUSH(hw);
1854 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1855 E1000_WRITE_FLUSH(hw);
1857 e1000_release_swflag_ich8lan(hw);
1859 /* verify the register updates */
1860 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1861 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1862 return E1000_SUCCESS;
1864 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1865 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1869 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1870 return -E1000_ERR_CONFIG;
1874 * e1000_rar_set_pch_lpt - Set receive address registers
1875 * @hw: pointer to the HW structure
1876 * @addr: pointer to the receive address
1877 * @index: receive address array register
1879 * Sets the receive address register array at index to the address passed
1880 * in by addr. For LPT, RAR[0] is the base address register that is to
1881 * contain the MAC address. SHRA[0-10] are the shared receive address
1882 * registers that are shared between the Host and manageability engine (ME).
1884 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1886 u32 rar_low, rar_high;
1889 DEBUGFUNC("e1000_rar_set_pch_lpt");
1891 /* HW expects these in little endian so we reverse the byte order
1892 * from network order (big endian) to little endian
1894 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1895 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1897 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1899 /* If MAC address zero, no need to set the AV bit */
1900 if (rar_low || rar_high)
1901 rar_high |= E1000_RAH_AV;
1904 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1905 E1000_WRITE_FLUSH(hw);
1906 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1907 E1000_WRITE_FLUSH(hw);
1908 return E1000_SUCCESS;
1911 /* The manageability engine (ME) can lock certain SHRAR registers that
1912 * it is using - those registers are unavailable for use.
1914 if (index < hw->mac.rar_entry_count) {
1915 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1916 E1000_FWSM_WLOCK_MAC_MASK;
1917 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1919 /* Check if all SHRAR registers are locked */
1923 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1926 ret_val = e1000_acquire_swflag_ich8lan(hw);
1931 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1933 E1000_WRITE_FLUSH(hw);
1934 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1936 E1000_WRITE_FLUSH(hw);
1938 e1000_release_swflag_ich8lan(hw);
1940 /* verify the register updates */
1941 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1942 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1943 return E1000_SUCCESS;
1948 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1949 return -E1000_ERR_CONFIG;
1952 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1954 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1955 * @hw: pointer to the HW structure
1956 * @mc_addr_list: array of multicast addresses to program
1957 * @mc_addr_count: number of multicast addresses to program
1959 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1960 * The caller must have a packed mc_addr_list of multicast addresses.
1962 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1970 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1972 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1974 ret_val = hw->phy.ops.acquire(hw);
1978 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1982 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1983 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1984 (u16)(hw->mac.mta_shadow[i] &
1986 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1987 (u16)((hw->mac.mta_shadow[i] >> 16) &
1991 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1994 hw->phy.ops.release(hw);
1997 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1999 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2000 * @hw: pointer to the HW structure
2002 * Checks if firmware is blocking the reset of the PHY.
2003 * This is a function pointer entry point only called by
2006 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2009 bool blocked = false;
2012 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2015 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2016 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2022 } while (blocked && (i++ < 30));
2023 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2027 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2028 * @hw: pointer to the HW structure
2030 * Assumes semaphore already acquired.
2033 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2036 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2037 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2038 E1000_STRAP_SMT_FREQ_SHIFT;
2041 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2043 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2047 phy_data &= ~HV_SMB_ADDR_MASK;
2048 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2049 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2051 if (hw->phy.type == e1000_phy_i217) {
2052 /* Restore SMBus frequency */
2054 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2055 phy_data |= (freq & (1 << 0)) <<
2056 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2057 phy_data |= (freq & (1 << 1)) <<
2058 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2060 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2064 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2068 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2069 * @hw: pointer to the HW structure
2071 * SW should configure the LCD from the NVM extended configuration region
2072 * as a workaround for certain parts.
2074 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2076 struct e1000_phy_info *phy = &hw->phy;
2077 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2078 s32 ret_val = E1000_SUCCESS;
2079 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2081 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2083 /* Initialize the PHY from the NVM on ICH platforms. This
2084 * is needed due to an issue where the NVM configuration is
2085 * not properly autoloaded after power transitions.
2086 * Therefore, after each PHY reset, we will load the
2087 * configuration data out of the NVM manually.
2089 switch (hw->mac.type) {
2091 if (phy->type != e1000_phy_igp_3)
2094 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2095 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2096 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2103 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2109 ret_val = hw->phy.ops.acquire(hw);
2113 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2114 if (!(data & sw_cfg_mask))
2117 /* Make sure HW does not configure LCD from PHY
2118 * extended configuration before SW configuration
2120 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2121 if ((hw->mac.type < e1000_pch2lan) &&
2122 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2125 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2126 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2127 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2131 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2132 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2134 if (((hw->mac.type == e1000_pchlan) &&
2135 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2136 (hw->mac.type > e1000_pchlan)) {
2137 /* HW configures the SMBus address and LEDs when the
2138 * OEM and LCD Write Enable bits are set in the NVM.
2139 * When both NVM bits are cleared, SW will configure
2142 ret_val = e1000_write_smbus_addr(hw);
2146 data = E1000_READ_REG(hw, E1000_LEDCTL);
2147 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2153 /* Configure LCD from extended configuration region. */
2155 /* cnf_base_addr is in DWORD */
2156 word_addr = (u16)(cnf_base_addr << 1);
2158 for (i = 0; i < cnf_size; i++) {
2159 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2164 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2169 /* Save off the PHY page for future writes. */
2170 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2171 phy_page = reg_data;
2175 reg_addr &= PHY_REG_MASK;
2176 reg_addr |= phy_page;
2178 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2185 hw->phy.ops.release(hw);
2190 * e1000_k1_gig_workaround_hv - K1 Si workaround
2191 * @hw: pointer to the HW structure
2192 * @link: link up bool flag
2194 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2195 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2196 * If link is down, the function will restore the default K1 setting located
2199 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2201 s32 ret_val = E1000_SUCCESS;
2203 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2205 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2207 if (hw->mac.type != e1000_pchlan)
2208 return E1000_SUCCESS;
2210 /* Wrap the whole flow with the sw flag */
2211 ret_val = hw->phy.ops.acquire(hw);
2215 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2217 if (hw->phy.type == e1000_phy_82578) {
2218 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2223 status_reg &= (BM_CS_STATUS_LINK_UP |
2224 BM_CS_STATUS_RESOLVED |
2225 BM_CS_STATUS_SPEED_MASK);
2227 if (status_reg == (BM_CS_STATUS_LINK_UP |
2228 BM_CS_STATUS_RESOLVED |
2229 BM_CS_STATUS_SPEED_1000))
2233 if (hw->phy.type == e1000_phy_82577) {
2234 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2239 status_reg &= (HV_M_STATUS_LINK_UP |
2240 HV_M_STATUS_AUTONEG_COMPLETE |
2241 HV_M_STATUS_SPEED_MASK);
2243 if (status_reg == (HV_M_STATUS_LINK_UP |
2244 HV_M_STATUS_AUTONEG_COMPLETE |
2245 HV_M_STATUS_SPEED_1000))
2249 /* Link stall fix for link up */
2250 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2256 /* Link stall fix for link down */
2257 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2263 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2266 hw->phy.ops.release(hw);
2272 * e1000_configure_k1_ich8lan - Configure K1 power state
2273 * @hw: pointer to the HW structure
2274 * @enable: K1 state to configure
2276 * Configure the K1 power state based on the provided parameter.
2277 * Assumes semaphore already acquired.
2279 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2281 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2289 DEBUGFUNC("e1000_configure_k1_ich8lan");
2291 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2297 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2299 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2301 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2307 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2308 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2310 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2311 reg |= E1000_CTRL_FRCSPD;
2312 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2314 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2315 E1000_WRITE_FLUSH(hw);
2317 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2318 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2319 E1000_WRITE_FLUSH(hw);
2322 return E1000_SUCCESS;
2326 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2327 * @hw: pointer to the HW structure
2328 * @d0_state: boolean if entering d0 or d3 device state
2330 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2331 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2332 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2334 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2340 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2342 if (hw->mac.type < e1000_pchlan)
2345 ret_val = hw->phy.ops.acquire(hw);
2349 if (hw->mac.type == e1000_pchlan) {
2350 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2351 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2355 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2356 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2359 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2361 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2365 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2368 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2369 oem_reg |= HV_OEM_BITS_GBE_DIS;
2371 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2372 oem_reg |= HV_OEM_BITS_LPLU;
2374 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2375 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2376 oem_reg |= HV_OEM_BITS_GBE_DIS;
2378 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2379 E1000_PHY_CTRL_NOND0A_LPLU))
2380 oem_reg |= HV_OEM_BITS_LPLU;
2383 /* Set Restart auto-neg to activate the bits */
2384 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2385 !hw->phy.ops.check_reset_block(hw))
2386 oem_reg |= HV_OEM_BITS_RESTART_AN;
2388 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2391 hw->phy.ops.release(hw);
2398 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2399 * @hw: pointer to the HW structure
2401 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2406 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2408 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2412 data |= HV_KMRN_MDIO_SLOW;
2414 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2420 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2421 * done after every PHY reset.
2423 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2425 s32 ret_val = E1000_SUCCESS;
2428 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2430 if (hw->mac.type != e1000_pchlan)
2431 return E1000_SUCCESS;
2433 /* Set MDIO slow mode before any other MDIO access */
2434 if (hw->phy.type == e1000_phy_82577) {
2435 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2440 if (((hw->phy.type == e1000_phy_82577) &&
2441 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2442 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2443 /* Disable generation of early preamble */
2444 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2448 /* Preamble tuning for SSC */
2449 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2455 if (hw->phy.type == e1000_phy_82578) {
2456 /* Return registers to default by doing a soft reset then
2457 * writing 0x3140 to the control register.
2459 if (hw->phy.revision < 2) {
2460 e1000_phy_sw_reset_generic(hw);
2461 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2467 ret_val = hw->phy.ops.acquire(hw);
2472 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2473 hw->phy.ops.release(hw);
2477 /* Configure the K1 Si workaround during phy reset assuming there is
2478 * link so that it disables K1 if link is in 1Gbps.
2480 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2484 /* Workaround for link disconnects on a busy hub in half duplex */
2485 ret_val = hw->phy.ops.acquire(hw);
2488 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2491 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2496 /* set MSE higher to enable link to stay up when noise is high */
2497 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2499 hw->phy.ops.release(hw);
2505 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2506 * @hw: pointer to the HW structure
2508 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2514 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2516 ret_val = hw->phy.ops.acquire(hw);
2519 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2523 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2524 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2525 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2526 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2527 (u16)(mac_reg & 0xFFFF));
2528 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2529 (u16)((mac_reg >> 16) & 0xFFFF));
2531 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2532 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2533 (u16)(mac_reg & 0xFFFF));
2534 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2535 (u16)((mac_reg & E1000_RAH_AV)
2539 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2542 hw->phy.ops.release(hw);
2545 #ifndef CRC32_OS_SUPPORT
2546 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2548 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2549 u32 i, j, mask, crc;
2551 DEBUGFUNC("e1000_calc_rx_da_crc");
2554 for (i = 0; i < 6; i++) {
2556 for (j = 8; j > 0; j--) {
2557 mask = (crc & 1) * (-1);
2558 crc = (crc >> 1) ^ (poly & mask);
2564 #endif /* CRC32_OS_SUPPORT */
2566 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2568 * @hw: pointer to the HW structure
2569 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2571 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2573 s32 ret_val = E1000_SUCCESS;
2578 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2580 if (hw->mac.type < e1000_pch2lan)
2581 return E1000_SUCCESS;
2583 /* disable Rx path while enabling/disabling workaround */
2584 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2585 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2586 phy_reg | (1 << 14));
2591 /* Write Rx addresses (rar_entry_count for RAL/H, and
2592 * SHRAL/H) and initial CRC values to the MAC
2594 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2595 u8 mac_addr[ETH_ADDR_LEN] = {0};
2596 u32 addr_high, addr_low;
2598 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2599 if (!(addr_high & E1000_RAH_AV))
2601 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2602 mac_addr[0] = (addr_low & 0xFF);
2603 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2604 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2605 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2606 mac_addr[4] = (addr_high & 0xFF);
2607 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2609 #ifndef CRC32_OS_SUPPORT
2610 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2611 e1000_calc_rx_da_crc(mac_addr));
2612 #else /* CRC32_OS_SUPPORT */
2613 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2614 E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2615 #endif /* CRC32_OS_SUPPORT */
2618 /* Write Rx addresses to the PHY */
2619 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2621 /* Enable jumbo frame workaround in the MAC */
2622 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2623 mac_reg &= ~(1 << 14);
2624 mac_reg |= (7 << 15);
2625 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2627 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2628 mac_reg |= E1000_RCTL_SECRC;
2629 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2631 ret_val = e1000_read_kmrn_reg_generic(hw,
2632 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2636 ret_val = e1000_write_kmrn_reg_generic(hw,
2637 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2641 ret_val = e1000_read_kmrn_reg_generic(hw,
2642 E1000_KMRNCTRLSTA_HD_CTRL,
2646 data &= ~(0xF << 8);
2648 ret_val = e1000_write_kmrn_reg_generic(hw,
2649 E1000_KMRNCTRLSTA_HD_CTRL,
2654 /* Enable jumbo frame workaround in the PHY */
2655 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2656 data &= ~(0x7F << 5);
2657 data |= (0x37 << 5);
2658 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2661 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2663 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2666 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2667 data &= ~(0x3FF << 2);
2668 data |= (E1000_TX_PTR_GAP << 2);
2669 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2672 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2675 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2676 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2681 /* Write MAC register values back to h/w defaults */
2682 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2683 mac_reg &= ~(0xF << 14);
2684 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2686 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2687 mac_reg &= ~E1000_RCTL_SECRC;
2688 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2690 ret_val = e1000_read_kmrn_reg_generic(hw,
2691 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2695 ret_val = e1000_write_kmrn_reg_generic(hw,
2696 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2700 ret_val = e1000_read_kmrn_reg_generic(hw,
2701 E1000_KMRNCTRLSTA_HD_CTRL,
2705 data &= ~(0xF << 8);
2707 ret_val = e1000_write_kmrn_reg_generic(hw,
2708 E1000_KMRNCTRLSTA_HD_CTRL,
2713 /* Write PHY register values back to h/w defaults */
2714 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2715 data &= ~(0x7F << 5);
2716 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2719 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2721 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2724 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2725 data &= ~(0x3FF << 2);
2727 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2730 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2733 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2734 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2740 /* re-enable Rx path after enabling/disabling workaround */
2741 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2746 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2747 * done after every PHY reset.
2749 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2751 s32 ret_val = E1000_SUCCESS;
2753 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2755 if (hw->mac.type != e1000_pch2lan)
2756 return E1000_SUCCESS;
2758 /* Set MDIO slow mode before any other MDIO access */
2759 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2763 ret_val = hw->phy.ops.acquire(hw);
2766 /* set MSE higher to enable link to stay up when noise is high */
2767 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2770 /* drop link after 5 times MSE threshold was reached */
2771 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2773 hw->phy.ops.release(hw);
2779 * e1000_k1_gig_workaround_lv - K1 Si workaround
2780 * @hw: pointer to the HW structure
2782 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2783 * Disable K1 for 1000 and 100 speeds
2785 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2787 s32 ret_val = E1000_SUCCESS;
2790 DEBUGFUNC("e1000_k1_workaround_lv");
2792 if (hw->mac.type != e1000_pch2lan)
2793 return E1000_SUCCESS;
2795 /* Set K1 beacon duration based on 10Mbs speed */
2796 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2800 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2801 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2803 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2806 /* LV 1G/100 Packet drop issue wa */
2807 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2811 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2812 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2818 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2819 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2820 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2821 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2829 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2830 * @hw: pointer to the HW structure
2831 * @gate: boolean set to true to gate, false to ungate
2833 * Gate/ungate the automatic PHY configuration via hardware; perform
2834 * the configuration via software instead.
2836 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2840 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2842 if (hw->mac.type < e1000_pch2lan)
2845 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2848 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2850 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2852 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2856 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2857 * @hw: pointer to the HW structure
2859 * Check the appropriate indication the MAC has finished configuring the
2860 * PHY after a software reset.
2862 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2864 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2866 DEBUGFUNC("e1000_lan_init_done_ich8lan");
2868 /* Wait for basic configuration completes before proceeding */
2870 data = E1000_READ_REG(hw, E1000_STATUS);
2871 data &= E1000_STATUS_LAN_INIT_DONE;
2873 } while ((!data) && --loop);
2875 /* If basic configuration is incomplete before the above loop
2876 * count reaches 0, loading the configuration from NVM will
2877 * leave the PHY in a bad state possibly resulting in no link.
2880 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2882 /* Clear the Init Done bit for the next init event */
2883 data = E1000_READ_REG(hw, E1000_STATUS);
2884 data &= ~E1000_STATUS_LAN_INIT_DONE;
2885 E1000_WRITE_REG(hw, E1000_STATUS, data);
2889 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2890 * @hw: pointer to the HW structure
2892 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2894 s32 ret_val = E1000_SUCCESS;
2897 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2899 if (hw->phy.ops.check_reset_block(hw))
2900 return E1000_SUCCESS;
2902 /* Allow time for h/w to get to quiescent state after reset */
2905 /* Perform any necessary post-reset workarounds */
2906 switch (hw->mac.type) {
2908 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2913 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2921 /* Clear the host wakeup bit after lcd reset */
2922 if (hw->mac.type >= e1000_pchlan) {
2923 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
2924 reg &= ~BM_WUC_HOST_WU_BIT;
2925 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2928 /* Configure the LCD with the extended configuration region in NVM */
2929 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2933 /* Configure the LCD with the OEM bits in NVM */
2934 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2936 if (hw->mac.type == e1000_pch2lan) {
2937 /* Ungate automatic PHY configuration on non-managed 82579 */
2938 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2939 E1000_ICH_FWSM_FW_VALID)) {
2941 e1000_gate_hw_phy_config_ich8lan(hw, false);
2944 /* Set EEE LPI Update Timer to 200usec */
2945 ret_val = hw->phy.ops.acquire(hw);
2948 ret_val = e1000_write_emi_reg_locked(hw,
2949 I82579_LPI_UPDATE_TIMER,
2951 hw->phy.ops.release(hw);
2958 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2959 * @hw: pointer to the HW structure
2962 * This is a function pointer entry point called by drivers
2963 * or other shared routines.
2965 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2967 s32 ret_val = E1000_SUCCESS;
2969 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2971 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2972 if ((hw->mac.type == e1000_pch2lan) &&
2973 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2974 e1000_gate_hw_phy_config_ich8lan(hw, true);
2976 ret_val = e1000_phy_hw_reset_generic(hw);
2980 return e1000_post_phy_reset_ich8lan(hw);
2984 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2985 * @hw: pointer to the HW structure
2986 * @active: true to enable LPLU, false to disable
2988 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2989 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2990 * the phy speed. This function will manually set the LPLU bit and restart
2991 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2992 * since it configures the same bit.
2994 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2999 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3000 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3005 oem_reg |= HV_OEM_BITS_LPLU;
3007 oem_reg &= ~HV_OEM_BITS_LPLU;
3009 if (!hw->phy.ops.check_reset_block(hw))
3010 oem_reg |= HV_OEM_BITS_RESTART_AN;
3012 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3016 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3017 * @hw: pointer to the HW structure
3018 * @active: true to enable LPLU, false to disable
3020 * Sets the LPLU D0 state according to the active flag. When
3021 * activating LPLU this function also disables smart speed
3022 * and vice versa. LPLU will not be activated unless the
3023 * device autonegotiation advertisement meets standards of
3024 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3025 * This is a function pointer entry point only called by
3026 * PHY setup routines.
3028 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3030 struct e1000_phy_info *phy = &hw->phy;
3032 s32 ret_val = E1000_SUCCESS;
3035 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3037 if (phy->type == e1000_phy_ife)
3038 return E1000_SUCCESS;
3040 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3043 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3044 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3046 if (phy->type != e1000_phy_igp_3)
3047 return E1000_SUCCESS;
3049 /* Call gig speed drop workaround on LPLU before accessing
3052 if (hw->mac.type == e1000_ich8lan)
3053 e1000_gig_downshift_workaround_ich8lan(hw);
3055 /* When LPLU is enabled, we should disable SmartSpeed */
3056 ret_val = phy->ops.read_reg(hw,
3057 IGP01E1000_PHY_PORT_CONFIG,
3061 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3062 ret_val = phy->ops.write_reg(hw,
3063 IGP01E1000_PHY_PORT_CONFIG,
3068 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3069 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3071 if (phy->type != e1000_phy_igp_3)
3072 return E1000_SUCCESS;
3074 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3075 * during Dx states where the power conservation is most
3076 * important. During driver activity we should enable
3077 * SmartSpeed, so performance is maintained.
3079 if (phy->smart_speed == e1000_smart_speed_on) {
3080 ret_val = phy->ops.read_reg(hw,
3081 IGP01E1000_PHY_PORT_CONFIG,
3086 data |= IGP01E1000_PSCFR_SMART_SPEED;
3087 ret_val = phy->ops.write_reg(hw,
3088 IGP01E1000_PHY_PORT_CONFIG,
3092 } else if (phy->smart_speed == e1000_smart_speed_off) {
3093 ret_val = phy->ops.read_reg(hw,
3094 IGP01E1000_PHY_PORT_CONFIG,
3099 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3100 ret_val = phy->ops.write_reg(hw,
3101 IGP01E1000_PHY_PORT_CONFIG,
3108 return E1000_SUCCESS;
3112 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3113 * @hw: pointer to the HW structure
3114 * @active: true to enable LPLU, false to disable
3116 * Sets the LPLU D3 state according to the active flag. When
3117 * activating LPLU this function also disables smart speed
3118 * and vice versa. LPLU will not be activated unless the
3119 * device autonegotiation advertisement meets standards of
3120 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3121 * This is a function pointer entry point only called by
3122 * PHY setup routines.
3124 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3126 struct e1000_phy_info *phy = &hw->phy;
3128 s32 ret_val = E1000_SUCCESS;
3131 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3133 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3136 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3137 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3139 if (phy->type != e1000_phy_igp_3)
3140 return E1000_SUCCESS;
3142 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3143 * during Dx states where the power conservation is most
3144 * important. During driver activity we should enable
3145 * SmartSpeed, so performance is maintained.
3147 if (phy->smart_speed == e1000_smart_speed_on) {
3148 ret_val = phy->ops.read_reg(hw,
3149 IGP01E1000_PHY_PORT_CONFIG,
3154 data |= IGP01E1000_PSCFR_SMART_SPEED;
3155 ret_val = phy->ops.write_reg(hw,
3156 IGP01E1000_PHY_PORT_CONFIG,
3160 } else if (phy->smart_speed == e1000_smart_speed_off) {
3161 ret_val = phy->ops.read_reg(hw,
3162 IGP01E1000_PHY_PORT_CONFIG,
3167 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3168 ret_val = phy->ops.write_reg(hw,
3169 IGP01E1000_PHY_PORT_CONFIG,
3174 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3175 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3176 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3177 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3178 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3180 if (phy->type != e1000_phy_igp_3)
3181 return E1000_SUCCESS;
3183 /* Call gig speed drop workaround on LPLU before accessing
3186 if (hw->mac.type == e1000_ich8lan)
3187 e1000_gig_downshift_workaround_ich8lan(hw);
3189 /* When LPLU is enabled, we should disable SmartSpeed */
3190 ret_val = phy->ops.read_reg(hw,
3191 IGP01E1000_PHY_PORT_CONFIG,
3196 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3197 ret_val = phy->ops.write_reg(hw,
3198 IGP01E1000_PHY_PORT_CONFIG,
3206 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3207 * @hw: pointer to the HW structure
3208 * @bank: pointer to the variable that returns the active bank
3210 * Reads signature byte from the NVM using the flash access registers.
3211 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3213 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3216 struct e1000_nvm_info *nvm = &hw->nvm;
3217 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3218 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3223 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3225 switch (hw->mac.type) {
3228 eecd = E1000_READ_REG(hw, E1000_EECD);
3229 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3230 E1000_EECD_SEC1VAL_VALID_MASK) {
3231 if (eecd & E1000_EECD_SEC1VAL)
3236 return E1000_SUCCESS;
3238 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3241 /* set bank to 0 in case flash read fails */
3245 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3249 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3250 E1000_ICH_NVM_SIG_VALUE) {
3252 return E1000_SUCCESS;
3256 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3261 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3262 E1000_ICH_NVM_SIG_VALUE) {
3264 return E1000_SUCCESS;
3267 DEBUGOUT("ERROR: No valid NVM bank present\n");
3268 return -E1000_ERR_NVM;
3273 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3274 * @hw: pointer to the HW structure
3275 * @offset: The offset (in bytes) of the word(s) to read.
3276 * @words: Size of data to read in words
3277 * @data: Pointer to the word(s) to read at offset.
3279 * Reads a word(s) from the NVM using the flash access registers.
3281 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3284 struct e1000_nvm_info *nvm = &hw->nvm;
3285 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3287 s32 ret_val = E1000_SUCCESS;
3291 DEBUGFUNC("e1000_read_nvm_ich8lan");
3293 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3295 DEBUGOUT("nvm parameter(s) out of bounds\n");
3296 ret_val = -E1000_ERR_NVM;
3300 nvm->ops.acquire(hw);
3302 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3303 if (ret_val != E1000_SUCCESS) {
3304 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3308 act_offset = (bank) ? nvm->flash_bank_size : 0;
3309 act_offset += offset;
3311 ret_val = E1000_SUCCESS;
3312 for (i = 0; i < words; i++) {
3313 if (dev_spec->shadow_ram[offset+i].modified) {
3314 data[i] = dev_spec->shadow_ram[offset+i].value;
3316 ret_val = e1000_read_flash_word_ich8lan(hw,
3325 nvm->ops.release(hw);
3329 DEBUGOUT1("NVM read error: %d\n", ret_val);
3335 * e1000_flash_cycle_init_ich8lan - Initialize flash
3336 * @hw: pointer to the HW structure
3338 * This function does initial flash setup so that a new read/write/erase cycle
3341 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3343 union ich8_hws_flash_status hsfsts;
3344 s32 ret_val = -E1000_ERR_NVM;
3346 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3348 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3350 /* Check if the flash descriptor is valid */
3351 if (!hsfsts.hsf_status.fldesvalid) {
3352 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3353 return -E1000_ERR_NVM;
3356 /* Clear FCERR and DAEL in hw status by writing 1 */
3357 hsfsts.hsf_status.flcerr = 1;
3358 hsfsts.hsf_status.dael = 1;
3359 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3361 /* Either we should have a hardware SPI cycle in progress
3362 * bit to check against, in order to start a new cycle or
3363 * FDONE bit should be changed in the hardware so that it
3364 * is 1 after hardware reset, which can then be used as an
3365 * indication whether a cycle is in progress or has been
3369 if (!hsfsts.hsf_status.flcinprog) {
3370 /* There is no cycle running at present,
3371 * so we can start a cycle.
3372 * Begin by setting Flash Cycle Done.
3374 hsfsts.hsf_status.flcdone = 1;
3375 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3376 ret_val = E1000_SUCCESS;
3380 /* Otherwise poll for sometime so the current
3381 * cycle has a chance to end before giving up.
3383 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3384 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3386 if (!hsfsts.hsf_status.flcinprog) {
3387 ret_val = E1000_SUCCESS;
3392 if (ret_val == E1000_SUCCESS) {
3393 /* Successful in waiting for previous cycle to timeout,
3394 * now set the Flash Cycle Done.
3396 hsfsts.hsf_status.flcdone = 1;
3397 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3400 DEBUGOUT("Flash controller busy, cannot get access\n");
3408 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3409 * @hw: pointer to the HW structure
3410 * @timeout: maximum time to wait for completion
3412 * This function starts a flash cycle and waits for its completion.
3414 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3416 union ich8_hws_flash_ctrl hsflctl;
3417 union ich8_hws_flash_status hsfsts;
3420 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3422 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3423 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3424 hsflctl.hsf_ctrl.flcgo = 1;
3426 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3428 /* wait till FDONE bit is set to 1 */
3430 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3431 if (hsfsts.hsf_status.flcdone)
3434 } while (i++ < timeout);
3436 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3437 return E1000_SUCCESS;
3439 return -E1000_ERR_NVM;
3443 * e1000_read_flash_word_ich8lan - Read word from flash
3444 * @hw: pointer to the HW structure
3445 * @offset: offset to data location
3446 * @data: pointer to the location for storing the data
3448 * Reads the flash word at offset into data. Offset is converted
3449 * to bytes before read.
3451 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3454 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3457 return -E1000_ERR_NVM;
3459 /* Must convert offset into bytes. */
3462 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3466 * e1000_read_flash_byte_ich8lan - Read byte from flash
3467 * @hw: pointer to the HW structure
3468 * @offset: The offset of the byte to read.
3469 * @data: Pointer to a byte to store the value read.
3471 * Reads a single byte from the NVM using the flash access registers.
3473 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3479 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3486 return E1000_SUCCESS;
3490 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3491 * @hw: pointer to the HW structure
3492 * @offset: The offset (in bytes) of the byte or word to read.
3493 * @size: Size of data to read, 1=byte 2=word
3494 * @data: Pointer to the word to store the value read.
3496 * Reads a byte or word from the NVM using the flash access registers.
3498 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3501 union ich8_hws_flash_status hsfsts;
3502 union ich8_hws_flash_ctrl hsflctl;
3503 u32 flash_linear_addr;
3505 s32 ret_val = -E1000_ERR_NVM;
3508 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3510 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3511 return -E1000_ERR_NVM;
3512 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3513 hw->nvm.flash_base_addr);
3518 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3519 if (ret_val != E1000_SUCCESS)
3521 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3523 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3524 hsflctl.hsf_ctrl.fldbcount = size - 1;
3525 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3526 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3527 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3529 ret_val = e1000_flash_cycle_ich8lan(hw,
3530 ICH_FLASH_READ_COMMAND_TIMEOUT);
3532 /* Check if FCERR is set to 1, if set to 1, clear it
3533 * and try the whole sequence a few more times, else
3534 * read in (shift in) the Flash Data0, the order is
3535 * least significant byte first msb to lsb
3537 if (ret_val == E1000_SUCCESS) {
3538 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3540 *data = (u8)(flash_data & 0x000000FF);
3542 *data = (u16)(flash_data & 0x0000FFFF);
3545 /* If we've gotten here, then things are probably
3546 * completely hosed, but if the error condition is
3547 * detected, it won't hurt to give it another try...
3548 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3550 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3552 if (hsfsts.hsf_status.flcerr) {
3553 /* Repeat for some time before giving up. */
3555 } else if (!hsfsts.hsf_status.flcdone) {
3556 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3560 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3567 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3568 * @hw: pointer to the HW structure
3569 * @offset: The offset (in bytes) of the word(s) to write.
3570 * @words: Size of data to write in words
3571 * @data: Pointer to the word(s) to write at offset.
3573 * Writes a byte or word to the NVM using the flash access registers.
3575 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3578 struct e1000_nvm_info *nvm = &hw->nvm;
3579 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3582 DEBUGFUNC("e1000_write_nvm_ich8lan");
3584 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3586 DEBUGOUT("nvm parameter(s) out of bounds\n");
3587 return -E1000_ERR_NVM;
3590 nvm->ops.acquire(hw);
3592 for (i = 0; i < words; i++) {
3593 dev_spec->shadow_ram[offset+i].modified = true;
3594 dev_spec->shadow_ram[offset+i].value = data[i];
3597 nvm->ops.release(hw);
3599 return E1000_SUCCESS;
3603 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3604 * @hw: pointer to the HW structure
3606 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3607 * which writes the checksum to the shadow ram. The changes in the shadow
3608 * ram are then committed to the EEPROM by processing each bank at a time
3609 * checking for the modified bit and writing only the pending changes.
3610 * After a successful commit, the shadow ram is cleared and is ready for
3613 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3615 struct e1000_nvm_info *nvm = &hw->nvm;
3616 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3617 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3621 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3623 ret_val = e1000_update_nvm_checksum_generic(hw);
3627 if (nvm->type != e1000_nvm_flash_sw)
3630 nvm->ops.acquire(hw);
3632 /* We're writing to the opposite bank so if we're on bank 1,
3633 * write to bank 0 etc. We also need to erase the segment that
3634 * is going to be written
3636 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3637 if (ret_val != E1000_SUCCESS) {
3638 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3643 new_bank_offset = nvm->flash_bank_size;
3644 old_bank_offset = 0;
3645 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3649 old_bank_offset = nvm->flash_bank_size;
3650 new_bank_offset = 0;
3651 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3655 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3656 if (dev_spec->shadow_ram[i].modified) {
3657 data = dev_spec->shadow_ram[i].value;
3659 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3665 /* If the word is 0x13, then make sure the signature bits
3666 * (15:14) are 11b until the commit has completed.
3667 * This will allow us to write 10b which indicates the
3668 * signature is valid. We want to do this after the write
3669 * has completed so that we don't mark the segment valid
3670 * while the write is still in progress
3672 if (i == E1000_ICH_NVM_SIG_WORD)
3673 data |= E1000_ICH_NVM_SIG_MASK;
3675 /* Convert offset to bytes. */
3676 act_offset = (i + new_bank_offset) << 1;
3680 /* Write the bytes to the new bank. */
3681 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3688 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3695 /* Don't bother writing the segment valid bits if sector
3696 * programming failed.
3699 DEBUGOUT("Flash commit failed.\n");
3703 /* Finally validate the new segment by setting bit 15:14
3704 * to 10b in word 0x13 , this can be done without an
3705 * erase as well since these bits are 11 to start with
3706 * and we need to change bit 14 to 0b
3708 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3709 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3714 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
3719 /* And invalidate the previously valid segment by setting
3720 * its signature word (0x13) high_byte to 0b. This can be
3721 * done without an erase because flash erase sets all bits
3722 * to 1's. We can write 1's to 0's without an erase
3724 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3726 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3731 /* Great! Everything worked, we can now clear the cached entries. */
3732 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3733 dev_spec->shadow_ram[i].modified = false;
3734 dev_spec->shadow_ram[i].value = 0xFFFF;
3738 nvm->ops.release(hw);
3740 /* Reload the EEPROM, or else modifications will not appear
3741 * until after the next adapter reset.
3744 nvm->ops.reload(hw);
3750 DEBUGOUT1("NVM update error: %d\n", ret_val);
3756 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3757 * @hw: pointer to the HW structure
3759 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3760 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3761 * calculated, in which case we need to calculate the checksum and set bit 6.
3763 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3768 u16 valid_csum_mask;
3770 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3772 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3773 * the checksum needs to be fixed. This bit is an indication that
3774 * the NVM was prepared by OEM software and did not calculate
3775 * the checksum...a likely scenario.
3777 switch (hw->mac.type) {
3780 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3783 word = NVM_FUTURE_INIT_WORD1;
3784 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3788 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3792 if (!(data & valid_csum_mask)) {
3793 data |= valid_csum_mask;
3794 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3797 ret_val = hw->nvm.ops.update(hw);
3802 return e1000_validate_nvm_checksum_generic(hw);
3806 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3807 * @hw: pointer to the HW structure
3808 * @offset: The offset (in bytes) of the byte/word to read.
3809 * @size: Size of data to read, 1=byte 2=word
3810 * @data: The byte(s) to write to the NVM.
3812 * Writes one/two bytes to the NVM using the flash access registers.
3814 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3817 union ich8_hws_flash_status hsfsts;
3818 union ich8_hws_flash_ctrl hsflctl;
3819 u32 flash_linear_addr;
3824 DEBUGFUNC("e1000_write_ich8_data");
3826 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3827 return -E1000_ERR_NVM;
3829 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3830 hw->nvm.flash_base_addr);
3835 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3836 if (ret_val != E1000_SUCCESS)
3838 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3840 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3841 hsflctl.hsf_ctrl.fldbcount = size - 1;
3842 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3843 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3845 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3848 flash_data = (u32)data & 0x00FF;
3850 flash_data = (u32)data;
3852 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3854 /* check if FCERR is set to 1 , if set to 1, clear it
3855 * and try the whole sequence a few more times else done
3858 e1000_flash_cycle_ich8lan(hw,
3859 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3860 if (ret_val == E1000_SUCCESS)
3863 /* If we're here, then things are most likely
3864 * completely hosed, but if the error condition
3865 * is detected, it won't hurt to give it another
3866 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3868 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3869 if (hsfsts.hsf_status.flcerr)
3870 /* Repeat for some time before giving up. */
3872 if (!hsfsts.hsf_status.flcdone) {
3873 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3876 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3883 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3884 * @hw: pointer to the HW structure
3885 * @offset: The index of the byte to read.
3886 * @data: The byte to write to the NVM.
3888 * Writes a single byte to the NVM using the flash access registers.
3890 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3893 u16 word = (u16)data;
3895 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3897 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3903 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3904 * @hw: pointer to the HW structure
3905 * @offset: The offset of the byte to write.
3906 * @byte: The byte to write to the NVM.
3908 * Writes a single byte to the NVM using the flash access registers.
3909 * Goes through a retry algorithm before giving up.
3911 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3912 u32 offset, u8 byte)
3915 u16 program_retries;
3917 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3919 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3923 for (program_retries = 0; program_retries < 100; program_retries++) {
3924 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3926 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3927 if (ret_val == E1000_SUCCESS)
3930 if (program_retries == 100)
3931 return -E1000_ERR_NVM;
3933 return E1000_SUCCESS;
3937 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3938 * @hw: pointer to the HW structure
3939 * @bank: 0 for first bank, 1 for second bank, etc.
3941 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3942 * bank N is 4096 * N + flash_reg_addr.
3944 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3946 struct e1000_nvm_info *nvm = &hw->nvm;
3947 union ich8_hws_flash_status hsfsts;
3948 union ich8_hws_flash_ctrl hsflctl;
3949 u32 flash_linear_addr;
3950 /* bank size is in 16bit words - adjust to bytes */
3951 u32 flash_bank_size = nvm->flash_bank_size * 2;
3954 s32 j, iteration, sector_size;
3956 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3958 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3960 /* Determine HW Sector size: Read BERASE bits of hw flash status
3962 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3963 * consecutive sectors. The start index for the nth Hw sector
3964 * can be calculated as = bank * 4096 + n * 256
3965 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3966 * The start index for the nth Hw sector can be calculated
3968 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3969 * (ich9 only, otherwise error condition)
3970 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3972 switch (hsfsts.hsf_status.berasesz) {
3974 /* Hw sector size 256 */
3975 sector_size = ICH_FLASH_SEG_SIZE_256;
3976 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3979 sector_size = ICH_FLASH_SEG_SIZE_4K;
3983 sector_size = ICH_FLASH_SEG_SIZE_8K;
3987 sector_size = ICH_FLASH_SEG_SIZE_64K;
3991 return -E1000_ERR_NVM;
3994 /* Start with the base address, then add the sector offset. */
3995 flash_linear_addr = hw->nvm.flash_base_addr;
3996 flash_linear_addr += (bank) ? flash_bank_size : 0;
3998 for (j = 0; j < iteration; j++) {
4000 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4003 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4007 /* Write a value 11 (block Erase) in Flash
4008 * Cycle field in hw flash control
4011 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4013 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4014 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4017 /* Write the last 24 bits of an index within the
4018 * block into Flash Linear address field in Flash
4021 flash_linear_addr += (j * sector_size);
4022 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4025 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4026 if (ret_val == E1000_SUCCESS)
4029 /* Check if FCERR is set to 1. If 1,
4030 * clear it and try the whole sequence
4031 * a few more times else Done
4033 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4035 if (hsfsts.hsf_status.flcerr)
4036 /* repeat for some time before giving up */
4038 else if (!hsfsts.hsf_status.flcdone)
4040 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4043 return E1000_SUCCESS;
4047 * e1000_valid_led_default_ich8lan - Set the default LED settings
4048 * @hw: pointer to the HW structure
4049 * @data: Pointer to the LED settings
4051 * Reads the LED default settings from the NVM to data. If the NVM LED
4052 * settings is all 0's or F's, set the LED default to a valid LED default
4055 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4059 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4061 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4063 DEBUGOUT("NVM Read Error\n");
4067 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4068 *data = ID_LED_DEFAULT_ICH8LAN;
4070 return E1000_SUCCESS;
4074 * e1000_id_led_init_pchlan - store LED configurations
4075 * @hw: pointer to the HW structure
4077 * PCH does not control LEDs via the LEDCTL register, rather it uses
4078 * the PHY LED configuration register.
4080 * PCH also does not have an "always on" or "always off" mode which
4081 * complicates the ID feature. Instead of using the "on" mode to indicate
4082 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4083 * use "link_up" mode. The LEDs will still ID on request if there is no
4084 * link based on logic in e1000_led_[on|off]_pchlan().
4086 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4088 struct e1000_mac_info *mac = &hw->mac;
4090 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4091 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4092 u16 data, i, temp, shift;
4094 DEBUGFUNC("e1000_id_led_init_pchlan");
4096 /* Get default ID LED modes */
4097 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4101 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4102 mac->ledctl_mode1 = mac->ledctl_default;
4103 mac->ledctl_mode2 = mac->ledctl_default;
4105 for (i = 0; i < 4; i++) {
4106 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4109 case ID_LED_ON1_DEF2:
4110 case ID_LED_ON1_ON2:
4111 case ID_LED_ON1_OFF2:
4112 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4113 mac->ledctl_mode1 |= (ledctl_on << shift);
4115 case ID_LED_OFF1_DEF2:
4116 case ID_LED_OFF1_ON2:
4117 case ID_LED_OFF1_OFF2:
4118 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4119 mac->ledctl_mode1 |= (ledctl_off << shift);
4126 case ID_LED_DEF1_ON2:
4127 case ID_LED_ON1_ON2:
4128 case ID_LED_OFF1_ON2:
4129 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4130 mac->ledctl_mode2 |= (ledctl_on << shift);
4132 case ID_LED_DEF1_OFF2:
4133 case ID_LED_ON1_OFF2:
4134 case ID_LED_OFF1_OFF2:
4135 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4136 mac->ledctl_mode2 |= (ledctl_off << shift);
4144 return E1000_SUCCESS;
4148 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4149 * @hw: pointer to the HW structure
4151 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4152 * register, so the the bus width is hard coded.
4154 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4156 struct e1000_bus_info *bus = &hw->bus;
4159 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4161 ret_val = e1000_get_bus_info_pcie_generic(hw);
4163 /* ICH devices are "PCI Express"-ish. They have
4164 * a configuration space, but do not contain
4165 * PCI Express Capability registers, so bus width
4166 * must be hardcoded.
4168 if (bus->width == e1000_bus_width_unknown)
4169 bus->width = e1000_bus_width_pcie_x1;
4175 * e1000_reset_hw_ich8lan - Reset the hardware
4176 * @hw: pointer to the HW structure
4178 * Does a full reset of the hardware which includes a reset of the PHY and
4181 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4183 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4188 DEBUGFUNC("e1000_reset_hw_ich8lan");
4190 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4191 * on the last TLP read/write transaction when MAC is reset.
4193 ret_val = e1000_disable_pcie_master_generic(hw);
4195 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4197 DEBUGOUT("Masking off all interrupts\n");
4198 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4200 /* Disable the Transmit and Receive units. Then delay to allow
4201 * any pending transactions to complete before we hit the MAC
4202 * with the global reset.
4204 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4205 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4206 E1000_WRITE_FLUSH(hw);
4210 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4211 if (hw->mac.type == e1000_ich8lan) {
4212 /* Set Tx and Rx buffer allocation to 8k apiece. */
4213 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4214 /* Set Packet Buffer Size to 16k. */
4215 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4218 if (hw->mac.type == e1000_pchlan) {
4219 /* Save the NVM K1 bit setting*/
4220 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4224 if (kum_cfg & E1000_NVM_K1_ENABLE)
4225 dev_spec->nvm_k1_enabled = true;
4227 dev_spec->nvm_k1_enabled = false;
4230 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4232 if (!hw->phy.ops.check_reset_block(hw)) {
4233 /* Full-chip reset requires MAC and PHY reset at the same
4234 * time to make sure the interface between MAC and the
4235 * external PHY is reset.
4237 ctrl |= E1000_CTRL_PHY_RST;
4239 /* Gate automatic PHY configuration by hardware on
4242 if ((hw->mac.type == e1000_pch2lan) &&
4243 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4244 e1000_gate_hw_phy_config_ich8lan(hw, true);
4246 ret_val = e1000_acquire_swflag_ich8lan(hw);
4247 DEBUGOUT("Issuing a global reset to ich8lan\n");
4248 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4249 /* cannot issue a flush here because it hangs the hardware */
4252 /* Set Phy Config Counter to 50msec */
4253 if (hw->mac.type == e1000_pch2lan) {
4254 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4255 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4256 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4257 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4261 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4263 if (ctrl & E1000_CTRL_PHY_RST) {
4264 ret_val = hw->phy.ops.get_cfg_done(hw);
4268 ret_val = e1000_post_phy_reset_ich8lan(hw);
4273 /* For PCH, this write will make sure that any noise
4274 * will be detected as a CRC error and be dropped rather than show up
4275 * as a bad packet to the DMA engine.
4277 if (hw->mac.type == e1000_pchlan)
4278 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4280 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4281 E1000_READ_REG(hw, E1000_ICR);
4283 reg = E1000_READ_REG(hw, E1000_KABGTXD);
4284 reg |= E1000_KABGTXD_BGSQLBIAS;
4285 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4287 return E1000_SUCCESS;
4291 * e1000_init_hw_ich8lan - Initialize the hardware
4292 * @hw: pointer to the HW structure
4294 * Prepares the hardware for transmit and receive by doing the following:
4295 * - initialize hardware bits
4296 * - initialize LED identification
4297 * - setup receive address registers
4298 * - setup flow control
4299 * - setup transmit descriptors
4300 * - clear statistics
4302 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4304 struct e1000_mac_info *mac = &hw->mac;
4305 u32 ctrl_ext, txdctl, snoop;
4309 DEBUGFUNC("e1000_init_hw_ich8lan");
4311 e1000_initialize_hw_bits_ich8lan(hw);
4313 /* Initialize identification LED */
4314 ret_val = mac->ops.id_led_init(hw);
4315 /* An error is not fatal and we should not stop init due to this */
4317 DEBUGOUT("Error initializing identification LED\n");
4319 /* Setup the receive address. */
4320 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4322 /* Zero out the Multicast HASH table */
4323 DEBUGOUT("Zeroing the MTA\n");
4324 for (i = 0; i < mac->mta_reg_count; i++)
4325 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4327 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4328 * the ME. Disable wakeup by clearing the host wakeup bit.
4329 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4331 if (hw->phy.type == e1000_phy_82578) {
4332 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4333 i &= ~BM_WUC_HOST_WU_BIT;
4334 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4335 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4340 /* Setup link and flow control */
4341 ret_val = mac->ops.setup_link(hw);
4343 /* Set the transmit descriptor write-back policy for both queues */
4344 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4345 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4346 E1000_TXDCTL_FULL_TX_DESC_WB);
4347 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4348 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4349 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4350 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4351 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4352 E1000_TXDCTL_FULL_TX_DESC_WB);
4353 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4354 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4355 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4357 /* ICH8 has opposite polarity of no_snoop bits.
4358 * By default, we should use snoop behavior.
4360 if (mac->type == e1000_ich8lan)
4361 snoop = PCIE_ICH8_SNOOP_ALL;
4363 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4364 e1000_set_pcie_no_snoop_generic(hw, snoop);
4366 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4367 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4368 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4370 /* Clear all of the statistics registers (clear on read). It is
4371 * important that we do this after we have tried to establish link
4372 * because the symbol error count will increment wildly if there
4375 e1000_clear_hw_cntrs_ich8lan(hw);
4381 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4382 * @hw: pointer to the HW structure
4384 * Sets/Clears required hardware bits necessary for correctly setting up the
4385 * hardware for transmit and receive.
4387 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4391 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4393 /* Extended Device Control */
4394 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4396 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4397 if (hw->mac.type >= e1000_pchlan)
4398 reg |= E1000_CTRL_EXT_PHYPDEN;
4399 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4401 /* Transmit Descriptor Control 0 */
4402 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4404 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4406 /* Transmit Descriptor Control 1 */
4407 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4409 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4411 /* Transmit Arbitration Control 0 */
4412 reg = E1000_READ_REG(hw, E1000_TARC(0));
4413 if (hw->mac.type == e1000_ich8lan)
4414 reg |= (1 << 28) | (1 << 29);
4415 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4416 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4418 /* Transmit Arbitration Control 1 */
4419 reg = E1000_READ_REG(hw, E1000_TARC(1));
4420 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4424 reg |= (1 << 24) | (1 << 26) | (1 << 30);
4425 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4428 if (hw->mac.type == e1000_ich8lan) {
4429 reg = E1000_READ_REG(hw, E1000_STATUS);
4431 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4434 /* work-around descriptor data corruption issue during nfs v2 udp
4435 * traffic, just disable the nfs filtering capability
4437 reg = E1000_READ_REG(hw, E1000_RFCTL);
4438 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4440 /* Disable IPv6 extension header parsing because some malformed
4441 * IPv6 headers can hang the Rx.
4443 if (hw->mac.type == e1000_ich8lan)
4444 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4445 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4447 /* Enable ECC on Lynxpoint */
4448 if (hw->mac.type == e1000_pch_lpt) {
4449 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4450 reg |= E1000_PBECCSTS_ECC_ENABLE;
4451 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4453 reg = E1000_READ_REG(hw, E1000_CTRL);
4454 reg |= E1000_CTRL_MEHE;
4455 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4462 * e1000_setup_link_ich8lan - Setup flow control and link settings
4463 * @hw: pointer to the HW structure
4465 * Determines which flow control settings to use, then configures flow
4466 * control. Calls the appropriate media-specific link configuration
4467 * function. Assuming the adapter has a valid link partner, a valid link
4468 * should be established. Assumes the hardware has previously been reset
4469 * and the transmitter and receiver are not enabled.
4471 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4475 DEBUGFUNC("e1000_setup_link_ich8lan");
4477 if (hw->phy.ops.check_reset_block(hw))
4478 return E1000_SUCCESS;
4480 /* ICH parts do not have a word in the NVM to determine
4481 * the default flow control setting, so we explicitly
4484 if (hw->fc.requested_mode == e1000_fc_default)
4485 hw->fc.requested_mode = e1000_fc_full;
4487 /* Save off the requested flow control mode for use later. Depending
4488 * on the link partner's capabilities, we may or may not use this mode.
4490 hw->fc.current_mode = hw->fc.requested_mode;
4492 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4493 hw->fc.current_mode);
4495 /* Continue to configure the copper link. */
4496 ret_val = hw->mac.ops.setup_physical_interface(hw);
4500 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4501 if ((hw->phy.type == e1000_phy_82578) ||
4502 (hw->phy.type == e1000_phy_82579) ||
4503 (hw->phy.type == e1000_phy_i217) ||
4504 (hw->phy.type == e1000_phy_82577)) {
4505 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4507 ret_val = hw->phy.ops.write_reg(hw,
4508 PHY_REG(BM_PORT_CTRL_PAGE, 27),
4514 return e1000_set_fc_watermarks_generic(hw);
4518 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4519 * @hw: pointer to the HW structure
4521 * Configures the kumeran interface to the PHY to wait the appropriate time
4522 * when polling the PHY, then call the generic setup_copper_link to finish
4523 * configuring the copper link.
4525 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4531 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4533 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4534 ctrl |= E1000_CTRL_SLU;
4535 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4536 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4538 /* Set the mac to wait the maximum time between each iteration
4539 * and increase the max iterations when polling the phy;
4540 * this fixes erroneous timeouts at 10Mbps.
4542 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4546 ret_val = e1000_read_kmrn_reg_generic(hw,
4547 E1000_KMRNCTRLSTA_INBAND_PARAM,
4552 ret_val = e1000_write_kmrn_reg_generic(hw,
4553 E1000_KMRNCTRLSTA_INBAND_PARAM,
4558 switch (hw->phy.type) {
4559 case e1000_phy_igp_3:
4560 ret_val = e1000_copper_link_setup_igp(hw);
4565 case e1000_phy_82578:
4566 ret_val = e1000_copper_link_setup_m88(hw);
4570 case e1000_phy_82577:
4571 case e1000_phy_82579:
4572 ret_val = e1000_copper_link_setup_82577(hw);
4577 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4582 reg_data &= ~IFE_PMC_AUTO_MDIX;
4584 switch (hw->phy.mdix) {
4586 reg_data &= ~IFE_PMC_FORCE_MDIX;
4589 reg_data |= IFE_PMC_FORCE_MDIX;
4593 reg_data |= IFE_PMC_AUTO_MDIX;
4596 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4605 return e1000_setup_copper_link_generic(hw);
4609 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4610 * @hw: pointer to the HW structure
4612 * Calls the PHY specific link setup function and then calls the
4613 * generic setup_copper_link to finish configuring the link for
4614 * Lynxpoint PCH devices
4616 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4621 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4623 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4624 ctrl |= E1000_CTRL_SLU;
4625 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4626 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4628 ret_val = e1000_copper_link_setup_82577(hw);
4632 return e1000_setup_copper_link_generic(hw);
4636 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4637 * @hw: pointer to the HW structure
4638 * @speed: pointer to store current link speed
4639 * @duplex: pointer to store the current link duplex
4641 * Calls the generic get_speed_and_duplex to retrieve the current link
4642 * information and then calls the Kumeran lock loss workaround for links at
4645 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4650 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4652 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4656 if ((hw->mac.type == e1000_ich8lan) &&
4657 (hw->phy.type == e1000_phy_igp_3) &&
4658 (*speed == SPEED_1000)) {
4659 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4666 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4667 * @hw: pointer to the HW structure
4669 * Work-around for 82566 Kumeran PCS lock loss:
4670 * On link status change (i.e. PCI reset, speed change) and link is up and
4672 * 0) if workaround is optionally disabled do nothing
4673 * 1) wait 1ms for Kumeran link to come up
4674 * 2) check Kumeran Diagnostic register PCS lock loss bit
4675 * 3) if not set the link is locked (all is good), otherwise...
4677 * 5) repeat up to 10 times
4678 * Note: this is only called for IGP3 copper when speed is 1gb.
4680 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4682 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4688 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4690 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4691 return E1000_SUCCESS;
4693 /* Make sure link is up before proceeding. If not just return.
4694 * Attempting this while link is negotiating fouled up link
4697 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4699 return E1000_SUCCESS;
4701 for (i = 0; i < 10; i++) {
4702 /* read once to clear */
4703 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4706 /* and again to get new status */
4707 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4711 /* check for PCS lock */
4712 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4713 return E1000_SUCCESS;
4715 /* Issue PHY reset */
4716 hw->phy.ops.reset(hw);
4719 /* Disable GigE link negotiation */
4720 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4721 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4722 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4723 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4725 /* Call gig speed drop workaround on Gig disable before accessing
4728 e1000_gig_downshift_workaround_ich8lan(hw);
4730 /* unable to acquire PCS lock */
4731 return -E1000_ERR_PHY;
4735 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4736 * @hw: pointer to the HW structure
4737 * @state: boolean value used to set the current Kumeran workaround state
4739 * If ICH8, set the current Kumeran workaround state (enabled - true
4740 * /disabled - false).
4742 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4745 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4747 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4749 if (hw->mac.type != e1000_ich8lan) {
4750 DEBUGOUT("Workaround applies to ICH8 only.\n");
4754 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4760 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4761 * @hw: pointer to the HW structure
4763 * Workaround for 82566 power-down on D3 entry:
4764 * 1) disable gigabit link
4765 * 2) write VR power-down enable
4767 * Continue if successful, else issue LCD reset and repeat
4769 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4775 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4777 if (hw->phy.type != e1000_phy_igp_3)
4780 /* Try the workaround twice (if needed) */
4783 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4784 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4785 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4786 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4788 /* Call gig speed drop workaround on Gig disable before
4789 * accessing any PHY registers
4791 if (hw->mac.type == e1000_ich8lan)
4792 e1000_gig_downshift_workaround_ich8lan(hw);
4794 /* Write VR power-down enable */
4795 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4796 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4797 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4798 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4800 /* Read it back and test */
4801 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4802 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4803 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4806 /* Issue PHY reset and repeat at most one more time */
4807 reg = E1000_READ_REG(hw, E1000_CTRL);
4808 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4814 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4815 * @hw: pointer to the HW structure
4817 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4818 * LPLU, Gig disable, MDIC PHY reset):
4819 * 1) Set Kumeran Near-end loopback
4820 * 2) Clear Kumeran Near-end loopback
4821 * Should only be called for ICH8[m] devices with any 1G Phy.
4823 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4828 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4830 if ((hw->mac.type != e1000_ich8lan) ||
4831 (hw->phy.type == e1000_phy_ife))
4834 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4838 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4839 ret_val = e1000_write_kmrn_reg_generic(hw,
4840 E1000_KMRNCTRLSTA_DIAG_OFFSET,
4844 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4845 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4850 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4851 * @hw: pointer to the HW structure
4853 * During S0 to Sx transition, it is possible the link remains at gig
4854 * instead of negotiating to a lower speed. Before going to Sx, set
4855 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4856 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4857 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4858 * needs to be written.
4859 * Parts that support (and are linked to a partner which support) EEE in
4860 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4861 * than 10Mbps w/o EEE.
4863 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4865 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4869 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4871 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4872 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4874 if (hw->phy.type == e1000_phy_i217) {
4875 u16 phy_reg, device_id = hw->device_id;
4877 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4878 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4879 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4880 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4881 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4883 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4884 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4887 ret_val = hw->phy.ops.acquire(hw);
4891 if (!dev_spec->eee_disable) {
4895 e1000_read_emi_reg_locked(hw,
4896 I217_EEE_ADVERTISEMENT,
4901 /* Disable LPLU if both link partners support 100BaseT
4902 * EEE and 100Full is advertised on both ends of the
4903 * link, and enable Auto Enable LPI since there will
4904 * be no driver to enable LPI while in Sx.
4906 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4907 (dev_spec->eee_lp_ability &
4908 I82579_EEE_100_SUPPORTED) &&
4909 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4910 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4911 E1000_PHY_CTRL_NOND0A_LPLU);
4913 /* Set Auto Enable LPI after link up */
4914 hw->phy.ops.read_reg_locked(hw,
4917 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4918 hw->phy.ops.write_reg_locked(hw,
4924 /* For i217 Intel Rapid Start Technology support,
4925 * when the system is going into Sx and no manageability engine
4926 * is present, the driver must configure proxy to reset only on
4927 * power good. LPI (Low Power Idle) state must also reset only
4928 * on power good, as well as the MTA (Multicast table array).
4929 * The SMBus release must also be disabled on LCD reset.
4931 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4932 E1000_ICH_FWSM_FW_VALID)) {
4933 /* Enable proxy to reset only on power good. */
4934 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4936 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4937 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4940 /* Set bit enable LPI (EEE) to reset only on
4943 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4944 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4945 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4947 /* Disable the SMB release on LCD reset. */
4948 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4949 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4950 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4953 /* Enable MTA to reset for Intel Rapid Start Technology
4956 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4957 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4958 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4961 hw->phy.ops.release(hw);
4964 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4966 if (hw->mac.type == e1000_ich8lan)
4967 e1000_gig_downshift_workaround_ich8lan(hw);
4969 if (hw->mac.type >= e1000_pchlan) {
4970 e1000_oem_bits_config_ich8lan(hw, false);
4972 /* Reset PHY to activate OEM bits on 82577/8 */
4973 if (hw->mac.type == e1000_pchlan)
4974 e1000_phy_hw_reset_generic(hw);
4976 ret_val = hw->phy.ops.acquire(hw);
4979 e1000_write_smbus_addr(hw);
4980 hw->phy.ops.release(hw);
4987 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4988 * @hw: pointer to the HW structure
4990 * During Sx to S0 transitions on non-managed devices or managed devices
4991 * on which PHY resets are not blocked, if the PHY registers cannot be
4992 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4994 * On i217, setup Intel Rapid Start Technology.
4996 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5000 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5001 if (hw->mac.type < e1000_pch2lan)
5002 return E1000_SUCCESS;
5004 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5006 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5010 /* For i217 Intel Rapid Start Technology support when the system
5011 * is transitioning from Sx and no manageability engine is present
5012 * configure SMBus to restore on reset, disable proxy, and enable
5013 * the reset on MTA (Multicast table array).
5015 if (hw->phy.type == e1000_phy_i217) {
5018 ret_val = hw->phy.ops.acquire(hw);
5020 DEBUGOUT("Failed to setup iRST\n");
5024 /* Clear Auto Enable LPI after link up */
5025 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5026 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5027 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5029 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5030 E1000_ICH_FWSM_FW_VALID)) {
5031 /* Restore clear on SMB if no manageability engine
5034 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5038 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5039 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5042 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5044 /* Enable reset on MTA */
5045 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5049 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5050 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5053 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5054 hw->phy.ops.release(hw);
5057 return E1000_SUCCESS;
5061 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5062 * @hw: pointer to the HW structure
5064 * Return the LED back to the default configuration.
5066 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5068 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5070 if (hw->phy.type == e1000_phy_ife)
5071 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5074 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5075 return E1000_SUCCESS;
5079 * e1000_led_on_ich8lan - Turn LEDs on
5080 * @hw: pointer to the HW structure
5084 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5086 DEBUGFUNC("e1000_led_on_ich8lan");
5088 if (hw->phy.type == e1000_phy_ife)
5089 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5090 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5092 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5093 return E1000_SUCCESS;
5097 * e1000_led_off_ich8lan - Turn LEDs off
5098 * @hw: pointer to the HW structure
5100 * Turn off the LEDs.
5102 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5104 DEBUGFUNC("e1000_led_off_ich8lan");
5106 if (hw->phy.type == e1000_phy_ife)
5107 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5108 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5110 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5111 return E1000_SUCCESS;
5115 * e1000_setup_led_pchlan - Configures SW controllable LED
5116 * @hw: pointer to the HW structure
5118 * This prepares the SW controllable LED for use.
5120 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5122 DEBUGFUNC("e1000_setup_led_pchlan");
5124 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5125 (u16)hw->mac.ledctl_mode1);
5129 * e1000_cleanup_led_pchlan - Restore the default LED operation
5130 * @hw: pointer to the HW structure
5132 * Return the LED back to the default configuration.
5134 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5136 DEBUGFUNC("e1000_cleanup_led_pchlan");
5138 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5139 (u16)hw->mac.ledctl_default);
5143 * e1000_led_on_pchlan - Turn LEDs on
5144 * @hw: pointer to the HW structure
5148 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5150 u16 data = (u16)hw->mac.ledctl_mode2;
5153 DEBUGFUNC("e1000_led_on_pchlan");
5155 /* If no link, then turn LED on by setting the invert bit
5156 * for each LED that's mode is "link_up" in ledctl_mode2.
5158 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5159 for (i = 0; i < 3; i++) {
5160 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5161 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5162 E1000_LEDCTL_MODE_LINK_UP)
5164 if (led & E1000_PHY_LED0_IVRT)
5165 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5167 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5171 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5175 * e1000_led_off_pchlan - Turn LEDs off
5176 * @hw: pointer to the HW structure
5178 * Turn off the LEDs.
5180 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5182 u16 data = (u16)hw->mac.ledctl_mode1;
5185 DEBUGFUNC("e1000_led_off_pchlan");
5187 /* If no link, then turn LED off by clearing the invert bit
5188 * for each LED that's mode is "link_up" in ledctl_mode1.
5190 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5191 for (i = 0; i < 3; i++) {
5192 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5193 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5194 E1000_LEDCTL_MODE_LINK_UP)
5196 if (led & E1000_PHY_LED0_IVRT)
5197 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5199 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5203 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5207 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5208 * @hw: pointer to the HW structure
5210 * Read appropriate register for the config done bit for completion status
5211 * and configure the PHY through s/w for EEPROM-less parts.
5213 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5214 * config done bit, so only an error is logged and continues. If we were
5215 * to return with error, EEPROM-less silicon would not be able to be reset
5218 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5220 s32 ret_val = E1000_SUCCESS;
5224 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5226 e1000_get_cfg_done_generic(hw);
5228 /* Wait for indication from h/w that it has completed basic config */
5229 if (hw->mac.type >= e1000_ich10lan) {
5230 e1000_lan_init_done_ich8lan(hw);
5232 ret_val = e1000_get_auto_rd_done_generic(hw);
5234 /* When auto config read does not complete, do not
5235 * return with an error. This can happen in situations
5236 * where there is no eeprom and prevents getting link.
5238 DEBUGOUT("Auto Read Done did not complete\n");
5239 ret_val = E1000_SUCCESS;
5243 /* Clear PHY Reset Asserted bit */
5244 status = E1000_READ_REG(hw, E1000_STATUS);
5245 if (status & E1000_STATUS_PHYRA)
5246 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5248 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5250 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5251 if (hw->mac.type <= e1000_ich9lan) {
5252 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5253 (hw->phy.type == e1000_phy_igp_3)) {
5254 e1000_phy_init_script_igp3(hw);
5257 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5258 /* Maybe we should do a basic PHY config */
5259 DEBUGOUT("EEPROM not present\n");
5260 ret_val = -E1000_ERR_CONFIG;
5268 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5269 * @hw: pointer to the HW structure
5271 * In the case of a PHY power down to save power, or to turn off link during a
5272 * driver unload, or wake on lan is not enabled, remove the link.
5274 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5276 /* If the management interface is not enabled, then power down */
5277 if (!(hw->mac.ops.check_mng_mode(hw) ||
5278 hw->phy.ops.check_reset_block(hw)))
5279 e1000_power_down_phy_copper(hw);
5285 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5286 * @hw: pointer to the HW structure
5288 * Clears hardware counters specific to the silicon family and calls
5289 * clear_hw_cntrs_generic to clear all general purpose counters.
5291 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5296 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5298 e1000_clear_hw_cntrs_base_generic(hw);
5300 E1000_READ_REG(hw, E1000_ALGNERRC);
5301 E1000_READ_REG(hw, E1000_RXERRC);
5302 E1000_READ_REG(hw, E1000_TNCRS);
5303 E1000_READ_REG(hw, E1000_CEXTERR);
5304 E1000_READ_REG(hw, E1000_TSCTC);
5305 E1000_READ_REG(hw, E1000_TSCTFC);
5307 E1000_READ_REG(hw, E1000_MGTPRC);
5308 E1000_READ_REG(hw, E1000_MGTPDC);
5309 E1000_READ_REG(hw, E1000_MGTPTC);
5311 E1000_READ_REG(hw, E1000_IAC);
5312 E1000_READ_REG(hw, E1000_ICRXOC);
5314 /* Clear PHY statistics registers */
5315 if ((hw->phy.type == e1000_phy_82578) ||
5316 (hw->phy.type == e1000_phy_82579) ||
5317 (hw->phy.type == e1000_phy_i217) ||
5318 (hw->phy.type == e1000_phy_82577)) {
5319 ret_val = hw->phy.ops.acquire(hw);
5322 ret_val = hw->phy.ops.set_page(hw,
5323 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5326 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5327 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5328 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5329 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5330 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5331 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5332 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5333 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5334 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5335 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5336 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5337 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5338 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5339 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5341 hw->phy.ops.release(hw);
5346 * e1000_configure_k0s_lpt - Configure K0s power state
5347 * @hw: pointer to the HW structure
5348 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
5349 * 0 corresponds to 128ns, each value over 0 doubles the duration.
5350 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
5351 * 0 corresponds to 128ns, each value over 0 doubles the duration.
5353 * Configure the K1 power state based on the provided parameter.
5354 * Assumes semaphore already acquired.
5356 * Success returns 0, Failure returns:
5357 * -E1000_ERR_PHY (-2) in case of access error
5358 * -E1000_ERR_PARAM (-4) in case of parameters error
5360 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
5365 DEBUGFUNC("e1000_configure_k0s_lpt");
5367 if (entry_latency > 3 || min_time > 4)
5368 return -E1000_ERR_PARAM;
5370 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5375 /* for now don't touch the latency */
5376 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
5377 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
5379 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5384 return E1000_SUCCESS;