drivers/net/e1000/base/e1000_ich8lan.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001 - 2015 Intel Corporation
   3  */
   4
   5 /* 82562G 10/100 Network Connection
   6  * 82562G-2 10/100 Network Connection
   7  * 82562GT 10/100 Network Connection
   8  * 82562GT-2 10/100 Network Connection
   9  * 82562V 10/100 Network Connection
  10  * 82562V-2 10/100 Network Connection
  11  * 82566DC-2 Gigabit Network Connection
  12  * 82566DC Gigabit Network Connection
  13  * 82566DM-2 Gigabit Network Connection
  14  * 82566DM Gigabit Network Connection
  15  * 82566MC Gigabit Network Connection
  16  * 82566MM Gigabit Network Connection
  17  * 82567LM Gigabit Network Connection
  18  * 82567LF Gigabit Network Connection
  19  * 82567V Gigabit Network Connection
  20  * 82567LM-2 Gigabit Network Connection
  21  * 82567LF-2 Gigabit Network Connection
  22  * 82567V-2 Gigabit Network Connection
  23  * 82567LF-3 Gigabit Network Connection
  24  * 82567LM-3 Gigabit Network Connection
  25  * 82567LM-4 Gigabit Network Connection
  26  * 82577LM Gigabit Network Connection
  27  * 82577LC Gigabit Network Connection
  28  * 82578DM Gigabit Network Connection
  29  * 82578DC Gigabit Network Connection
  30  * 82579LM Gigabit Network Connection
  31  * 82579V Gigabit Network Connection
  32  * Ethernet Connection I217-LM
  33  * Ethernet Connection I217-V
  34  * Ethernet Connection I218-V
  35  * Ethernet Connection I218-LM
  36  * Ethernet Connection (2) I218-LM
  37  * Ethernet Connection (2) I218-V
  38  * Ethernet Connection (3) I218-LM
  39  * Ethernet Connection (3) I218-V
  40  */
  41
  42 #include "e1000_api.h"
  43
  44 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  45 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  46 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  47 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  48 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  49 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  50 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  51 STATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  52 STATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  53 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  54 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  55 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  56                                               u8 *mc_addr_list,
  57                                               u32 mc_addr_count);
  58 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  59 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  60 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  61 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  62 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  63                                             bool active);
  64 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  65                                             bool active);
  66 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  67                                    u16 words, u16 *data);
  68 STATIC s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
  69                                u16 *data);
  70 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  71                                     u16 words, u16 *data);
  72 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  73 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  74 STATIC s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
  75 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  76                                             u16 *data);
  77 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
  78 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
  79 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
  80 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
  81 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
  82 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
  83 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
  84 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
  85                                            u16 *speed, u16 *duplex);
  86 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
  87 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
  88 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
  90 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
  91 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
  92 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
  93 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
  94 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  95 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
  96 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  97 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
  98 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
  99                                           u32 offset, u8 *data);
 100 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 101                                           u8 size, u16 *data);
 102 STATIC s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 103                                             u32 *data);
 104 STATIC s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 105                                            u32 offset, u32 *data);
 106 STATIC s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 107                                              u32 offset, u32 data);
 108 STATIC s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 109                                                   u32 offset, u32 dword);
 110 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 111                                           u32 offset, u16 *data);
 112 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 113                                                  u32 offset, u8 byte);
 114 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 115 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 116 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 117 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 118 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 119 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 120
 121 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 122 /* Offset 04h HSFSTS */
 123 union ich8_hws_flash_status {
 124         struct ich8_hsfsts {
 125                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 126                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 127                 u16 dael:1; /* bit 2 Direct Access error Log */
 128                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 129                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 130                 u16 reserved1:2; /* bit 13:6 Reserved */
 131                 u16 reserved2:6; /* bit 13:6 Reserved */
 132                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 133                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 134         } hsf_status;
 135         u16 regval;
 136 };
 137
 138 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 139 /* Offset 06h FLCTL */
 140 union ich8_hws_flash_ctrl {
 141         struct ich8_hsflctl {
 142                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 143                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 144                 u16 reserved:5;   /* 7:3 Reserved  */
 145                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 146                 u16 flockdn:6;   /* 15:10 Reserved */
 147         } hsf_ctrl;
 148         u16 regval;
 149 };
 150
 151 /* ICH Flash Region Access Permissions */
 152 union ich8_hws_flash_regacc {
 153         struct ich8_flracc {
 154                 u32 grra:8; /* 0:7 GbE region Read Access */
 155                 u32 grwa:8; /* 8:15 GbE region Write Access */
 156                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 157                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 158         } hsf_flregacc;
 159         u16 regval;
 160 };
 161
 162 /**
 163  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 164  *  @hw: pointer to the HW structure
 165  *
 166  *  Test access to the PHY registers by reading the PHY ID registers.  If
 167  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 168  *  otherwise assume the read PHY ID is correct if it is valid.
 169  *
 170  *  Assumes the sw/fw/hw semaphore is already acquired.
 171  **/
 172 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 173 {
 174         u16 phy_reg = 0;
 175         u32 phy_id = 0;
 176         s32 ret_val = 0;
 177         u16 retry_count;
 178         u32 mac_reg = 0;
 179
 180         for (retry_count = 0; retry_count < 2; retry_count++) {
 181                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 182                 if (ret_val || (phy_reg == 0xFFFF))
 183                         continue;
 184                 phy_id = (u32)(phy_reg << 16);
 185
 186                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 187                 if (ret_val || (phy_reg == 0xFFFF)) {
 188                         phy_id = 0;
 189                         continue;
 190                 }
 191                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 192                 break;
 193         }
 194
 195         if (hw->phy.id) {
 196                 if  (hw->phy.id == phy_id)
 197                         goto out;
 198         } else if (phy_id) {
 199                 hw->phy.id = phy_id;
 200                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 201                 goto out;
 202         }
 203
 204         /* In case the PHY needs to be in mdio slow mode,
 205          * set slow mode and try to get the PHY id again.
 206          */
 207         if (hw->mac.type < e1000_pch_lpt) {
 208                 hw->phy.ops.release(hw);
 209                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 210                 if (!ret_val)
 211                         ret_val = e1000_get_phy_id(hw);
 212                 hw->phy.ops.acquire(hw);
 213         }
 214
 215         if (ret_val)
 216                 return false;
 217 out:
 218         if (hw->mac.type >= e1000_pch_lpt) {
 219                 /* Only unforce SMBus if ME is not active */
 220                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
 221                     E1000_ICH_FWSM_FW_VALID)) {
 222                         /* Unforce SMBus mode in PHY */
 223                         hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 224                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 225                         hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 226
 227                         /* Unforce SMBus mode in MAC */
 228                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 229                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 230                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 231                 }
 232         }
 233
 234         return true;
 235 }
 236
 237 /**
 238  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 239  *  @hw: pointer to the HW structure
 240  *
 241  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 242  *  used to reset the PHY to a quiescent state when necessary.
 243  **/
 244 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 245 {
 246         u32 mac_reg;
 247
 248         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 249
 250         /* Set Phy Config Counter to 50msec */
 251         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 252         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 253         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 254         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 255
 256         /* Toggle LANPHYPC Value bit */
 257         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 258         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 259         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 260         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 261         E1000_WRITE_FLUSH(hw);
 262         msec_delay(1);
 263         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 264         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 265         E1000_WRITE_FLUSH(hw);
 266
 267         if (hw->mac.type < e1000_pch_lpt) {
 268                 msec_delay(50);
 269         } else {
 270                 u16 count = 20;
 271
 272                 do {
 273                         msec_delay(5);
 274                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 275                            E1000_CTRL_EXT_LPCD) && count--);
 276
 277                 msec_delay(30);
 278         }
 279 }
 280
 281 /**
 282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  Workarounds/flow necessary for PHY initialization during driver load
 286  *  and resume paths.
 287  **/
 288 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 289 {
 290         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 291         s32 ret_val;
 292
 293         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 294
 295         /* Gate automatic PHY configuration by hardware on managed and
 296          * non-managed 82579 and newer adapters.
 297          */
 298         e1000_gate_hw_phy_config_ich8lan(hw, true);
 299
 300 #ifdef ULP_SUPPORT
 301         /* It is not possible to be certain of the current state of ULP
 302          * so forcibly disable it.
 303          */
 304         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 305
 306 #endif /* ULP_SUPPORT */
 307         ret_val = hw->phy.ops.acquire(hw);
 308         if (ret_val) {
 309                 DEBUGOUT("Failed to initialize PHY flow\n");
 310                 goto out;
 311         }
 312
 313         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 314          * inaccessible and resetting the PHY is not blocked, toggle the
 315          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 316          */
 317         switch (hw->mac.type) {
 318         case e1000_pch_lpt:
 319         case e1000_pch_spt:
 320         case e1000_pch_cnp:
 321         case e1000_pch_adp:
 322                 if (e1000_phy_is_accessible_pchlan(hw))
 323                         break;
 324
 325                 /* Before toggling LANPHYPC, see if PHY is accessible by
 326                  * forcing MAC to SMBus mode first.
 327                  */
 328                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 329                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 330                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 331
 332                 /* Wait 50 milliseconds for MAC to finish any retries
 333                  * that it might be trying to perform from previous
 334                  * attempts to acknowledge any phy read requests.
 335                  */
 336                  msec_delay(50);
 337
 338                 /* fall-through */
 339         case e1000_pch2lan:
 340                 if (e1000_phy_is_accessible_pchlan(hw))
 341                         break;
 342
 343                 /* fall-through */
 344         case e1000_pchlan:
 345                 if ((hw->mac.type == e1000_pchlan) &&
 346                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 347                         break;
 348
 349                 if (hw->phy.ops.check_reset_block(hw)) {
 350                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 351                         ret_val = -E1000_ERR_PHY;
 352                         break;
 353                 }
 354
 355                 /* Toggle LANPHYPC Value bit */
 356                 e1000_toggle_lanphypc_pch_lpt(hw);
 357                 if (hw->mac.type >= e1000_pch_lpt) {
 358                         if (e1000_phy_is_accessible_pchlan(hw))
 359                                 break;
 360
 361                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 362                          * so ensure that the MAC is also out of SMBus mode
 363                          */
 364                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 365                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 366                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 367
 368                         if (e1000_phy_is_accessible_pchlan(hw))
 369                                 break;
 370
 371                         ret_val = -E1000_ERR_PHY;
 372                 }
 373                 break;
 374         default:
 375                 break;
 376         }
 377
 378         hw->phy.ops.release(hw);
 379         if (!ret_val) {
 380
 381                 /* Check to see if able to reset PHY.  Print error if not */
 382                 if (hw->phy.ops.check_reset_block(hw)) {
 383                         ERROR_REPORT("Reset blocked by ME\n");
 384                         goto out;
 385                 }
 386
 387                 /* Reset the PHY before any access to it.  Doing so, ensures
 388                  * that the PHY is in a known good state before we read/write
 389                  * PHY registers.  The generic reset is sufficient here,
 390                  * because we haven't determined the PHY type yet.
 391                  */
 392                 ret_val = e1000_phy_hw_reset_generic(hw);
 393                 if (ret_val)
 394                         goto out;
 395
 396                 /* On a successful reset, possibly need to wait for the PHY
 397                  * to quiesce to an accessible state before returning control
 398                  * to the calling function.  If the PHY does not quiesce, then
 399                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 400                  *  the PHY is in.
 401                  */
 402                 ret_val = hw->phy.ops.check_reset_block(hw);
 403                 if (ret_val)
 404                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 405         }
 406
 407 out:
 408         /* Ungate automatic PHY configuration on non-managed 82579 */
 409         if ((hw->mac.type == e1000_pch2lan) &&
 410             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 411                 msec_delay(10);
 412                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 413         }
 414
 415         return ret_val;
 416 }
 417
 418 /**
 419  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 420  *  @hw: pointer to the HW structure
 421  *
 422  *  Initialize family-specific PHY parameters and function pointers.
 423  **/
 424 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 425 {
 426         struct e1000_phy_info *phy = &hw->phy;
 427         s32 ret_val;
 428
 429         DEBUGFUNC("e1000_init_phy_params_pchlan");
 430
 431         phy->addr               = 1;
 432         phy->reset_delay_us     = 100;
 433
 434         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 435         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 436         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 437         phy->ops.set_page       = e1000_set_page_igp;
 438         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 439         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 440         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 441         phy->ops.release        = e1000_release_swflag_ich8lan;
 442         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 443         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 444         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 445         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 446         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 447         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 448         phy->ops.power_up       = e1000_power_up_phy_copper;
 449         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 450         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 451
 452         phy->id = e1000_phy_unknown;
 453
 454         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 455         if (ret_val)
 456                 return ret_val;
 457
 458         if (phy->id == e1000_phy_unknown)
 459                 switch (hw->mac.type) {
 460                 default:
 461                         ret_val = e1000_get_phy_id(hw);
 462                         if (ret_val)
 463                                 return ret_val;
 464                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 465                                 break;
 466                         /* fall-through */
 467                 case e1000_pch2lan:
 468                 case e1000_pch_lpt:
 469                 case e1000_pch_spt:
 470                 case e1000_pch_cnp:
 471                 case e1000_pch_adp:
 472                         /* In case the PHY needs to be in mdio slow mode,
 473                          * set slow mode and try to get the PHY id again.
 474                          */
 475                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 476                         if (ret_val)
 477                                 return ret_val;
 478                         ret_val = e1000_get_phy_id(hw);
 479                         if (ret_val)
 480                                 return ret_val;
 481                         break;
 482                 }
 483         phy->type = e1000_get_phy_type_from_id(phy->id);
 484
 485         switch (phy->type) {
 486         case e1000_phy_82577:
 487         case e1000_phy_82579:
 488         case e1000_phy_i217:
 489                 phy->ops.check_polarity = e1000_check_polarity_82577;
 490                 phy->ops.force_speed_duplex =
 491                         e1000_phy_force_speed_duplex_82577;
 492                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 493                 phy->ops.get_info = e1000_get_phy_info_82577;
 494                 phy->ops.commit = e1000_phy_sw_reset_generic;
 495                 break;
 496         case e1000_phy_82578:
 497                 phy->ops.check_polarity = e1000_check_polarity_m88;
 498                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 499                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 500                 phy->ops.get_info = e1000_get_phy_info_m88;
 501                 break;
 502         default:
 503                 ret_val = -E1000_ERR_PHY;
 504                 break;
 505         }
 506
 507         return ret_val;
 508 }
 509
 510 /**
 511  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 512  *  @hw: pointer to the HW structure
 513  *
 514  *  Initialize family-specific PHY parameters and function pointers.
 515  **/
 516 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 517 {
 518         struct e1000_phy_info *phy = &hw->phy;
 519         s32 ret_val;
 520         u16 i = 0;
 521
 522         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 523
 524         phy->addr               = 1;
 525         phy->reset_delay_us     = 100;
 526
 527         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 528         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 529         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 530         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 531         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 532         phy->ops.release        = e1000_release_swflag_ich8lan;
 533         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 534         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 535         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 536         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 537         phy->ops.power_up       = e1000_power_up_phy_copper;
 538         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 539
 540         /* We may need to do this twice - once for IGP and if that fails,
 541          * we'll set BM func pointers and try again
 542          */
 543         ret_val = e1000_determine_phy_address(hw);
 544         if (ret_val) {
 545                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 546                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 547                 ret_val = e1000_determine_phy_address(hw);
 548                 if (ret_val) {
 549                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 550                         return ret_val;
 551                 }
 552         }
 553
 554         phy->id = 0;
 555         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 556                (i++ < 100)) {
 557                 msec_delay(1);
 558                 ret_val = e1000_get_phy_id(hw);
 559                 if (ret_val)
 560                         return ret_val;
 561         }
 562
 563         /* Verify phy id */
 564         switch (phy->id) {
 565         case IGP03E1000_E_PHY_ID:
 566                 phy->type = e1000_phy_igp_3;
 567                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 568                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 569                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 570                 phy->ops.get_info = e1000_get_phy_info_igp;
 571                 phy->ops.check_polarity = e1000_check_polarity_igp;
 572                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 573                 break;
 574         case IFE_E_PHY_ID:
 575         case IFE_PLUS_E_PHY_ID:
 576         case IFE_C_E_PHY_ID:
 577                 phy->type = e1000_phy_ife;
 578                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 579                 phy->ops.get_info = e1000_get_phy_info_ife;
 580                 phy->ops.check_polarity = e1000_check_polarity_ife;
 581                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 582                 break;
 583         case BME1000_E_PHY_ID:
 584                 phy->type = e1000_phy_bm;
 585                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 586                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 587                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 588                 phy->ops.commit = e1000_phy_sw_reset_generic;
 589                 phy->ops.get_info = e1000_get_phy_info_m88;
 590                 phy->ops.check_polarity = e1000_check_polarity_m88;
 591                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 592                 break;
 593         default:
 594                 return -E1000_ERR_PHY;
 595                 break;
 596         }
 597
 598         return E1000_SUCCESS;
 599 }
 600
 601 /**
 602  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 603  *  @hw: pointer to the HW structure
 604  *
 605  *  Initialize family-specific NVM parameters and function
 606  *  pointers.
 607  **/
 608 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 609 {
 610         struct e1000_nvm_info *nvm = &hw->nvm;
 611         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 612         u32 gfpreg, sector_base_addr, sector_end_addr;
 613         u16 i;
 614         u32 nvm_size;
 615
 616         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 617
 618         nvm->type = e1000_nvm_flash_sw;
 619
 620         if (hw->mac.type >= e1000_pch_spt) {
 621                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 622                  * STRAP register. This is because in SPT the GbE Flash region
 623                  * is no longer accessed through the flash registers. Instead,
 624                  * the mechanism has changed, and the Flash region access
 625                  * registers are now implemented in GbE memory space.
 626                  */
 627                 nvm->flash_base_addr = 0;
 628                 nvm_size =
 629                     (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
 630                     * NVM_SIZE_MULTIPLIER;
 631                 nvm->flash_bank_size = nvm_size / 2;
 632                 /* Adjust to word count */
 633                 nvm->flash_bank_size /= sizeof(u16);
 634                 /* Set the base address for flash register access */
 635                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 636         } else {
 637                 /* Can't read flash registers if register set isn't mapped. */
 638                 if (!hw->flash_address) {
 639                         DEBUGOUT("ERROR: Flash registers not mapped\n");
 640                         return -E1000_ERR_CONFIG;
 641                 }
 642
 643                 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 644
 645                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 646                  * Add 1 to sector_end_addr since this sector is included in
 647                  * the overall size.
 648                  */
 649                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 650                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 651
 652                 /* flash_base_addr is byte-aligned */
 653                 nvm->flash_base_addr = sector_base_addr
 654                                        << FLASH_SECTOR_ADDR_SHIFT;
 655
 656                 /* find total size of the NVM, then cut in half since the total
 657                  * size represents two separate NVM banks.
 658                  */
 659                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 660                                         << FLASH_SECTOR_ADDR_SHIFT);
 661                 nvm->flash_bank_size /= 2;
 662                 /* Adjust to word count */
 663                 nvm->flash_bank_size /= sizeof(u16);
 664         }
 665
 666         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 667
 668         /* Clear shadow ram */
 669         for (i = 0; i < nvm->word_size; i++) {
 670                 dev_spec->shadow_ram[i].modified = false;
 671                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 672         }
 673
 674         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 675         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 676
 677         /* Function Pointers */
 678         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 679         nvm->ops.release        = e1000_release_nvm_ich8lan;
 680         if (hw->mac.type >= e1000_pch_spt) {
 681                 nvm->ops.read   = e1000_read_nvm_spt;
 682                 nvm->ops.update = e1000_update_nvm_checksum_spt;
 683         } else {
 684                 nvm->ops.read   = e1000_read_nvm_ich8lan;
 685                 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
 686         }
 687         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 688         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 689         nvm->ops.write          = e1000_write_nvm_ich8lan;
 690
 691         return E1000_SUCCESS;
 692 }
 693
 694 /**
 695  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 696  *  @hw: pointer to the HW structure
 697  *
 698  *  Initialize family-specific MAC parameters and function
 699  *  pointers.
 700  **/
 701 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 702 {
 703         struct e1000_mac_info *mac = &hw->mac;
 704 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 705         u16 pci_cfg;
 706 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 707
 708         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 709
 710         /* Set media type function pointer */
 711         hw->phy.media_type = e1000_media_type_copper;
 712
 713         /* Set mta register count */
 714         mac->mta_reg_count = 32;
 715         /* Set rar entry count */
 716         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 717         if (mac->type == e1000_ich8lan)
 718                 mac->rar_entry_count--;
 719         /* Set if part includes ASF firmware */
 720         mac->asf_firmware_present = true;
 721         /* FWSM register */
 722         mac->has_fwsm = true;
 723         /* ARC subsystem not supported */
 724         mac->arc_subsystem_valid = false;
 725         /* Adaptive IFS supported */
 726         mac->adaptive_ifs = true;
 727
 728         /* Function pointers */
 729
 730         /* bus type/speed/width */
 731         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 732         /* function id */
 733         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 734         /* reset */
 735         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 736         /* hw initialization */
 737         mac->ops.init_hw = e1000_init_hw_ich8lan;
 738         /* link setup */
 739         mac->ops.setup_link = e1000_setup_link_ich8lan;
 740         /* physical interface setup */
 741         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 742         /* check for link */
 743         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 744         /* link info */
 745         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 746         /* multicast address update */
 747         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 748         /* clear hardware counters */
 749         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 750
 751         /* LED and other operations */
 752         switch (mac->type) {
 753         case e1000_ich8lan:
 754         case e1000_ich9lan:
 755         case e1000_ich10lan:
 756                 /* check management mode */
 757                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 758                 /* ID LED init */
 759                 mac->ops.id_led_init = e1000_id_led_init_generic;
 760                 /* blink LED */
 761                 mac->ops.blink_led = e1000_blink_led_generic;
 762                 /* setup LED */
 763                 mac->ops.setup_led = e1000_setup_led_generic;
 764                 /* cleanup LED */
 765                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 766                 /* turn on/off LED */
 767                 mac->ops.led_on = e1000_led_on_ich8lan;
 768                 mac->ops.led_off = e1000_led_off_ich8lan;
 769                 break;
 770         case e1000_pch2lan:
 771                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 772                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 773                 /* fall-through */
 774         case e1000_pch_lpt:
 775         case e1000_pch_spt:
 776         case e1000_pch_cnp:
 777         case e1000_pch_adp:
 778                 /* multicast address update for pch2 */
 779                 mac->ops.update_mc_addr_list =
 780                         e1000_update_mc_addr_list_pch2lan;
 781                 /* fall-through */
 782         case e1000_pchlan:
 783 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 784                 /* save PCH revision_id */
 785                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 786                 /* SPT uses full byte for revision ID,
 787                  * as opposed to previous generations
 788                  */
 789                 if (hw->mac.type >= e1000_pch_spt)
 790                         hw->revision_id = (u8)(pci_cfg &= 0x00FF);
 791                 else
 792                         hw->revision_id = (u8)(pci_cfg &= 0x000F);
 793 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 794                 /* check management mode */
 795                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 796                 /* ID LED init */
 797                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 798                 /* setup LED */
 799                 mac->ops.setup_led = e1000_setup_led_pchlan;
 800                 /* cleanup LED */
 801                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 802                 /* turn on/off LED */
 803                 mac->ops.led_on = e1000_led_on_pchlan;
 804                 mac->ops.led_off = e1000_led_off_pchlan;
 805                 break;
 806         default:
 807                 break;
 808         }
 809
 810         if (mac->type >= e1000_pch_lpt) {
 811                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 812                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 813                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 814         }
 815
 816         /* Enable PCS Lock-loss workaround for ICH8 */
 817         if (mac->type == e1000_ich8lan)
 818                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 819
 820         return E1000_SUCCESS;
 821 }
 822
 823 /**
 824  *  __e1000_access_emi_reg_locked - Read/write EMI register
 825  *  @hw: pointer to the HW structure
 826  *  @address: EMI address to program
 827  *  @data: pointer to value to read/write from/to the EMI address
 828  *  @read: boolean flag to indicate read or write
 829  *
 830  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 831  **/
 832 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 833                                          u16 *data, bool read)
 834 {
 835         s32 ret_val;
 836
 837         DEBUGFUNC("__e1000_access_emi_reg_locked");
 838
 839         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 840         if (ret_val)
 841                 return ret_val;
 842
 843         if (read)
 844                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 845                                                       data);
 846         else
 847                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 848                                                        *data);
 849
 850         return ret_val;
 851 }
 852
 853 /**
 854  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 855  *  @hw: pointer to the HW structure
 856  *  @addr: EMI address to program
 857  *  @data: value to be read from the EMI address
 858  *
 859  *  Assumes the SW/FW/HW Semaphore is already acquired.
 860  **/
 861 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 862 {
 863         DEBUGFUNC("e1000_read_emi_reg_locked");
 864
 865         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 866 }
 867
 868 /**
 869  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 870  *  @hw: pointer to the HW structure
 871  *  @addr: EMI address to program
 872  *  @data: value to be written to the EMI address
 873  *
 874  *  Assumes the SW/FW/HW Semaphore is already acquired.
 875  **/
 876 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 877 {
 878         DEBUGFUNC("e1000_read_emi_reg_locked");
 879
 880         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 881 }
 882
 883 /**
 884  *  e1000_set_eee_pchlan - Enable/disable EEE support
 885  *  @hw: pointer to the HW structure
 886  *
 887  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 888  *  the link and the EEE capabilities of the link partner.  The LPI Control
 889  *  register bits will remain set only if/when link is up.
 890  *
 891  *  EEE LPI must not be asserted earlier than one second after link is up.
 892  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 893  *  can be link issues with some switches.  Other devices can have EEE LPI
 894  *  enabled immediately upon link up since they have a timer in hardware which
 895  *  prevents LPI from being asserted too early.
 896  **/
 897 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 898 {
 899         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 900         s32 ret_val;
 901         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 902
 903         DEBUGFUNC("e1000_set_eee_pchlan");
 904
 905         switch (hw->phy.type) {
 906         case e1000_phy_82579:
 907                 lpa = I82579_EEE_LP_ABILITY;
 908                 pcs_status = I82579_EEE_PCS_STATUS;
 909                 adv_addr = I82579_EEE_ADVERTISEMENT;
 910                 break;
 911         case e1000_phy_i217:
 912                 lpa = I217_EEE_LP_ABILITY;
 913                 pcs_status = I217_EEE_PCS_STATUS;
 914                 adv_addr = I217_EEE_ADVERTISEMENT;
 915                 break;
 916         default:
 917                 return E1000_SUCCESS;
 918         }
 919
 920         ret_val = hw->phy.ops.acquire(hw);
 921         if (ret_val)
 922                 return ret_val;
 923
 924         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 925         if (ret_val)
 926                 goto release;
 927
 928         /* Clear bits that enable EEE in various speeds */
 929         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 930
 931         /* Enable EEE if not disabled by user */
 932         if (!dev_spec->eee_disable) {
 933                 /* Save off link partner's EEE ability */
 934                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 935                                                     &dev_spec->eee_lp_ability);
 936                 if (ret_val)
 937                         goto release;
 938
 939                 /* Read EEE advertisement */
 940                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 941                 if (ret_val)
 942                         goto release;
 943
 944                 /* Enable EEE only for speeds in which the link partner is
 945                  * EEE capable and for which we advertise EEE.
 946                  */
 947                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 948                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 949
 950                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 951                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 952                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 953                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 954                         else
 955                                 /* EEE is not supported in 100Half, so ignore
 956                                  * partner's EEE in 100 ability if full-duplex
 957                                  * is not advertised.
 958                                  */
 959                                 dev_spec->eee_lp_ability &=
 960                                     ~I82579_EEE_100_SUPPORTED;
 961                 }
 962         }
 963
 964         if (hw->phy.type == e1000_phy_82579) {
 965                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 966                                                     &data);
 967                 if (ret_val)
 968                         goto release;
 969
 970                 data &= ~I82579_LPI_100_PLL_SHUT;
 971                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 972                                                      data);
 973         }
 974
 975         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 976         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 977         if (ret_val)
 978                 goto release;
 979
 980         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 981 release:
 982         hw->phy.ops.release(hw);
 983
 984         return ret_val;
 985 }
 986
 987 /**
 988  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 989  *  @hw:   pointer to the HW structure
 990  *  @link: link up bool flag
 991  *
 992  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 993  *  preventing further DMA write requests.  Workaround the issue by disabling
 994  *  the de-assertion of the clock request when in 1Gpbs mode.
 995  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 996  *  speeds in order to avoid Tx hangs.
 997  **/
 998 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 999 {
1000         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1001         u32 status = E1000_READ_REG(hw, E1000_STATUS);
1002         s32 ret_val = E1000_SUCCESS;
1003         u16 reg;
1004
1005         if (link && (status & E1000_STATUS_SPEED_1000)) {
1006                 ret_val = hw->phy.ops.acquire(hw);
1007                 if (ret_val)
1008                         return ret_val;
1009
1010                 ret_val =
1011                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1012                                                &reg);
1013                 if (ret_val)
1014                         goto release;
1015
1016                 ret_val =
1017                     e1000_write_kmrn_reg_locked(hw,
1018                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1019                                                 reg &
1020                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1021                 if (ret_val)
1022                         goto release;
1023
1024                 usec_delay(10);
1025
1026                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1027                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1028
1029                 ret_val =
1030                     e1000_write_kmrn_reg_locked(hw,
1031                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1032                                                 reg);
1033 release:
1034                 hw->phy.ops.release(hw);
1035         } else {
1036                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1037                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1038
1039                 if ((hw->phy.revision > 5) || !link ||
1040                     ((status & E1000_STATUS_SPEED_100) &&
1041                      (status & E1000_STATUS_FD)))
1042                         goto update_fextnvm6;
1043
1044                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1045                 if (ret_val)
1046                         return ret_val;
1047
1048                 /* Clear link status transmit timeout */
1049                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1050
1051                 if (status & E1000_STATUS_SPEED_100) {
1052                         /* Set inband Tx timeout to 5x10us for 100Half */
1053                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1054
1055                         /* Do not extend the K1 entry latency for 100Half */
1056                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1057                 } else {
1058                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1059                         reg |= 50 <<
1060                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1061
1062                         /* Extend the K1 entry latency for 10 Mbps */
1063                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1064                 }
1065
1066                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1067                 if (ret_val)
1068                         return ret_val;
1069
1070 update_fextnvm6:
1071                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1072         }
1073
1074         return ret_val;
1075 }
1076
1077 #ifdef ULP_SUPPORT
1078 /**
1079  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1080  *  @hw: pointer to the HW structure
1081  *  @to_sx: boolean indicating a system power state transition to Sx
1082  *
1083  *  When link is down, configure ULP mode to significantly reduce the power
1084  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1085  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1086  *  system, configure the ULP mode by software.
1087  */
1088 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1089 {
1090         u32 mac_reg;
1091         s32 ret_val = E1000_SUCCESS;
1092         u16 phy_reg;
1093         u16 oem_reg = 0;
1094
1095         if ((hw->mac.type < e1000_pch_lpt) ||
1096             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1097             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1098             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1099             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1100             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1101                 return 0;
1102
1103         if (!to_sx) {
1104                 int i = 0;
1105                 /* Poll up to 5 seconds for Cable Disconnected indication */
1106                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1107                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1108                         /* Bail if link is re-acquired */
1109                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1110                                 return -E1000_ERR_PHY;
1111                         if (i++ == 100)
1112                                 break;
1113
1114                         msec_delay(50);
1115                 }
1116                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1117                           (E1000_READ_REG(hw, E1000_FEXT) &
1118                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1119                           i * 50);
1120                 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1121                     E1000_FEXT_PHY_CABLE_DISCONNECTED))
1122                         return 0;
1123         }
1124
1125         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1126                 /* Request ME configure ULP mode in the PHY */
1127                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1128                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1129                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1130
1131                 goto out;
1132         }
1133
1134         ret_val = hw->phy.ops.acquire(hw);
1135         if (ret_val)
1136                 goto out;
1137
1138         /* During S0 Idle keep the phy in PCI-E mode */
1139         if (hw->dev_spec.ich8lan.smbus_disable)
1140                 goto skip_smbus;
1141
1142         /* Force SMBus mode in PHY */
1143         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1144         if (ret_val)
1145                 goto release;
1146         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1147         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1148
1149         /* Force SMBus mode in MAC */
1150         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1151         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1152         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1153
1154         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1155          * LPLU and disable Gig speed when entering ULP
1156          */
1157         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1158                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1159                                                        &oem_reg);
1160                 if (ret_val)
1161                         goto release;
1162
1163                 phy_reg = oem_reg;
1164                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1165
1166                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1167                                                         phy_reg);
1168
1169                 if (ret_val)
1170                         goto release;
1171         }
1172
1173 skip_smbus:
1174         if (!to_sx) {
1175                 /* Change the 'Link Status Change' interrupt to trigger
1176                  * on 'Cable Status Change'
1177                  */
1178                 ret_val = e1000_read_kmrn_reg_locked(hw,
1179                                                      E1000_KMRNCTRLSTA_OP_MODES,
1180                                                      &phy_reg);
1181                 if (ret_val)
1182                         goto release;
1183                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1184                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1185                                             phy_reg);
1186         }
1187
1188         /* Set Inband ULP Exit, Reset to SMBus mode and
1189          * Disable SMBus Release on PERST# in PHY
1190          */
1191         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1192         if (ret_val)
1193                 goto release;
1194         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1195                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1196         if (to_sx) {
1197                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1198                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1199                 else
1200                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1201
1202                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1203                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1204         } else {
1205                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1206                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1207                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1208         }
1209         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1210
1211         /* Set Disable SMBus Release on PERST# in MAC */
1212         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1213         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1214         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1215
1216         /* Commit ULP changes in PHY by starting auto ULP configuration */
1217         phy_reg |= I218_ULP_CONFIG1_START;
1218         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1219
1220         if (!to_sx) {
1221                 /* Disable Tx so that the MAC doesn't send any (buffered)
1222                  * packets to the PHY.
1223                  */
1224                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1225                 mac_reg &= ~E1000_TCTL_EN;
1226                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1227         }
1228
1229         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1230             to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1231                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1232                                                         oem_reg);
1233                 if (ret_val)
1234                         goto release;
1235         }
1236
1237 release:
1238         hw->phy.ops.release(hw);
1239 out:
1240         if (ret_val)
1241                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1242         else
1243                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1244
1245         return ret_val;
1246 }
1247
1248 /**
1249  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1250  *  @hw: pointer to the HW structure
1251  *  @force: boolean indicating whether or not to force disabling ULP
1252  *
1253  *  Un-configure ULP mode when link is up, the system is transitioned from
1254  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1255  *  system, poll for an indication from ME that ULP has been un-configured.
1256  *  If not on an ME enabled system, un-configure the ULP mode by software.
1257  *
1258  *  During nominal operation, this function is called when link is acquired
1259  *  to disable ULP mode (force=false); otherwise, for example when unloading
1260  *  the driver or during Sx->S0 transitions, this is called with force=true
1261  *  to forcibly disable ULP.
1262
1263  *  When the cable is plugged in while the device is in D0, a Cable Status
1264  *  Change interrupt is generated which causes this function to be called
1265  *  to partially disable ULP mode and restart autonegotiation.  This function
1266  *  is then called again due to the resulting Link Status Change interrupt
1267  *  to finish cleaning up after the ULP flow.
1268  */
1269 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1270 {
1271         s32 ret_val = E1000_SUCCESS;
1272         u8 ulp_exit_timeout = 30;
1273         u32 mac_reg;
1274         u16 phy_reg;
1275         int i = 0;
1276
1277         if ((hw->mac.type < e1000_pch_lpt) ||
1278             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1279             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1280             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1281             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1282             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1283                 return 0;
1284
1285         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1286                 if (force) {
1287                         /* Request ME un-configure ULP mode in the PHY */
1288                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1289                         mac_reg &= ~E1000_H2ME_ULP;
1290                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1291                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1292                 }
1293
1294                 if (hw->mac.type == e1000_pch_cnp)
1295                         ulp_exit_timeout = 100;
1296
1297                 while (E1000_READ_REG(hw, E1000_FWSM) &
1298                        E1000_FWSM_ULP_CFG_DONE) {
1299                         if (i++ == ulp_exit_timeout) {
1300                                 ret_val = -E1000_ERR_PHY;
1301                                 goto out;
1302                         }
1303
1304                         msec_delay(10);
1305                 }
1306                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1307
1308                 if (force) {
1309                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1310                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1311                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1312                 } else {
1313                         /* Clear H2ME.ULP after ME ULP configuration */
1314                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1315                         mac_reg &= ~E1000_H2ME_ULP;
1316                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1317
1318                         /* Restore link speed advertisements and restart
1319                          * Auto-negotiation
1320                          */
1321                         if (hw->mac.autoneg) {
1322                                 ret_val = e1000_phy_setup_autoneg(hw);
1323                                 if (ret_val)
1324                                         goto out;
1325                         } else {
1326                                 ret_val = e1000_setup_copper_link_generic(hw);
1327                                 if (ret_val)
1328                                         goto out;
1329                         }
1330                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1331                 }
1332
1333                 goto out;
1334         }
1335
1336         ret_val = hw->phy.ops.acquire(hw);
1337         if (ret_val)
1338                 goto out;
1339
1340         /* Revert the change to the 'Link Status Change'
1341          * interrupt to trigger on 'Cable Status Change'
1342          */
1343         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1344                                              &phy_reg);
1345         if (ret_val)
1346                 goto release;
1347         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1348         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1349
1350         if (force)
1351                 /* Toggle LANPHYPC Value bit */
1352                 e1000_toggle_lanphypc_pch_lpt(hw);
1353
1354         /* Unforce SMBus mode in PHY */
1355         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1356         if (ret_val) {
1357                 /* The MAC might be in PCIe mode, so temporarily force to
1358                  * SMBus mode in order to access the PHY.
1359                  */
1360                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1361                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1362                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1363
1364                 msec_delay(50);
1365
1366                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1367                                                        &phy_reg);
1368                 if (ret_val)
1369                         goto release;
1370         }
1371         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1372         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1373
1374         /* Unforce SMBus mode in MAC */
1375         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1376         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1377         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1378
1379         /* When ULP mode was previously entered, K1 was disabled by the
1380          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1381          */
1382         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1383         if (ret_val)
1384                 goto release;
1385         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1386         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1387
1388         /* Clear ULP enabled configuration */
1389         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1390         if (ret_val)
1391                 goto release;
1392         /* CSC interrupt received due to ULP Indication */
1393         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1394                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1395                              I218_ULP_CONFIG1_STICKY_ULP |
1396                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1397                              I218_ULP_CONFIG1_WOL_HOST |
1398                              I218_ULP_CONFIG1_INBAND_EXIT |
1399                              I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1400                              I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1401                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1402                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1403
1404                 /* Commit ULP changes by starting auto ULP configuration */
1405                 phy_reg |= I218_ULP_CONFIG1_START;
1406                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1407
1408                 /* Clear Disable SMBus Release on PERST# in MAC */
1409                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1410                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1411                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1412
1413                 if (!force) {
1414                         hw->phy.ops.release(hw);
1415
1416                         if (hw->mac.autoneg)
1417                                 e1000_phy_setup_autoneg(hw);
1418                         else
1419                                 e1000_setup_copper_link_generic(hw);
1420
1421                         e1000_sw_lcd_config_ich8lan(hw);
1422
1423                         e1000_oem_bits_config_ich8lan(hw, true);
1424
1425                         /* Set ULP state to unknown and return non-zero to
1426                          * indicate no link (yet) and re-enter on the next LSC
1427                          * to finish disabling ULP flow.
1428                          */
1429                         hw->dev_spec.ich8lan.ulp_state =
1430                             e1000_ulp_state_unknown;
1431
1432                         return 1;
1433                 }
1434         }
1435
1436         /* Re-enable Tx */
1437         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1438         mac_reg |= E1000_TCTL_EN;
1439         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1440
1441 release:
1442         hw->phy.ops.release(hw);
1443         if (force) {
1444                 hw->phy.ops.reset(hw);
1445                 msec_delay(50);
1446         }
1447 out:
1448         if (ret_val)
1449                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1450         else
1451                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1452
1453         return ret_val;
1454 }
1455
1456 #endif /* ULP_SUPPORT */
1457
1458
1459 /**
1460  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1461  *  @hw: pointer to the HW structure
1462  *
1463  *  Checks to see of the link status of the hardware has changed.  If a
1464  *  change in link status has been detected, then we read the PHY registers
1465  *  to get the current speed/duplex if link exists.
1466  **/
1467 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1468 {
1469         struct e1000_mac_info *mac = &hw->mac;
1470         s32 ret_val, tipg_reg = 0;
1471         u16 emi_addr, emi_val = 0;
1472         bool link = false;
1473         u16 phy_reg;
1474
1475         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1476
1477         /* We only want to go out to the PHY registers to see if Auto-Neg
1478          * has completed and/or if our link status has changed.  The
1479          * get_link_status flag is set upon receiving a Link Status
1480          * Change or Rx Sequence Error interrupt.
1481          */
1482         if (!mac->get_link_status)
1483                 return E1000_SUCCESS;
1484
1485         if ((hw->mac.type < e1000_pch_lpt) ||
1486             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1487             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1488                 /* First we want to see if the MII Status Register reports
1489                  * link.  If so, then we want to get the current speed/duplex
1490                  * of the PHY.
1491                  */
1492                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1493                 if (ret_val)
1494                         return ret_val;
1495         } else {
1496                 /* Check the MAC's STATUS register to determine link state
1497                  * since the PHY could be inaccessible while in ULP mode.
1498                  */
1499                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1500                 if (link)
1501                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1502                 else
1503                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1504                 if (ret_val)
1505                         return ret_val;
1506         }
1507
1508         if (hw->mac.type == e1000_pchlan) {
1509                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1510                 if (ret_val)
1511                         return ret_val;
1512         }
1513
1514         /* When connected at 10Mbps half-duplex, some parts are excessively
1515          * aggressive resulting in many collisions. To avoid this, increase
1516          * the IPG and reduce Rx latency in the PHY.
1517          */
1518         if ((hw->mac.type >= e1000_pch2lan) && link) {
1519                 u16 speed, duplex;
1520
1521                 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1522                 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1523                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1524
1525                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1526                         tipg_reg |= 0xFF;
1527                         /* Reduce Rx latency in analog PHY */
1528                         emi_val = 0;
1529                 } else if (hw->mac.type >= e1000_pch_spt &&
1530                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1531                         tipg_reg |= 0xC;
1532                         emi_val = 1;
1533                 } else {
1534                         /* Roll back the default values */
1535                         tipg_reg |= 0x08;
1536                         emi_val = 1;
1537                 }
1538
1539                 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1540
1541                 ret_val = hw->phy.ops.acquire(hw);
1542                 if (ret_val)
1543                         return ret_val;
1544
1545                 if (hw->mac.type == e1000_pch2lan)
1546                         emi_addr = I82579_RX_CONFIG;
1547                 else
1548                         emi_addr = I217_RX_CONFIG;
1549                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1550
1551
1552                 if (hw->mac.type >= e1000_pch_lpt) {
1553                         hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1554                                                     &phy_reg);
1555                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1556                         if (speed == SPEED_100 || speed == SPEED_10)
1557                                 phy_reg |= 0x3E8;
1558                         else
1559                                 phy_reg |= 0xFA;
1560                         hw->phy.ops.write_reg_locked(hw,
1561                                                      I217_PLL_CLOCK_GATE_REG,
1562                                                      phy_reg);
1563
1564                         if (speed == SPEED_1000) {
1565                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1566                                                             &phy_reg);
1567
1568                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1569
1570                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1571                                                              phy_reg);
1572                                 }
1573                  }
1574                 hw->phy.ops.release(hw);
1575
1576                 if (ret_val)
1577                         return ret_val;
1578
1579                 if (hw->mac.type >= e1000_pch_spt) {
1580                         u16 data;
1581                         u16 ptr_gap;
1582
1583                         if (speed == SPEED_1000) {
1584                                 ret_val = hw->phy.ops.acquire(hw);
1585                                 if (ret_val)
1586                                         return ret_val;
1587
1588                                 ret_val = hw->phy.ops.read_reg_locked(hw,
1589                                                               PHY_REG(776, 20),
1590                                                               &data);
1591                                 if (ret_val) {
1592                                         hw->phy.ops.release(hw);
1593                                         return ret_val;
1594                                 }
1595
1596                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1597                                 if (ptr_gap < 0x18) {
1598                                         data &= ~(0x3FF << 2);
1599                                         data |= (0x18 << 2);
1600                                         ret_val =
1601                                                 hw->phy.ops.write_reg_locked(hw,
1602                                                         PHY_REG(776, 20), data);
1603                                 }
1604                                 hw->phy.ops.release(hw);
1605                                 if (ret_val)
1606                                         return ret_val;
1607                         } else {
1608                                 ret_val = hw->phy.ops.acquire(hw);
1609                                 if (ret_val)
1610                                         return ret_val;
1611
1612                                 ret_val = hw->phy.ops.write_reg_locked(hw,
1613                                                              PHY_REG(776, 20),
1614                                                              0xC023);
1615                                 hw->phy.ops.release(hw);
1616                                 if (ret_val)
1617                                         return ret_val;
1618
1619                         }
1620                 }
1621         }
1622
1623         /* I217 Packet Loss issue:
1624          * ensure that FEXTNVM4 Beacon Duration is set correctly
1625          * on power up.
1626          * Set the Beacon Duration for I217 to 8 usec
1627          */
1628         if (hw->mac.type >= e1000_pch_lpt) {
1629                 u32 mac_reg;
1630
1631                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1632                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1633                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1634                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1635         }
1636
1637         /* Work-around I218 hang issue */
1638         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1639             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1640             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1641             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1642                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1643                 if (ret_val)
1644                         return ret_val;
1645         }
1646         /* Clear link partner's EEE ability */
1647         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1648
1649         /* Configure K0s minimum time */
1650         if (hw->mac.type >= e1000_pch_lpt) {
1651                 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1652         }
1653
1654         if (hw->mac.type >= e1000_pch_lpt) {
1655                 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1656
1657                 if (hw->mac.type == e1000_pch_spt) {
1658                         /* FEXTNVM6 K1-off workaround - for SPT only */
1659                         u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1660
1661                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1662                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1663                         else
1664                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1665                 }
1666
1667                 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1668                         fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1669
1670                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1671         }
1672
1673         if (!link)
1674                 return E1000_SUCCESS; /* No link detected */
1675
1676         mac->get_link_status = false;
1677
1678         switch (hw->mac.type) {
1679         case e1000_pch2lan:
1680                 ret_val = e1000_k1_workaround_lv(hw);
1681                 if (ret_val)
1682                         return ret_val;
1683                 /* fall-thru */
1684         case e1000_pchlan:
1685                 if (hw->phy.type == e1000_phy_82578) {
1686                         ret_val = e1000_link_stall_workaround_hv(hw);
1687                         if (ret_val)
1688                                 return ret_val;
1689                 }
1690
1691                 /* Workaround for PCHx parts in half-duplex:
1692                  * Set the number of preambles removed from the packet
1693                  * when it is passed from the PHY to the MAC to prevent
1694                  * the MAC from misinterpreting the packet type.
1695                  */
1696                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1697                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1698
1699                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1700                     E1000_STATUS_FD)
1701                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1702
1703                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1704                 break;
1705         default:
1706                 break;
1707         }
1708
1709         /* Check if there was DownShift, must be checked
1710          * immediately after link-up
1711          */
1712         e1000_check_downshift_generic(hw);
1713
1714         /* Enable/Disable EEE after link up */
1715         if (hw->phy.type > e1000_phy_82579) {
1716                 ret_val = e1000_set_eee_pchlan(hw);
1717                 if (ret_val)
1718                         return ret_val;
1719         }
1720
1721         /* If we are forcing speed/duplex, then we simply return since
1722          * we have already determined whether we have link or not.
1723          */
1724         if (!mac->autoneg)
1725                 return -E1000_ERR_CONFIG;
1726
1727         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1728          * of MAC speed/duplex configuration.  So we only need to
1729          * configure Collision Distance in the MAC.
1730          */
1731         mac->ops.config_collision_dist(hw);
1732
1733         /* Configure Flow Control now that Auto-Neg has completed.
1734          * First, we need to restore the desired flow control
1735          * settings because we may have had to re-autoneg with a
1736          * different link partner.
1737          */
1738         ret_val = e1000_config_fc_after_link_up_generic(hw);
1739         if (ret_val)
1740                 DEBUGOUT("Error configuring flow control\n");
1741
1742         return ret_val;
1743 }
1744
1745 /**
1746  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1747  *  @hw: pointer to the HW structure
1748  *
1749  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1750  **/
1751 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1752 {
1753         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1754
1755         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1756         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1757         switch (hw->mac.type) {
1758         case e1000_ich8lan:
1759         case e1000_ich9lan:
1760         case e1000_ich10lan:
1761                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1762                 break;
1763         case e1000_pchlan:
1764         case e1000_pch2lan:
1765         case e1000_pch_lpt:
1766         case e1000_pch_spt:
1767         case e1000_pch_cnp:
1768         case e1000_pch_adp:
1769                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1770                 break;
1771         default:
1772                 break;
1773         }
1774 }
1775
1776 /**
1777  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1778  *  @hw: pointer to the HW structure
1779  *
1780  *  Acquires the mutex for performing NVM operations.
1781  **/
1782 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1783 {
1784         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1785
1786         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1787
1788         return E1000_SUCCESS;
1789 }
1790
1791 /**
1792  *  e1000_release_nvm_ich8lan - Release NVM mutex
1793  *  @hw: pointer to the HW structure
1794  *
1795  *  Releases the mutex used while performing NVM operations.
1796  **/
1797 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1798 {
1799         DEBUGFUNC("e1000_release_nvm_ich8lan");
1800
1801         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1802
1803         return;
1804 }
1805
1806 /**
1807  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1808  *  @hw: pointer to the HW structure
1809  *
1810  *  Acquires the software control flag for performing PHY and select
1811  *  MAC CSR accesses.
1812  **/
1813 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1814 {
1815         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1816         s32 ret_val = E1000_SUCCESS;
1817
1818         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1819
1820         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1821
1822         while (timeout) {
1823                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1824                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1825                         break;
1826
1827                 msec_delay_irq(1);
1828                 timeout--;
1829         }
1830
1831         if (!timeout) {
1832                 DEBUGOUT("SW has already locked the resource.\n");
1833                 ret_val = -E1000_ERR_CONFIG;
1834                 goto out;
1835         }
1836
1837         timeout = SW_FLAG_TIMEOUT;
1838
1839         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1840         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1841
1842         while (timeout) {
1843                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1844                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1845                         break;
1846
1847                 msec_delay_irq(1);
1848                 timeout--;
1849         }
1850
1851         if (!timeout) {
1852                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1853                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1854                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1855                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1856                 ret_val = -E1000_ERR_CONFIG;
1857                 goto out;
1858         }
1859
1860 out:
1861         if (ret_val)
1862                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1863
1864         return ret_val;
1865 }
1866
1867 /**
1868  *  e1000_release_swflag_ich8lan - Release software control flag
1869  *  @hw: pointer to the HW structure
1870  *
1871  *  Releases the software control flag for performing PHY and select
1872  *  MAC CSR accesses.
1873  **/
1874 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1875 {
1876         u32 extcnf_ctrl;
1877
1878         DEBUGFUNC("e1000_release_swflag_ich8lan");
1879
1880         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1881
1882         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1883                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1884                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1885         } else {
1886                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1887         }
1888
1889         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1890
1891         return;
1892 }
1893
1894 /**
1895  *  e1000_check_mng_mode_ich8lan - Checks management mode
1896  *  @hw: pointer to the HW structure
1897  *
1898  *  This checks if the adapter has any manageability enabled.
1899  *  This is a function pointer entry point only called by read/write
1900  *  routines for the PHY and NVM parts.
1901  **/
1902 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1903 {
1904         u32 fwsm;
1905
1906         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1907
1908         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1909
1910         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1911                ((fwsm & E1000_FWSM_MODE_MASK) ==
1912                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1913 }
1914
1915 /**
1916  *  e1000_check_mng_mode_pchlan - Checks management mode
1917  *  @hw: pointer to the HW structure
1918  *
1919  *  This checks if the adapter has iAMT enabled.
1920  *  This is a function pointer entry point only called by read/write
1921  *  routines for the PHY and NVM parts.
1922  **/
1923 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1924 {
1925         u32 fwsm;
1926
1927         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1928
1929         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1930
1931         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1932                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1933 }
1934
1935 /**
1936  *  e1000_rar_set_pch2lan - Set receive address register
1937  *  @hw: pointer to the HW structure
1938  *  @addr: pointer to the receive address
1939  *  @index: receive address array register
1940  *
1941  *  Sets the receive address array register at index to the address passed
1942  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1943  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1944  *  Use SHRA[0-3] in place of those reserved for ME.
1945  **/
1946 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1947 {
1948         u32 rar_low, rar_high;
1949
1950         DEBUGFUNC("e1000_rar_set_pch2lan");
1951
1952         /* HW expects these in little endian so we reverse the byte order
1953          * from network order (big endian) to little endian
1954          */
1955         rar_low = ((u32) addr[0] |
1956                    ((u32) addr[1] << 8) |
1957                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1958
1959         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1960
1961         /* If MAC address zero, no need to set the AV bit */
1962         if (rar_low || rar_high)
1963                 rar_high |= E1000_RAH_AV;
1964
1965         if (index == 0) {
1966                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1967                 E1000_WRITE_FLUSH(hw);
1968                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1969                 E1000_WRITE_FLUSH(hw);
1970                 return E1000_SUCCESS;
1971         }
1972
1973         /* RAR[1-6] are owned by manageability.  Skip those and program the
1974          * next address into the SHRA register array.
1975          */
1976         if (index < (u32) (hw->mac.rar_entry_count)) {
1977                 s32 ret_val;
1978
1979                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1980                 if (ret_val)
1981                         goto out;
1982
1983                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1984                 E1000_WRITE_FLUSH(hw);
1985                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1986                 E1000_WRITE_FLUSH(hw);
1987
1988                 e1000_release_swflag_ich8lan(hw);
1989
1990                 /* verify the register updates */
1991                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1992                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1993                         return E1000_SUCCESS;
1994
1995                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1996                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1997         }
1998
1999 out:
2000         DEBUGOUT1("Failed to write receive address at index %d\n", index);
2001         return -E1000_ERR_CONFIG;
2002 }
2003
2004 /**
2005  *  e1000_rar_set_pch_lpt - Set receive address registers
2006  *  @hw: pointer to the HW structure
2007  *  @addr: pointer to the receive address
2008  *  @index: receive address array register
2009  *
2010  *  Sets the receive address register array at index to the address passed
2011  *  in by addr. For LPT, RAR[0] is the base address register that is to
2012  *  contain the MAC address. SHRA[0-10] are the shared receive address
2013  *  registers that are shared between the Host and manageability engine (ME).
2014  **/
2015 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2016 {
2017         u32 rar_low, rar_high;
2018         u32 wlock_mac;
2019
2020         DEBUGFUNC("e1000_rar_set_pch_lpt");
2021
2022         /* HW expects these in little endian so we reverse the byte order
2023          * from network order (big endian) to little endian
2024          */
2025         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2026                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2027
2028         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2029
2030         /* If MAC address zero, no need to set the AV bit */
2031         if (rar_low || rar_high)
2032                 rar_high |= E1000_RAH_AV;
2033
2034         if (index == 0) {
2035                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2036                 E1000_WRITE_FLUSH(hw);
2037                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2038                 E1000_WRITE_FLUSH(hw);
2039                 return E1000_SUCCESS;
2040         }
2041
2042         /* The manageability engine (ME) can lock certain SHRAR registers that
2043          * it is using - those registers are unavailable for use.
2044          */
2045         if (index < hw->mac.rar_entry_count) {
2046                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2047                             E1000_FWSM_WLOCK_MAC_MASK;
2048                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2049
2050                 /* Check if all SHRAR registers are locked */
2051                 if (wlock_mac == 1)
2052                         goto out;
2053
2054                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2055                         s32 ret_val;
2056
2057                         ret_val = e1000_acquire_swflag_ich8lan(hw);
2058
2059                         if (ret_val)
2060                                 goto out;
2061
2062                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2063                                         rar_low);
2064                         E1000_WRITE_FLUSH(hw);
2065                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2066                                         rar_high);
2067                         E1000_WRITE_FLUSH(hw);
2068
2069                         e1000_release_swflag_ich8lan(hw);
2070
2071                         /* verify the register updates */
2072                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2073                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2074                                 return E1000_SUCCESS;
2075                 }
2076         }
2077
2078 out:
2079         DEBUGOUT1("Failed to write receive address at index %d\n", index);
2080         return -E1000_ERR_CONFIG;
2081 }
2082
2083 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
2084 /**
2085  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2086  *  @hw: pointer to the HW structure
2087  *  @mc_addr_list: array of multicast addresses to program
2088  *  @mc_addr_count: number of multicast addresses to program
2089  *
2090  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2091  *  The caller must have a packed mc_addr_list of multicast addresses.
2092  **/
2093 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2094                                               u8 *mc_addr_list,
2095                                               u32 mc_addr_count)
2096 {
2097         u16 phy_reg = 0;
2098         int i;
2099         s32 ret_val;
2100
2101         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2102
2103         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2104
2105         ret_val = hw->phy.ops.acquire(hw);
2106         if (ret_val)
2107                 return;
2108
2109         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2110         if (ret_val)
2111                 goto release;
2112
2113         for (i = 0; i < hw->mac.mta_reg_count; i++) {
2114                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2115                                            (u16)(hw->mac.mta_shadow[i] &
2116                                                  0xFFFF));
2117                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2118                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
2119                                                  0xFFFF));
2120         }
2121
2122         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2123
2124 release:
2125         hw->phy.ops.release(hw);
2126 }
2127
2128 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
2129 /**
2130  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2131  *  @hw: pointer to the HW structure
2132  *
2133  *  Checks if firmware is blocking the reset of the PHY.
2134  *  This is a function pointer entry point only called by
2135  *  reset routines.
2136  **/
2137 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2138 {
2139         u32 fwsm;
2140         bool blocked = false;
2141         int i = 0;
2142
2143         DEBUGFUNC("e1000_check_reset_block_ich8lan");
2144
2145         do {
2146                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2147                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2148                         blocked = true;
2149                         msec_delay(10);
2150                         continue;
2151                 }
2152                 blocked = false;
2153         } while (blocked && (i++ < 30));
2154         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2155 }
2156
2157 /**
2158  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2159  *  @hw: pointer to the HW structure
2160  *
2161  *  Assumes semaphore already acquired.
2162  *
2163  **/
2164 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2165 {
2166         u16 phy_data;
2167         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2168         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2169                 E1000_STRAP_SMT_FREQ_SHIFT;
2170         s32 ret_val;
2171
2172         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2173
2174         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2175         if (ret_val)
2176                 return ret_val;
2177
2178         phy_data &= ~HV_SMB_ADDR_MASK;
2179         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2180         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2181
2182         if (hw->phy.type == e1000_phy_i217) {
2183                 /* Restore SMBus frequency */
2184                 if (freq--) {
2185                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2186                         phy_data |= (freq & (1 << 0)) <<
2187                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2188                         phy_data |= (freq & (1 << 1)) <<
2189                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2190                 } else {
2191                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2192                 }
2193         }
2194
2195         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2196 }
2197
2198 /**
2199  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2200  *  @hw:   pointer to the HW structure
2201  *
2202  *  SW should configure the LCD from the NVM extended configuration region
2203  *  as a workaround for certain parts.
2204  **/
2205 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2206 {
2207         struct e1000_phy_info *phy = &hw->phy;
2208         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2209         s32 ret_val = E1000_SUCCESS;
2210         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2211
2212         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2213
2214         /* Initialize the PHY from the NVM on ICH platforms.  This
2215          * is needed due to an issue where the NVM configuration is
2216          * not properly autoloaded after power transitions.
2217          * Therefore, after each PHY reset, we will load the
2218          * configuration data out of the NVM manually.
2219          */
2220         switch (hw->mac.type) {
2221         case e1000_ich8lan:
2222                 if (phy->type != e1000_phy_igp_3)
2223                         return ret_val;
2224
2225                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2226                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2227                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2228                         break;
2229                 }
2230                 /* Fall-thru */
2231         case e1000_pchlan:
2232         case e1000_pch2lan:
2233         case e1000_pch_lpt:
2234         case e1000_pch_spt:
2235         case e1000_pch_cnp:
2236         case e1000_pch_adp:
2237                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2238                 break;
2239         default:
2240                 return ret_val;
2241         }
2242
2243         ret_val = hw->phy.ops.acquire(hw);
2244         if (ret_val)
2245                 return ret_val;
2246
2247         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2248         if (!(data & sw_cfg_mask))
2249                 goto release;
2250
2251         /* Make sure HW does not configure LCD from PHY
2252          * extended configuration before SW configuration
2253          */
2254         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2255         if ((hw->mac.type < e1000_pch2lan) &&
2256             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2257                         goto release;
2258
2259         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2260         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2261         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2262         if (!cnf_size)
2263                 goto release;
2264
2265         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2266         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2267
2268         if (((hw->mac.type == e1000_pchlan) &&
2269              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2270             (hw->mac.type > e1000_pchlan)) {
2271                 /* HW configures the SMBus address and LEDs when the
2272                  * OEM and LCD Write Enable bits are set in the NVM.
2273                  * When both NVM bits are cleared, SW will configure
2274                  * them instead.
2275                  */
2276                 ret_val = e1000_write_smbus_addr(hw);
2277                 if (ret_val)
2278                         goto release;
2279
2280                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2281                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2282                                                         (u16)data);
2283                 if (ret_val)
2284                         goto release;
2285         }
2286
2287         /* Configure LCD from extended configuration region. */
2288
2289         /* cnf_base_addr is in DWORD */
2290         word_addr = (u16)(cnf_base_addr << 1);
2291
2292         for (i = 0; i < cnf_size; i++) {
2293                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2294                                            &reg_data);
2295                 if (ret_val)
2296                         goto release;
2297
2298                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2299                                            1, &reg_addr);
2300                 if (ret_val)
2301                         goto release;
2302
2303                 /* Save off the PHY page for future writes. */
2304                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2305                         phy_page = reg_data;
2306                         continue;
2307                 }
2308
2309                 reg_addr &= PHY_REG_MASK;
2310                 reg_addr |= phy_page;
2311
2312                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2313                                                     reg_data);
2314                 if (ret_val)
2315                         goto release;
2316         }
2317
2318 release:
2319         hw->phy.ops.release(hw);
2320         return ret_val;
2321 }
2322
2323 /**
2324  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2325  *  @hw:   pointer to the HW structure
2326  *  @link: link up bool flag
2327  *
2328  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2329  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2330  *  If link is down, the function will restore the default K1 setting located
2331  *  in the NVM.
2332  **/
2333 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2334 {
2335         s32 ret_val = E1000_SUCCESS;
2336         u16 status_reg = 0;
2337         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2338
2339         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2340
2341         if (hw->mac.type != e1000_pchlan)
2342                 return E1000_SUCCESS;
2343
2344         /* Wrap the whole flow with the sw flag */
2345         ret_val = hw->phy.ops.acquire(hw);
2346         if (ret_val)
2347                 return ret_val;
2348
2349         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2350         if (link) {
2351                 if (hw->phy.type == e1000_phy_82578) {
2352                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2353                                                               &status_reg);
2354                         if (ret_val)
2355                                 goto release;
2356
2357                         status_reg &= (BM_CS_STATUS_LINK_UP |
2358                                        BM_CS_STATUS_RESOLVED |
2359                                        BM_CS_STATUS_SPEED_MASK);
2360
2361                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2362                                            BM_CS_STATUS_RESOLVED |
2363                                            BM_CS_STATUS_SPEED_1000))
2364                                 k1_enable = false;
2365                 }
2366
2367                 if (hw->phy.type == e1000_phy_82577) {
2368                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2369                                                               &status_reg);
2370                         if (ret_val)
2371                                 goto release;
2372
2373                         status_reg &= (HV_M_STATUS_LINK_UP |
2374                                        HV_M_STATUS_AUTONEG_COMPLETE |
2375                                        HV_M_STATUS_SPEED_MASK);
2376
2377                         if (status_reg == (HV_M_STATUS_LINK_UP |
2378                                            HV_M_STATUS_AUTONEG_COMPLETE |
2379                                            HV_M_STATUS_SPEED_1000))
2380                                 k1_enable = false;
2381                 }
2382
2383                 /* Link stall fix for link up */
2384                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2385                                                        0x0100);
2386                 if (ret_val)
2387                         goto release;
2388
2389         } else {
2390                 /* Link stall fix for link down */
2391                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2392                                                        0x4100);
2393                 if (ret_val)
2394                         goto release;
2395         }
2396
2397         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2398
2399 release:
2400         hw->phy.ops.release(hw);
2401
2402         return ret_val;
2403 }
2404
2405 /**
2406  *  e1000_configure_k1_ich8lan - Configure K1 power state
2407  *  @hw: pointer to the HW structure
2408  *  @k1_enable: K1 state to configure
2409  *
2410  *  Configure the K1 power state based on the provided parameter.
2411  *  Assumes semaphore already acquired.
2412  *
2413  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2414  **/
2415 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2416 {
2417         s32 ret_val;
2418         u32 ctrl_reg = 0;
2419         u32 ctrl_ext = 0;
2420         u32 reg = 0;
2421         u16 kmrn_reg = 0;
2422
2423         DEBUGFUNC("e1000_configure_k1_ich8lan");
2424
2425         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2426                                              &kmrn_reg);
2427         if (ret_val)
2428                 return ret_val;
2429
2430         if (k1_enable)
2431                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2432         else
2433                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2434
2435         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2436                                               kmrn_reg);
2437         if (ret_val)
2438                 return ret_val;
2439
2440         usec_delay(20);
2441         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2442         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2443
2444         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2445         reg |= E1000_CTRL_FRCSPD;
2446         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2447
2448         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2449         E1000_WRITE_FLUSH(hw);
2450         usec_delay(20);
2451         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2452         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2453         E1000_WRITE_FLUSH(hw);
2454         usec_delay(20);
2455
2456         return E1000_SUCCESS;
2457 }
2458
2459 /**
2460  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2461  *  @hw:       pointer to the HW structure
2462  *  @d0_state: boolean if entering d0 or d3 device state
2463  *
2464  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2465  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2466  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2467  **/
2468 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2469 {
2470         s32 ret_val = 0;
2471         u32 mac_reg;
2472         u16 oem_reg;
2473
2474         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2475
2476         if (hw->mac.type < e1000_pchlan)
2477                 return ret_val;
2478
2479         ret_val = hw->phy.ops.acquire(hw);
2480         if (ret_val)
2481                 return ret_val;
2482
2483         if (hw->mac.type == e1000_pchlan) {
2484                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2485                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2486                         goto release;
2487         }
2488
2489         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2490         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2491                 goto release;
2492
2493         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2494
2495         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2496         if (ret_val)
2497                 goto release;
2498
2499         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2500
2501         if (d0_state) {
2502                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2503                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2504
2505                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2506                         oem_reg |= HV_OEM_BITS_LPLU;
2507         } else {
2508                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2509                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2510                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2511
2512                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2513                     E1000_PHY_CTRL_NOND0A_LPLU))
2514                         oem_reg |= HV_OEM_BITS_LPLU;
2515         }
2516
2517         /* Set Restart auto-neg to activate the bits */
2518         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2519             !hw->phy.ops.check_reset_block(hw))
2520                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2521
2522         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2523
2524 release:
2525         hw->phy.ops.release(hw);
2526
2527         return ret_val;
2528 }
2529
2530
2531 /**
2532  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2533  *  @hw:   pointer to the HW structure
2534  **/
2535 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2536 {
2537         s32 ret_val;
2538         u16 data;
2539
2540         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2541
2542         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2543         if (ret_val)
2544                 return ret_val;
2545
2546         data |= HV_KMRN_MDIO_SLOW;
2547
2548         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2549
2550         return ret_val;
2551 }
2552
2553 /**
2554  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2555  *  done after every PHY reset.
2556  *  @hw: pointer to the HW structure
2557  **/
2558 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2559 {
2560         s32 ret_val = E1000_SUCCESS;
2561         u16 phy_data;
2562
2563         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2564
2565         if (hw->mac.type != e1000_pchlan)
2566                 return E1000_SUCCESS;
2567
2568         /* Set MDIO slow mode before any other MDIO access */
2569         if (hw->phy.type == e1000_phy_82577) {
2570                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2571                 if (ret_val)
2572                         return ret_val;
2573         }
2574
2575         if (((hw->phy.type == e1000_phy_82577) &&
2576              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2577             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2578                 /* Disable generation of early preamble */
2579                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2580                 if (ret_val)
2581                         return ret_val;
2582
2583                 /* Preamble tuning for SSC */
2584                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2585                                                 0xA204);
2586                 if (ret_val)
2587                         return ret_val;
2588         }
2589
2590         if (hw->phy.type == e1000_phy_82578) {
2591                 /* Return registers to default by doing a soft reset then
2592                  * writing 0x3140 to the control register.
2593                  */
2594                 if (hw->phy.revision < 2) {
2595                         e1000_phy_sw_reset_generic(hw);
2596                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2597                                                         0x3140);
2598                 }
2599         }
2600
2601         /* Select page 0 */
2602         ret_val = hw->phy.ops.acquire(hw);
2603         if (ret_val)
2604                 return ret_val;
2605
2606         hw->phy.addr = 1;
2607         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2608         hw->phy.ops.release(hw);
2609         if (ret_val)
2610                 return ret_val;
2611
2612         /* Configure the K1 Si workaround during phy reset assuming there is
2613          * link so that it disables K1 if link is in 1Gbps.
2614          */
2615         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2616         if (ret_val)
2617                 return ret_val;
2618
2619         /* Workaround for link disconnects on a busy hub in half duplex */
2620         ret_val = hw->phy.ops.acquire(hw);
2621         if (ret_val)
2622                 return ret_val;
2623         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2624         if (ret_val)
2625                 goto release;
2626         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2627                                                phy_data & 0x00FF);
2628         if (ret_val)
2629                 goto release;
2630
2631         /* set MSE higher to enable link to stay up when noise is high */
2632         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2633 release:
2634         hw->phy.ops.release(hw);
2635
2636         return ret_val;
2637 }
2638
2639 /**
2640  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2641  *  @hw:   pointer to the HW structure
2642  **/
2643 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2644 {
2645         u32 mac_reg;
2646         u16 i, phy_reg = 0;
2647         s32 ret_val;
2648
2649         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2650
2651         ret_val = hw->phy.ops.acquire(hw);
2652         if (ret_val)
2653                 return;
2654         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2655         if (ret_val)
2656                 goto release;
2657
2658         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2659         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2660                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2661                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2662                                            (u16)(mac_reg & 0xFFFF));
2663                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2664                                            (u16)((mac_reg >> 16) & 0xFFFF));
2665
2666                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2667                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2668                                            (u16)(mac_reg & 0xFFFF));
2669                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2670                                            (u16)((mac_reg & E1000_RAH_AV)
2671                                                  >> 16));
2672         }
2673
2674         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2675
2676 release:
2677         hw->phy.ops.release(hw);
2678 }
2679
2680 #ifndef CRC32_OS_SUPPORT
2681 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2682 {
2683         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2684         u32 i, j, mask, crc;
2685
2686         DEBUGFUNC("e1000_calc_rx_da_crc");
2687
2688         crc = 0xffffffff;
2689         for (i = 0; i < 6; i++) {
2690                 crc = crc ^ mac[i];
2691                 for (j = 8; j > 0; j--) {
2692                         mask = (crc & 1) * (-1);
2693                         crc = (crc >> 1) ^ (poly & mask);
2694                 }
2695         }
2696         return ~crc;
2697 }
2698
2699 #endif /* CRC32_OS_SUPPORT */
2700 /**
2701  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2702  *  with 82579 PHY
2703  *  @hw: pointer to the HW structure
2704  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2705  **/
2706 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2707 {
2708         s32 ret_val = E1000_SUCCESS;
2709         u16 phy_reg, data;
2710         u32 mac_reg;
2711         u16 i;
2712
2713         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2714
2715         if (hw->mac.type < e1000_pch2lan)
2716                 return E1000_SUCCESS;
2717
2718         /* disable Rx path while enabling/disabling workaround */
2719         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2720         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2721                                         phy_reg | (1 << 14));
2722         if (ret_val)
2723                 return ret_val;
2724
2725         if (enable) {
2726                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2727                  * SHRAL/H) and initial CRC values to the MAC
2728                  */
2729                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2730                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2731                         u32 addr_high, addr_low;
2732
2733                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2734                         if (!(addr_high & E1000_RAH_AV))
2735                                 continue;
2736                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2737                         mac_addr[0] = (addr_low & 0xFF);
2738                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2739                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2740                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2741                         mac_addr[4] = (addr_high & 0xFF);
2742                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2743
2744 #ifndef CRC32_OS_SUPPORT
2745                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2746                                         e1000_calc_rx_da_crc(mac_addr));
2747 #else /* CRC32_OS_SUPPORT */
2748                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2749                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2750 #endif /* CRC32_OS_SUPPORT */
2751                 }
2752
2753                 /* Write Rx addresses to the PHY */
2754                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2755
2756                 /* Enable jumbo frame workaround in the MAC */
2757                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2758                 mac_reg &= ~(1 << 14);
2759                 mac_reg |= (7 << 15);
2760                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2761
2762                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2763                 mac_reg |= E1000_RCTL_SECRC;
2764                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2765
2766                 ret_val = e1000_read_kmrn_reg_generic(hw,
2767                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2768                                                 &data);
2769                 if (ret_val)
2770                         return ret_val;
2771                 ret_val = e1000_write_kmrn_reg_generic(hw,
2772                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2773                                                 data | (1 << 0));
2774                 if (ret_val)
2775                         return ret_val;
2776                 ret_val = e1000_read_kmrn_reg_generic(hw,
2777                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2778                                                 &data);
2779                 if (ret_val)
2780                         return ret_val;
2781                 data &= ~(0xF << 8);
2782                 data |= (0xB << 8);
2783                 ret_val = e1000_write_kmrn_reg_generic(hw,
2784                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2785                                                 data);
2786                 if (ret_val)
2787                         return ret_val;
2788
2789                 /* Enable jumbo frame workaround in the PHY */
2790                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2791                 data &= ~(0x7F << 5);
2792                 data |= (0x37 << 5);
2793                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2794                 if (ret_val)
2795                         return ret_val;
2796                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2797                 data &= ~(1 << 13);
2798                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2799                 if (ret_val)
2800                         return ret_val;
2801                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2802                 data &= ~(0x3FF << 2);
2803                 data |= (E1000_TX_PTR_GAP << 2);
2804                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2805                 if (ret_val)
2806                         return ret_val;
2807                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2808                 if (ret_val)
2809                         return ret_val;
2810                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2811                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2812                                                 (1 << 10));
2813                 if (ret_val)
2814                         return ret_val;
2815         } else {
2816                 /* Write MAC register values back to h/w defaults */
2817                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2818                 mac_reg &= ~(0xF << 14);
2819                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2820
2821                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2822                 mac_reg &= ~E1000_RCTL_SECRC;
2823                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2824
2825                 ret_val = e1000_read_kmrn_reg_generic(hw,
2826                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2827                                                 &data);
2828                 if (ret_val)
2829                         return ret_val;
2830                 ret_val = e1000_write_kmrn_reg_generic(hw,
2831                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2832                                                 data & ~(1 << 0));
2833                 if (ret_val)
2834                         return ret_val;
2835                 ret_val = e1000_read_kmrn_reg_generic(hw,
2836                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2837                                                 &data);
2838                 if (ret_val)
2839                         return ret_val;
2840                 data &= ~(0xF << 8);
2841                 data |= (0xB << 8);
2842                 ret_val = e1000_write_kmrn_reg_generic(hw,
2843                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2844                                                 data);
2845                 if (ret_val)
2846                         return ret_val;
2847
2848                 /* Write PHY register values back to h/w defaults */
2849                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2850                 data &= ~(0x7F << 5);
2851                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2852                 if (ret_val)
2853                         return ret_val;
2854                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2855                 data |= (1 << 13);
2856                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2857                 if (ret_val)
2858                         return ret_val;
2859                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2860                 data &= ~(0x3FF << 2);
2861                 data |= (0x8 << 2);
2862                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2863                 if (ret_val)
2864                         return ret_val;
2865                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2866                 if (ret_val)
2867                         return ret_val;
2868                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2869                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2870                                                 ~(1 << 10));
2871                 if (ret_val)
2872                         return ret_val;
2873         }
2874
2875         /* re-enable Rx path after enabling/disabling workaround */
2876         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2877                                      ~(1 << 14));
2878 }
2879
2880 /**
2881  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2882  *  done after every PHY reset.
2883  *  @hw: pointer to the HW structure
2884  **/
2885 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2886 {
2887         s32 ret_val = E1000_SUCCESS;
2888
2889         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2890
2891         if (hw->mac.type != e1000_pch2lan)
2892                 return E1000_SUCCESS;
2893
2894         /* Set MDIO slow mode before any other MDIO access */
2895         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2896         if (ret_val)
2897                 return ret_val;
2898
2899         ret_val = hw->phy.ops.acquire(hw);
2900         if (ret_val)
2901                 return ret_val;
2902         /* set MSE higher to enable link to stay up when noise is high */
2903         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2904         if (ret_val)
2905                 goto release;
2906         /* drop link after 5 times MSE threshold was reached */
2907         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2908 release:
2909         hw->phy.ops.release(hw);
2910
2911         return ret_val;
2912 }
2913
2914 /**
2915  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2916  *  @hw:   pointer to the HW structure
2917  *
2918  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2919  *  Disable K1 for 1000 and 100 speeds
2920  **/
2921 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2922 {
2923         s32 ret_val = E1000_SUCCESS;
2924         u16 status_reg = 0;
2925
2926         DEBUGFUNC("e1000_k1_workaround_lv");
2927
2928         if (hw->mac.type != e1000_pch2lan)
2929                 return E1000_SUCCESS;
2930
2931         /* Set K1 beacon duration based on 10Mbs speed */
2932         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2933         if (ret_val)
2934                 return ret_val;
2935
2936         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2937             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2938                 if (status_reg &
2939                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2940                         u16 pm_phy_reg;
2941
2942                         /* LV 1G/100 Packet drop issue wa  */
2943                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2944                                                        &pm_phy_reg);
2945                         if (ret_val)
2946                                 return ret_val;
2947                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2948                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2949                                                         pm_phy_reg);
2950                         if (ret_val)
2951                                 return ret_val;
2952                 } else {
2953                         u32 mac_reg;
2954                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2955                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2956                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2957                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2958                 }
2959         }
2960
2961         return ret_val;
2962 }
2963
2964 /**
2965  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2966  *  @hw:   pointer to the HW structure
2967  *  @gate: boolean set to true to gate, false to ungate
2968  *
2969  *  Gate/ungate the automatic PHY configuration via hardware; perform
2970  *  the configuration via software instead.
2971  **/
2972 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2973 {
2974         u32 extcnf_ctrl;
2975
2976         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2977
2978         if (hw->mac.type < e1000_pch2lan)
2979                 return;
2980
2981         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2982
2983         if (gate)
2984                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2985         else
2986                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2987
2988         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2989 }
2990
2991 /**
2992  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2993  *  @hw: pointer to the HW structure
2994  *
2995  *  Check the appropriate indication the MAC has finished configuring the
2996  *  PHY after a software reset.
2997  **/
2998 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2999 {
3000         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3001
3002         DEBUGFUNC("e1000_lan_init_done_ich8lan");
3003
3004         /* Wait for basic configuration completes before proceeding */
3005         do {
3006                 data = E1000_READ_REG(hw, E1000_STATUS);
3007                 data &= E1000_STATUS_LAN_INIT_DONE;
3008                 usec_delay(100);
3009         } while ((!data) && --loop);
3010
3011         /* If basic configuration is incomplete before the above loop
3012          * count reaches 0, loading the configuration from NVM will
3013          * leave the PHY in a bad state possibly resulting in no link.
3014          */
3015         if (loop == 0)
3016                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3017
3018         /* Clear the Init Done bit for the next init event */
3019         data = E1000_READ_REG(hw, E1000_STATUS);
3020         data &= ~E1000_STATUS_LAN_INIT_DONE;
3021         E1000_WRITE_REG(hw, E1000_STATUS, data);
3022 }
3023
3024 /**
3025  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3026  *  @hw: pointer to the HW structure
3027  **/
3028 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3029 {
3030         s32 ret_val = E1000_SUCCESS;
3031         u16 reg;
3032
3033         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3034
3035         if (hw->phy.ops.check_reset_block(hw))
3036                 return E1000_SUCCESS;
3037
3038         /* Allow time for h/w to get to quiescent state after reset */
3039         msec_delay(10);
3040
3041         /* Perform any necessary post-reset workarounds */
3042         switch (hw->mac.type) {
3043         case e1000_pchlan:
3044                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3045                 if (ret_val)
3046                         return ret_val;
3047                 break;
3048         case e1000_pch2lan:
3049                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3050                 if (ret_val)
3051                         return ret_val;
3052                 break;
3053         default:
3054                 break;
3055         }
3056
3057         /* Clear the host wakeup bit after lcd reset */
3058         if (hw->mac.type >= e1000_pchlan) {
3059                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
3060                 reg &= ~BM_WUC_HOST_WU_BIT;
3061                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3062         }
3063
3064         /* Configure the LCD with the extended configuration region in NVM */
3065         ret_val = e1000_sw_lcd_config_ich8lan(hw);
3066         if (ret_val)
3067                 return ret_val;
3068
3069         /* Configure the LCD with the OEM bits in NVM */
3070         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3071
3072         if (hw->mac.type == e1000_pch2lan) {
3073                 /* Ungate automatic PHY configuration on non-managed 82579 */
3074                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3075                     E1000_ICH_FWSM_FW_VALID)) {
3076                         msec_delay(10);
3077                         e1000_gate_hw_phy_config_ich8lan(hw, false);
3078                 }
3079
3080                 /* Set EEE LPI Update Timer to 200usec */
3081                 ret_val = hw->phy.ops.acquire(hw);
3082                 if (ret_val)
3083                         return ret_val;
3084                 ret_val = e1000_write_emi_reg_locked(hw,
3085                                                      I82579_LPI_UPDATE_TIMER,
3086                                                      0x1387);
3087                 hw->phy.ops.release(hw);
3088         }
3089
3090         return ret_val;
3091 }
3092
3093 /**
3094  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3095  *  @hw: pointer to the HW structure
3096  *
3097  *  Resets the PHY
3098  *  This is a function pointer entry point called by drivers
3099  *  or other shared routines.
3100  **/
3101 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3102 {
3103         s32 ret_val = E1000_SUCCESS;
3104
3105         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3106
3107         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3108         if ((hw->mac.type == e1000_pch2lan) &&
3109             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3110                 e1000_gate_hw_phy_config_ich8lan(hw, true);
3111
3112         ret_val = e1000_phy_hw_reset_generic(hw);
3113         if (ret_val)
3114                 return ret_val;
3115
3116         return e1000_post_phy_reset_ich8lan(hw);
3117 }
3118
3119 /**
3120  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3121  *  @hw: pointer to the HW structure
3122  *  @active: true to enable LPLU, false to disable
3123  *
3124  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
3125  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3126  *  the phy speed. This function will manually set the LPLU bit and restart
3127  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
3128  *  since it configures the same bit.
3129  **/
3130 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3131 {
3132         s32 ret_val;
3133         u16 oem_reg;
3134
3135         DEBUGFUNC("e1000_set_lplu_state_pchlan");
3136         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3137         if (ret_val)
3138                 return ret_val;
3139
3140         if (active)
3141                 oem_reg |= HV_OEM_BITS_LPLU;
3142         else
3143                 oem_reg &= ~HV_OEM_BITS_LPLU;
3144
3145         if (!hw->phy.ops.check_reset_block(hw))
3146                 oem_reg |= HV_OEM_BITS_RESTART_AN;
3147
3148         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3149 }
3150
3151 /**
3152  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3153  *  @hw: pointer to the HW structure
3154  *  @active: true to enable LPLU, false to disable
3155  *
3156  *  Sets the LPLU D0 state according to the active flag.  When
3157  *  activating LPLU this function also disables smart speed
3158  *  and vice versa.  LPLU will not be activated unless the
3159  *  device autonegotiation advertisement meets standards of
3160  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3161  *  This is a function pointer entry point only called by
3162  *  PHY setup routines.
3163  **/
3164 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3165 {
3166         struct e1000_phy_info *phy = &hw->phy;
3167         u32 phy_ctrl;
3168         s32 ret_val = E1000_SUCCESS;
3169         u16 data;
3170
3171         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3172
3173         if (phy->type == e1000_phy_ife)
3174                 return E1000_SUCCESS;
3175
3176         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3177
3178         if (active) {
3179                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3180                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3181
3182                 if (phy->type != e1000_phy_igp_3)
3183                         return E1000_SUCCESS;
3184
3185                 /* Call gig speed drop workaround on LPLU before accessing
3186                  * any PHY registers
3187                  */
3188                 if (hw->mac.type == e1000_ich8lan)
3189                         e1000_gig_downshift_workaround_ich8lan(hw);
3190
3191                 /* When LPLU is enabled, we should disable SmartSpeed */
3192                 ret_val = phy->ops.read_reg(hw,
3193                                             IGP01E1000_PHY_PORT_CONFIG,
3194                                             &data);
3195                 if (ret_val)
3196                         return ret_val;
3197                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3198                 ret_val = phy->ops.write_reg(hw,
3199                                              IGP01E1000_PHY_PORT_CONFIG,
3200                                              data);
3201                 if (ret_val)
3202                         return ret_val;
3203         } else {
3204                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3205                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3206
3207                 if (phy->type != e1000_phy_igp_3)
3208                         return E1000_SUCCESS;
3209
3210                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3211                  * during Dx states where the power conservation is most
3212                  * important.  During driver activity we should enable
3213                  * SmartSpeed, so performance is maintained.
3214                  */
3215                 if (phy->smart_speed == e1000_smart_speed_on) {
3216                         ret_val = phy->ops.read_reg(hw,
3217                                                     IGP01E1000_PHY_PORT_CONFIG,
3218                                                     &data);
3219                         if (ret_val)
3220                                 return ret_val;
3221
3222                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3223                         ret_val = phy->ops.write_reg(hw,
3224                                                      IGP01E1000_PHY_PORT_CONFIG,
3225                                                      data);
3226                         if (ret_val)
3227                                 return ret_val;
3228                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3229                         ret_val = phy->ops.read_reg(hw,
3230                                                     IGP01E1000_PHY_PORT_CONFIG,
3231                                                     &data);
3232                         if (ret_val)
3233                                 return ret_val;
3234
3235                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3236                         ret_val = phy->ops.write_reg(hw,
3237                                                      IGP01E1000_PHY_PORT_CONFIG,
3238                                                      data);
3239                         if (ret_val)
3240                                 return ret_val;
3241                 }
3242         }
3243
3244         return E1000_SUCCESS;
3245 }
3246
3247 /**
3248  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3249  *  @hw: pointer to the HW structure
3250  *  @active: true to enable LPLU, false to disable
3251  *
3252  *  Sets the LPLU D3 state according to the active flag.  When
3253  *  activating LPLU this function also disables smart speed
3254  *  and vice versa.  LPLU will not be activated unless the
3255  *  device autonegotiation advertisement meets standards of
3256  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3257  *  This is a function pointer entry point only called by
3258  *  PHY setup routines.
3259  **/
3260 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3261 {
3262         struct e1000_phy_info *phy = &hw->phy;
3263         u32 phy_ctrl;
3264         s32 ret_val = E1000_SUCCESS;
3265         u16 data;
3266
3267         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3268
3269         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3270
3271         if (!active) {
3272                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3273                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3274
3275                 if (phy->type != e1000_phy_igp_3)
3276                         return E1000_SUCCESS;
3277
3278                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3279                  * during Dx states where the power conservation is most
3280                  * important.  During driver activity we should enable
3281                  * SmartSpeed, so performance is maintained.
3282                  */
3283                 if (phy->smart_speed == e1000_smart_speed_on) {
3284                         ret_val = phy->ops.read_reg(hw,
3285                                                     IGP01E1000_PHY_PORT_CONFIG,
3286                                                     &data);
3287                         if (ret_val)
3288                                 return ret_val;
3289
3290                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3291                         ret_val = phy->ops.write_reg(hw,
3292                                                      IGP01E1000_PHY_PORT_CONFIG,
3293                                                      data);
3294                         if (ret_val)
3295                                 return ret_val;
3296                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3297                         ret_val = phy->ops.read_reg(hw,
3298                                                     IGP01E1000_PHY_PORT_CONFIG,
3299                                                     &data);
3300                         if (ret_val)
3301                                 return ret_val;
3302
3303                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3304                         ret_val = phy->ops.write_reg(hw,
3305                                                      IGP01E1000_PHY_PORT_CONFIG,
3306                                                      data);
3307                         if (ret_val)
3308                                 return ret_val;
3309                 }
3310         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3311                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3312                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3313                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3314                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3315
3316                 if (phy->type != e1000_phy_igp_3)
3317                         return E1000_SUCCESS;
3318
3319                 /* Call gig speed drop workaround on LPLU before accessing
3320                  * any PHY registers
3321                  */
3322                 if (hw->mac.type == e1000_ich8lan)
3323                         e1000_gig_downshift_workaround_ich8lan(hw);
3324
3325                 /* When LPLU is enabled, we should disable SmartSpeed */
3326                 ret_val = phy->ops.read_reg(hw,
3327                                             IGP01E1000_PHY_PORT_CONFIG,
3328                                             &data);
3329                 if (ret_val)
3330                         return ret_val;
3331
3332                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3333                 ret_val = phy->ops.write_reg(hw,
3334                                              IGP01E1000_PHY_PORT_CONFIG,
3335                                              data);
3336         }
3337
3338         return ret_val;
3339 }
3340
3341 /**
3342  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3343  *  @hw: pointer to the HW structure
3344  *  @bank:  pointer to the variable that returns the active bank
3345  *
3346  *  Reads signature byte from the NVM using the flash access registers.
3347  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3348  **/
3349 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3350 {
3351         u32 eecd;
3352         struct e1000_nvm_info *nvm = &hw->nvm;
3353         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3354         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3355         u32 nvm_dword = 0;
3356         u8 sig_byte = 0;
3357         s32 ret_val;
3358
3359         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3360
3361         switch (hw->mac.type) {
3362         case e1000_pch_spt:
3363         case e1000_pch_cnp:
3364         case e1000_pch_adp:
3365                 bank1_offset = nvm->flash_bank_size;
3366                 act_offset = E1000_ICH_NVM_SIG_WORD;
3367
3368                 /* set bank to 0 in case flash read fails */
3369                 *bank = 0;
3370
3371                 /* Check bank 0 */
3372                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3373                                                          &nvm_dword);
3374                 if (ret_val)
3375                         return ret_val;
3376                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3377                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3378                     E1000_ICH_NVM_SIG_VALUE) {
3379                         *bank = 0;
3380                         return E1000_SUCCESS;
3381                 }
3382
3383                 /* Check bank 1 */
3384                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3385                                                          bank1_offset,
3386                                                          &nvm_dword);
3387                 if (ret_val)
3388                         return ret_val;
3389                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3390                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3391                     E1000_ICH_NVM_SIG_VALUE) {
3392                         *bank = 1;
3393                         return E1000_SUCCESS;
3394                 }
3395
3396                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3397                 return -E1000_ERR_NVM;
3398         case e1000_ich8lan:
3399         case e1000_ich9lan:
3400                 eecd = E1000_READ_REG(hw, E1000_EECD);
3401                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3402                     E1000_EECD_SEC1VAL_VALID_MASK) {
3403                         if (eecd & E1000_EECD_SEC1VAL)
3404                                 *bank = 1;
3405                         else
3406                                 *bank = 0;
3407
3408                         return E1000_SUCCESS;
3409                 }
3410                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3411                 /* fall-thru */
3412         default:
3413                 /* set bank to 0 in case flash read fails */
3414                 *bank = 0;
3415
3416                 /* Check bank 0 */
3417                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3418                                                         &sig_byte);
3419                 if (ret_val)
3420                         return ret_val;
3421                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3422                     E1000_ICH_NVM_SIG_VALUE) {
3423                         *bank = 0;
3424                         return E1000_SUCCESS;
3425                 }
3426
3427                 /* Check bank 1 */
3428                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3429                                                         bank1_offset,
3430                                                         &sig_byte);
3431                 if (ret_val)
3432                         return ret_val;
3433                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3434                     E1000_ICH_NVM_SIG_VALUE) {
3435                         *bank = 1;
3436                         return E1000_SUCCESS;
3437                 }
3438
3439                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3440                 return -E1000_ERR_NVM;
3441         }
3442 }
3443
3444 /**
3445  *  e1000_read_nvm_spt - NVM access for SPT
3446  *  @hw: pointer to the HW structure
3447  *  @offset: The offset (in bytes) of the word(s) to read.
3448  *  @words: Size of data to read in words.
3449  *  @data: pointer to the word(s) to read at offset.
3450  *
3451  *  Reads a word(s) from the NVM
3452  **/
3453 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3454                               u16 *data)
3455 {
3456         struct e1000_nvm_info *nvm = &hw->nvm;
3457         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3458         u32 act_offset;
3459         s32 ret_val = E1000_SUCCESS;
3460         u32 bank = 0;
3461         u32 dword = 0;
3462         u16 offset_to_read;
3463         u16 i;
3464
3465         DEBUGFUNC("e1000_read_nvm_spt");
3466
3467         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3468             (words == 0)) {
3469                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3470                 ret_val = -E1000_ERR_NVM;
3471                 goto out;
3472         }
3473
3474         nvm->ops.acquire(hw);
3475
3476         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3477         if (ret_val != E1000_SUCCESS) {
3478                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3479                 bank = 0;
3480         }
3481
3482         act_offset = (bank) ? nvm->flash_bank_size : 0;
3483         act_offset += offset;
3484
3485         ret_val = E1000_SUCCESS;
3486
3487         for (i = 0; i < words; i += 2) {
3488                 if (words - i == 1) {
3489                         if (dev_spec->shadow_ram[offset + i].modified) {
3490                                 data[i] =
3491                                     dev_spec->shadow_ram[offset + i].value;
3492                         } else {
3493                                 offset_to_read = act_offset + i -
3494                                                  ((act_offset + i) % 2);
3495                                 ret_val =
3496                                    e1000_read_flash_dword_ich8lan(hw,
3497                                                                  offset_to_read,
3498                                                                  &dword);
3499                                 if (ret_val)
3500                                         break;
3501                                 if ((act_offset + i) % 2 == 0)
3502                                         data[i] = (u16)(dword & 0xFFFF);
3503                                 else
3504                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3505                         }
3506                 } else {
3507                         offset_to_read = act_offset + i;
3508                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3509                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3510                                 ret_val =
3511                                    e1000_read_flash_dword_ich8lan(hw,
3512                                                                  offset_to_read,
3513                                                                  &dword);
3514                                 if (ret_val)
3515                                         break;
3516                         }
3517                         if (dev_spec->shadow_ram[offset + i].modified)
3518                                 data[i] =
3519                                     dev_spec->shadow_ram[offset + i].value;
3520                         else
3521                                 data[i] = (u16)(dword & 0xFFFF);
3522                         if (dev_spec->shadow_ram[offset + i + 1].modified)
3523                                 data[i + 1] =
3524                                    dev_spec->shadow_ram[offset + i + 1].value;
3525                         else
3526                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3527                 }
3528         }
3529
3530         nvm->ops.release(hw);
3531
3532 out:
3533         if (ret_val)
3534                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3535
3536         return ret_val;
3537 }
3538
3539 /**
3540  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3541  *  @hw: pointer to the HW structure
3542  *  @offset: The offset (in bytes) of the word(s) to read.
3543  *  @words: Size of data to read in words
3544  *  @data: Pointer to the word(s) to read at offset.
3545  *
3546  *  Reads a word(s) from the NVM using the flash access registers.
3547  **/
3548 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3549                                   u16 *data)
3550 {
3551         struct e1000_nvm_info *nvm = &hw->nvm;
3552         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3553         u32 act_offset;
3554         s32 ret_val = E1000_SUCCESS;
3555         u32 bank = 0;
3556         u16 i, word;
3557
3558         DEBUGFUNC("e1000_read_nvm_ich8lan");
3559
3560         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3561             (words == 0)) {
3562                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3563                 ret_val = -E1000_ERR_NVM;
3564                 goto out;
3565         }
3566
3567         nvm->ops.acquire(hw);
3568
3569         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3570         if (ret_val != E1000_SUCCESS) {
3571                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3572                 bank = 0;
3573         }
3574
3575         act_offset = (bank) ? nvm->flash_bank_size : 0;
3576         act_offset += offset;
3577
3578         ret_val = E1000_SUCCESS;
3579         for (i = 0; i < words; i++) {
3580                 if (dev_spec->shadow_ram[offset + i].modified) {
3581                         data[i] = dev_spec->shadow_ram[offset + i].value;
3582                 } else {
3583                         ret_val = e1000_read_flash_word_ich8lan(hw,
3584                                                                 act_offset + i,
3585                                                                 &word);
3586                         if (ret_val)
3587                                 break;
3588                         data[i] = word;
3589                 }
3590         }
3591
3592         nvm->ops.release(hw);
3593
3594 out:
3595         if (ret_val)
3596                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3597
3598         return ret_val;
3599 }
3600
3601 /**
3602  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3603  *  @hw: pointer to the HW structure
3604  *
3605  *  This function does initial flash setup so that a new read/write/erase cycle
3606  *  can be started.
3607  **/
3608 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3609 {
3610         union ich8_hws_flash_status hsfsts;
3611         s32 ret_val = -E1000_ERR_NVM;
3612
3613         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3614
3615         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3616
3617         /* Check if the flash descriptor is valid */
3618         if (!hsfsts.hsf_status.fldesvalid) {
3619                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3620                 return -E1000_ERR_NVM;
3621         }
3622
3623         /* Clear FCERR and DAEL in hw status by writing 1 */
3624         hsfsts.hsf_status.flcerr = 1;
3625         hsfsts.hsf_status.dael = 1;
3626         if (hw->mac.type >= e1000_pch_spt)
3627                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3628                                       hsfsts.regval & 0xFFFF);
3629         else
3630                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3631
3632         /* Either we should have a hardware SPI cycle in progress
3633          * bit to check against, in order to start a new cycle or
3634          * FDONE bit should be changed in the hardware so that it
3635          * is 1 after hardware reset, which can then be used as an
3636          * indication whether a cycle is in progress or has been
3637          * completed.
3638          */
3639
3640         if (!hsfsts.hsf_status.flcinprog) {
3641                 /* There is no cycle running at present,
3642                  * so we can start a cycle.
3643                  * Begin by setting Flash Cycle Done.
3644                  */
3645                 hsfsts.hsf_status.flcdone = 1;
3646                 if (hw->mac.type >= e1000_pch_spt)
3647                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3648                                               hsfsts.regval & 0xFFFF);
3649                 else
3650                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3651                                                 hsfsts.regval);
3652                 ret_val = E1000_SUCCESS;
3653         } else {
3654                 s32 i;
3655
3656                 /* Otherwise poll for sometime so the current
3657                  * cycle has a chance to end before giving up.
3658                  */
3659                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3660                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3661                                                               ICH_FLASH_HSFSTS);
3662                         if (!hsfsts.hsf_status.flcinprog) {
3663                                 ret_val = E1000_SUCCESS;
3664                                 break;
3665                         }
3666                         usec_delay(1);
3667                 }
3668                 if (ret_val == E1000_SUCCESS) {
3669                         /* Successful in waiting for previous cycle to timeout,
3670                          * now set the Flash Cycle Done.
3671                          */
3672                         hsfsts.hsf_status.flcdone = 1;
3673                         if (hw->mac.type >= e1000_pch_spt)
3674                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3675                                                       hsfsts.regval & 0xFFFF);
3676                         else
3677                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3678                                                         hsfsts.regval);
3679                 } else {
3680                         DEBUGOUT("Flash controller busy, cannot get access\n");
3681                 }
3682         }
3683
3684         return ret_val;
3685 }
3686
3687 /**
3688  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3689  *  @hw: pointer to the HW structure
3690  *  @timeout: maximum time to wait for completion
3691  *
3692  *  This function starts a flash cycle and waits for its completion.
3693  **/
3694 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3695 {
3696         union ich8_hws_flash_ctrl hsflctl;
3697         union ich8_hws_flash_status hsfsts;
3698         u32 i = 0;
3699
3700         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3701
3702         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3703         if (hw->mac.type >= e1000_pch_spt)
3704                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3705         else
3706                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3707         hsflctl.hsf_ctrl.flcgo = 1;
3708
3709         if (hw->mac.type >= e1000_pch_spt)
3710                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3711                                       hsflctl.regval << 16);
3712         else
3713                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3714
3715         /* wait till FDONE bit is set to 1 */
3716         do {
3717                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3718                 if (hsfsts.hsf_status.flcdone)
3719                         break;
3720                 usec_delay(1);
3721         } while (i++ < timeout);
3722
3723         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3724                 return E1000_SUCCESS;
3725
3726         return -E1000_ERR_NVM;
3727 }
3728
3729 /**
3730  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3731  *  @hw: pointer to the HW structure
3732  *  @offset: offset to data location
3733  *  @data: pointer to the location for storing the data
3734  *
3735  *  Reads the flash dword at offset into data.  Offset is converted
3736  *  to bytes before read.
3737  **/
3738 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3739                                           u32 *data)
3740 {
3741         DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3742
3743         if (!data)
3744                 return -E1000_ERR_NVM;
3745
3746         /* Must convert word offset into bytes. */
3747         offset <<= 1;
3748
3749         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3750 }
3751
3752 /**
3753  *  e1000_read_flash_word_ich8lan - Read word from flash
3754  *  @hw: pointer to the HW structure
3755  *  @offset: offset to data location
3756  *  @data: pointer to the location for storing the data
3757  *
3758  *  Reads the flash word at offset into data.  Offset is converted
3759  *  to bytes before read.
3760  **/
3761 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3762                                          u16 *data)
3763 {
3764         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3765
3766         if (!data)
3767                 return -E1000_ERR_NVM;
3768
3769         /* Must convert offset into bytes. */
3770         offset <<= 1;
3771
3772         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3773 }
3774
3775 /**
3776  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3777  *  @hw: pointer to the HW structure
3778  *  @offset: The offset of the byte to read.
3779  *  @data: Pointer to a byte to store the value read.
3780  *
3781  *  Reads a single byte from the NVM using the flash access registers.
3782  **/
3783 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3784                                          u8 *data)
3785 {
3786         s32 ret_val;
3787         u16 word = 0;
3788
3789         /* In SPT, only 32 bits access is supported,
3790          * so this function should not be called.
3791          */
3792         if (hw->mac.type >= e1000_pch_spt)
3793                 return -E1000_ERR_NVM;
3794         else
3795                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3796
3797         if (ret_val)
3798                 return ret_val;
3799
3800         *data = (u8)word;
3801
3802         return E1000_SUCCESS;
3803 }
3804
3805 /**
3806  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3807  *  @hw: pointer to the HW structure
3808  *  @offset: The offset (in bytes) of the byte or word to read.
3809  *  @size: Size of data to read, 1=byte 2=word
3810  *  @data: Pointer to the word to store the value read.
3811  *
3812  *  Reads a byte or word from the NVM using the flash access registers.
3813  **/
3814 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3815                                          u8 size, u16 *data)
3816 {
3817         union ich8_hws_flash_status hsfsts;
3818         union ich8_hws_flash_ctrl hsflctl;
3819         u32 flash_linear_addr;
3820         u32 flash_data = 0;
3821         s32 ret_val = -E1000_ERR_NVM;
3822         u8 count = 0;
3823
3824         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3825
3826         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3827                 return -E1000_ERR_NVM;
3828         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3829                              hw->nvm.flash_base_addr);
3830
3831         do {
3832                 usec_delay(1);
3833                 /* Steps */
3834                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3835                 if (ret_val != E1000_SUCCESS)
3836                         break;
3837                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3838
3839                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3840                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3841                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3842                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3843                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3844
3845                 ret_val = e1000_flash_cycle_ich8lan(hw,
3846                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3847
3848                 /* Check if FCERR is set to 1, if set to 1, clear it
3849                  * and try the whole sequence a few more times, else
3850                  * read in (shift in) the Flash Data0, the order is
3851                  * least significant byte first msb to lsb
3852                  */
3853                 if (ret_val == E1000_SUCCESS) {
3854                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3855                         if (size == 1)
3856                                 *data = (u8)(flash_data & 0x000000FF);
3857                         else if (size == 2)
3858                                 *data = (u16)(flash_data & 0x0000FFFF);
3859                         break;
3860                 } else {
3861                         /* If we've gotten here, then things are probably
3862                          * completely hosed, but if the error condition is
3863                          * detected, it won't hurt to give it another try...
3864                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3865                          */
3866                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3867                                                               ICH_FLASH_HSFSTS);
3868                         if (hsfsts.hsf_status.flcerr) {
3869                                 /* Repeat for some time before giving up. */
3870                                 continue;
3871                         } else if (!hsfsts.hsf_status.flcdone) {
3872                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3873                                 break;
3874                         }
3875                 }
3876         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3877
3878         return ret_val;
3879 }
3880
3881 /**
3882  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3883  *  @hw: pointer to the HW structure
3884  *  @offset: The offset (in bytes) of the dword to read.
3885  *  @data: Pointer to the dword to store the value read.
3886  *
3887  *  Reads a byte or word from the NVM using the flash access registers.
3888  **/
3889 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3890                                            u32 *data)
3891 {
3892         union ich8_hws_flash_status hsfsts;
3893         union ich8_hws_flash_ctrl hsflctl;
3894         u32 flash_linear_addr;
3895         s32 ret_val = -E1000_ERR_NVM;
3896         u8 count = 0;
3897
3898         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3899
3900                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3901                     hw->mac.type < e1000_pch_spt)
3902                         return -E1000_ERR_NVM;
3903         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3904                              hw->nvm.flash_base_addr);
3905
3906         do {
3907                 usec_delay(1);
3908                 /* Steps */
3909                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3910                 if (ret_val != E1000_SUCCESS)
3911                         break;
3912                 /* In SPT, This register is in Lan memory space, not flash.
3913                  * Therefore, only 32 bit access is supported
3914                  */
3915                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3916
3917                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3918                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3919                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3920                 /* In SPT, This register is in Lan memory space, not flash.
3921                  * Therefore, only 32 bit access is supported
3922                  */
3923                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3924                                       (u32)hsflctl.regval << 16);
3925                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3926
3927                 ret_val = e1000_flash_cycle_ich8lan(hw,
3928                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3929
3930                 /* Check if FCERR is set to 1, if set to 1, clear it
3931                  * and try the whole sequence a few more times, else
3932                  * read in (shift in) the Flash Data0, the order is
3933                  * least significant byte first msb to lsb
3934                  */
3935                 if (ret_val == E1000_SUCCESS) {
3936                         *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3937                         break;
3938                 } else {
3939                         /* If we've gotten here, then things are probably
3940                          * completely hosed, but if the error condition is
3941                          * detected, it won't hurt to give it another try...
3942                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3943                          */
3944                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3945                                                               ICH_FLASH_HSFSTS);
3946                         if (hsfsts.hsf_status.flcerr) {
3947                                 /* Repeat for some time before giving up. */
3948                                 continue;
3949                         } else if (!hsfsts.hsf_status.flcdone) {
3950                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3951                                 break;
3952                         }
3953                 }
3954         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3955
3956         return ret_val;
3957 }
3958
3959 /**
3960  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3961  *  @hw: pointer to the HW structure
3962  *  @offset: The offset (in bytes) of the word(s) to write.
3963  *  @words: Size of data to write in words
3964  *  @data: Pointer to the word(s) to write at offset.
3965  *
3966  *  Writes a byte or word to the NVM using the flash access registers.
3967  **/
3968 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3969                                    u16 *data)
3970 {
3971         struct e1000_nvm_info *nvm = &hw->nvm;
3972         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3973         u16 i;
3974
3975         DEBUGFUNC("e1000_write_nvm_ich8lan");
3976
3977         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3978             (words == 0)) {
3979                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3980                 return -E1000_ERR_NVM;
3981         }
3982
3983         nvm->ops.acquire(hw);
3984
3985         for (i = 0; i < words; i++) {
3986                 dev_spec->shadow_ram[offset + i].modified = true;
3987                 dev_spec->shadow_ram[offset + i].value = data[i];
3988         }
3989
3990         nvm->ops.release(hw);
3991
3992         return E1000_SUCCESS;
3993 }
3994
3995 /**
3996  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3997  *  @hw: pointer to the HW structure
3998  *
3999  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4000  *  which writes the checksum to the shadow ram.  The changes in the shadow
4001  *  ram are then committed to the EEPROM by processing each bank at a time
4002  *  checking for the modified bit and writing only the pending changes.
4003  *  After a successful commit, the shadow ram is cleared and is ready for
4004  *  future writes.
4005  **/
4006 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4007 {
4008         struct e1000_nvm_info *nvm = &hw->nvm;
4009         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4010         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4011         s32 ret_val;
4012         u32 dword = 0;
4013
4014         DEBUGFUNC("e1000_update_nvm_checksum_spt");
4015
4016         ret_val = e1000_update_nvm_checksum_generic(hw);
4017         if (ret_val)
4018                 goto out;
4019
4020         if (nvm->type != e1000_nvm_flash_sw)
4021                 goto out;
4022
4023         nvm->ops.acquire(hw);
4024
4025         /* We're writing to the opposite bank so if we're on bank 1,
4026          * write to bank 0 etc.  We also need to erase the segment that
4027          * is going to be written
4028          */
4029         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4030         if (ret_val != E1000_SUCCESS) {
4031                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4032                 bank = 0;
4033         }
4034
4035         if (bank == 0) {
4036                 new_bank_offset = nvm->flash_bank_size;
4037                 old_bank_offset = 0;
4038                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4039                 if (ret_val)
4040                         goto release;
4041         } else {
4042                 old_bank_offset = nvm->flash_bank_size;
4043                 new_bank_offset = 0;
4044                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4045                 if (ret_val)
4046                         goto release;
4047         }
4048         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4049                 /* Determine whether to write the value stored
4050                  * in the other NVM bank or a modified value stored
4051                  * in the shadow RAM
4052                  */
4053                 ret_val = e1000_read_flash_dword_ich8lan(hw,
4054                                                          i + old_bank_offset,
4055                                                          &dword);
4056
4057                 if (dev_spec->shadow_ram[i].modified) {
4058                         dword &= 0xffff0000;
4059                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4060                 }
4061                 if (dev_spec->shadow_ram[i + 1].modified) {
4062                         dword &= 0x0000ffff;
4063                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4064                                   << 16);
4065                 }
4066                 if (ret_val)
4067                         break;
4068
4069                 /* If the word is 0x13, then make sure the signature bits
4070                  * (15:14) are 11b until the commit has completed.
4071                  * This will allow us to write 10b which indicates the
4072                  * signature is valid.  We want to do this after the write
4073                  * has completed so that we don't mark the segment valid
4074                  * while the write is still in progress
4075                  */
4076                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4077                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
4078
4079                 /* Convert offset to bytes. */
4080                 act_offset = (i + new_bank_offset) << 1;
4081
4082                 usec_delay(100);
4083
4084                 /* Write the data to the new bank. Offset in words*/
4085                 act_offset = i + new_bank_offset;
4086                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4087                                                                 dword);
4088                 if (ret_val)
4089                         break;
4090          }
4091
4092         /* Don't bother writing the segment valid bits if sector
4093          * programming failed.
4094          */
4095         if (ret_val) {
4096                 DEBUGOUT("Flash commit failed.\n");
4097                 goto release;
4098         }
4099
4100         /* Finally validate the new segment by setting bit 15:14
4101          * to 10b in word 0x13 , this can be done without an
4102          * erase as well since these bits are 11 to start with
4103          * and we need to change bit 14 to 0b
4104          */
4105         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4106
4107         /*offset in words but we read dword*/
4108         --act_offset;
4109         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4110
4111         if (ret_val)
4112                 goto release;
4113
4114         dword &= 0xBFFFFFFF;
4115         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4116
4117         if (ret_val)
4118                 goto release;
4119
4120         /* offset in words but we read dword*/
4121         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4122         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4123
4124         if (ret_val)
4125                 goto release;
4126
4127         dword &= 0x00FFFFFF;
4128         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4129
4130         if (ret_val)
4131                 goto release;
4132
4133         /* Great!  Everything worked, we can now clear the cached entries. */
4134         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4135                 dev_spec->shadow_ram[i].modified = false;
4136                 dev_spec->shadow_ram[i].value = 0xFFFF;
4137         }
4138
4139 release:
4140         nvm->ops.release(hw);
4141
4142         /* Reload the EEPROM, or else modifications will not appear
4143          * until after the next adapter reset.
4144          */
4145         if (!ret_val) {
4146                 nvm->ops.reload(hw);
4147                 msec_delay(10);
4148         }
4149
4150 out:
4151         if (ret_val)
4152                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4153
4154         return ret_val;
4155 }
4156
4157 /**
4158  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4159  *  @hw: pointer to the HW structure
4160  *
4161  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4162  *  which writes the checksum to the shadow ram.  The changes in the shadow
4163  *  ram are then committed to the EEPROM by processing each bank at a time
4164  *  checking for the modified bit and writing only the pending changes.
4165  *  After a successful commit, the shadow ram is cleared and is ready for
4166  *  future writes.
4167  **/
4168 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4169 {
4170         struct e1000_nvm_info *nvm = &hw->nvm;
4171         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4172         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4173         s32 ret_val;
4174         u16 data = 0;
4175
4176         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4177
4178         ret_val = e1000_update_nvm_checksum_generic(hw);
4179         if (ret_val)
4180                 goto out;
4181
4182         if (nvm->type != e1000_nvm_flash_sw)
4183                 goto out;
4184
4185         nvm->ops.acquire(hw);
4186
4187         /* We're writing to the opposite bank so if we're on bank 1,
4188          * write to bank 0 etc.  We also need to erase the segment that
4189          * is going to be written
4190          */
4191         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4192         if (ret_val != E1000_SUCCESS) {
4193                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4194                 bank = 0;
4195         }
4196
4197         if (bank == 0) {
4198                 new_bank_offset = nvm->flash_bank_size;
4199                 old_bank_offset = 0;
4200                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4201                 if (ret_val)
4202                         goto release;
4203         } else {
4204                 old_bank_offset = nvm->flash_bank_size;
4205                 new_bank_offset = 0;
4206                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4207                 if (ret_val)
4208                         goto release;
4209         }
4210         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4211                 if (dev_spec->shadow_ram[i].modified) {
4212                         data = dev_spec->shadow_ram[i].value;
4213                 } else {
4214                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
4215                                                                 old_bank_offset,
4216                                                                 &data);
4217                         if (ret_val)
4218                                 break;
4219                 }
4220                 /* If the word is 0x13, then make sure the signature bits
4221                  * (15:14) are 11b until the commit has completed.
4222                  * This will allow us to write 10b which indicates the
4223                  * signature is valid.  We want to do this after the write
4224                  * has completed so that we don't mark the segment valid
4225                  * while the write is still in progress
4226                  */
4227                 if (i == E1000_ICH_NVM_SIG_WORD)
4228                         data |= E1000_ICH_NVM_SIG_MASK;
4229
4230                 /* Convert offset to bytes. */
4231                 act_offset = (i + new_bank_offset) << 1;
4232
4233                 usec_delay(100);
4234
4235                 /* Write the bytes to the new bank. */
4236                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4237                                                                act_offset,
4238                                                                (u8)data);
4239                 if (ret_val)
4240                         break;
4241
4242                 usec_delay(100);
4243                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4244                                                           act_offset + 1,
4245                                                           (u8)(data >> 8));
4246                 if (ret_val)
4247                         break;
4248         }
4249
4250         /* Don't bother writing the segment valid bits if sector
4251          * programming failed.
4252          */
4253         if (ret_val) {
4254                 DEBUGOUT("Flash commit failed.\n");
4255                 goto release;
4256         }
4257
4258         /* Finally validate the new segment by setting bit 15:14
4259          * to 10b in word 0x13 , this can be done without an
4260          * erase as well since these bits are 11 to start with
4261          * and we need to change bit 14 to 0b
4262          */
4263         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4264         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4265         if (ret_val)
4266                 goto release;
4267
4268         data &= 0xBFFF;
4269         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4270                                                        (u8)(data >> 8));
4271         if (ret_val)
4272                 goto release;
4273
4274         /* And invalidate the previously valid segment by setting
4275          * its signature word (0x13) high_byte to 0b. This can be
4276          * done without an erase because flash erase sets all bits
4277          * to 1's. We can write 1's to 0's without an erase
4278          */
4279         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4280
4281         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4282
4283         if (ret_val)
4284                 goto release;
4285
4286         /* Great!  Everything worked, we can now clear the cached entries. */
4287         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4288                 dev_spec->shadow_ram[i].modified = false;
4289                 dev_spec->shadow_ram[i].value = 0xFFFF;
4290         }
4291
4292 release:
4293         nvm->ops.release(hw);
4294
4295         /* Reload the EEPROM, or else modifications will not appear
4296          * until after the next adapter reset.
4297          */
4298         if (!ret_val) {
4299                 nvm->ops.reload(hw);
4300                 msec_delay(10);
4301         }
4302
4303 out:
4304         if (ret_val)
4305                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4306
4307         return ret_val;
4308 }
4309
4310 /**
4311  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4312  *  @hw: pointer to the HW structure
4313  *
4314  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4315  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4316  *  calculated, in which case we need to calculate the checksum and set bit 6.
4317  **/
4318 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4319 {
4320         s32 ret_val;
4321         u16 data;
4322         u16 word;
4323         u16 valid_csum_mask;
4324
4325         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4326
4327         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4328          * the checksum needs to be fixed.  This bit is an indication that
4329          * the NVM was prepared by OEM software and did not calculate
4330          * the checksum...a likely scenario.
4331          */
4332         switch (hw->mac.type) {
4333         case e1000_pch_lpt:
4334         case e1000_pch_spt:
4335         case e1000_pch_cnp:
4336         case e1000_pch_adp:
4337                 word = NVM_COMPAT;
4338                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4339                 break;
4340         default:
4341                 word = NVM_FUTURE_INIT_WORD1;
4342                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4343                 break;
4344         }
4345
4346         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4347         if (ret_val)
4348                 return ret_val;
4349
4350         if (!(data & valid_csum_mask)) {
4351                 data |= valid_csum_mask;
4352                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4353                 if (ret_val)
4354                         return ret_val;
4355                 ret_val = hw->nvm.ops.update(hw);
4356                 if (ret_val)
4357                         return ret_val;
4358         }
4359
4360         return e1000_validate_nvm_checksum_generic(hw);
4361 }
4362
4363 /**
4364  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4365  *  @hw: pointer to the HW structure
4366  *  @offset: The offset (in bytes) of the byte/word to read.
4367  *  @size: Size of data to read, 1=byte 2=word
4368  *  @data: The byte(s) to write to the NVM.
4369  *
4370  *  Writes one/two bytes to the NVM using the flash access registers.
4371  **/
4372 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4373                                           u8 size, u16 data)
4374 {
4375         union ich8_hws_flash_status hsfsts;
4376         union ich8_hws_flash_ctrl hsflctl;
4377         u32 flash_linear_addr;
4378         u32 flash_data = 0;
4379         s32 ret_val;
4380         u8 count = 0;
4381
4382         DEBUGFUNC("e1000_write_ich8_data");
4383
4384         if (hw->mac.type >= e1000_pch_spt) {
4385                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4386                         return -E1000_ERR_NVM;
4387         } else {
4388                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4389                         return -E1000_ERR_NVM;
4390         }
4391
4392         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4393                              hw->nvm.flash_base_addr);
4394
4395         do {
4396                 usec_delay(1);
4397                 /* Steps */
4398                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4399                 if (ret_val != E1000_SUCCESS)
4400                         break;
4401                 /* In SPT, This register is in Lan memory space, not
4402                  * flash.  Therefore, only 32 bit access is supported
4403                  */
4404                 if (hw->mac.type >= e1000_pch_spt)
4405                         hsflctl.regval =
4406                             E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4407                 else
4408                         hsflctl.regval =
4409                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4410
4411                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4412                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4413                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4414                 /* In SPT, This register is in Lan memory space,
4415                  * not flash.  Therefore, only 32 bit access is
4416                  * supported
4417                  */
4418                 if (hw->mac.type >= e1000_pch_spt)
4419                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4420                                               hsflctl.regval << 16);
4421                 else
4422                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4423                                                 hsflctl.regval);
4424
4425                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4426
4427                 if (size == 1)
4428                         flash_data = (u32)data & 0x00FF;
4429                 else
4430                         flash_data = (u32)data;
4431
4432                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4433
4434                 /* check if FCERR is set to 1 , if set to 1, clear it
4435                  * and try the whole sequence a few more times else done
4436                  */
4437                 ret_val =
4438                     e1000_flash_cycle_ich8lan(hw,
4439                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4440                 if (ret_val == E1000_SUCCESS)
4441                         break;
4442
4443                 /* If we're here, then things are most likely
4444                  * completely hosed, but if the error condition
4445                  * is detected, it won't hurt to give it another
4446                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4447                  */
4448                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4449                 if (hsfsts.hsf_status.flcerr)
4450                         /* Repeat for some time before giving up. */
4451                         continue;
4452                 if (!hsfsts.hsf_status.flcdone) {
4453                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4454                         break;
4455                 }
4456         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4457
4458         return ret_val;
4459 }
4460
4461 /**
4462 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4463 *  @hw: pointer to the HW structure
4464 *  @offset: The offset (in bytes) of the dwords to read.
4465 *  @data: The 4 bytes to write to the NVM.
4466 *
4467 *  Writes one/two/four bytes to the NVM using the flash access registers.
4468 **/
4469 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4470                                             u32 data)
4471 {
4472         union ich8_hws_flash_status hsfsts;
4473         union ich8_hws_flash_ctrl hsflctl;
4474         u32 flash_linear_addr;
4475         s32 ret_val;
4476         u8 count = 0;
4477
4478         DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4479
4480         if (hw->mac.type >= e1000_pch_spt) {
4481                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4482                         return -E1000_ERR_NVM;
4483         }
4484         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4485                              hw->nvm.flash_base_addr);
4486         do {
4487                 usec_delay(1);
4488                 /* Steps */
4489                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4490                 if (ret_val != E1000_SUCCESS)
4491                         break;
4492
4493                 /* In SPT, This register is in Lan memory space, not
4494                  * flash.  Therefore, only 32 bit access is supported
4495                  */
4496                 if (hw->mac.type >= e1000_pch_spt)
4497                         hsflctl.regval = E1000_READ_FLASH_REG(hw,
4498                                                               ICH_FLASH_HSFSTS)
4499                                          >> 16;
4500                 else
4501                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4502                                                               ICH_FLASH_HSFCTL);
4503
4504                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4505                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4506
4507                 /* In SPT, This register is in Lan memory space,
4508                  * not flash.  Therefore, only 32 bit access is
4509                  * supported
4510                  */
4511                 if (hw->mac.type >= e1000_pch_spt)
4512                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4513                                               hsflctl.regval << 16);
4514                 else
4515                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4516                                                 hsflctl.regval);
4517
4518                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4519
4520                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4521
4522                 /* check if FCERR is set to 1 , if set to 1, clear it
4523                  * and try the whole sequence a few more times else done
4524                  */
4525                 ret_val = e1000_flash_cycle_ich8lan(hw,
4526                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4527
4528                 if (ret_val == E1000_SUCCESS)
4529                         break;
4530
4531                 /* If we're here, then things are most likely
4532                  * completely hosed, but if the error condition
4533                  * is detected, it won't hurt to give it another
4534                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4535                  */
4536                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4537
4538                 if (hsfsts.hsf_status.flcerr)
4539                         /* Repeat for some time before giving up. */
4540                         continue;
4541                 if (!hsfsts.hsf_status.flcdone) {
4542                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4543                         break;
4544                 }
4545         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4546
4547         return ret_val;
4548 }
4549
4550 /**
4551  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4552  *  @hw: pointer to the HW structure
4553  *  @offset: The index of the byte to read.
4554  *  @data: The byte to write to the NVM.
4555  *
4556  *  Writes a single byte to the NVM using the flash access registers.
4557  **/
4558 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4559                                           u8 data)
4560 {
4561         u16 word = (u16)data;
4562
4563         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4564
4565         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4566 }
4567
4568 /**
4569 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4570 *  @hw: pointer to the HW structure
4571 *  @offset: The offset of the word to write.
4572 *  @dword: The dword to write to the NVM.
4573 *
4574 *  Writes a single dword to the NVM using the flash access registers.
4575 *  Goes through a retry algorithm before giving up.
4576 **/
4577 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4578                                                  u32 offset, u32 dword)
4579 {
4580         s32 ret_val;
4581         u16 program_retries;
4582
4583         DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4584
4585         /* Must convert word offset into bytes. */
4586         offset <<= 1;
4587
4588         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4589
4590         if (!ret_val)
4591                 return ret_val;
4592         for (program_retries = 0; program_retries < 100; program_retries++) {
4593                 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4594                 usec_delay(100);
4595                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4596                 if (ret_val == E1000_SUCCESS)
4597                         break;
4598         }
4599         if (program_retries == 100)
4600                 return -E1000_ERR_NVM;
4601
4602         return E1000_SUCCESS;
4603 }
4604
4605 /**
4606  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4607  *  @hw: pointer to the HW structure
4608  *  @offset: The offset of the byte to write.
4609  *  @byte: The byte to write to the NVM.
4610  *
4611  *  Writes a single byte to the NVM using the flash access registers.
4612  *  Goes through a retry algorithm before giving up.
4613  **/
4614 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4615                                                 u32 offset, u8 byte)
4616 {
4617         s32 ret_val;
4618         u16 program_retries;
4619
4620         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4621
4622         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4623         if (!ret_val)
4624                 return ret_val;
4625
4626         for (program_retries = 0; program_retries < 100; program_retries++) {
4627                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4628                 usec_delay(100);
4629                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4630                 if (ret_val == E1000_SUCCESS)
4631                         break;
4632         }
4633         if (program_retries == 100)
4634                 return -E1000_ERR_NVM;
4635
4636         return E1000_SUCCESS;
4637 }
4638
4639 /**
4640  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4641  *  @hw: pointer to the HW structure
4642  *  @bank: 0 for first bank, 1 for second bank, etc.
4643  *
4644  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4645  *  bank N is 4096 * N + flash_reg_addr.
4646  **/
4647 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4648 {
4649         struct e1000_nvm_info *nvm = &hw->nvm;
4650         union ich8_hws_flash_status hsfsts;
4651         union ich8_hws_flash_ctrl hsflctl;
4652         u32 flash_linear_addr;
4653         /* bank size is in 16bit words - adjust to bytes */
4654         u32 flash_bank_size = nvm->flash_bank_size * 2;
4655         s32 ret_val;
4656         s32 count = 0;
4657         s32 j, iteration, sector_size;
4658
4659         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4660
4661         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4662
4663         /* Determine HW Sector size: Read BERASE bits of hw flash status
4664          * register
4665          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4666          *     consecutive sectors.  The start index for the nth Hw sector
4667          *     can be calculated as = bank * 4096 + n * 256
4668          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4669          *     The start index for the nth Hw sector can be calculated
4670          *     as = bank * 4096
4671          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4672          *     (ich9 only, otherwise error condition)
4673          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4674          */
4675         switch (hsfsts.hsf_status.berasesz) {
4676         case 0:
4677                 /* Hw sector size 256 */
4678                 sector_size = ICH_FLASH_SEG_SIZE_256;
4679                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4680                 break;
4681         case 1:
4682                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4683                 iteration = 1;
4684                 break;
4685         case 2:
4686                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4687                 iteration = 1;
4688                 break;
4689         case 3:
4690                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4691                 iteration = 1;
4692                 break;
4693         default:
4694                 return -E1000_ERR_NVM;
4695         }
4696
4697         /* Start with the base address, then add the sector offset. */
4698         flash_linear_addr = hw->nvm.flash_base_addr;
4699         flash_linear_addr += (bank) ? flash_bank_size : 0;
4700
4701         for (j = 0; j < iteration; j++) {
4702                 do {
4703                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4704
4705                         /* Steps */
4706                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4707                         if (ret_val)
4708                                 return ret_val;
4709
4710                         /* Write a value 11 (block Erase) in Flash
4711                          * Cycle field in hw flash control
4712                          */
4713                         if (hw->mac.type >= e1000_pch_spt)
4714                                 hsflctl.regval =
4715                                     E1000_READ_FLASH_REG(hw,
4716                                                          ICH_FLASH_HSFSTS)>>16;
4717                         else
4718                                 hsflctl.regval =
4719                                     E1000_READ_FLASH_REG16(hw,
4720                                                            ICH_FLASH_HSFCTL);
4721
4722                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4723                         if (hw->mac.type >= e1000_pch_spt)
4724                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4725                                                       hsflctl.regval << 16);
4726                         else
4727                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4728                                                         hsflctl.regval);
4729
4730                         /* Write the last 24 bits of an index within the
4731                          * block into Flash Linear address field in Flash
4732                          * Address.
4733                          */
4734                         flash_linear_addr += (j * sector_size);
4735                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4736                                               flash_linear_addr);
4737
4738                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4739                         if (ret_val == E1000_SUCCESS)
4740                                 break;
4741
4742                         /* Check if FCERR is set to 1.  If 1,
4743                          * clear it and try the whole sequence
4744                          * a few more times else Done
4745                          */
4746                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4747                                                       ICH_FLASH_HSFSTS);
4748                         if (hsfsts.hsf_status.flcerr)
4749                                 /* repeat for some time before giving up */
4750                                 continue;
4751                         else if (!hsfsts.hsf_status.flcdone)
4752                                 return ret_val;
4753                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4754         }
4755
4756         return E1000_SUCCESS;
4757 }
4758
4759 /**
4760  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4761  *  @hw: pointer to the HW structure
4762  *  @data: Pointer to the LED settings
4763  *
4764  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4765  *  settings is all 0's or F's, set the LED default to a valid LED default
4766  *  setting.
4767  **/
4768 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4769 {
4770         s32 ret_val;
4771
4772         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4773
4774         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4775         if (ret_val) {
4776                 DEBUGOUT("NVM Read Error\n");
4777                 return ret_val;
4778         }
4779
4780         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4781                 *data = ID_LED_DEFAULT_ICH8LAN;
4782
4783         return E1000_SUCCESS;
4784 }
4785
4786 /**
4787  *  e1000_id_led_init_pchlan - store LED configurations
4788  *  @hw: pointer to the HW structure
4789  *
4790  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4791  *  the PHY LED configuration register.
4792  *
4793  *  PCH also does not have an "always on" or "always off" mode which
4794  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4795  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4796  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4797  *  link based on logic in e1000_led_[on|off]_pchlan().
4798  **/
4799 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4800 {
4801         struct e1000_mac_info *mac = &hw->mac;
4802         s32 ret_val;
4803         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4804         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4805         u16 data, i, temp, shift;
4806
4807         DEBUGFUNC("e1000_id_led_init_pchlan");
4808
4809         /* Get default ID LED modes */
4810         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4811         if (ret_val)
4812                 return ret_val;
4813
4814         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4815         mac->ledctl_mode1 = mac->ledctl_default;
4816         mac->ledctl_mode2 = mac->ledctl_default;
4817
4818         for (i = 0; i < 4; i++) {
4819                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4820                 shift = (i * 5);
4821                 switch (temp) {
4822                 case ID_LED_ON1_DEF2:
4823                 case ID_LED_ON1_ON2:
4824                 case ID_LED_ON1_OFF2:
4825                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4826                         mac->ledctl_mode1 |= (ledctl_on << shift);
4827                         break;
4828                 case ID_LED_OFF1_DEF2:
4829                 case ID_LED_OFF1_ON2:
4830                 case ID_LED_OFF1_OFF2:
4831                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4832                         mac->ledctl_mode1 |= (ledctl_off << shift);
4833                         break;
4834                 default:
4835                         /* Do nothing */
4836                         break;
4837                 }
4838                 switch (temp) {
4839                 case ID_LED_DEF1_ON2:
4840                 case ID_LED_ON1_ON2:
4841                 case ID_LED_OFF1_ON2:
4842                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4843                         mac->ledctl_mode2 |= (ledctl_on << shift);
4844                         break;
4845                 case ID_LED_DEF1_OFF2:
4846                 case ID_LED_ON1_OFF2:
4847                 case ID_LED_OFF1_OFF2:
4848                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4849                         mac->ledctl_mode2 |= (ledctl_off << shift);
4850                         break;
4851                 default:
4852                         /* Do nothing */
4853                         break;
4854                 }
4855         }
4856
4857         return E1000_SUCCESS;
4858 }
4859
4860 /**
4861  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4862  *  @hw: pointer to the HW structure
4863  *
4864  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4865  *  register, so the bus width is hard coded.
4866  **/
4867 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4868 {
4869         struct e1000_bus_info *bus = &hw->bus;
4870         s32 ret_val;
4871
4872         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4873
4874         ret_val = e1000_get_bus_info_pcie_generic(hw);
4875
4876         /* ICH devices are "PCI Express"-ish.  They have
4877          * a configuration space, but do not contain
4878          * PCI Express Capability registers, so bus width
4879          * must be hardcoded.
4880          */
4881         if (bus->width == e1000_bus_width_unknown)
4882                 bus->width = e1000_bus_width_pcie_x1;
4883
4884         return ret_val;
4885 }
4886
4887 /**
4888  *  e1000_reset_hw_ich8lan - Reset the hardware
4889  *  @hw: pointer to the HW structure
4890  *
4891  *  Does a full reset of the hardware which includes a reset of the PHY and
4892  *  MAC.
4893  **/
4894 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4895 {
4896         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4897         u16 kum_cfg;
4898         u32 ctrl, reg;
4899         s32 ret_val;
4900         u16 pci_cfg;
4901
4902         DEBUGFUNC("e1000_reset_hw_ich8lan");
4903
4904         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4905          * on the last TLP read/write transaction when MAC is reset.
4906          */
4907         ret_val = e1000_disable_pcie_master_generic(hw);
4908         if (ret_val)
4909                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4910
4911         DEBUGOUT("Masking off all interrupts\n");
4912         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4913
4914         /* Disable the Transmit and Receive units.  Then delay to allow
4915          * any pending transactions to complete before we hit the MAC
4916          * with the global reset.
4917          */
4918         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4919         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4920         E1000_WRITE_FLUSH(hw);
4921
4922         msec_delay(10);
4923
4924         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4925         if (hw->mac.type == e1000_ich8lan) {
4926                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4927                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4928                 /* Set Packet Buffer Size to 16k. */
4929                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4930         }
4931
4932         if (hw->mac.type == e1000_pchlan) {
4933                 /* Save the NVM K1 bit setting*/
4934                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4935                 if (ret_val)
4936                         return ret_val;
4937
4938                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4939                         dev_spec->nvm_k1_enabled = true;
4940                 else
4941                         dev_spec->nvm_k1_enabled = false;
4942         }
4943
4944         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4945
4946         if (!hw->phy.ops.check_reset_block(hw)) {
4947                 /* Full-chip reset requires MAC and PHY reset at the same
4948                  * time to make sure the interface between MAC and the
4949                  * external PHY is reset.
4950                  */
4951                 ctrl |= E1000_CTRL_PHY_RST;
4952
4953                 /* Gate automatic PHY configuration by hardware on
4954                  * non-managed 82579
4955                  */
4956                 if ((hw->mac.type == e1000_pch2lan) &&
4957                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4958                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4959         }
4960         ret_val = e1000_acquire_swflag_ich8lan(hw);
4961
4962         /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
4963          * may occur during global reset and cause system hang.
4964          * Configuration space access creates the needed delay.
4965          * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
4966          * insures configuration space read is done before global reset.
4967          */
4968         e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4969         E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4970         DEBUGOUT("Issuing a global reset to ich8lan\n");
4971         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4972         /* cannot issue a flush here because it hangs the hardware */
4973         msec_delay(20);
4974
4975         /* Configuration space access improve HW level time sync mechanism.
4976          * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
4977          * value to insure configuration space read is done
4978          * before any access to mac register.
4979          */
4980         e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
4981         E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
4982
4983         /* Set Phy Config Counter to 50msec */
4984         if (hw->mac.type == e1000_pch2lan) {
4985                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4986                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4987                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4988                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4989         }
4990
4991         if (!ret_val)
4992                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4993
4994         if (ctrl & E1000_CTRL_PHY_RST) {
4995                 ret_val = hw->phy.ops.get_cfg_done(hw);
4996                 if (ret_val)
4997                         return ret_val;
4998
4999                 ret_val = e1000_post_phy_reset_ich8lan(hw);
5000                 if (ret_val)
5001                         return ret_val;
5002         }
5003
5004         /* For PCH, this write will make sure that any noise
5005          * will be detected as a CRC error and be dropped rather than show up
5006          * as a bad packet to the DMA engine.
5007          */
5008         if (hw->mac.type == e1000_pchlan)
5009                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5010
5011         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5012         E1000_READ_REG(hw, E1000_ICR);
5013
5014         reg = E1000_READ_REG(hw, E1000_KABGTXD);
5015         reg |= E1000_KABGTXD_BGSQLBIAS;
5016         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5017
5018         return E1000_SUCCESS;
5019 }
5020
5021 /**
5022  *  e1000_init_hw_ich8lan - Initialize the hardware
5023  *  @hw: pointer to the HW structure
5024  *
5025  *  Prepares the hardware for transmit and receive by doing the following:
5026  *   - initialize hardware bits
5027  *   - initialize LED identification
5028  *   - setup receive address registers
5029  *   - setup flow control
5030  *   - setup transmit descriptors
5031  *   - clear statistics
5032  **/
5033 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5034 {
5035         struct e1000_mac_info *mac = &hw->mac;
5036         u32 ctrl_ext, txdctl, snoop;
5037         s32 ret_val;
5038         u16 i;
5039
5040         DEBUGFUNC("e1000_init_hw_ich8lan");
5041
5042         e1000_initialize_hw_bits_ich8lan(hw);
5043
5044         /* Initialize identification LED */
5045         ret_val = mac->ops.id_led_init(hw);
5046         /* An error is not fatal and we should not stop init due to this */
5047         if (ret_val)
5048                 DEBUGOUT("Error initializing identification LED\n");
5049
5050         /* Setup the receive address. */
5051         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5052
5053         /* Zero out the Multicast HASH table */
5054         DEBUGOUT("Zeroing the MTA\n");
5055         for (i = 0; i < mac->mta_reg_count; i++)
5056                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5057
5058         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5059          * the ME.  Disable wakeup by clearing the host wakeup bit.
5060          * Reset the phy after disabling host wakeup to reset the Rx buffer.
5061          */
5062         if (hw->phy.type == e1000_phy_82578) {
5063                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5064                 i &= ~BM_WUC_HOST_WU_BIT;
5065                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5066                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5067                 if (ret_val)
5068                         return ret_val;
5069         }
5070
5071         /* Setup link and flow control */
5072         ret_val = mac->ops.setup_link(hw);
5073
5074         /* Set the transmit descriptor write-back policy for both queues */
5075         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5076         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5077                   E1000_TXDCTL_FULL_TX_DESC_WB);
5078         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5079                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5080         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5081         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5082         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5083                   E1000_TXDCTL_FULL_TX_DESC_WB);
5084         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5085                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5086         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5087
5088         /* ICH8 has opposite polarity of no_snoop bits.
5089          * By default, we should use snoop behavior.
5090          */
5091         if (mac->type == e1000_ich8lan)
5092                 snoop = PCIE_ICH8_SNOOP_ALL;
5093         else
5094                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5095         e1000_set_pcie_no_snoop_generic(hw, snoop);
5096
5097         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5098         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5099         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5100
5101         /* Clear all of the statistics registers (clear on read).  It is
5102          * important that we do this after we have tried to establish link
5103          * because the symbol error count will increment wildly if there
5104          * is no link.
5105          */
5106         e1000_clear_hw_cntrs_ich8lan(hw);
5107
5108         return ret_val;
5109 }
5110
5111 /**
5112  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5113  *  @hw: pointer to the HW structure
5114  *
5115  *  Sets/Clears required hardware bits necessary for correctly setting up the
5116  *  hardware for transmit and receive.
5117  **/
5118 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5119 {
5120         u32 reg;
5121
5122         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5123
5124         /* Extended Device Control */
5125         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5126         reg |= (1 << 22);
5127         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5128         if (hw->mac.type >= e1000_pchlan)
5129                 reg |= E1000_CTRL_EXT_PHYPDEN;
5130         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5131
5132         /* Transmit Descriptor Control 0 */
5133         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5134         reg |= (1 << 22);
5135         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5136
5137         /* Transmit Descriptor Control 1 */
5138         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5139         reg |= (1 << 22);
5140         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5141
5142         /* Transmit Arbitration Control 0 */
5143         reg = E1000_READ_REG(hw, E1000_TARC(0));
5144         if (hw->mac.type == e1000_ich8lan)
5145                 reg |= (1 << 28) | (1 << 29);
5146         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5147         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5148
5149         /* Transmit Arbitration Control 1 */
5150         reg = E1000_READ_REG(hw, E1000_TARC(1));
5151         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5152                 reg &= ~(1 << 28);
5153         else
5154                 reg |= (1 << 28);
5155         reg |= (1 << 24) | (1 << 26) | (1 << 30);
5156         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5157
5158         /* Device Status */
5159         if (hw->mac.type == e1000_ich8lan) {
5160                 reg = E1000_READ_REG(hw, E1000_STATUS);
5161                 reg &= ~(1U << 31);
5162                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5163         }
5164
5165         /* work-around descriptor data corruption issue during nfs v2 udp
5166          * traffic, just disable the nfs filtering capability
5167          */
5168         reg = E1000_READ_REG(hw, E1000_RFCTL);
5169         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5170
5171         /* Disable IPv6 extension header parsing because some malformed
5172          * IPv6 headers can hang the Rx.
5173          */
5174         if (hw->mac.type == e1000_ich8lan)
5175                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5176         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5177
5178         /* Enable ECC on Lynxpoint */
5179         if (hw->mac.type >= e1000_pch_lpt) {
5180                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5181                 reg |= E1000_PBECCSTS_ECC_ENABLE;
5182                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5183
5184                 reg = E1000_READ_REG(hw, E1000_CTRL);
5185                 reg |= E1000_CTRL_MEHE;
5186                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5187         }
5188
5189         return;
5190 }
5191
5192 /**
5193  *  e1000_setup_link_ich8lan - Setup flow control and link settings
5194  *  @hw: pointer to the HW structure
5195  *
5196  *  Determines which flow control settings to use, then configures flow
5197  *  control.  Calls the appropriate media-specific link configuration
5198  *  function.  Assuming the adapter has a valid link partner, a valid link
5199  *  should be established.  Assumes the hardware has previously been reset
5200  *  and the transmitter and receiver are not enabled.
5201  **/
5202 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5203 {
5204         s32 ret_val;
5205
5206         DEBUGFUNC("e1000_setup_link_ich8lan");
5207
5208         /* ICH parts do not have a word in the NVM to determine
5209          * the default flow control setting, so we explicitly
5210          * set it to full.
5211          */
5212         if (hw->fc.requested_mode == e1000_fc_default)
5213                 hw->fc.requested_mode = e1000_fc_full;
5214
5215         /* Save off the requested flow control mode for use later.  Depending
5216          * on the link partner's capabilities, we may or may not use this mode.
5217          */
5218         hw->fc.current_mode = hw->fc.requested_mode;
5219
5220         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5221                 hw->fc.current_mode);
5222
5223         if (!hw->phy.ops.check_reset_block(hw)) {
5224                 /* Continue to configure the copper link. */
5225                 ret_val = hw->mac.ops.setup_physical_interface(hw);
5226                 if (ret_val)
5227                         return ret_val;
5228         }
5229
5230         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5231         if ((hw->phy.type == e1000_phy_82578) ||
5232             (hw->phy.type == e1000_phy_82579) ||
5233             (hw->phy.type == e1000_phy_i217) ||
5234             (hw->phy.type == e1000_phy_82577)) {
5235                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5236
5237                 ret_val = hw->phy.ops.write_reg(hw,
5238                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
5239                                              hw->fc.pause_time);
5240                 if (ret_val)
5241                         return ret_val;
5242         }
5243
5244         return e1000_set_fc_watermarks_generic(hw);
5245 }
5246
5247 /**
5248  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5249  *  @hw: pointer to the HW structure
5250  *
5251  *  Configures the kumeran interface to the PHY to wait the appropriate time
5252  *  when polling the PHY, then call the generic setup_copper_link to finish
5253  *  configuring the copper link.
5254  **/
5255 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5256 {
5257         u32 ctrl;
5258         s32 ret_val;
5259         u16 reg_data;
5260
5261         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5262
5263         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5264         ctrl |= E1000_CTRL_SLU;
5265         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5266         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5267
5268         /* Set the mac to wait the maximum time between each iteration
5269          * and increase the max iterations when polling the phy;
5270          * this fixes erroneous timeouts at 10Mbps.
5271          */
5272         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5273                                                0xFFFF);
5274         if (ret_val)
5275                 return ret_val;
5276         ret_val = e1000_read_kmrn_reg_generic(hw,
5277                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
5278                                               &reg_data);
5279         if (ret_val)
5280                 return ret_val;
5281         reg_data |= 0x3F;
5282         ret_val = e1000_write_kmrn_reg_generic(hw,
5283                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
5284                                                reg_data);
5285         if (ret_val)
5286                 return ret_val;
5287
5288         switch (hw->phy.type) {
5289         case e1000_phy_igp_3:
5290                 ret_val = e1000_copper_link_setup_igp(hw);
5291                 if (ret_val)
5292                         return ret_val;
5293                 break;
5294         case e1000_phy_bm:
5295         case e1000_phy_82578:
5296                 ret_val = e1000_copper_link_setup_m88(hw);
5297                 if (ret_val)
5298                         return ret_val;
5299                 break;
5300         case e1000_phy_82577:
5301         case e1000_phy_82579:
5302                 ret_val = e1000_copper_link_setup_82577(hw);
5303                 if (ret_val)
5304                         return ret_val;
5305                 break;
5306         case e1000_phy_ife:
5307                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5308                                                &reg_data);
5309                 if (ret_val)
5310                         return ret_val;
5311
5312                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5313
5314                 switch (hw->phy.mdix) {
5315                 case 1:
5316                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5317                         break;
5318                 case 2:
5319                         reg_data |= IFE_PMC_FORCE_MDIX;
5320                         break;
5321                 case 0:
5322                 default:
5323                         reg_data |= IFE_PMC_AUTO_MDIX;
5324                         break;
5325                 }
5326                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5327                                                 reg_data);
5328                 if (ret_val)
5329                         return ret_val;
5330                 break;
5331         default:
5332                 break;
5333         }
5334
5335         return e1000_setup_copper_link_generic(hw);
5336 }
5337
5338 /**
5339  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5340  *  @hw: pointer to the HW structure
5341  *
5342  *  Calls the PHY specific link setup function and then calls the
5343  *  generic setup_copper_link to finish configuring the link for
5344  *  Lynxpoint PCH devices
5345  **/
5346 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5347 {
5348         u32 ctrl;
5349         s32 ret_val;
5350
5351         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5352
5353         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5354         ctrl |= E1000_CTRL_SLU;
5355         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5356         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5357
5358         ret_val = e1000_copper_link_setup_82577(hw);
5359         if (ret_val)
5360                 return ret_val;
5361
5362         return e1000_setup_copper_link_generic(hw);
5363 }
5364
5365 /**
5366  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5367  *  @hw: pointer to the HW structure
5368  *  @speed: pointer to store current link speed
5369  *  @duplex: pointer to store the current link duplex
5370  *
5371  *  Calls the generic get_speed_and_duplex to retrieve the current link
5372  *  information and then calls the Kumeran lock loss workaround for links at
5373  *  gigabit speeds.
5374  **/
5375 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5376                                           u16 *duplex)
5377 {
5378         s32 ret_val;
5379
5380         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5381
5382         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5383         if (ret_val)
5384                 return ret_val;
5385
5386         if ((hw->mac.type == e1000_ich8lan) &&
5387             (hw->phy.type == e1000_phy_igp_3) &&
5388             (*speed == SPEED_1000)) {
5389                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5390         }
5391
5392         return ret_val;
5393 }
5394
5395 /**
5396  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5397  *  @hw: pointer to the HW structure
5398  *
5399  *  Work-around for 82566 Kumeran PCS lock loss:
5400  *  On link status change (i.e. PCI reset, speed change) and link is up and
5401  *  speed is gigabit-
5402  *    0) if workaround is optionally disabled do nothing
5403  *    1) wait 1ms for Kumeran link to come up
5404  *    2) check Kumeran Diagnostic register PCS lock loss bit
5405  *    3) if not set the link is locked (all is good), otherwise...
5406  *    4) reset the PHY
5407  *    5) repeat up to 10 times
5408  *  Note: this is only called for IGP3 copper when speed is 1gb.
5409  **/
5410 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5411 {
5412         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5413         u32 phy_ctrl;
5414         s32 ret_val;
5415         u16 i, data;
5416         bool link;
5417
5418         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5419
5420         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5421                 return E1000_SUCCESS;
5422
5423         /* Make sure link is up before proceeding.  If not just return.
5424          * Attempting this while link is negotiating fouled up link
5425          * stability
5426          */
5427         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5428         if (!link)
5429                 return E1000_SUCCESS;
5430
5431         for (i = 0; i < 10; i++) {
5432                 /* read once to clear */
5433                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5434                 if (ret_val)
5435                         return ret_val;
5436                 /* and again to get new status */
5437                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5438                 if (ret_val)
5439                         return ret_val;
5440
5441                 /* check for PCS lock */
5442                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5443                         return E1000_SUCCESS;
5444
5445                 /* Issue PHY reset */
5446                 hw->phy.ops.reset(hw);
5447                 msec_delay_irq(5);
5448         }
5449         /* Disable GigE link negotiation */
5450         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5451         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5452                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5453         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5454
5455         /* Call gig speed drop workaround on Gig disable before accessing
5456          * any PHY registers
5457          */
5458         e1000_gig_downshift_workaround_ich8lan(hw);
5459
5460         /* unable to acquire PCS lock */
5461         return -E1000_ERR_PHY;
5462 }
5463
5464 /**
5465  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5466  *  @hw: pointer to the HW structure
5467  *  @state: boolean value used to set the current Kumeran workaround state
5468  *
5469  *  If ICH8, set the current Kumeran workaround state (enabled - true
5470  *  /disabled - false).
5471  **/
5472 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5473                                                  bool state)
5474 {
5475         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5476
5477         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5478
5479         if (hw->mac.type != e1000_ich8lan) {
5480                 DEBUGOUT("Workaround applies to ICH8 only.\n");
5481                 return;
5482         }
5483
5484         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5485
5486         return;
5487 }
5488
5489 /**
5490  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5491  *  @hw: pointer to the HW structure
5492  *
5493  *  Workaround for 82566 power-down on D3 entry:
5494  *    1) disable gigabit link
5495  *    2) write VR power-down enable
5496  *    3) read it back
5497  *  Continue if successful, else issue LCD reset and repeat
5498  **/
5499 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5500 {
5501         u32 reg;
5502         u16 data;
5503         u8  retry = 0;
5504
5505         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5506
5507         if (hw->phy.type != e1000_phy_igp_3)
5508                 return;
5509
5510         /* Try the workaround twice (if needed) */
5511         do {
5512                 /* Disable link */
5513                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5514                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5515                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5516                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5517
5518                 /* Call gig speed drop workaround on Gig disable before
5519                  * accessing any PHY registers
5520                  */
5521                 if (hw->mac.type == e1000_ich8lan)
5522                         e1000_gig_downshift_workaround_ich8lan(hw);
5523
5524                 /* Write VR power-down enable */
5525                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5526                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5527                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5528                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5529
5530                 /* Read it back and test */
5531                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5532                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5533                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5534                         break;
5535
5536                 /* Issue PHY reset and repeat at most one more time */
5537                 reg = E1000_READ_REG(hw, E1000_CTRL);
5538                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5539                 retry++;
5540         } while (retry);
5541 }
5542
5543 /**
5544  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5545  *  @hw: pointer to the HW structure
5546  *
5547  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5548  *  LPLU, Gig disable, MDIC PHY reset):
5549  *    1) Set Kumeran Near-end loopback
5550  *    2) Clear Kumeran Near-end loopback
5551  *  Should only be called for ICH8[m] devices with any 1G Phy.
5552  **/
5553 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5554 {
5555         s32 ret_val;
5556         u16 reg_data = 0;
5557
5558         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5559
5560         if ((hw->mac.type != e1000_ich8lan) ||
5561             (hw->phy.type == e1000_phy_ife))
5562                 return;
5563
5564         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5565                                               &reg_data);
5566         if (ret_val)
5567                 return;
5568         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5569         ret_val = e1000_write_kmrn_reg_generic(hw,
5570                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
5571                                                reg_data);
5572         if (ret_val)
5573                 return;
5574         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5575         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5576                                      reg_data);
5577 }
5578
5579 /**
5580  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5581  *  @hw: pointer to the HW structure
5582  *
5583  *  During S0 to Sx transition, it is possible the link remains at gig
5584  *  instead of negotiating to a lower speed.  Before going to Sx, set
5585  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5586  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5587  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5588  *  needs to be written.
5589  *  Parts that support (and are linked to a partner which support) EEE in
5590  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5591  *  than 10Mbps w/o EEE.
5592  **/
5593 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5594 {
5595         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5596         u32 phy_ctrl;
5597         s32 ret_val;
5598
5599         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5600
5601         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5602         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5603
5604         if (hw->phy.type == e1000_phy_i217) {
5605                 u16 phy_reg, device_id = hw->device_id;
5606
5607                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5608                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5609                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5610                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5611                     (hw->mac.type >= e1000_pch_spt)) {
5612                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5613
5614                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5615                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5616                 }
5617
5618                 ret_val = hw->phy.ops.acquire(hw);
5619                 if (ret_val)
5620                         goto out;
5621
5622                 if (!dev_spec->eee_disable) {
5623                         u16 eee_advert;
5624
5625                         ret_val =
5626                             e1000_read_emi_reg_locked(hw,
5627                                                       I217_EEE_ADVERTISEMENT,
5628                                                       &eee_advert);
5629                         if (ret_val)
5630                                 goto release;
5631
5632                         /* Disable LPLU if both link partners support 100BaseT
5633                          * EEE and 100Full is advertised on both ends of the
5634                          * link, and enable Auto Enable LPI since there will
5635                          * be no driver to enable LPI while in Sx.
5636                          */
5637                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5638                             (dev_spec->eee_lp_ability &
5639                              I82579_EEE_100_SUPPORTED) &&
5640                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5641                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5642                                               E1000_PHY_CTRL_NOND0A_LPLU);
5643
5644                                 /* Set Auto Enable LPI after link up */
5645                                 hw->phy.ops.read_reg_locked(hw,
5646                                                             I217_LPI_GPIO_CTRL,
5647                                                             &phy_reg);
5648                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5649                                 hw->phy.ops.write_reg_locked(hw,
5650                                                              I217_LPI_GPIO_CTRL,
5651                                                              phy_reg);
5652                         }
5653                 }
5654
5655                 /* For i217 Intel Rapid Start Technology support,
5656                  * when the system is going into Sx and no manageability engine
5657                  * is present, the driver must configure proxy to reset only on
5658                  * power good.  LPI (Low Power Idle) state must also reset only
5659                  * on power good, as well as the MTA (Multicast table array).
5660                  * The SMBus release must also be disabled on LCD reset.
5661                  */
5662                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5663                       E1000_ICH_FWSM_FW_VALID)) {
5664                         /* Enable proxy to reset only on power good. */
5665                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5666                                                     &phy_reg);
5667                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5668                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5669                                                      phy_reg);
5670
5671                         /* Set bit enable LPI (EEE) to reset only on
5672                          * power good.
5673                         */
5674                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5675                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5676                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5677
5678                         /* Disable the SMB release on LCD reset. */
5679                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5680                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5681                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5682                 }
5683
5684                 /* Enable MTA to reset for Intel Rapid Start Technology
5685                  * Support
5686                  */
5687                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5688                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5689                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5690
5691 release:
5692                 hw->phy.ops.release(hw);
5693         }
5694 out:
5695         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5696
5697         if (hw->mac.type == e1000_ich8lan)
5698                 e1000_gig_downshift_workaround_ich8lan(hw);
5699
5700         if (hw->mac.type >= e1000_pchlan) {
5701                 e1000_oem_bits_config_ich8lan(hw, false);
5702
5703                 /* Reset PHY to activate OEM bits on 82577/8 */
5704                 if (hw->mac.type == e1000_pchlan)
5705                         e1000_phy_hw_reset_generic(hw);
5706
5707                 ret_val = hw->phy.ops.acquire(hw);
5708                 if (ret_val)
5709                         return;
5710                 e1000_write_smbus_addr(hw);
5711                 hw->phy.ops.release(hw);
5712         }
5713
5714         return;
5715 }
5716
5717 /**
5718  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5719  *  @hw: pointer to the HW structure
5720  *
5721  *  During Sx to S0 transitions on non-managed devices or managed devices
5722  *  on which PHY resets are not blocked, if the PHY registers cannot be
5723  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5724  *  the PHY.
5725  *  On i217, setup Intel Rapid Start Technology.
5726  **/
5727 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5728 {
5729         s32 ret_val;
5730
5731         DEBUGFUNC("e1000_resume_workarounds_pchlan");
5732         if (hw->mac.type < e1000_pch2lan)
5733                 return E1000_SUCCESS;
5734
5735         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5736         if (ret_val) {
5737                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5738                 return ret_val;
5739         }
5740
5741         /* For i217 Intel Rapid Start Technology support when the system
5742          * is transitioning from Sx and no manageability engine is present
5743          * configure SMBus to restore on reset, disable proxy, and enable
5744          * the reset on MTA (Multicast table array).
5745          */
5746         if (hw->phy.type == e1000_phy_i217) {
5747                 u16 phy_reg;
5748
5749                 ret_val = hw->phy.ops.acquire(hw);
5750                 if (ret_val) {
5751                         DEBUGOUT("Failed to setup iRST\n");
5752                         return ret_val;
5753                 }
5754
5755                 /* Clear Auto Enable LPI after link up */
5756                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5757                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5758                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5759
5760                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5761                     E1000_ICH_FWSM_FW_VALID)) {
5762                         /* Restore clear on SMB if no manageability engine
5763                          * is present
5764                          */
5765                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5766                                                               &phy_reg);
5767                         if (ret_val)
5768                                 goto release;
5769                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5770                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5771
5772                         /* Disable Proxy */
5773                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5774                 }
5775                 /* Enable reset on MTA */
5776                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5777                                                       &phy_reg);
5778                 if (ret_val)
5779                         goto release;
5780                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5781                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5782 release:
5783                 if (ret_val)
5784                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5785                 hw->phy.ops.release(hw);
5786                 return ret_val;
5787         }
5788         return E1000_SUCCESS;
5789 }
5790
5791 /**
5792  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5793  *  @hw: pointer to the HW structure
5794  *
5795  *  Return the LED back to the default configuration.
5796  **/
5797 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5798 {
5799         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5800
5801         if (hw->phy.type == e1000_phy_ife)
5802                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5803                                              0);
5804
5805         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5806         return E1000_SUCCESS;
5807 }
5808
5809 /**
5810  *  e1000_led_on_ich8lan - Turn LEDs on
5811  *  @hw: pointer to the HW structure
5812  *
5813  *  Turn on the LEDs.
5814  **/
5815 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5816 {
5817         DEBUGFUNC("e1000_led_on_ich8lan");
5818
5819         if (hw->phy.type == e1000_phy_ife)
5820                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5821                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5822
5823         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5824         return E1000_SUCCESS;
5825 }
5826
5827 /**
5828  *  e1000_led_off_ich8lan - Turn LEDs off
5829  *  @hw: pointer to the HW structure
5830  *
5831  *  Turn off the LEDs.
5832  **/
5833 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5834 {
5835         DEBUGFUNC("e1000_led_off_ich8lan");
5836
5837         if (hw->phy.type == e1000_phy_ife)
5838                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5839                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5840
5841         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5842         return E1000_SUCCESS;
5843 }
5844
5845 /**
5846  *  e1000_setup_led_pchlan - Configures SW controllable LED
5847  *  @hw: pointer to the HW structure
5848  *
5849  *  This prepares the SW controllable LED for use.
5850  **/
5851 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5852 {
5853         DEBUGFUNC("e1000_setup_led_pchlan");
5854
5855         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5856                                      (u16)hw->mac.ledctl_mode1);
5857 }
5858
5859 /**
5860  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5861  *  @hw: pointer to the HW structure
5862  *
5863  *  Return the LED back to the default configuration.
5864  **/
5865 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5866 {
5867         DEBUGFUNC("e1000_cleanup_led_pchlan");
5868
5869         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5870                                      (u16)hw->mac.ledctl_default);
5871 }
5872
5873 /**
5874  *  e1000_led_on_pchlan - Turn LEDs on
5875  *  @hw: pointer to the HW structure
5876  *
5877  *  Turn on the LEDs.
5878  **/
5879 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5880 {
5881         u16 data = (u16)hw->mac.ledctl_mode2;
5882         u32 i, led;
5883
5884         DEBUGFUNC("e1000_led_on_pchlan");
5885
5886         /* If no link, then turn LED on by setting the invert bit
5887          * for each LED that's mode is "link_up" in ledctl_mode2.
5888          */
5889         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5890                 for (i = 0; i < 3; i++) {
5891                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5892                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5893                             E1000_LEDCTL_MODE_LINK_UP)
5894                                 continue;
5895                         if (led & E1000_PHY_LED0_IVRT)
5896                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5897                         else
5898                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5899                 }
5900         }
5901
5902         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5903 }
5904
5905 /**
5906  *  e1000_led_off_pchlan - Turn LEDs off
5907  *  @hw: pointer to the HW structure
5908  *
5909  *  Turn off the LEDs.
5910  **/
5911 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5912 {
5913         u16 data = (u16)hw->mac.ledctl_mode1;
5914         u32 i, led;
5915
5916         DEBUGFUNC("e1000_led_off_pchlan");
5917
5918         /* If no link, then turn LED off by clearing the invert bit
5919          * for each LED that's mode is "link_up" in ledctl_mode1.
5920          */
5921         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5922                 for (i = 0; i < 3; i++) {
5923                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5924                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5925                             E1000_LEDCTL_MODE_LINK_UP)
5926                                 continue;
5927                         if (led & E1000_PHY_LED0_IVRT)
5928                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5929                         else
5930                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5931                 }
5932         }
5933
5934         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5935 }
5936
5937 /**
5938  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5939  *  @hw: pointer to the HW structure
5940  *
5941  *  Read appropriate register for the config done bit for completion status
5942  *  and configure the PHY through s/w for EEPROM-less parts.
5943  *
5944  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5945  *  config done bit, so only an error is logged and continues.  If we were
5946  *  to return with error, EEPROM-less silicon would not be able to be reset
5947  *  or change link.
5948  **/
5949 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5950 {
5951         s32 ret_val = E1000_SUCCESS;
5952         u32 bank = 0;
5953         u32 status;
5954
5955         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5956
5957         e1000_get_cfg_done_generic(hw);
5958
5959         /* Wait for indication from h/w that it has completed basic config */
5960         if (hw->mac.type >= e1000_ich10lan) {
5961                 e1000_lan_init_done_ich8lan(hw);
5962         } else {
5963                 ret_val = e1000_get_auto_rd_done_generic(hw);
5964                 if (ret_val) {
5965                         /* When auto config read does not complete, do not
5966                          * return with an error. This can happen in situations
5967                          * where there is no eeprom and prevents getting link.
5968                          */
5969                         DEBUGOUT("Auto Read Done did not complete\n");
5970                         ret_val = E1000_SUCCESS;
5971                 }
5972         }
5973
5974         /* Clear PHY Reset Asserted bit */
5975         status = E1000_READ_REG(hw, E1000_STATUS);
5976         if (status & E1000_STATUS_PHYRA)
5977                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5978         else
5979                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5980
5981         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5982         if (hw->mac.type <= e1000_ich9lan) {
5983                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5984                     (hw->phy.type == e1000_phy_igp_3)) {
5985                         e1000_phy_init_script_igp3(hw);
5986                 }
5987         } else {
5988                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5989                         /* Maybe we should do a basic PHY config */
5990                         DEBUGOUT("EEPROM not present\n");
5991                         ret_val = -E1000_ERR_CONFIG;
5992                 }
5993         }
5994
5995         return ret_val;
5996 }
5997
5998 /**
5999  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6000  * @hw: pointer to the HW structure
6001  *
6002  * In the case of a PHY power down to save power, or to turn off link during a
6003  * driver unload, or wake on lan is not enabled, remove the link.
6004  **/
6005 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6006 {
6007         /* If the management interface is not enabled, then power down */
6008         if (!(hw->mac.ops.check_mng_mode(hw) ||
6009               hw->phy.ops.check_reset_block(hw)))
6010                 e1000_power_down_phy_copper(hw);
6011
6012         return;
6013 }
6014
6015 /**
6016  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6017  *  @hw: pointer to the HW structure
6018  *
6019  *  Clears hardware counters specific to the silicon family and calls
6020  *  clear_hw_cntrs_generic to clear all general purpose counters.
6021  **/
6022 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6023 {
6024         u16 phy_data;
6025         s32 ret_val;
6026
6027         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6028
6029         e1000_clear_hw_cntrs_base_generic(hw);
6030
6031         E1000_READ_REG(hw, E1000_ALGNERRC);
6032         E1000_READ_REG(hw, E1000_RXERRC);
6033         E1000_READ_REG(hw, E1000_TNCRS);
6034         E1000_READ_REG(hw, E1000_CEXTERR);
6035         E1000_READ_REG(hw, E1000_TSCTC);
6036         E1000_READ_REG(hw, E1000_TSCTFC);
6037
6038         E1000_READ_REG(hw, E1000_MGTPRC);
6039         E1000_READ_REG(hw, E1000_MGTPDC);
6040         E1000_READ_REG(hw, E1000_MGTPTC);
6041
6042         E1000_READ_REG(hw, E1000_IAC);
6043         E1000_READ_REG(hw, E1000_ICRXOC);
6044
6045         /* Clear PHY statistics registers */
6046         if ((hw->phy.type == e1000_phy_82578) ||
6047             (hw->phy.type == e1000_phy_82579) ||
6048             (hw->phy.type == e1000_phy_i217) ||
6049             (hw->phy.type == e1000_phy_82577)) {
6050                 ret_val = hw->phy.ops.acquire(hw);
6051                 if (ret_val)
6052                         return;
6053                 ret_val = hw->phy.ops.set_page(hw,
6054                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
6055                 if (ret_val)
6056                         goto release;
6057                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6058                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6059                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6060                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6061                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6062                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6063                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6064                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6065                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6066                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6067                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6068                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6069                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6070                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6071 release:
6072                 hw->phy.ops.release(hw);
6073         }
6074 }
6075
6076 /**
6077  *  e1000_configure_k0s_lpt - Configure K0s power state
6078  *  @hw: pointer to the HW structure
6079  *  @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6080  *      0 corresponds to 128ns, each value over 0 doubles the duration.
6081  *  @min_time: Minimum Tx idle period allowed  - valid values are 0 to 4.
6082  *      0 corresponds to 128ns, each value over 0 doubles the duration.
6083  *
6084  *  Configure the K1 power state based on the provided parameter.
6085  *  Assumes semaphore already acquired.
6086  *
6087  *  Success returns 0, Failure returns:
6088  *      -E1000_ERR_PHY (-2) in case of access error
6089  *      -E1000_ERR_PARAM (-4) in case of parameters error
6090  **/
6091 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6092 {
6093         s32 ret_val;
6094         u16 kmrn_reg = 0;
6095
6096         DEBUGFUNC("e1000_configure_k0s_lpt");
6097
6098         if (entry_latency > 3 || min_time > 4)
6099                 return -E1000_ERR_PARAM;
6100
6101         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6102                                              &kmrn_reg);
6103         if (ret_val)
6104                 return ret_val;
6105
6106         /* for now don't touch the latency */
6107         kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6108         kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6109
6110         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6111                                               kmrn_reg);
6112         if (ret_val)
6113                 return ret_val;
6114
6115         return E1000_SUCCESS;
6116 }