1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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32 ***************************************************************************/
34 /* 82562G 10/100 Network Connection
35 * 82562G-2 10/100 Network Connection
36 * 82562GT 10/100 Network Connection
37 * 82562GT-2 10/100 Network Connection
38 * 82562V 10/100 Network Connection
39 * 82562V-2 10/100 Network Connection
40 * 82566DC-2 Gigabit Network Connection
41 * 82566DC Gigabit Network Connection
42 * 82566DM-2 Gigabit Network Connection
43 * 82566DM Gigabit Network Connection
44 * 82566MC Gigabit Network Connection
45 * 82566MM Gigabit Network Connection
46 * 82567LM Gigabit Network Connection
47 * 82567LF Gigabit Network Connection
48 * 82567V Gigabit Network Connection
49 * 82567LM-2 Gigabit Network Connection
50 * 82567LF-2 Gigabit Network Connection
51 * 82567V-2 Gigabit Network Connection
52 * 82567LF-3 Gigabit Network Connection
53 * 82567LM-3 Gigabit Network Connection
54 * 82567LM-4 Gigabit Network Connection
55 * 82577LM Gigabit Network Connection
56 * 82577LC Gigabit Network Connection
57 * 82578DM Gigabit Network Connection
58 * 82578DC Gigabit Network Connection
59 * 82579LM Gigabit Network Connection
60 * 82579V Gigabit Network Connection
61 * Ethernet Connection I217-LM
62 * Ethernet Connection I217-V
63 * Ethernet Connection I218-V
64 * Ethernet Connection I218-LM
65 * Ethernet Connection (2) I218-LM
66 * Ethernet Connection (2) I218-V
67 * Ethernet Connection (3) I218-LM
68 * Ethernet Connection (3) I218-V
71 #include "e1000_api.h"
73 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
74 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
84 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
87 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
88 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
89 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
90 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
91 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
93 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
95 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
98 u16 words, u16 *data);
99 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
100 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
103 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
104 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
105 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
106 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
107 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
108 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
109 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
110 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
111 u16 *speed, u16 *duplex);
112 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
113 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
114 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
115 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
116 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
117 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
118 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
119 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
120 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
121 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
122 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
123 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
124 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
125 u32 offset, u8 *data);
126 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
128 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
129 u32 offset, u16 *data);
130 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
131 u32 offset, u8 byte);
132 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
133 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
134 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
135 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
136 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
137 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
139 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
140 /* Offset 04h HSFSTS */
141 union ich8_hws_flash_status {
143 u16 flcdone:1; /* bit 0 Flash Cycle Done */
144 u16 flcerr:1; /* bit 1 Flash Cycle Error */
145 u16 dael:1; /* bit 2 Direct Access error Log */
146 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
147 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
148 u16 reserved1:2; /* bit 13:6 Reserved */
149 u16 reserved2:6; /* bit 13:6 Reserved */
150 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
151 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
156 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
157 /* Offset 06h FLCTL */
158 union ich8_hws_flash_ctrl {
159 struct ich8_hsflctl {
160 u16 flcgo:1; /* 0 Flash Cycle Go */
161 u16 flcycle:2; /* 2:1 Flash Cycle */
162 u16 reserved:5; /* 7:3 Reserved */
163 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
164 u16 flockdn:6; /* 15:10 Reserved */
169 /* ICH Flash Region Access Permissions */
170 union ich8_hws_flash_regacc {
172 u32 grra:8; /* 0:7 GbE region Read Access */
173 u32 grwa:8; /* 8:15 GbE region Write Access */
174 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
175 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
181 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
182 * @hw: pointer to the HW structure
184 * Test access to the PHY registers by reading the PHY ID registers. If
185 * the PHY ID is already known (e.g. resume path) compare it with known ID,
186 * otherwise assume the read PHY ID is correct if it is valid.
188 * Assumes the sw/fw/hw semaphore is already acquired.
190 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
198 for (retry_count = 0; retry_count < 2; retry_count++) {
199 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
200 if (ret_val || (phy_reg == 0xFFFF))
202 phy_id = (u32)(phy_reg << 16);
204 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
205 if (ret_val || (phy_reg == 0xFFFF)) {
209 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
214 if (hw->phy.id == phy_id)
218 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
222 /* In case the PHY needs to be in mdio slow mode,
223 * set slow mode and try to get the PHY id again.
225 if (hw->mac.type < e1000_pch_lpt) {
226 hw->phy.ops.release(hw);
227 ret_val = e1000_set_mdio_slow_mode_hv(hw);
229 ret_val = e1000_get_phy_id(hw);
230 hw->phy.ops.acquire(hw);
236 if (hw->mac.type == e1000_pch_lpt) {
237 /* Only unforce SMBus if ME is not active */
238 if (!(E1000_READ_REG(hw, E1000_FWSM) &
239 E1000_ICH_FWSM_FW_VALID)) {
240 /* Unforce SMBus mode in PHY */
241 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
242 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
243 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
245 /* Unforce SMBus mode in MAC */
246 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
247 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
248 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
256 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
257 * @hw: pointer to the HW structure
259 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
260 * used to reset the PHY to a quiescent state when necessary.
262 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
266 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
268 /* Set Phy Config Counter to 50msec */
269 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
270 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
271 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
272 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
274 /* Toggle LANPHYPC Value bit */
275 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
276 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
277 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
278 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
279 E1000_WRITE_FLUSH(hw);
281 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
282 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
283 E1000_WRITE_FLUSH(hw);
285 if (hw->mac.type < e1000_pch_lpt) {
292 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
293 E1000_CTRL_EXT_LPCD) && count--);
300 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
301 * @hw: pointer to the HW structure
303 * Workarounds/flow necessary for PHY initialization during driver load
306 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
308 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
311 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
313 /* Gate automatic PHY configuration by hardware on managed and
314 * non-managed 82579 and newer adapters.
316 e1000_gate_hw_phy_config_ich8lan(hw, true);
319 /* It is not possible to be certain of the current state of ULP
320 * so forcibly disable it.
322 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
324 #endif /* ULP_SUPPORT */
325 ret_val = hw->phy.ops.acquire(hw);
327 DEBUGOUT("Failed to initialize PHY flow\n");
331 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
332 * inaccessible and resetting the PHY is not blocked, toggle the
333 * LANPHYPC Value bit to force the interconnect to PCIe mode.
335 switch (hw->mac.type) {
337 if (e1000_phy_is_accessible_pchlan(hw))
340 /* Before toggling LANPHYPC, see if PHY is accessible by
341 * forcing MAC to SMBus mode first.
343 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
344 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
345 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
347 /* Wait 50 milliseconds for MAC to finish any retries
348 * that it might be trying to perform from previous
349 * attempts to acknowledge any phy read requests.
355 if (e1000_phy_is_accessible_pchlan(hw))
360 if ((hw->mac.type == e1000_pchlan) &&
361 (fwsm & E1000_ICH_FWSM_FW_VALID))
364 if (hw->phy.ops.check_reset_block(hw)) {
365 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
366 ret_val = -E1000_ERR_PHY;
370 /* Toggle LANPHYPC Value bit */
371 e1000_toggle_lanphypc_pch_lpt(hw);
372 if (hw->mac.type >= e1000_pch_lpt) {
373 if (e1000_phy_is_accessible_pchlan(hw))
376 /* Toggling LANPHYPC brings the PHY out of SMBus mode
377 * so ensure that the MAC is also out of SMBus mode
379 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
380 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
381 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
383 if (e1000_phy_is_accessible_pchlan(hw))
386 ret_val = -E1000_ERR_PHY;
393 hw->phy.ops.release(hw);
396 /* Check to see if able to reset PHY. Print error if not */
397 if (hw->phy.ops.check_reset_block(hw)) {
398 ERROR_REPORT("Reset blocked by ME\n");
402 /* Reset the PHY before any access to it. Doing so, ensures
403 * that the PHY is in a known good state before we read/write
404 * PHY registers. The generic reset is sufficient here,
405 * because we haven't determined the PHY type yet.
407 ret_val = e1000_phy_hw_reset_generic(hw);
411 /* On a successful reset, possibly need to wait for the PHY
412 * to quiesce to an accessible state before returning control
413 * to the calling function. If the PHY does not quiesce, then
414 * return E1000E_BLK_PHY_RESET, as this is the condition that
417 ret_val = hw->phy.ops.check_reset_block(hw);
419 ERROR_REPORT("ME blocked access to PHY after reset\n");
423 /* Ungate automatic PHY configuration on non-managed 82579 */
424 if ((hw->mac.type == e1000_pch2lan) &&
425 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
427 e1000_gate_hw_phy_config_ich8lan(hw, false);
434 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
435 * @hw: pointer to the HW structure
437 * Initialize family-specific PHY parameters and function pointers.
439 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
441 struct e1000_phy_info *phy = &hw->phy;
444 DEBUGFUNC("e1000_init_phy_params_pchlan");
447 phy->reset_delay_us = 100;
449 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
450 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
451 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
452 phy->ops.set_page = e1000_set_page_igp;
453 phy->ops.read_reg = e1000_read_phy_reg_hv;
454 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
455 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
456 phy->ops.release = e1000_release_swflag_ich8lan;
457 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
458 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
459 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
460 phy->ops.write_reg = e1000_write_phy_reg_hv;
461 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
462 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
463 phy->ops.power_up = e1000_power_up_phy_copper;
464 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
465 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
467 phy->id = e1000_phy_unknown;
469 ret_val = e1000_init_phy_workarounds_pchlan(hw);
473 if (phy->id == e1000_phy_unknown)
474 switch (hw->mac.type) {
476 ret_val = e1000_get_phy_id(hw);
479 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
484 /* In case the PHY needs to be in mdio slow mode,
485 * set slow mode and try to get the PHY id again.
487 ret_val = e1000_set_mdio_slow_mode_hv(hw);
490 ret_val = e1000_get_phy_id(hw);
495 phy->type = e1000_get_phy_type_from_id(phy->id);
498 case e1000_phy_82577:
499 case e1000_phy_82579:
501 phy->ops.check_polarity = e1000_check_polarity_82577;
502 phy->ops.force_speed_duplex =
503 e1000_phy_force_speed_duplex_82577;
504 phy->ops.get_cable_length = e1000_get_cable_length_82577;
505 phy->ops.get_info = e1000_get_phy_info_82577;
506 phy->ops.commit = e1000_phy_sw_reset_generic;
508 case e1000_phy_82578:
509 phy->ops.check_polarity = e1000_check_polarity_m88;
510 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
511 phy->ops.get_cable_length = e1000_get_cable_length_m88;
512 phy->ops.get_info = e1000_get_phy_info_m88;
515 ret_val = -E1000_ERR_PHY;
523 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
524 * @hw: pointer to the HW structure
526 * Initialize family-specific PHY parameters and function pointers.
528 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
530 struct e1000_phy_info *phy = &hw->phy;
534 DEBUGFUNC("e1000_init_phy_params_ich8lan");
537 phy->reset_delay_us = 100;
539 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
540 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
541 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
542 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
543 phy->ops.read_reg = e1000_read_phy_reg_igp;
544 phy->ops.release = e1000_release_swflag_ich8lan;
545 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
546 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
547 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
548 phy->ops.write_reg = e1000_write_phy_reg_igp;
549 phy->ops.power_up = e1000_power_up_phy_copper;
550 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
552 /* We may need to do this twice - once for IGP and if that fails,
553 * we'll set BM func pointers and try again
555 ret_val = e1000_determine_phy_address(hw);
557 phy->ops.write_reg = e1000_write_phy_reg_bm;
558 phy->ops.read_reg = e1000_read_phy_reg_bm;
559 ret_val = e1000_determine_phy_address(hw);
561 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
567 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
570 ret_val = e1000_get_phy_id(hw);
577 case IGP03E1000_E_PHY_ID:
578 phy->type = e1000_phy_igp_3;
579 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
580 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
581 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
582 phy->ops.get_info = e1000_get_phy_info_igp;
583 phy->ops.check_polarity = e1000_check_polarity_igp;
584 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
587 case IFE_PLUS_E_PHY_ID:
589 phy->type = e1000_phy_ife;
590 phy->autoneg_mask = E1000_ALL_NOT_GIG;
591 phy->ops.get_info = e1000_get_phy_info_ife;
592 phy->ops.check_polarity = e1000_check_polarity_ife;
593 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
595 case BME1000_E_PHY_ID:
596 phy->type = e1000_phy_bm;
597 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
598 phy->ops.read_reg = e1000_read_phy_reg_bm;
599 phy->ops.write_reg = e1000_write_phy_reg_bm;
600 phy->ops.commit = e1000_phy_sw_reset_generic;
601 phy->ops.get_info = e1000_get_phy_info_m88;
602 phy->ops.check_polarity = e1000_check_polarity_m88;
603 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
606 return -E1000_ERR_PHY;
610 return E1000_SUCCESS;
614 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
615 * @hw: pointer to the HW structure
617 * Initialize family-specific NVM parameters and function
620 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
622 struct e1000_nvm_info *nvm = &hw->nvm;
623 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
624 u32 gfpreg, sector_base_addr, sector_end_addr;
627 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
629 /* Can't read flash registers if the register set isn't mapped. */
630 nvm->type = e1000_nvm_flash_sw;
631 if (!hw->flash_address) {
632 DEBUGOUT("ERROR: Flash registers not mapped\n");
633 return -E1000_ERR_CONFIG;
636 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
638 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
639 * Add 1 to sector_end_addr since this sector is included in
642 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
643 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
645 /* flash_base_addr is byte-aligned */
646 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
648 /* find total size of the NVM, then cut in half since the total
649 * size represents two separate NVM banks.
651 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
652 << FLASH_SECTOR_ADDR_SHIFT);
653 nvm->flash_bank_size /= 2;
654 /* Adjust to word count */
655 nvm->flash_bank_size /= sizeof(u16);
657 nvm->word_size = E1000_SHADOW_RAM_WORDS;
659 /* Clear shadow ram */
660 for (i = 0; i < nvm->word_size; i++) {
661 dev_spec->shadow_ram[i].modified = false;
662 dev_spec->shadow_ram[i].value = 0xFFFF;
665 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
666 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
668 /* Function Pointers */
669 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
670 nvm->ops.release = e1000_release_nvm_ich8lan;
671 nvm->ops.read = e1000_read_nvm_ich8lan;
672 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
673 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
674 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
675 nvm->ops.write = e1000_write_nvm_ich8lan;
677 return E1000_SUCCESS;
681 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
682 * @hw: pointer to the HW structure
684 * Initialize family-specific MAC parameters and function
687 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
689 struct e1000_mac_info *mac = &hw->mac;
690 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
692 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
694 DEBUGFUNC("e1000_init_mac_params_ich8lan");
696 /* Set media type function pointer */
697 hw->phy.media_type = e1000_media_type_copper;
699 /* Set mta register count */
700 mac->mta_reg_count = 32;
701 /* Set rar entry count */
702 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
703 if (mac->type == e1000_ich8lan)
704 mac->rar_entry_count--;
705 /* Set if part includes ASF firmware */
706 mac->asf_firmware_present = true;
708 mac->has_fwsm = true;
709 /* ARC subsystem not supported */
710 mac->arc_subsystem_valid = false;
711 /* Adaptive IFS supported */
712 mac->adaptive_ifs = true;
714 /* Function pointers */
716 /* bus type/speed/width */
717 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
719 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
721 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
722 /* hw initialization */
723 mac->ops.init_hw = e1000_init_hw_ich8lan;
725 mac->ops.setup_link = e1000_setup_link_ich8lan;
726 /* physical interface setup */
727 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
729 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
731 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
732 /* multicast address update */
733 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
734 /* clear hardware counters */
735 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
737 /* LED and other operations */
742 /* check management mode */
743 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
745 mac->ops.id_led_init = e1000_id_led_init_generic;
747 mac->ops.blink_led = e1000_blink_led_generic;
749 mac->ops.setup_led = e1000_setup_led_generic;
751 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
752 /* turn on/off LED */
753 mac->ops.led_on = e1000_led_on_ich8lan;
754 mac->ops.led_off = e1000_led_off_ich8lan;
757 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
758 mac->ops.rar_set = e1000_rar_set_pch2lan;
761 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
762 /* multicast address update for pch2 */
763 mac->ops.update_mc_addr_list =
764 e1000_update_mc_addr_list_pch2lan;
768 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
769 /* save PCH revision_id */
770 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
771 hw->revision_id = (u8)(pci_cfg &= 0x000F);
772 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
773 /* check management mode */
774 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
776 mac->ops.id_led_init = e1000_id_led_init_pchlan;
778 mac->ops.setup_led = e1000_setup_led_pchlan;
780 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
781 /* turn on/off LED */
782 mac->ops.led_on = e1000_led_on_pchlan;
783 mac->ops.led_off = e1000_led_off_pchlan;
789 if (mac->type == e1000_pch_lpt) {
790 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
791 mac->ops.rar_set = e1000_rar_set_pch_lpt;
792 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
795 /* Enable PCS Lock-loss workaround for ICH8 */
796 if (mac->type == e1000_ich8lan)
797 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
799 return E1000_SUCCESS;
803 * __e1000_access_emi_reg_locked - Read/write EMI register
804 * @hw: pointer to the HW structure
805 * @addr: EMI address to program
806 * @data: pointer to value to read/write from/to the EMI address
807 * @read: boolean flag to indicate read or write
809 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
811 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
812 u16 *data, bool read)
816 DEBUGFUNC("__e1000_access_emi_reg_locked");
818 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
823 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
826 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
833 * e1000_read_emi_reg_locked - Read Extended Management Interface register
834 * @hw: pointer to the HW structure
835 * @addr: EMI address to program
836 * @data: value to be read from the EMI address
838 * Assumes the SW/FW/HW Semaphore is already acquired.
840 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
842 DEBUGFUNC("e1000_read_emi_reg_locked");
844 return __e1000_access_emi_reg_locked(hw, addr, data, true);
848 * e1000_write_emi_reg_locked - Write Extended Management Interface register
849 * @hw: pointer to the HW structure
850 * @addr: EMI address to program
851 * @data: value to be written to the EMI address
853 * Assumes the SW/FW/HW Semaphore is already acquired.
855 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
857 DEBUGFUNC("e1000_read_emi_reg_locked");
859 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
863 * e1000_set_eee_pchlan - Enable/disable EEE support
864 * @hw: pointer to the HW structure
866 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
867 * the link and the EEE capabilities of the link partner. The LPI Control
868 * register bits will remain set only if/when link is up.
870 * EEE LPI must not be asserted earlier than one second after link is up.
871 * On 82579, EEE LPI should not be enabled until such time otherwise there
872 * can be link issues with some switches. Other devices can have EEE LPI
873 * enabled immediately upon link up since they have a timer in hardware which
874 * prevents LPI from being asserted too early.
876 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
878 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
880 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
882 DEBUGFUNC("e1000_set_eee_pchlan");
884 switch (hw->phy.type) {
885 case e1000_phy_82579:
886 lpa = I82579_EEE_LP_ABILITY;
887 pcs_status = I82579_EEE_PCS_STATUS;
888 adv_addr = I82579_EEE_ADVERTISEMENT;
891 lpa = I217_EEE_LP_ABILITY;
892 pcs_status = I217_EEE_PCS_STATUS;
893 adv_addr = I217_EEE_ADVERTISEMENT;
896 return E1000_SUCCESS;
899 ret_val = hw->phy.ops.acquire(hw);
903 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
907 /* Clear bits that enable EEE in various speeds */
908 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
910 /* Enable EEE if not disabled by user */
911 if (!dev_spec->eee_disable) {
912 /* Save off link partner's EEE ability */
913 ret_val = e1000_read_emi_reg_locked(hw, lpa,
914 &dev_spec->eee_lp_ability);
918 /* Read EEE advertisement */
919 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
923 /* Enable EEE only for speeds in which the link partner is
924 * EEE capable and for which we advertise EEE.
926 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
927 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
929 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
930 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
931 if (data & NWAY_LPAR_100TX_FD_CAPS)
932 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
934 /* EEE is not supported in 100Half, so ignore
935 * partner's EEE in 100 ability if full-duplex
938 dev_spec->eee_lp_ability &=
939 ~I82579_EEE_100_SUPPORTED;
943 if (hw->phy.type == e1000_phy_82579) {
944 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
949 data &= ~I82579_LPI_100_PLL_SHUT;
950 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
954 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
955 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
959 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
961 hw->phy.ops.release(hw);
967 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
968 * @hw: pointer to the HW structure
969 * @link: link up bool flag
971 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
972 * preventing further DMA write requests. Workaround the issue by disabling
973 * the de-assertion of the clock request when in 1Gpbs mode.
974 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
975 * speeds in order to avoid Tx hangs.
977 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
979 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
980 u32 status = E1000_READ_REG(hw, E1000_STATUS);
981 s32 ret_val = E1000_SUCCESS;
984 if (link && (status & E1000_STATUS_SPEED_1000)) {
985 ret_val = hw->phy.ops.acquire(hw);
990 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
996 e1000_write_kmrn_reg_locked(hw,
997 E1000_KMRNCTRLSTA_K1_CONFIG,
999 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1005 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1006 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1009 e1000_write_kmrn_reg_locked(hw,
1010 E1000_KMRNCTRLSTA_K1_CONFIG,
1013 hw->phy.ops.release(hw);
1015 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1016 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1018 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1019 (status & E1000_STATUS_FD)))
1020 goto update_fextnvm6;
1022 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1026 /* Clear link status transmit timeout */
1027 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1029 if (status & E1000_STATUS_SPEED_100) {
1030 /* Set inband Tx timeout to 5x10us for 100Half */
1031 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1033 /* Do not extend the K1 entry latency for 100Half */
1034 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1036 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1038 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1040 /* Extend the K1 entry latency for 10 Mbps */
1041 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1044 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1049 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1057 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1058 * @hw: pointer to the HW structure
1059 * @to_sx: boolean indicating a system power state transition to Sx
1061 * When link is down, configure ULP mode to significantly reduce the power
1062 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1063 * ME firmware to start the ULP configuration. If not on an ME enabled
1064 * system, configure the ULP mode by software.
1066 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1069 s32 ret_val = E1000_SUCCESS;
1072 if ((hw->mac.type < e1000_pch_lpt) ||
1073 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1074 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1075 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1076 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1077 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1082 /* Poll up to 5 seconds for Cable Disconnected indication */
1083 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1084 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1085 /* Bail if link is re-acquired */
1086 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1087 return -E1000_ERR_PHY;
1093 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1094 (E1000_READ_REG(hw, E1000_FEXT) &
1095 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1097 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1098 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1102 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103 /* Request ME configure ULP mode in the PHY */
1104 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1105 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1111 ret_val = hw->phy.ops.acquire(hw);
1115 /* During S0 Idle keep the phy in PCI-E mode */
1116 if (hw->dev_spec.ich8lan.smbus_disable)
1119 /* Force SMBus mode in PHY */
1120 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1123 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1124 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1126 /* Force SMBus mode in MAC */
1127 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1128 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1129 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1133 /* Change the 'Link Status Change' interrupt to trigger
1134 * on 'Cable Status Change'
1136 ret_val = e1000_read_kmrn_reg_locked(hw,
1137 E1000_KMRNCTRLSTA_OP_MODES,
1141 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1142 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1146 /* Set Inband ULP Exit, Reset to SMBus mode and
1147 * Disable SMBus Release on PERST# in PHY
1149 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1152 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1153 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1155 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1156 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1158 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1160 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1161 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1163 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1164 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1165 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1167 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1169 /* Set Disable SMBus Release on PERST# in MAC */
1170 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1171 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1172 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1174 /* Commit ULP changes in PHY by starting auto ULP configuration */
1175 phy_reg |= I218_ULP_CONFIG1_START;
1176 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1179 /* Disable Tx so that the MAC doesn't send any (buffered)
1180 * packets to the PHY.
1182 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1183 mac_reg &= ~E1000_TCTL_EN;
1184 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1188 hw->phy.ops.release(hw);
1191 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1193 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1199 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1200 * @hw: pointer to the HW structure
1201 * @force: boolean indicating whether or not to force disabling ULP
1203 * Un-configure ULP mode when link is up, the system is transitioned from
1204 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1205 * system, poll for an indication from ME that ULP has been un-configured.
1206 * If not on an ME enabled system, un-configure the ULP mode by software.
1208 * During nominal operation, this function is called when link is acquired
1209 * to disable ULP mode (force=false); otherwise, for example when unloading
1210 * the driver or during Sx->S0 transitions, this is called with force=true
1211 * to forcibly disable ULP.
1213 * When the cable is plugged in while the device is in D0, a Cable Status
1214 * Change interrupt is generated which causes this function to be called
1215 * to partially disable ULP mode and restart autonegotiation. This function
1216 * is then called again due to the resulting Link Status Change interrupt
1217 * to finish cleaning up after the ULP flow.
1219 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1221 s32 ret_val = E1000_SUCCESS;
1226 if ((hw->mac.type < e1000_pch_lpt) ||
1227 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1228 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1229 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1230 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1231 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1234 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1236 /* Request ME un-configure ULP mode in the PHY */
1237 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1238 mac_reg &= ~E1000_H2ME_ULP;
1239 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1240 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1243 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1244 while (E1000_READ_REG(hw, E1000_FWSM) &
1245 E1000_FWSM_ULP_CFG_DONE) {
1247 ret_val = -E1000_ERR_PHY;
1253 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1256 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1257 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1258 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1260 /* Clear H2ME.ULP after ME ULP configuration */
1261 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1262 mac_reg &= ~E1000_H2ME_ULP;
1263 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1265 /* Restore link speed advertisements and restart
1268 if (hw->mac.autoneg) {
1269 ret_val = e1000_phy_setup_autoneg(hw);
1273 ret_val = e1000_setup_copper_link_generic(hw);
1277 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1283 ret_val = hw->phy.ops.acquire(hw);
1287 /* Revert the change to the 'Link Status Change'
1288 * interrupt to trigger on 'Cable Status Change'
1290 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1294 phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1295 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1298 /* Toggle LANPHYPC Value bit */
1299 e1000_toggle_lanphypc_pch_lpt(hw);
1301 /* Unforce SMBus mode in PHY */
1302 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1304 /* The MAC might be in PCIe mode, so temporarily force to
1305 * SMBus mode in order to access the PHY.
1307 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1308 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1309 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1313 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1318 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1319 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1321 /* Unforce SMBus mode in MAC */
1322 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1323 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1324 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1326 /* When ULP mode was previously entered, K1 was disabled by the
1327 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1329 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1332 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1333 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1335 /* Clear ULP enabled configuration */
1336 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1339 /* CSC interrupt received due to ULP Indication */
1340 if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1341 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1342 I218_ULP_CONFIG1_STICKY_ULP |
1343 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1344 I218_ULP_CONFIG1_WOL_HOST |
1345 I218_ULP_CONFIG1_INBAND_EXIT |
1346 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1347 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1349 /* Commit ULP changes by starting auto ULP configuration */
1350 phy_reg |= I218_ULP_CONFIG1_START;
1351 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1353 /* Clear Disable SMBus Release on PERST# in MAC */
1354 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1355 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1356 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1359 hw->phy.ops.release(hw);
1361 if (hw->mac.autoneg)
1362 e1000_phy_setup_autoneg(hw);
1364 e1000_setup_copper_link_generic(hw);
1366 e1000_sw_lcd_config_ich8lan(hw);
1368 e1000_oem_bits_config_ich8lan(hw, true);
1370 /* Set ULP state to unknown and return non-zero to
1371 * indicate no link (yet) and re-enter on the next LSC
1372 * to finish disabling ULP flow.
1374 hw->dev_spec.ich8lan.ulp_state =
1375 e1000_ulp_state_unknown;
1382 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1383 mac_reg |= E1000_TCTL_EN;
1384 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1387 hw->phy.ops.release(hw);
1389 hw->phy.ops.reset(hw);
1394 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1396 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1401 #endif /* ULP_SUPPORT */
1403 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1404 * @hw: pointer to the HW structure
1406 * Checks to see of the link status of the hardware has changed. If a
1407 * change in link status has been detected, then we read the PHY registers
1408 * to get the current speed/duplex if link exists.
1410 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1412 struct e1000_mac_info *mac = &hw->mac;
1413 s32 ret_val, tipg_reg = 0;
1414 u16 emi_addr, emi_val = 0;
1418 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1420 /* We only want to go out to the PHY registers to see if Auto-Neg
1421 * has completed and/or if our link status has changed. The
1422 * get_link_status flag is set upon receiving a Link Status
1423 * Change or Rx Sequence Error interrupt.
1425 if (!mac->get_link_status)
1426 return E1000_SUCCESS;
1428 if ((hw->mac.type < e1000_pch_lpt) ||
1429 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1430 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1431 /* First we want to see if the MII Status Register reports
1432 * link. If so, then we want to get the current speed/duplex
1435 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1439 /* Check the MAC's STATUS register to determine link state
1440 * since the PHY could be inaccessible while in ULP mode.
1442 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1444 ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1446 ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1451 if (hw->mac.type == e1000_pchlan) {
1452 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1457 /* When connected at 10Mbps half-duplex, some parts are excessively
1458 * aggressive resulting in many collisions. To avoid this, increase
1459 * the IPG and reduce Rx latency in the PHY.
1461 if (((hw->mac.type == e1000_pch2lan) ||
1462 (hw->mac.type == e1000_pch_lpt)) && link) {
1465 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1466 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1467 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1469 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1471 /* Reduce Rx latency in analog PHY */
1474 /* Roll back the default values */
1479 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1481 ret_val = hw->phy.ops.acquire(hw);
1485 if (hw->mac.type == e1000_pch2lan)
1486 emi_addr = I82579_RX_CONFIG;
1488 emi_addr = I217_RX_CONFIG;
1489 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1492 if (hw->mac.type >= e1000_pch_lpt) {
1495 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1497 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1498 if (speed == SPEED_100 || speed == SPEED_10)
1502 hw->phy.ops.write_reg_locked(hw,
1503 I217_PLL_CLOCK_GATE_REG,
1506 hw->phy.ops.release(hw);
1512 /* I217 Packet Loss issue:
1513 * ensure that FEXTNVM4 Beacon Duration is set correctly
1515 * Set the Beacon Duration for I217 to 8 usec
1517 if (hw->mac.type == e1000_pch_lpt) {
1520 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1521 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1522 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1523 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1526 /* Work-around I218 hang issue */
1527 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1528 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1529 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1530 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1531 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1535 /* Clear link partner's EEE ability */
1536 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1538 /* Configure K0s minimum time */
1539 if (hw->mac.type == e1000_pch_lpt) {
1540 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1544 return E1000_SUCCESS; /* No link detected */
1546 mac->get_link_status = false;
1548 switch (hw->mac.type) {
1550 ret_val = e1000_k1_workaround_lv(hw);
1555 if (hw->phy.type == e1000_phy_82578) {
1556 ret_val = e1000_link_stall_workaround_hv(hw);
1561 /* Workaround for PCHx parts in half-duplex:
1562 * Set the number of preambles removed from the packet
1563 * when it is passed from the PHY to the MAC to prevent
1564 * the MAC from misinterpreting the packet type.
1566 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1567 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1569 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1571 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1573 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1579 /* Check if there was DownShift, must be checked
1580 * immediately after link-up
1582 e1000_check_downshift_generic(hw);
1584 /* Enable/Disable EEE after link up */
1585 if (hw->phy.type > e1000_phy_82579) {
1586 ret_val = e1000_set_eee_pchlan(hw);
1591 /* If we are forcing speed/duplex, then we simply return since
1592 * we have already determined whether we have link or not.
1595 return -E1000_ERR_CONFIG;
1597 /* Auto-Neg is enabled. Auto Speed Detection takes care
1598 * of MAC speed/duplex configuration. So we only need to
1599 * configure Collision Distance in the MAC.
1601 mac->ops.config_collision_dist(hw);
1603 /* Configure Flow Control now that Auto-Neg has completed.
1604 * First, we need to restore the desired flow control
1605 * settings because we may have had to re-autoneg with a
1606 * different link partner.
1608 ret_val = e1000_config_fc_after_link_up_generic(hw);
1610 DEBUGOUT("Error configuring flow control\n");
1616 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1617 * @hw: pointer to the HW structure
1619 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1621 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1623 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1625 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1626 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1627 switch (hw->mac.type) {
1630 case e1000_ich10lan:
1631 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1636 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1644 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1645 * @hw: pointer to the HW structure
1647 * Acquires the mutex for performing NVM operations.
1649 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1651 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1653 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1655 return E1000_SUCCESS;
1659 * e1000_release_nvm_ich8lan - Release NVM mutex
1660 * @hw: pointer to the HW structure
1662 * Releases the mutex used while performing NVM operations.
1664 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1666 DEBUGFUNC("e1000_release_nvm_ich8lan");
1668 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1674 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1675 * @hw: pointer to the HW structure
1677 * Acquires the software control flag for performing PHY and select
1680 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1682 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1683 s32 ret_val = E1000_SUCCESS;
1685 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1687 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1690 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1691 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1699 DEBUGOUT("SW has already locked the resource.\n");
1700 ret_val = -E1000_ERR_CONFIG;
1704 timeout = SW_FLAG_TIMEOUT;
1706 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1707 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1710 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1711 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1719 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1720 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1721 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1722 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1723 ret_val = -E1000_ERR_CONFIG;
1729 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1735 * e1000_release_swflag_ich8lan - Release software control flag
1736 * @hw: pointer to the HW structure
1738 * Releases the software control flag for performing PHY and select
1741 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1745 DEBUGFUNC("e1000_release_swflag_ich8lan");
1747 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1749 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1750 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1751 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1753 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1756 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1762 * e1000_check_mng_mode_ich8lan - Checks management mode
1763 * @hw: pointer to the HW structure
1765 * This checks if the adapter has any manageability enabled.
1766 * This is a function pointer entry point only called by read/write
1767 * routines for the PHY and NVM parts.
1769 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1773 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1775 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1777 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1778 ((fwsm & E1000_FWSM_MODE_MASK) ==
1779 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1783 * e1000_check_mng_mode_pchlan - Checks management mode
1784 * @hw: pointer to the HW structure
1786 * This checks if the adapter has iAMT enabled.
1787 * This is a function pointer entry point only called by read/write
1788 * routines for the PHY and NVM parts.
1790 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1794 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1796 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1798 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1799 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1803 * e1000_rar_set_pch2lan - Set receive address register
1804 * @hw: pointer to the HW structure
1805 * @addr: pointer to the receive address
1806 * @index: receive address array register
1808 * Sets the receive address array register at index to the address passed
1809 * in by addr. For 82579, RAR[0] is the base address register that is to
1810 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1811 * Use SHRA[0-3] in place of those reserved for ME.
1813 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1815 u32 rar_low, rar_high;
1817 DEBUGFUNC("e1000_rar_set_pch2lan");
1819 /* HW expects these in little endian so we reverse the byte order
1820 * from network order (big endian) to little endian
1822 rar_low = ((u32) addr[0] |
1823 ((u32) addr[1] << 8) |
1824 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1826 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1828 /* If MAC address zero, no need to set the AV bit */
1829 if (rar_low || rar_high)
1830 rar_high |= E1000_RAH_AV;
1833 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1834 E1000_WRITE_FLUSH(hw);
1835 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1836 E1000_WRITE_FLUSH(hw);
1837 return E1000_SUCCESS;
1840 /* RAR[1-6] are owned by manageability. Skip those and program the
1841 * next address into the SHRA register array.
1843 if (index < (u32) (hw->mac.rar_entry_count)) {
1846 ret_val = e1000_acquire_swflag_ich8lan(hw);
1850 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1851 E1000_WRITE_FLUSH(hw);
1852 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1853 E1000_WRITE_FLUSH(hw);
1855 e1000_release_swflag_ich8lan(hw);
1857 /* verify the register updates */
1858 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1859 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1860 return E1000_SUCCESS;
1862 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1863 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1867 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1868 return -E1000_ERR_CONFIG;
1872 * e1000_rar_set_pch_lpt - Set receive address registers
1873 * @hw: pointer to the HW structure
1874 * @addr: pointer to the receive address
1875 * @index: receive address array register
1877 * Sets the receive address register array at index to the address passed
1878 * in by addr. For LPT, RAR[0] is the base address register that is to
1879 * contain the MAC address. SHRA[0-10] are the shared receive address
1880 * registers that are shared between the Host and manageability engine (ME).
1882 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1884 u32 rar_low, rar_high;
1887 DEBUGFUNC("e1000_rar_set_pch_lpt");
1889 /* HW expects these in little endian so we reverse the byte order
1890 * from network order (big endian) to little endian
1892 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1893 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1895 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1897 /* If MAC address zero, no need to set the AV bit */
1898 if (rar_low || rar_high)
1899 rar_high |= E1000_RAH_AV;
1902 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1903 E1000_WRITE_FLUSH(hw);
1904 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1905 E1000_WRITE_FLUSH(hw);
1906 return E1000_SUCCESS;
1909 /* The manageability engine (ME) can lock certain SHRAR registers that
1910 * it is using - those registers are unavailable for use.
1912 if (index < hw->mac.rar_entry_count) {
1913 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1914 E1000_FWSM_WLOCK_MAC_MASK;
1915 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1917 /* Check if all SHRAR registers are locked */
1921 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1924 ret_val = e1000_acquire_swflag_ich8lan(hw);
1929 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1931 E1000_WRITE_FLUSH(hw);
1932 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1934 E1000_WRITE_FLUSH(hw);
1936 e1000_release_swflag_ich8lan(hw);
1938 /* verify the register updates */
1939 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1940 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1941 return E1000_SUCCESS;
1946 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1947 return -E1000_ERR_CONFIG;
1950 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1952 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1953 * @hw: pointer to the HW structure
1954 * @mc_addr_list: array of multicast addresses to program
1955 * @mc_addr_count: number of multicast addresses to program
1957 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1958 * The caller must have a packed mc_addr_list of multicast addresses.
1960 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1968 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1970 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1972 ret_val = hw->phy.ops.acquire(hw);
1976 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1980 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1981 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1982 (u16)(hw->mac.mta_shadow[i] &
1984 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1985 (u16)((hw->mac.mta_shadow[i] >> 16) &
1989 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1992 hw->phy.ops.release(hw);
1995 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1997 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1998 * @hw: pointer to the HW structure
2000 * Checks if firmware is blocking the reset of the PHY.
2001 * This is a function pointer entry point only called by
2004 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2007 bool blocked = false;
2010 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2013 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2014 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2020 } while (blocked && (i++ < 30));
2021 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2025 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2026 * @hw: pointer to the HW structure
2028 * Assumes semaphore already acquired.
2031 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2034 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2035 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2036 E1000_STRAP_SMT_FREQ_SHIFT;
2039 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2041 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2045 phy_data &= ~HV_SMB_ADDR_MASK;
2046 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2047 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2049 if (hw->phy.type == e1000_phy_i217) {
2050 /* Restore SMBus frequency */
2052 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2053 phy_data |= (freq & (1 << 0)) <<
2054 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2055 phy_data |= (freq & (1 << 1)) <<
2056 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2058 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2062 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2066 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2067 * @hw: pointer to the HW structure
2069 * SW should configure the LCD from the NVM extended configuration region
2070 * as a workaround for certain parts.
2072 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2074 struct e1000_phy_info *phy = &hw->phy;
2075 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2076 s32 ret_val = E1000_SUCCESS;
2077 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2079 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2081 /* Initialize the PHY from the NVM on ICH platforms. This
2082 * is needed due to an issue where the NVM configuration is
2083 * not properly autoloaded after power transitions.
2084 * Therefore, after each PHY reset, we will load the
2085 * configuration data out of the NVM manually.
2087 switch (hw->mac.type) {
2089 if (phy->type != e1000_phy_igp_3)
2092 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2093 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2094 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2101 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2107 ret_val = hw->phy.ops.acquire(hw);
2111 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2112 if (!(data & sw_cfg_mask))
2115 /* Make sure HW does not configure LCD from PHY
2116 * extended configuration before SW configuration
2118 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2119 if ((hw->mac.type < e1000_pch2lan) &&
2120 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2123 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2124 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2125 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2129 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2130 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2132 if (((hw->mac.type == e1000_pchlan) &&
2133 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2134 (hw->mac.type > e1000_pchlan)) {
2135 /* HW configures the SMBus address and LEDs when the
2136 * OEM and LCD Write Enable bits are set in the NVM.
2137 * When both NVM bits are cleared, SW will configure
2140 ret_val = e1000_write_smbus_addr(hw);
2144 data = E1000_READ_REG(hw, E1000_LEDCTL);
2145 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2151 /* Configure LCD from extended configuration region. */
2153 /* cnf_base_addr is in DWORD */
2154 word_addr = (u16)(cnf_base_addr << 1);
2156 for (i = 0; i < cnf_size; i++) {
2157 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2162 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2167 /* Save off the PHY page for future writes. */
2168 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2169 phy_page = reg_data;
2173 reg_addr &= PHY_REG_MASK;
2174 reg_addr |= phy_page;
2176 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2183 hw->phy.ops.release(hw);
2188 * e1000_k1_gig_workaround_hv - K1 Si workaround
2189 * @hw: pointer to the HW structure
2190 * @link: link up bool flag
2192 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2193 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2194 * If link is down, the function will restore the default K1 setting located
2197 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2199 s32 ret_val = E1000_SUCCESS;
2201 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2203 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2205 if (hw->mac.type != e1000_pchlan)
2206 return E1000_SUCCESS;
2208 /* Wrap the whole flow with the sw flag */
2209 ret_val = hw->phy.ops.acquire(hw);
2213 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2215 if (hw->phy.type == e1000_phy_82578) {
2216 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2221 status_reg &= (BM_CS_STATUS_LINK_UP |
2222 BM_CS_STATUS_RESOLVED |
2223 BM_CS_STATUS_SPEED_MASK);
2225 if (status_reg == (BM_CS_STATUS_LINK_UP |
2226 BM_CS_STATUS_RESOLVED |
2227 BM_CS_STATUS_SPEED_1000))
2231 if (hw->phy.type == e1000_phy_82577) {
2232 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2237 status_reg &= (HV_M_STATUS_LINK_UP |
2238 HV_M_STATUS_AUTONEG_COMPLETE |
2239 HV_M_STATUS_SPEED_MASK);
2241 if (status_reg == (HV_M_STATUS_LINK_UP |
2242 HV_M_STATUS_AUTONEG_COMPLETE |
2243 HV_M_STATUS_SPEED_1000))
2247 /* Link stall fix for link up */
2248 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2254 /* Link stall fix for link down */
2255 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2261 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2264 hw->phy.ops.release(hw);
2270 * e1000_configure_k1_ich8lan - Configure K1 power state
2271 * @hw: pointer to the HW structure
2272 * @enable: K1 state to configure
2274 * Configure the K1 power state based on the provided parameter.
2275 * Assumes semaphore already acquired.
2277 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2279 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2287 DEBUGFUNC("e1000_configure_k1_ich8lan");
2289 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2295 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2297 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2299 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2305 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2306 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2308 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2309 reg |= E1000_CTRL_FRCSPD;
2310 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2312 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2313 E1000_WRITE_FLUSH(hw);
2315 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2316 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2317 E1000_WRITE_FLUSH(hw);
2320 return E1000_SUCCESS;
2324 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2325 * @hw: pointer to the HW structure
2326 * @d0_state: boolean if entering d0 or d3 device state
2328 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2329 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2330 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2332 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2338 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2340 if (hw->mac.type < e1000_pchlan)
2343 ret_val = hw->phy.ops.acquire(hw);
2347 if (hw->mac.type == e1000_pchlan) {
2348 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2349 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2353 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2354 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2357 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2359 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2363 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2366 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2367 oem_reg |= HV_OEM_BITS_GBE_DIS;
2369 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2370 oem_reg |= HV_OEM_BITS_LPLU;
2372 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2373 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2374 oem_reg |= HV_OEM_BITS_GBE_DIS;
2376 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2377 E1000_PHY_CTRL_NOND0A_LPLU))
2378 oem_reg |= HV_OEM_BITS_LPLU;
2381 /* Set Restart auto-neg to activate the bits */
2382 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2383 !hw->phy.ops.check_reset_block(hw))
2384 oem_reg |= HV_OEM_BITS_RESTART_AN;
2386 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2389 hw->phy.ops.release(hw);
2396 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2397 * @hw: pointer to the HW structure
2399 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2404 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2406 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2410 data |= HV_KMRN_MDIO_SLOW;
2412 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2418 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2419 * done after every PHY reset.
2421 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2423 s32 ret_val = E1000_SUCCESS;
2426 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2428 if (hw->mac.type != e1000_pchlan)
2429 return E1000_SUCCESS;
2431 /* Set MDIO slow mode before any other MDIO access */
2432 if (hw->phy.type == e1000_phy_82577) {
2433 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2438 if (((hw->phy.type == e1000_phy_82577) &&
2439 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2440 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2441 /* Disable generation of early preamble */
2442 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2446 /* Preamble tuning for SSC */
2447 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2453 if (hw->phy.type == e1000_phy_82578) {
2454 /* Return registers to default by doing a soft reset then
2455 * writing 0x3140 to the control register.
2457 if (hw->phy.revision < 2) {
2458 e1000_phy_sw_reset_generic(hw);
2459 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2465 ret_val = hw->phy.ops.acquire(hw);
2470 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2471 hw->phy.ops.release(hw);
2475 /* Configure the K1 Si workaround during phy reset assuming there is
2476 * link so that it disables K1 if link is in 1Gbps.
2478 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2482 /* Workaround for link disconnects on a busy hub in half duplex */
2483 ret_val = hw->phy.ops.acquire(hw);
2486 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2489 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2494 /* set MSE higher to enable link to stay up when noise is high */
2495 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2497 hw->phy.ops.release(hw);
2503 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2504 * @hw: pointer to the HW structure
2506 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2512 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2514 ret_val = hw->phy.ops.acquire(hw);
2517 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2521 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2522 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2523 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2524 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2525 (u16)(mac_reg & 0xFFFF));
2526 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2527 (u16)((mac_reg >> 16) & 0xFFFF));
2529 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2530 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2531 (u16)(mac_reg & 0xFFFF));
2532 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2533 (u16)((mac_reg & E1000_RAH_AV)
2537 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2540 hw->phy.ops.release(hw);
2543 #ifndef CRC32_OS_SUPPORT
2544 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2546 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2547 u32 i, j, mask, crc;
2549 DEBUGFUNC("e1000_calc_rx_da_crc");
2552 for (i = 0; i < 6; i++) {
2554 for (j = 8; j > 0; j--) {
2555 mask = (crc & 1) * (-1);
2556 crc = (crc >> 1) ^ (poly & mask);
2562 #endif /* CRC32_OS_SUPPORT */
2564 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2566 * @hw: pointer to the HW structure
2567 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2569 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2571 s32 ret_val = E1000_SUCCESS;
2576 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2578 if (hw->mac.type < e1000_pch2lan)
2579 return E1000_SUCCESS;
2581 /* disable Rx path while enabling/disabling workaround */
2582 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2583 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2584 phy_reg | (1 << 14));
2589 /* Write Rx addresses (rar_entry_count for RAL/H, and
2590 * SHRAL/H) and initial CRC values to the MAC
2592 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2593 u8 mac_addr[ETH_ADDR_LEN] = {0};
2594 u32 addr_high, addr_low;
2596 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2597 if (!(addr_high & E1000_RAH_AV))
2599 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2600 mac_addr[0] = (addr_low & 0xFF);
2601 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2602 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2603 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2604 mac_addr[4] = (addr_high & 0xFF);
2605 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2607 #ifndef CRC32_OS_SUPPORT
2608 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2609 e1000_calc_rx_da_crc(mac_addr));
2610 #else /* CRC32_OS_SUPPORT */
2611 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2612 E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2613 #endif /* CRC32_OS_SUPPORT */
2616 /* Write Rx addresses to the PHY */
2617 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2619 /* Enable jumbo frame workaround in the MAC */
2620 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2621 mac_reg &= ~(1 << 14);
2622 mac_reg |= (7 << 15);
2623 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2625 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2626 mac_reg |= E1000_RCTL_SECRC;
2627 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2629 ret_val = e1000_read_kmrn_reg_generic(hw,
2630 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2634 ret_val = e1000_write_kmrn_reg_generic(hw,
2635 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2639 ret_val = e1000_read_kmrn_reg_generic(hw,
2640 E1000_KMRNCTRLSTA_HD_CTRL,
2644 data &= ~(0xF << 8);
2646 ret_val = e1000_write_kmrn_reg_generic(hw,
2647 E1000_KMRNCTRLSTA_HD_CTRL,
2652 /* Enable jumbo frame workaround in the PHY */
2653 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2654 data &= ~(0x7F << 5);
2655 data |= (0x37 << 5);
2656 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2659 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2661 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2664 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2665 data &= ~(0x3FF << 2);
2666 data |= (E1000_TX_PTR_GAP << 2);
2667 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2670 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2673 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2674 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2679 /* Write MAC register values back to h/w defaults */
2680 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2681 mac_reg &= ~(0xF << 14);
2682 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2684 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2685 mac_reg &= ~E1000_RCTL_SECRC;
2686 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2688 ret_val = e1000_read_kmrn_reg_generic(hw,
2689 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2693 ret_val = e1000_write_kmrn_reg_generic(hw,
2694 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2698 ret_val = e1000_read_kmrn_reg_generic(hw,
2699 E1000_KMRNCTRLSTA_HD_CTRL,
2703 data &= ~(0xF << 8);
2705 ret_val = e1000_write_kmrn_reg_generic(hw,
2706 E1000_KMRNCTRLSTA_HD_CTRL,
2711 /* Write PHY register values back to h/w defaults */
2712 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2713 data &= ~(0x7F << 5);
2714 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2717 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2719 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2722 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2723 data &= ~(0x3FF << 2);
2725 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2728 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2731 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2732 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2738 /* re-enable Rx path after enabling/disabling workaround */
2739 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2744 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2745 * done after every PHY reset.
2747 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2749 s32 ret_val = E1000_SUCCESS;
2751 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2753 if (hw->mac.type != e1000_pch2lan)
2754 return E1000_SUCCESS;
2756 /* Set MDIO slow mode before any other MDIO access */
2757 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2761 ret_val = hw->phy.ops.acquire(hw);
2764 /* set MSE higher to enable link to stay up when noise is high */
2765 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2768 /* drop link after 5 times MSE threshold was reached */
2769 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2771 hw->phy.ops.release(hw);
2777 * e1000_k1_gig_workaround_lv - K1 Si workaround
2778 * @hw: pointer to the HW structure
2780 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2781 * Disable K1 for 1000 and 100 speeds
2783 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2785 s32 ret_val = E1000_SUCCESS;
2788 DEBUGFUNC("e1000_k1_workaround_lv");
2790 if (hw->mac.type != e1000_pch2lan)
2791 return E1000_SUCCESS;
2793 /* Set K1 beacon duration based on 10Mbs speed */
2794 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2798 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2799 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2801 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2804 /* LV 1G/100 Packet drop issue wa */
2805 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2809 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2810 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2816 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2817 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2818 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2819 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2827 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2828 * @hw: pointer to the HW structure
2829 * @gate: boolean set to true to gate, false to ungate
2831 * Gate/ungate the automatic PHY configuration via hardware; perform
2832 * the configuration via software instead.
2834 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2838 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2840 if (hw->mac.type < e1000_pch2lan)
2843 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2846 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2848 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2850 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2854 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2855 * @hw: pointer to the HW structure
2857 * Check the appropriate indication the MAC has finished configuring the
2858 * PHY after a software reset.
2860 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2862 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2864 DEBUGFUNC("e1000_lan_init_done_ich8lan");
2866 /* Wait for basic configuration completes before proceeding */
2868 data = E1000_READ_REG(hw, E1000_STATUS);
2869 data &= E1000_STATUS_LAN_INIT_DONE;
2871 } while ((!data) && --loop);
2873 /* If basic configuration is incomplete before the above loop
2874 * count reaches 0, loading the configuration from NVM will
2875 * leave the PHY in a bad state possibly resulting in no link.
2878 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2880 /* Clear the Init Done bit for the next init event */
2881 data = E1000_READ_REG(hw, E1000_STATUS);
2882 data &= ~E1000_STATUS_LAN_INIT_DONE;
2883 E1000_WRITE_REG(hw, E1000_STATUS, data);
2887 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2888 * @hw: pointer to the HW structure
2890 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2892 s32 ret_val = E1000_SUCCESS;
2895 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2897 if (hw->phy.ops.check_reset_block(hw))
2898 return E1000_SUCCESS;
2900 /* Allow time for h/w to get to quiescent state after reset */
2903 /* Perform any necessary post-reset workarounds */
2904 switch (hw->mac.type) {
2906 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2911 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2919 /* Clear the host wakeup bit after lcd reset */
2920 if (hw->mac.type >= e1000_pchlan) {
2921 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
2922 reg &= ~BM_WUC_HOST_WU_BIT;
2923 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2926 /* Configure the LCD with the extended configuration region in NVM */
2927 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2931 /* Configure the LCD with the OEM bits in NVM */
2932 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2934 if (hw->mac.type == e1000_pch2lan) {
2935 /* Ungate automatic PHY configuration on non-managed 82579 */
2936 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2937 E1000_ICH_FWSM_FW_VALID)) {
2939 e1000_gate_hw_phy_config_ich8lan(hw, false);
2942 /* Set EEE LPI Update Timer to 200usec */
2943 ret_val = hw->phy.ops.acquire(hw);
2946 ret_val = e1000_write_emi_reg_locked(hw,
2947 I82579_LPI_UPDATE_TIMER,
2949 hw->phy.ops.release(hw);
2956 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2957 * @hw: pointer to the HW structure
2960 * This is a function pointer entry point called by drivers
2961 * or other shared routines.
2963 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2965 s32 ret_val = E1000_SUCCESS;
2967 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2969 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2970 if ((hw->mac.type == e1000_pch2lan) &&
2971 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2972 e1000_gate_hw_phy_config_ich8lan(hw, true);
2974 ret_val = e1000_phy_hw_reset_generic(hw);
2978 return e1000_post_phy_reset_ich8lan(hw);
2982 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2983 * @hw: pointer to the HW structure
2984 * @active: true to enable LPLU, false to disable
2986 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2987 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2988 * the phy speed. This function will manually set the LPLU bit and restart
2989 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2990 * since it configures the same bit.
2992 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2997 DEBUGFUNC("e1000_set_lplu_state_pchlan");
2998 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3003 oem_reg |= HV_OEM_BITS_LPLU;
3005 oem_reg &= ~HV_OEM_BITS_LPLU;
3007 if (!hw->phy.ops.check_reset_block(hw))
3008 oem_reg |= HV_OEM_BITS_RESTART_AN;
3010 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3014 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3015 * @hw: pointer to the HW structure
3016 * @active: true to enable LPLU, false to disable
3018 * Sets the LPLU D0 state according to the active flag. When
3019 * activating LPLU this function also disables smart speed
3020 * and vice versa. LPLU will not be activated unless the
3021 * device autonegotiation advertisement meets standards of
3022 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3023 * This is a function pointer entry point only called by
3024 * PHY setup routines.
3026 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3028 struct e1000_phy_info *phy = &hw->phy;
3030 s32 ret_val = E1000_SUCCESS;
3033 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3035 if (phy->type == e1000_phy_ife)
3036 return E1000_SUCCESS;
3038 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3041 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3042 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3044 if (phy->type != e1000_phy_igp_3)
3045 return E1000_SUCCESS;
3047 /* Call gig speed drop workaround on LPLU before accessing
3050 if (hw->mac.type == e1000_ich8lan)
3051 e1000_gig_downshift_workaround_ich8lan(hw);
3053 /* When LPLU is enabled, we should disable SmartSpeed */
3054 ret_val = phy->ops.read_reg(hw,
3055 IGP01E1000_PHY_PORT_CONFIG,
3059 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3060 ret_val = phy->ops.write_reg(hw,
3061 IGP01E1000_PHY_PORT_CONFIG,
3066 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3067 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3069 if (phy->type != e1000_phy_igp_3)
3070 return E1000_SUCCESS;
3072 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3073 * during Dx states where the power conservation is most
3074 * important. During driver activity we should enable
3075 * SmartSpeed, so performance is maintained.
3077 if (phy->smart_speed == e1000_smart_speed_on) {
3078 ret_val = phy->ops.read_reg(hw,
3079 IGP01E1000_PHY_PORT_CONFIG,
3084 data |= IGP01E1000_PSCFR_SMART_SPEED;
3085 ret_val = phy->ops.write_reg(hw,
3086 IGP01E1000_PHY_PORT_CONFIG,
3090 } else if (phy->smart_speed == e1000_smart_speed_off) {
3091 ret_val = phy->ops.read_reg(hw,
3092 IGP01E1000_PHY_PORT_CONFIG,
3097 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3098 ret_val = phy->ops.write_reg(hw,
3099 IGP01E1000_PHY_PORT_CONFIG,
3106 return E1000_SUCCESS;
3110 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3111 * @hw: pointer to the HW structure
3112 * @active: true to enable LPLU, false to disable
3114 * Sets the LPLU D3 state according to the active flag. When
3115 * activating LPLU this function also disables smart speed
3116 * and vice versa. LPLU will not be activated unless the
3117 * device autonegotiation advertisement meets standards of
3118 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3119 * This is a function pointer entry point only called by
3120 * PHY setup routines.
3122 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3124 struct e1000_phy_info *phy = &hw->phy;
3126 s32 ret_val = E1000_SUCCESS;
3129 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3131 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3134 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3135 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3137 if (phy->type != e1000_phy_igp_3)
3138 return E1000_SUCCESS;
3140 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3141 * during Dx states where the power conservation is most
3142 * important. During driver activity we should enable
3143 * SmartSpeed, so performance is maintained.
3145 if (phy->smart_speed == e1000_smart_speed_on) {
3146 ret_val = phy->ops.read_reg(hw,
3147 IGP01E1000_PHY_PORT_CONFIG,
3152 data |= IGP01E1000_PSCFR_SMART_SPEED;
3153 ret_val = phy->ops.write_reg(hw,
3154 IGP01E1000_PHY_PORT_CONFIG,
3158 } else if (phy->smart_speed == e1000_smart_speed_off) {
3159 ret_val = phy->ops.read_reg(hw,
3160 IGP01E1000_PHY_PORT_CONFIG,
3165 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3166 ret_val = phy->ops.write_reg(hw,
3167 IGP01E1000_PHY_PORT_CONFIG,
3172 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3173 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3174 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3175 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3176 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3178 if (phy->type != e1000_phy_igp_3)
3179 return E1000_SUCCESS;
3181 /* Call gig speed drop workaround on LPLU before accessing
3184 if (hw->mac.type == e1000_ich8lan)
3185 e1000_gig_downshift_workaround_ich8lan(hw);
3187 /* When LPLU is enabled, we should disable SmartSpeed */
3188 ret_val = phy->ops.read_reg(hw,
3189 IGP01E1000_PHY_PORT_CONFIG,
3194 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3195 ret_val = phy->ops.write_reg(hw,
3196 IGP01E1000_PHY_PORT_CONFIG,
3204 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3205 * @hw: pointer to the HW structure
3206 * @bank: pointer to the variable that returns the active bank
3208 * Reads signature byte from the NVM using the flash access registers.
3209 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3211 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3214 struct e1000_nvm_info *nvm = &hw->nvm;
3215 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3216 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3221 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3223 switch (hw->mac.type) {
3226 eecd = E1000_READ_REG(hw, E1000_EECD);
3227 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3228 E1000_EECD_SEC1VAL_VALID_MASK) {
3229 if (eecd & E1000_EECD_SEC1VAL)
3234 return E1000_SUCCESS;
3236 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3239 /* set bank to 0 in case flash read fails */
3243 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3247 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3248 E1000_ICH_NVM_SIG_VALUE) {
3250 return E1000_SUCCESS;
3254 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3259 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3260 E1000_ICH_NVM_SIG_VALUE) {
3262 return E1000_SUCCESS;
3265 DEBUGOUT("ERROR: No valid NVM bank present\n");
3266 return -E1000_ERR_NVM;
3271 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3272 * @hw: pointer to the HW structure
3273 * @offset: The offset (in bytes) of the word(s) to read.
3274 * @words: Size of data to read in words
3275 * @data: Pointer to the word(s) to read at offset.
3277 * Reads a word(s) from the NVM using the flash access registers.
3279 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3282 struct e1000_nvm_info *nvm = &hw->nvm;
3283 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3285 s32 ret_val = E1000_SUCCESS;
3289 DEBUGFUNC("e1000_read_nvm_ich8lan");
3291 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3293 DEBUGOUT("nvm parameter(s) out of bounds\n");
3294 ret_val = -E1000_ERR_NVM;
3298 nvm->ops.acquire(hw);
3300 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3301 if (ret_val != E1000_SUCCESS) {
3302 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3306 act_offset = (bank) ? nvm->flash_bank_size : 0;
3307 act_offset += offset;
3309 ret_val = E1000_SUCCESS;
3310 for (i = 0; i < words; i++) {
3311 if (dev_spec->shadow_ram[offset+i].modified) {
3312 data[i] = dev_spec->shadow_ram[offset+i].value;
3314 ret_val = e1000_read_flash_word_ich8lan(hw,
3323 nvm->ops.release(hw);
3327 DEBUGOUT1("NVM read error: %d\n", ret_val);
3333 * e1000_flash_cycle_init_ich8lan - Initialize flash
3334 * @hw: pointer to the HW structure
3336 * This function does initial flash setup so that a new read/write/erase cycle
3339 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3341 union ich8_hws_flash_status hsfsts;
3342 s32 ret_val = -E1000_ERR_NVM;
3344 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3346 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3348 /* Check if the flash descriptor is valid */
3349 if (!hsfsts.hsf_status.fldesvalid) {
3350 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3351 return -E1000_ERR_NVM;
3354 /* Clear FCERR and DAEL in hw status by writing 1 */
3355 hsfsts.hsf_status.flcerr = 1;
3356 hsfsts.hsf_status.dael = 1;
3357 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3359 /* Either we should have a hardware SPI cycle in progress
3360 * bit to check against, in order to start a new cycle or
3361 * FDONE bit should be changed in the hardware so that it
3362 * is 1 after hardware reset, which can then be used as an
3363 * indication whether a cycle is in progress or has been
3367 if (!hsfsts.hsf_status.flcinprog) {
3368 /* There is no cycle running at present,
3369 * so we can start a cycle.
3370 * Begin by setting Flash Cycle Done.
3372 hsfsts.hsf_status.flcdone = 1;
3373 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3374 ret_val = E1000_SUCCESS;
3378 /* Otherwise poll for sometime so the current
3379 * cycle has a chance to end before giving up.
3381 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3382 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3384 if (!hsfsts.hsf_status.flcinprog) {
3385 ret_val = E1000_SUCCESS;
3390 if (ret_val == E1000_SUCCESS) {
3391 /* Successful in waiting for previous cycle to timeout,
3392 * now set the Flash Cycle Done.
3394 hsfsts.hsf_status.flcdone = 1;
3395 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3398 DEBUGOUT("Flash controller busy, cannot get access\n");
3406 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3407 * @hw: pointer to the HW structure
3408 * @timeout: maximum time to wait for completion
3410 * This function starts a flash cycle and waits for its completion.
3412 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3414 union ich8_hws_flash_ctrl hsflctl;
3415 union ich8_hws_flash_status hsfsts;
3418 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3420 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3421 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3422 hsflctl.hsf_ctrl.flcgo = 1;
3424 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3426 /* wait till FDONE bit is set to 1 */
3428 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3429 if (hsfsts.hsf_status.flcdone)
3432 } while (i++ < timeout);
3434 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3435 return E1000_SUCCESS;
3437 return -E1000_ERR_NVM;
3441 * e1000_read_flash_word_ich8lan - Read word from flash
3442 * @hw: pointer to the HW structure
3443 * @offset: offset to data location
3444 * @data: pointer to the location for storing the data
3446 * Reads the flash word at offset into data. Offset is converted
3447 * to bytes before read.
3449 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3452 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3455 return -E1000_ERR_NVM;
3457 /* Must convert offset into bytes. */
3460 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3464 * e1000_read_flash_byte_ich8lan - Read byte from flash
3465 * @hw: pointer to the HW structure
3466 * @offset: The offset of the byte to read.
3467 * @data: Pointer to a byte to store the value read.
3469 * Reads a single byte from the NVM using the flash access registers.
3471 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3477 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3484 return E1000_SUCCESS;
3488 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3489 * @hw: pointer to the HW structure
3490 * @offset: The offset (in bytes) of the byte or word to read.
3491 * @size: Size of data to read, 1=byte 2=word
3492 * @data: Pointer to the word to store the value read.
3494 * Reads a byte or word from the NVM using the flash access registers.
3496 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3499 union ich8_hws_flash_status hsfsts;
3500 union ich8_hws_flash_ctrl hsflctl;
3501 u32 flash_linear_addr;
3503 s32 ret_val = -E1000_ERR_NVM;
3506 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3508 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3509 return -E1000_ERR_NVM;
3510 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3511 hw->nvm.flash_base_addr);
3516 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3517 if (ret_val != E1000_SUCCESS)
3519 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3521 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3522 hsflctl.hsf_ctrl.fldbcount = size - 1;
3523 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3524 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3525 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3527 ret_val = e1000_flash_cycle_ich8lan(hw,
3528 ICH_FLASH_READ_COMMAND_TIMEOUT);
3530 /* Check if FCERR is set to 1, if set to 1, clear it
3531 * and try the whole sequence a few more times, else
3532 * read in (shift in) the Flash Data0, the order is
3533 * least significant byte first msb to lsb
3535 if (ret_val == E1000_SUCCESS) {
3536 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3538 *data = (u8)(flash_data & 0x000000FF);
3540 *data = (u16)(flash_data & 0x0000FFFF);
3543 /* If we've gotten here, then things are probably
3544 * completely hosed, but if the error condition is
3545 * detected, it won't hurt to give it another try...
3546 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3548 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3550 if (hsfsts.hsf_status.flcerr) {
3551 /* Repeat for some time before giving up. */
3553 } else if (!hsfsts.hsf_status.flcdone) {
3554 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3558 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3565 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3566 * @hw: pointer to the HW structure
3567 * @offset: The offset (in bytes) of the word(s) to write.
3568 * @words: Size of data to write in words
3569 * @data: Pointer to the word(s) to write at offset.
3571 * Writes a byte or word to the NVM using the flash access registers.
3573 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3576 struct e1000_nvm_info *nvm = &hw->nvm;
3577 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3580 DEBUGFUNC("e1000_write_nvm_ich8lan");
3582 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3584 DEBUGOUT("nvm parameter(s) out of bounds\n");
3585 return -E1000_ERR_NVM;
3588 nvm->ops.acquire(hw);
3590 for (i = 0; i < words; i++) {
3591 dev_spec->shadow_ram[offset+i].modified = true;
3592 dev_spec->shadow_ram[offset+i].value = data[i];
3595 nvm->ops.release(hw);
3597 return E1000_SUCCESS;
3601 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3602 * @hw: pointer to the HW structure
3604 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3605 * which writes the checksum to the shadow ram. The changes in the shadow
3606 * ram are then committed to the EEPROM by processing each bank at a time
3607 * checking for the modified bit and writing only the pending changes.
3608 * After a successful commit, the shadow ram is cleared and is ready for
3611 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3613 struct e1000_nvm_info *nvm = &hw->nvm;
3614 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3615 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3619 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3621 ret_val = e1000_update_nvm_checksum_generic(hw);
3625 if (nvm->type != e1000_nvm_flash_sw)
3628 nvm->ops.acquire(hw);
3630 /* We're writing to the opposite bank so if we're on bank 1,
3631 * write to bank 0 etc. We also need to erase the segment that
3632 * is going to be written
3634 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3635 if (ret_val != E1000_SUCCESS) {
3636 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3641 new_bank_offset = nvm->flash_bank_size;
3642 old_bank_offset = 0;
3643 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3647 old_bank_offset = nvm->flash_bank_size;
3648 new_bank_offset = 0;
3649 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3653 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3654 if (dev_spec->shadow_ram[i].modified) {
3655 data = dev_spec->shadow_ram[i].value;
3657 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3663 /* If the word is 0x13, then make sure the signature bits
3664 * (15:14) are 11b until the commit has completed.
3665 * This will allow us to write 10b which indicates the
3666 * signature is valid. We want to do this after the write
3667 * has completed so that we don't mark the segment valid
3668 * while the write is still in progress
3670 if (i == E1000_ICH_NVM_SIG_WORD)
3671 data |= E1000_ICH_NVM_SIG_MASK;
3673 /* Convert offset to bytes. */
3674 act_offset = (i + new_bank_offset) << 1;
3678 /* Write the bytes to the new bank. */
3679 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3686 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3693 /* Don't bother writing the segment valid bits if sector
3694 * programming failed.
3697 DEBUGOUT("Flash commit failed.\n");
3701 /* Finally validate the new segment by setting bit 15:14
3702 * to 10b in word 0x13 , this can be done without an
3703 * erase as well since these bits are 11 to start with
3704 * and we need to change bit 14 to 0b
3706 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3707 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3712 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
3717 /* And invalidate the previously valid segment by setting
3718 * its signature word (0x13) high_byte to 0b. This can be
3719 * done without an erase because flash erase sets all bits
3720 * to 1's. We can write 1's to 0's without an erase
3722 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3724 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3729 /* Great! Everything worked, we can now clear the cached entries. */
3730 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3731 dev_spec->shadow_ram[i].modified = false;
3732 dev_spec->shadow_ram[i].value = 0xFFFF;
3736 nvm->ops.release(hw);
3738 /* Reload the EEPROM, or else modifications will not appear
3739 * until after the next adapter reset.
3742 nvm->ops.reload(hw);
3748 DEBUGOUT1("NVM update error: %d\n", ret_val);
3754 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3755 * @hw: pointer to the HW structure
3757 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3758 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3759 * calculated, in which case we need to calculate the checksum and set bit 6.
3761 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3766 u16 valid_csum_mask;
3768 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3770 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3771 * the checksum needs to be fixed. This bit is an indication that
3772 * the NVM was prepared by OEM software and did not calculate
3773 * the checksum...a likely scenario.
3775 switch (hw->mac.type) {
3778 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3781 word = NVM_FUTURE_INIT_WORD1;
3782 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3786 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3790 if (!(data & valid_csum_mask)) {
3791 data |= valid_csum_mask;
3792 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3795 ret_val = hw->nvm.ops.update(hw);
3800 return e1000_validate_nvm_checksum_generic(hw);
3804 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3805 * @hw: pointer to the HW structure
3806 * @offset: The offset (in bytes) of the byte/word to read.
3807 * @size: Size of data to read, 1=byte 2=word
3808 * @data: The byte(s) to write to the NVM.
3810 * Writes one/two bytes to the NVM using the flash access registers.
3812 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3815 union ich8_hws_flash_status hsfsts;
3816 union ich8_hws_flash_ctrl hsflctl;
3817 u32 flash_linear_addr;
3822 DEBUGFUNC("e1000_write_ich8_data");
3824 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3825 return -E1000_ERR_NVM;
3827 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3828 hw->nvm.flash_base_addr);
3833 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3834 if (ret_val != E1000_SUCCESS)
3836 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3838 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3839 hsflctl.hsf_ctrl.fldbcount = size - 1;
3840 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3841 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3843 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3846 flash_data = (u32)data & 0x00FF;
3848 flash_data = (u32)data;
3850 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3852 /* check if FCERR is set to 1 , if set to 1, clear it
3853 * and try the whole sequence a few more times else done
3856 e1000_flash_cycle_ich8lan(hw,
3857 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3858 if (ret_val == E1000_SUCCESS)
3861 /* If we're here, then things are most likely
3862 * completely hosed, but if the error condition
3863 * is detected, it won't hurt to give it another
3864 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3866 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3867 if (hsfsts.hsf_status.flcerr)
3868 /* Repeat for some time before giving up. */
3870 if (!hsfsts.hsf_status.flcdone) {
3871 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3874 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3881 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3882 * @hw: pointer to the HW structure
3883 * @offset: The index of the byte to read.
3884 * @data: The byte to write to the NVM.
3886 * Writes a single byte to the NVM using the flash access registers.
3888 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3891 u16 word = (u16)data;
3893 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3895 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3901 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3902 * @hw: pointer to the HW structure
3903 * @offset: The offset of the byte to write.
3904 * @byte: The byte to write to the NVM.
3906 * Writes a single byte to the NVM using the flash access registers.
3907 * Goes through a retry algorithm before giving up.
3909 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3910 u32 offset, u8 byte)
3913 u16 program_retries;
3915 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3917 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3921 for (program_retries = 0; program_retries < 100; program_retries++) {
3922 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3924 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3925 if (ret_val == E1000_SUCCESS)
3928 if (program_retries == 100)
3929 return -E1000_ERR_NVM;
3931 return E1000_SUCCESS;
3935 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3936 * @hw: pointer to the HW structure
3937 * @bank: 0 for first bank, 1 for second bank, etc.
3939 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3940 * bank N is 4096 * N + flash_reg_addr.
3942 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3944 struct e1000_nvm_info *nvm = &hw->nvm;
3945 union ich8_hws_flash_status hsfsts;
3946 union ich8_hws_flash_ctrl hsflctl;
3947 u32 flash_linear_addr;
3948 /* bank size is in 16bit words - adjust to bytes */
3949 u32 flash_bank_size = nvm->flash_bank_size * 2;
3952 s32 j, iteration, sector_size;
3954 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3956 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3958 /* Determine HW Sector size: Read BERASE bits of hw flash status
3960 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3961 * consecutive sectors. The start index for the nth Hw sector
3962 * can be calculated as = bank * 4096 + n * 256
3963 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3964 * The start index for the nth Hw sector can be calculated
3966 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3967 * (ich9 only, otherwise error condition)
3968 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3970 switch (hsfsts.hsf_status.berasesz) {
3972 /* Hw sector size 256 */
3973 sector_size = ICH_FLASH_SEG_SIZE_256;
3974 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3977 sector_size = ICH_FLASH_SEG_SIZE_4K;
3981 sector_size = ICH_FLASH_SEG_SIZE_8K;
3985 sector_size = ICH_FLASH_SEG_SIZE_64K;
3989 return -E1000_ERR_NVM;
3992 /* Start with the base address, then add the sector offset. */
3993 flash_linear_addr = hw->nvm.flash_base_addr;
3994 flash_linear_addr += (bank) ? flash_bank_size : 0;
3996 for (j = 0; j < iteration; j++) {
3998 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4001 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4005 /* Write a value 11 (block Erase) in Flash
4006 * Cycle field in hw flash control
4009 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4011 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4012 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4015 /* Write the last 24 bits of an index within the
4016 * block into Flash Linear address field in Flash
4019 flash_linear_addr += (j * sector_size);
4020 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4023 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4024 if (ret_val == E1000_SUCCESS)
4027 /* Check if FCERR is set to 1. If 1,
4028 * clear it and try the whole sequence
4029 * a few more times else Done
4031 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4033 if (hsfsts.hsf_status.flcerr)
4034 /* repeat for some time before giving up */
4036 else if (!hsfsts.hsf_status.flcdone)
4038 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4041 return E1000_SUCCESS;
4045 * e1000_valid_led_default_ich8lan - Set the default LED settings
4046 * @hw: pointer to the HW structure
4047 * @data: Pointer to the LED settings
4049 * Reads the LED default settings from the NVM to data. If the NVM LED
4050 * settings is all 0's or F's, set the LED default to a valid LED default
4053 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4057 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4059 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4061 DEBUGOUT("NVM Read Error\n");
4065 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4066 *data = ID_LED_DEFAULT_ICH8LAN;
4068 return E1000_SUCCESS;
4072 * e1000_id_led_init_pchlan - store LED configurations
4073 * @hw: pointer to the HW structure
4075 * PCH does not control LEDs via the LEDCTL register, rather it uses
4076 * the PHY LED configuration register.
4078 * PCH also does not have an "always on" or "always off" mode which
4079 * complicates the ID feature. Instead of using the "on" mode to indicate
4080 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4081 * use "link_up" mode. The LEDs will still ID on request if there is no
4082 * link based on logic in e1000_led_[on|off]_pchlan().
4084 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4086 struct e1000_mac_info *mac = &hw->mac;
4088 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4089 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4090 u16 data, i, temp, shift;
4092 DEBUGFUNC("e1000_id_led_init_pchlan");
4094 /* Get default ID LED modes */
4095 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4099 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4100 mac->ledctl_mode1 = mac->ledctl_default;
4101 mac->ledctl_mode2 = mac->ledctl_default;
4103 for (i = 0; i < 4; i++) {
4104 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4107 case ID_LED_ON1_DEF2:
4108 case ID_LED_ON1_ON2:
4109 case ID_LED_ON1_OFF2:
4110 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4111 mac->ledctl_mode1 |= (ledctl_on << shift);
4113 case ID_LED_OFF1_DEF2:
4114 case ID_LED_OFF1_ON2:
4115 case ID_LED_OFF1_OFF2:
4116 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4117 mac->ledctl_mode1 |= (ledctl_off << shift);
4124 case ID_LED_DEF1_ON2:
4125 case ID_LED_ON1_ON2:
4126 case ID_LED_OFF1_ON2:
4127 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4128 mac->ledctl_mode2 |= (ledctl_on << shift);
4130 case ID_LED_DEF1_OFF2:
4131 case ID_LED_ON1_OFF2:
4132 case ID_LED_OFF1_OFF2:
4133 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4134 mac->ledctl_mode2 |= (ledctl_off << shift);
4142 return E1000_SUCCESS;
4146 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4147 * @hw: pointer to the HW structure
4149 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4150 * register, so the the bus width is hard coded.
4152 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4154 struct e1000_bus_info *bus = &hw->bus;
4157 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4159 ret_val = e1000_get_bus_info_pcie_generic(hw);
4161 /* ICH devices are "PCI Express"-ish. They have
4162 * a configuration space, but do not contain
4163 * PCI Express Capability registers, so bus width
4164 * must be hardcoded.
4166 if (bus->width == e1000_bus_width_unknown)
4167 bus->width = e1000_bus_width_pcie_x1;
4173 * e1000_reset_hw_ich8lan - Reset the hardware
4174 * @hw: pointer to the HW structure
4176 * Does a full reset of the hardware which includes a reset of the PHY and
4179 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4181 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4186 DEBUGFUNC("e1000_reset_hw_ich8lan");
4188 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4189 * on the last TLP read/write transaction when MAC is reset.
4191 ret_val = e1000_disable_pcie_master_generic(hw);
4193 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4195 DEBUGOUT("Masking off all interrupts\n");
4196 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4198 /* Disable the Transmit and Receive units. Then delay to allow
4199 * any pending transactions to complete before we hit the MAC
4200 * with the global reset.
4202 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4203 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4204 E1000_WRITE_FLUSH(hw);
4208 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4209 if (hw->mac.type == e1000_ich8lan) {
4210 /* Set Tx and Rx buffer allocation to 8k apiece. */
4211 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4212 /* Set Packet Buffer Size to 16k. */
4213 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4216 if (hw->mac.type == e1000_pchlan) {
4217 /* Save the NVM K1 bit setting*/
4218 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4222 if (kum_cfg & E1000_NVM_K1_ENABLE)
4223 dev_spec->nvm_k1_enabled = true;
4225 dev_spec->nvm_k1_enabled = false;
4228 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4230 if (!hw->phy.ops.check_reset_block(hw)) {
4231 /* Full-chip reset requires MAC and PHY reset at the same
4232 * time to make sure the interface between MAC and the
4233 * external PHY is reset.
4235 ctrl |= E1000_CTRL_PHY_RST;
4237 /* Gate automatic PHY configuration by hardware on
4240 if ((hw->mac.type == e1000_pch2lan) &&
4241 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4242 e1000_gate_hw_phy_config_ich8lan(hw, true);
4244 ret_val = e1000_acquire_swflag_ich8lan(hw);
4245 DEBUGOUT("Issuing a global reset to ich8lan\n");
4246 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4247 /* cannot issue a flush here because it hangs the hardware */
4250 /* Set Phy Config Counter to 50msec */
4251 if (hw->mac.type == e1000_pch2lan) {
4252 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4253 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4254 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4255 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4259 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4261 if (ctrl & E1000_CTRL_PHY_RST) {
4262 ret_val = hw->phy.ops.get_cfg_done(hw);
4266 ret_val = e1000_post_phy_reset_ich8lan(hw);
4271 /* For PCH, this write will make sure that any noise
4272 * will be detected as a CRC error and be dropped rather than show up
4273 * as a bad packet to the DMA engine.
4275 if (hw->mac.type == e1000_pchlan)
4276 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4278 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4279 E1000_READ_REG(hw, E1000_ICR);
4281 reg = E1000_READ_REG(hw, E1000_KABGTXD);
4282 reg |= E1000_KABGTXD_BGSQLBIAS;
4283 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4285 return E1000_SUCCESS;
4289 * e1000_init_hw_ich8lan - Initialize the hardware
4290 * @hw: pointer to the HW structure
4292 * Prepares the hardware for transmit and receive by doing the following:
4293 * - initialize hardware bits
4294 * - initialize LED identification
4295 * - setup receive address registers
4296 * - setup flow control
4297 * - setup transmit descriptors
4298 * - clear statistics
4300 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4302 struct e1000_mac_info *mac = &hw->mac;
4303 u32 ctrl_ext, txdctl, snoop;
4307 DEBUGFUNC("e1000_init_hw_ich8lan");
4309 e1000_initialize_hw_bits_ich8lan(hw);
4311 /* Initialize identification LED */
4312 ret_val = mac->ops.id_led_init(hw);
4313 /* An error is not fatal and we should not stop init due to this */
4315 DEBUGOUT("Error initializing identification LED\n");
4317 /* Setup the receive address. */
4318 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4320 /* Zero out the Multicast HASH table */
4321 DEBUGOUT("Zeroing the MTA\n");
4322 for (i = 0; i < mac->mta_reg_count; i++)
4323 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4325 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4326 * the ME. Disable wakeup by clearing the host wakeup bit.
4327 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4329 if (hw->phy.type == e1000_phy_82578) {
4330 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4331 i &= ~BM_WUC_HOST_WU_BIT;
4332 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4333 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4338 /* Setup link and flow control */
4339 ret_val = mac->ops.setup_link(hw);
4341 /* Set the transmit descriptor write-back policy for both queues */
4342 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4343 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4344 E1000_TXDCTL_FULL_TX_DESC_WB);
4345 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4346 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4347 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4348 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4349 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4350 E1000_TXDCTL_FULL_TX_DESC_WB);
4351 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4352 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4353 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4355 /* ICH8 has opposite polarity of no_snoop bits.
4356 * By default, we should use snoop behavior.
4358 if (mac->type == e1000_ich8lan)
4359 snoop = PCIE_ICH8_SNOOP_ALL;
4361 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4362 e1000_set_pcie_no_snoop_generic(hw, snoop);
4364 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4365 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4366 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4368 /* Clear all of the statistics registers (clear on read). It is
4369 * important that we do this after we have tried to establish link
4370 * because the symbol error count will increment wildly if there
4373 e1000_clear_hw_cntrs_ich8lan(hw);
4379 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4380 * @hw: pointer to the HW structure
4382 * Sets/Clears required hardware bits necessary for correctly setting up the
4383 * hardware for transmit and receive.
4385 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4389 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4391 /* Extended Device Control */
4392 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4394 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4395 if (hw->mac.type >= e1000_pchlan)
4396 reg |= E1000_CTRL_EXT_PHYPDEN;
4397 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4399 /* Transmit Descriptor Control 0 */
4400 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4402 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4404 /* Transmit Descriptor Control 1 */
4405 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4407 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4409 /* Transmit Arbitration Control 0 */
4410 reg = E1000_READ_REG(hw, E1000_TARC(0));
4411 if (hw->mac.type == e1000_ich8lan)
4412 reg |= (1 << 28) | (1 << 29);
4413 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4414 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4416 /* Transmit Arbitration Control 1 */
4417 reg = E1000_READ_REG(hw, E1000_TARC(1));
4418 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4422 reg |= (1 << 24) | (1 << 26) | (1 << 30);
4423 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4426 if (hw->mac.type == e1000_ich8lan) {
4427 reg = E1000_READ_REG(hw, E1000_STATUS);
4429 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4432 /* work-around descriptor data corruption issue during nfs v2 udp
4433 * traffic, just disable the nfs filtering capability
4435 reg = E1000_READ_REG(hw, E1000_RFCTL);
4436 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4438 /* Disable IPv6 extension header parsing because some malformed
4439 * IPv6 headers can hang the Rx.
4441 if (hw->mac.type == e1000_ich8lan)
4442 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4443 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4445 /* Enable ECC on Lynxpoint */
4446 if (hw->mac.type == e1000_pch_lpt) {
4447 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4448 reg |= E1000_PBECCSTS_ECC_ENABLE;
4449 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4451 reg = E1000_READ_REG(hw, E1000_CTRL);
4452 reg |= E1000_CTRL_MEHE;
4453 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4460 * e1000_setup_link_ich8lan - Setup flow control and link settings
4461 * @hw: pointer to the HW structure
4463 * Determines which flow control settings to use, then configures flow
4464 * control. Calls the appropriate media-specific link configuration
4465 * function. Assuming the adapter has a valid link partner, a valid link
4466 * should be established. Assumes the hardware has previously been reset
4467 * and the transmitter and receiver are not enabled.
4469 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4473 DEBUGFUNC("e1000_setup_link_ich8lan");
4475 if (hw->phy.ops.check_reset_block(hw))
4476 return E1000_SUCCESS;
4478 /* ICH parts do not have a word in the NVM to determine
4479 * the default flow control setting, so we explicitly
4482 if (hw->fc.requested_mode == e1000_fc_default)
4483 hw->fc.requested_mode = e1000_fc_full;
4485 /* Save off the requested flow control mode for use later. Depending
4486 * on the link partner's capabilities, we may or may not use this mode.
4488 hw->fc.current_mode = hw->fc.requested_mode;
4490 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4491 hw->fc.current_mode);
4493 /* Continue to configure the copper link. */
4494 ret_val = hw->mac.ops.setup_physical_interface(hw);
4498 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4499 if ((hw->phy.type == e1000_phy_82578) ||
4500 (hw->phy.type == e1000_phy_82579) ||
4501 (hw->phy.type == e1000_phy_i217) ||
4502 (hw->phy.type == e1000_phy_82577)) {
4503 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4505 ret_val = hw->phy.ops.write_reg(hw,
4506 PHY_REG(BM_PORT_CTRL_PAGE, 27),
4512 return e1000_set_fc_watermarks_generic(hw);
4516 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4517 * @hw: pointer to the HW structure
4519 * Configures the kumeran interface to the PHY to wait the appropriate time
4520 * when polling the PHY, then call the generic setup_copper_link to finish
4521 * configuring the copper link.
4523 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4529 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4531 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4532 ctrl |= E1000_CTRL_SLU;
4533 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4534 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4536 /* Set the mac to wait the maximum time between each iteration
4537 * and increase the max iterations when polling the phy;
4538 * this fixes erroneous timeouts at 10Mbps.
4540 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4544 ret_val = e1000_read_kmrn_reg_generic(hw,
4545 E1000_KMRNCTRLSTA_INBAND_PARAM,
4550 ret_val = e1000_write_kmrn_reg_generic(hw,
4551 E1000_KMRNCTRLSTA_INBAND_PARAM,
4556 switch (hw->phy.type) {
4557 case e1000_phy_igp_3:
4558 ret_val = e1000_copper_link_setup_igp(hw);
4563 case e1000_phy_82578:
4564 ret_val = e1000_copper_link_setup_m88(hw);
4568 case e1000_phy_82577:
4569 case e1000_phy_82579:
4570 ret_val = e1000_copper_link_setup_82577(hw);
4575 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4580 reg_data &= ~IFE_PMC_AUTO_MDIX;
4582 switch (hw->phy.mdix) {
4584 reg_data &= ~IFE_PMC_FORCE_MDIX;
4587 reg_data |= IFE_PMC_FORCE_MDIX;
4591 reg_data |= IFE_PMC_AUTO_MDIX;
4594 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4603 return e1000_setup_copper_link_generic(hw);
4607 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4608 * @hw: pointer to the HW structure
4610 * Calls the PHY specific link setup function and then calls the
4611 * generic setup_copper_link to finish configuring the link for
4612 * Lynxpoint PCH devices
4614 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4619 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4621 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4622 ctrl |= E1000_CTRL_SLU;
4623 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4624 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4626 ret_val = e1000_copper_link_setup_82577(hw);
4630 return e1000_setup_copper_link_generic(hw);
4634 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4635 * @hw: pointer to the HW structure
4636 * @speed: pointer to store current link speed
4637 * @duplex: pointer to store the current link duplex
4639 * Calls the generic get_speed_and_duplex to retrieve the current link
4640 * information and then calls the Kumeran lock loss workaround for links at
4643 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4648 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4650 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4654 if ((hw->mac.type == e1000_ich8lan) &&
4655 (hw->phy.type == e1000_phy_igp_3) &&
4656 (*speed == SPEED_1000)) {
4657 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4664 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4665 * @hw: pointer to the HW structure
4667 * Work-around for 82566 Kumeran PCS lock loss:
4668 * On link status change (i.e. PCI reset, speed change) and link is up and
4670 * 0) if workaround is optionally disabled do nothing
4671 * 1) wait 1ms for Kumeran link to come up
4672 * 2) check Kumeran Diagnostic register PCS lock loss bit
4673 * 3) if not set the link is locked (all is good), otherwise...
4675 * 5) repeat up to 10 times
4676 * Note: this is only called for IGP3 copper when speed is 1gb.
4678 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4680 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4686 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4688 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4689 return E1000_SUCCESS;
4691 /* Make sure link is up before proceeding. If not just return.
4692 * Attempting this while link is negotiating fouled up link
4695 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4697 return E1000_SUCCESS;
4699 for (i = 0; i < 10; i++) {
4700 /* read once to clear */
4701 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4704 /* and again to get new status */
4705 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4709 /* check for PCS lock */
4710 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4711 return E1000_SUCCESS;
4713 /* Issue PHY reset */
4714 hw->phy.ops.reset(hw);
4717 /* Disable GigE link negotiation */
4718 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4719 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4720 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4721 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4723 /* Call gig speed drop workaround on Gig disable before accessing
4726 e1000_gig_downshift_workaround_ich8lan(hw);
4728 /* unable to acquire PCS lock */
4729 return -E1000_ERR_PHY;
4733 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4734 * @hw: pointer to the HW structure
4735 * @state: boolean value used to set the current Kumeran workaround state
4737 * If ICH8, set the current Kumeran workaround state (enabled - true
4738 * /disabled - false).
4740 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4743 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4745 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4747 if (hw->mac.type != e1000_ich8lan) {
4748 DEBUGOUT("Workaround applies to ICH8 only.\n");
4752 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4758 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4759 * @hw: pointer to the HW structure
4761 * Workaround for 82566 power-down on D3 entry:
4762 * 1) disable gigabit link
4763 * 2) write VR power-down enable
4765 * Continue if successful, else issue LCD reset and repeat
4767 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4773 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4775 if (hw->phy.type != e1000_phy_igp_3)
4778 /* Try the workaround twice (if needed) */
4781 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4782 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4783 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4784 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4786 /* Call gig speed drop workaround on Gig disable before
4787 * accessing any PHY registers
4789 if (hw->mac.type == e1000_ich8lan)
4790 e1000_gig_downshift_workaround_ich8lan(hw);
4792 /* Write VR power-down enable */
4793 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4794 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4795 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4796 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4798 /* Read it back and test */
4799 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4800 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4801 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4804 /* Issue PHY reset and repeat at most one more time */
4805 reg = E1000_READ_REG(hw, E1000_CTRL);
4806 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4812 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4813 * @hw: pointer to the HW structure
4815 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4816 * LPLU, Gig disable, MDIC PHY reset):
4817 * 1) Set Kumeran Near-end loopback
4818 * 2) Clear Kumeran Near-end loopback
4819 * Should only be called for ICH8[m] devices with any 1G Phy.
4821 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4826 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4828 if ((hw->mac.type != e1000_ich8lan) ||
4829 (hw->phy.type == e1000_phy_ife))
4832 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4836 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4837 ret_val = e1000_write_kmrn_reg_generic(hw,
4838 E1000_KMRNCTRLSTA_DIAG_OFFSET,
4842 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4843 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4848 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4849 * @hw: pointer to the HW structure
4851 * During S0 to Sx transition, it is possible the link remains at gig
4852 * instead of negotiating to a lower speed. Before going to Sx, set
4853 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4854 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4855 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4856 * needs to be written.
4857 * Parts that support (and are linked to a partner which support) EEE in
4858 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4859 * than 10Mbps w/o EEE.
4861 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4863 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4867 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4869 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4870 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4872 if (hw->phy.type == e1000_phy_i217) {
4873 u16 phy_reg, device_id = hw->device_id;
4875 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4876 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4877 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4878 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4879 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4881 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4882 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4885 ret_val = hw->phy.ops.acquire(hw);
4889 if (!dev_spec->eee_disable) {
4893 e1000_read_emi_reg_locked(hw,
4894 I217_EEE_ADVERTISEMENT,
4899 /* Disable LPLU if both link partners support 100BaseT
4900 * EEE and 100Full is advertised on both ends of the
4901 * link, and enable Auto Enable LPI since there will
4902 * be no driver to enable LPI while in Sx.
4904 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4905 (dev_spec->eee_lp_ability &
4906 I82579_EEE_100_SUPPORTED) &&
4907 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4908 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4909 E1000_PHY_CTRL_NOND0A_LPLU);
4911 /* Set Auto Enable LPI after link up */
4912 hw->phy.ops.read_reg_locked(hw,
4915 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4916 hw->phy.ops.write_reg_locked(hw,
4922 /* For i217 Intel Rapid Start Technology support,
4923 * when the system is going into Sx and no manageability engine
4924 * is present, the driver must configure proxy to reset only on
4925 * power good. LPI (Low Power Idle) state must also reset only
4926 * on power good, as well as the MTA (Multicast table array).
4927 * The SMBus release must also be disabled on LCD reset.
4929 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4930 E1000_ICH_FWSM_FW_VALID)) {
4931 /* Enable proxy to reset only on power good. */
4932 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4934 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4935 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4938 /* Set bit enable LPI (EEE) to reset only on
4941 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4942 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4943 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4945 /* Disable the SMB release on LCD reset. */
4946 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4947 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4948 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4951 /* Enable MTA to reset for Intel Rapid Start Technology
4954 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4955 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4956 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4959 hw->phy.ops.release(hw);
4962 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4964 if (hw->mac.type == e1000_ich8lan)
4965 e1000_gig_downshift_workaround_ich8lan(hw);
4967 if (hw->mac.type >= e1000_pchlan) {
4968 e1000_oem_bits_config_ich8lan(hw, false);
4970 /* Reset PHY to activate OEM bits on 82577/8 */
4971 if (hw->mac.type == e1000_pchlan)
4972 e1000_phy_hw_reset_generic(hw);
4974 ret_val = hw->phy.ops.acquire(hw);
4977 e1000_write_smbus_addr(hw);
4978 hw->phy.ops.release(hw);
4985 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4986 * @hw: pointer to the HW structure
4988 * During Sx to S0 transitions on non-managed devices or managed devices
4989 * on which PHY resets are not blocked, if the PHY registers cannot be
4990 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4992 * On i217, setup Intel Rapid Start Technology.
4994 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4998 DEBUGFUNC("e1000_resume_workarounds_pchlan");
4999 if (hw->mac.type < e1000_pch2lan)
5000 return E1000_SUCCESS;
5002 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5004 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5008 /* For i217 Intel Rapid Start Technology support when the system
5009 * is transitioning from Sx and no manageability engine is present
5010 * configure SMBus to restore on reset, disable proxy, and enable
5011 * the reset on MTA (Multicast table array).
5013 if (hw->phy.type == e1000_phy_i217) {
5016 ret_val = hw->phy.ops.acquire(hw);
5018 DEBUGOUT("Failed to setup iRST\n");
5022 /* Clear Auto Enable LPI after link up */
5023 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5024 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5025 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5027 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5028 E1000_ICH_FWSM_FW_VALID)) {
5029 /* Restore clear on SMB if no manageability engine
5032 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5036 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5037 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5040 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5042 /* Enable reset on MTA */
5043 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5047 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5048 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5051 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5052 hw->phy.ops.release(hw);
5055 return E1000_SUCCESS;
5059 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5060 * @hw: pointer to the HW structure
5062 * Return the LED back to the default configuration.
5064 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5066 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5068 if (hw->phy.type == e1000_phy_ife)
5069 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5072 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5073 return E1000_SUCCESS;
5077 * e1000_led_on_ich8lan - Turn LEDs on
5078 * @hw: pointer to the HW structure
5082 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5084 DEBUGFUNC("e1000_led_on_ich8lan");
5086 if (hw->phy.type == e1000_phy_ife)
5087 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5088 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5090 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5091 return E1000_SUCCESS;
5095 * e1000_led_off_ich8lan - Turn LEDs off
5096 * @hw: pointer to the HW structure
5098 * Turn off the LEDs.
5100 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5102 DEBUGFUNC("e1000_led_off_ich8lan");
5104 if (hw->phy.type == e1000_phy_ife)
5105 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5106 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5108 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5109 return E1000_SUCCESS;
5113 * e1000_setup_led_pchlan - Configures SW controllable LED
5114 * @hw: pointer to the HW structure
5116 * This prepares the SW controllable LED for use.
5118 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5120 DEBUGFUNC("e1000_setup_led_pchlan");
5122 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5123 (u16)hw->mac.ledctl_mode1);
5127 * e1000_cleanup_led_pchlan - Restore the default LED operation
5128 * @hw: pointer to the HW structure
5130 * Return the LED back to the default configuration.
5132 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5134 DEBUGFUNC("e1000_cleanup_led_pchlan");
5136 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5137 (u16)hw->mac.ledctl_default);
5141 * e1000_led_on_pchlan - Turn LEDs on
5142 * @hw: pointer to the HW structure
5146 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5148 u16 data = (u16)hw->mac.ledctl_mode2;
5151 DEBUGFUNC("e1000_led_on_pchlan");
5153 /* If no link, then turn LED on by setting the invert bit
5154 * for each LED that's mode is "link_up" in ledctl_mode2.
5156 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5157 for (i = 0; i < 3; i++) {
5158 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5159 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5160 E1000_LEDCTL_MODE_LINK_UP)
5162 if (led & E1000_PHY_LED0_IVRT)
5163 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5165 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5169 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5173 * e1000_led_off_pchlan - Turn LEDs off
5174 * @hw: pointer to the HW structure
5176 * Turn off the LEDs.
5178 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5180 u16 data = (u16)hw->mac.ledctl_mode1;
5183 DEBUGFUNC("e1000_led_off_pchlan");
5185 /* If no link, then turn LED off by clearing the invert bit
5186 * for each LED that's mode is "link_up" in ledctl_mode1.
5188 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5189 for (i = 0; i < 3; i++) {
5190 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5191 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5192 E1000_LEDCTL_MODE_LINK_UP)
5194 if (led & E1000_PHY_LED0_IVRT)
5195 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5197 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5201 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5205 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5206 * @hw: pointer to the HW structure
5208 * Read appropriate register for the config done bit for completion status
5209 * and configure the PHY through s/w for EEPROM-less parts.
5211 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5212 * config done bit, so only an error is logged and continues. If we were
5213 * to return with error, EEPROM-less silicon would not be able to be reset
5216 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5218 s32 ret_val = E1000_SUCCESS;
5222 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5224 e1000_get_cfg_done_generic(hw);
5226 /* Wait for indication from h/w that it has completed basic config */
5227 if (hw->mac.type >= e1000_ich10lan) {
5228 e1000_lan_init_done_ich8lan(hw);
5230 ret_val = e1000_get_auto_rd_done_generic(hw);
5232 /* When auto config read does not complete, do not
5233 * return with an error. This can happen in situations
5234 * where there is no eeprom and prevents getting link.
5236 DEBUGOUT("Auto Read Done did not complete\n");
5237 ret_val = E1000_SUCCESS;
5241 /* Clear PHY Reset Asserted bit */
5242 status = E1000_READ_REG(hw, E1000_STATUS);
5243 if (status & E1000_STATUS_PHYRA)
5244 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5246 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5248 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5249 if (hw->mac.type <= e1000_ich9lan) {
5250 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5251 (hw->phy.type == e1000_phy_igp_3)) {
5252 e1000_phy_init_script_igp3(hw);
5255 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5256 /* Maybe we should do a basic PHY config */
5257 DEBUGOUT("EEPROM not present\n");
5258 ret_val = -E1000_ERR_CONFIG;
5266 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5267 * @hw: pointer to the HW structure
5269 * In the case of a PHY power down to save power, or to turn off link during a
5270 * driver unload, or wake on lan is not enabled, remove the link.
5272 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5274 /* If the management interface is not enabled, then power down */
5275 if (!(hw->mac.ops.check_mng_mode(hw) ||
5276 hw->phy.ops.check_reset_block(hw)))
5277 e1000_power_down_phy_copper(hw);
5283 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5284 * @hw: pointer to the HW structure
5286 * Clears hardware counters specific to the silicon family and calls
5287 * clear_hw_cntrs_generic to clear all general purpose counters.
5289 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5294 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5296 e1000_clear_hw_cntrs_base_generic(hw);
5298 E1000_READ_REG(hw, E1000_ALGNERRC);
5299 E1000_READ_REG(hw, E1000_RXERRC);
5300 E1000_READ_REG(hw, E1000_TNCRS);
5301 E1000_READ_REG(hw, E1000_CEXTERR);
5302 E1000_READ_REG(hw, E1000_TSCTC);
5303 E1000_READ_REG(hw, E1000_TSCTFC);
5305 E1000_READ_REG(hw, E1000_MGTPRC);
5306 E1000_READ_REG(hw, E1000_MGTPDC);
5307 E1000_READ_REG(hw, E1000_MGTPTC);
5309 E1000_READ_REG(hw, E1000_IAC);
5310 E1000_READ_REG(hw, E1000_ICRXOC);
5312 /* Clear PHY statistics registers */
5313 if ((hw->phy.type == e1000_phy_82578) ||
5314 (hw->phy.type == e1000_phy_82579) ||
5315 (hw->phy.type == e1000_phy_i217) ||
5316 (hw->phy.type == e1000_phy_82577)) {
5317 ret_val = hw->phy.ops.acquire(hw);
5320 ret_val = hw->phy.ops.set_page(hw,
5321 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5324 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5325 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5326 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5327 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5328 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5329 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5330 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5331 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5332 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5333 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5334 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5335 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5336 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5337 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5339 hw->phy.ops.release(hw);
5344 * e1000_configure_k0s_lpt - Configure K0s power state
5345 * @hw: pointer to the HW structure
5346 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
5347 * 0 corresponds to 128ns, each value over 0 doubles the duration.
5348 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
5349 * 0 corresponds to 128ns, each value over 0 doubles the duration.
5351 * Configure the K1 power state based on the provided parameter.
5352 * Assumes semaphore already acquired.
5354 * Success returns 0, Failure returns:
5355 * -E1000_ERR_PHY (-2) in case of access error
5356 * -E1000_ERR_PARAM (-4) in case of parameters error
5358 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
5363 DEBUGFUNC("e1000_configure_k0s_lpt");
5365 if (entry_latency > 3 || min_time > 4)
5366 return -E1000_ERR_PARAM;
5368 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5373 /* for now don't touch the latency */
5374 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
5375 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
5377 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5382 return E1000_SUCCESS;