1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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32 ***************************************************************************/
34 /* 82562G 10/100 Network Connection
35 * 82562G-2 10/100 Network Connection
36 * 82562GT 10/100 Network Connection
37 * 82562GT-2 10/100 Network Connection
38 * 82562V 10/100 Network Connection
39 * 82562V-2 10/100 Network Connection
40 * 82566DC-2 Gigabit Network Connection
41 * 82566DC Gigabit Network Connection
42 * 82566DM-2 Gigabit Network Connection
43 * 82566DM Gigabit Network Connection
44 * 82566MC Gigabit Network Connection
45 * 82566MM Gigabit Network Connection
46 * 82567LM Gigabit Network Connection
47 * 82567LF Gigabit Network Connection
48 * 82567V Gigabit Network Connection
49 * 82567LM-2 Gigabit Network Connection
50 * 82567LF-2 Gigabit Network Connection
51 * 82567V-2 Gigabit Network Connection
52 * 82567LF-3 Gigabit Network Connection
53 * 82567LM-3 Gigabit Network Connection
54 * 82567LM-4 Gigabit Network Connection
55 * 82577LM Gigabit Network Connection
56 * 82577LC Gigabit Network Connection
57 * 82578DM Gigabit Network Connection
58 * 82578DC Gigabit Network Connection
59 * 82579LM Gigabit Network Connection
60 * 82579V Gigabit Network Connection
61 * Ethernet Connection I217-LM
62 * Ethernet Connection I217-V
63 * Ethernet Connection I218-V
64 * Ethernet Connection I218-LM
65 * Ethernet Connection (2) I218-LM
66 * Ethernet Connection (2) I218-V
67 * Ethernet Connection (3) I218-LM
68 * Ethernet Connection (3) I218-V
71 #include "e1000_api.h"
73 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
74 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
84 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
87 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
88 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
89 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
90 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
91 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
93 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
95 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
99 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
100 u16 words, u16 *data);
101 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
102 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
103 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
104 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
106 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
107 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
108 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
109 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
110 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
111 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
112 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
113 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
114 u16 *speed, u16 *duplex);
115 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
116 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
117 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
118 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
119 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
120 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
121 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
122 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
123 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
124 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
125 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
126 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
127 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
128 u32 offset, u8 *data);
129 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
131 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
133 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
134 u32 offset, u32 *data);
135 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
136 u32 offset, u32 data);
137 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
138 u32 offset, u32 dword);
139 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
140 u32 offset, u16 *data);
141 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
142 u32 offset, u8 byte);
143 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
144 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
145 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
146 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
147 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
148 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
150 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
151 /* Offset 04h HSFSTS */
152 union ich8_hws_flash_status {
154 u16 flcdone:1; /* bit 0 Flash Cycle Done */
155 u16 flcerr:1; /* bit 1 Flash Cycle Error */
156 u16 dael:1; /* bit 2 Direct Access error Log */
157 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
158 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
159 u16 reserved1:2; /* bit 13:6 Reserved */
160 u16 reserved2:6; /* bit 13:6 Reserved */
161 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
162 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
167 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
168 /* Offset 06h FLCTL */
169 union ich8_hws_flash_ctrl {
170 struct ich8_hsflctl {
171 u16 flcgo:1; /* 0 Flash Cycle Go */
172 u16 flcycle:2; /* 2:1 Flash Cycle */
173 u16 reserved:5; /* 7:3 Reserved */
174 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
175 u16 flockdn:6; /* 15:10 Reserved */
180 /* ICH Flash Region Access Permissions */
181 union ich8_hws_flash_regacc {
183 u32 grra:8; /* 0:7 GbE region Read Access */
184 u32 grwa:8; /* 8:15 GbE region Write Access */
185 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
186 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
192 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
193 * @hw: pointer to the HW structure
195 * Test access to the PHY registers by reading the PHY ID registers. If
196 * the PHY ID is already known (e.g. resume path) compare it with known ID,
197 * otherwise assume the read PHY ID is correct if it is valid.
199 * Assumes the sw/fw/hw semaphore is already acquired.
201 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
209 for (retry_count = 0; retry_count < 2; retry_count++) {
210 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
211 if (ret_val || (phy_reg == 0xFFFF))
213 phy_id = (u32)(phy_reg << 16);
215 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
216 if (ret_val || (phy_reg == 0xFFFF)) {
220 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
225 if (hw->phy.id == phy_id)
229 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
233 /* In case the PHY needs to be in mdio slow mode,
234 * set slow mode and try to get the PHY id again.
236 if (hw->mac.type < e1000_pch_lpt) {
237 hw->phy.ops.release(hw);
238 ret_val = e1000_set_mdio_slow_mode_hv(hw);
240 ret_val = e1000_get_phy_id(hw);
241 hw->phy.ops.acquire(hw);
247 if (hw->mac.type >= e1000_pch_lpt) {
248 /* Only unforce SMBus if ME is not active */
249 if (!(E1000_READ_REG(hw, E1000_FWSM) &
250 E1000_ICH_FWSM_FW_VALID)) {
251 /* Unforce SMBus mode in PHY */
252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
253 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
256 /* Unforce SMBus mode in MAC */
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
258 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
259 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
267 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
268 * @hw: pointer to the HW structure
270 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
271 * used to reset the PHY to a quiescent state when necessary.
273 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
277 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
279 /* Set Phy Config Counter to 50msec */
280 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
281 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
282 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
283 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
285 /* Toggle LANPHYPC Value bit */
286 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
287 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
288 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
289 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
290 E1000_WRITE_FLUSH(hw);
292 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
294 E1000_WRITE_FLUSH(hw);
296 if (hw->mac.type < e1000_pch_lpt) {
303 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
304 E1000_CTRL_EXT_LPCD) && count--);
311 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
312 * @hw: pointer to the HW structure
314 * Workarounds/flow necessary for PHY initialization during driver load
317 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
319 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
322 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
324 /* Gate automatic PHY configuration by hardware on managed and
325 * non-managed 82579 and newer adapters.
327 e1000_gate_hw_phy_config_ich8lan(hw, true);
330 /* It is not possible to be certain of the current state of ULP
331 * so forcibly disable it.
333 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
335 #endif /* ULP_SUPPORT */
336 ret_val = hw->phy.ops.acquire(hw);
338 DEBUGOUT("Failed to initialize PHY flow\n");
342 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
343 * inaccessible and resetting the PHY is not blocked, toggle the
344 * LANPHYPC Value bit to force the interconnect to PCIe mode.
346 switch (hw->mac.type) {
349 if (e1000_phy_is_accessible_pchlan(hw))
352 /* Before toggling LANPHYPC, see if PHY is accessible by
353 * forcing MAC to SMBus mode first.
355 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
356 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
357 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
359 /* Wait 50 milliseconds for MAC to finish any retries
360 * that it might be trying to perform from previous
361 * attempts to acknowledge any phy read requests.
367 if (e1000_phy_is_accessible_pchlan(hw))
372 if ((hw->mac.type == e1000_pchlan) &&
373 (fwsm & E1000_ICH_FWSM_FW_VALID))
376 if (hw->phy.ops.check_reset_block(hw)) {
377 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
378 ret_val = -E1000_ERR_PHY;
382 /* Toggle LANPHYPC Value bit */
383 e1000_toggle_lanphypc_pch_lpt(hw);
384 if (hw->mac.type >= e1000_pch_lpt) {
385 if (e1000_phy_is_accessible_pchlan(hw))
388 /* Toggling LANPHYPC brings the PHY out of SMBus mode
389 * so ensure that the MAC is also out of SMBus mode
391 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
392 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
393 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
395 if (e1000_phy_is_accessible_pchlan(hw))
398 ret_val = -E1000_ERR_PHY;
405 hw->phy.ops.release(hw);
408 /* Check to see if able to reset PHY. Print error if not */
409 if (hw->phy.ops.check_reset_block(hw)) {
410 ERROR_REPORT("Reset blocked by ME\n");
414 /* Reset the PHY before any access to it. Doing so, ensures
415 * that the PHY is in a known good state before we read/write
416 * PHY registers. The generic reset is sufficient here,
417 * because we haven't determined the PHY type yet.
419 ret_val = e1000_phy_hw_reset_generic(hw);
423 /* On a successful reset, possibly need to wait for the PHY
424 * to quiesce to an accessible state before returning control
425 * to the calling function. If the PHY does not quiesce, then
426 * return E1000E_BLK_PHY_RESET, as this is the condition that
429 ret_val = hw->phy.ops.check_reset_block(hw);
431 ERROR_REPORT("ME blocked access to PHY after reset\n");
435 /* Ungate automatic PHY configuration on non-managed 82579 */
436 if ((hw->mac.type == e1000_pch2lan) &&
437 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
439 e1000_gate_hw_phy_config_ich8lan(hw, false);
446 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
447 * @hw: pointer to the HW structure
449 * Initialize family-specific PHY parameters and function pointers.
451 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
453 struct e1000_phy_info *phy = &hw->phy;
456 DEBUGFUNC("e1000_init_phy_params_pchlan");
459 phy->reset_delay_us = 100;
461 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
462 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
463 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
464 phy->ops.set_page = e1000_set_page_igp;
465 phy->ops.read_reg = e1000_read_phy_reg_hv;
466 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
467 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
468 phy->ops.release = e1000_release_swflag_ich8lan;
469 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
470 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
471 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
472 phy->ops.write_reg = e1000_write_phy_reg_hv;
473 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
474 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
475 phy->ops.power_up = e1000_power_up_phy_copper;
476 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
477 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
479 phy->id = e1000_phy_unknown;
481 ret_val = e1000_init_phy_workarounds_pchlan(hw);
485 if (phy->id == e1000_phy_unknown)
486 switch (hw->mac.type) {
488 ret_val = e1000_get_phy_id(hw);
491 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
497 /* In case the PHY needs to be in mdio slow mode,
498 * set slow mode and try to get the PHY id again.
500 ret_val = e1000_set_mdio_slow_mode_hv(hw);
503 ret_val = e1000_get_phy_id(hw);
508 phy->type = e1000_get_phy_type_from_id(phy->id);
511 case e1000_phy_82577:
512 case e1000_phy_82579:
514 phy->ops.check_polarity = e1000_check_polarity_82577;
515 phy->ops.force_speed_duplex =
516 e1000_phy_force_speed_duplex_82577;
517 phy->ops.get_cable_length = e1000_get_cable_length_82577;
518 phy->ops.get_info = e1000_get_phy_info_82577;
519 phy->ops.commit = e1000_phy_sw_reset_generic;
521 case e1000_phy_82578:
522 phy->ops.check_polarity = e1000_check_polarity_m88;
523 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
524 phy->ops.get_cable_length = e1000_get_cable_length_m88;
525 phy->ops.get_info = e1000_get_phy_info_m88;
528 ret_val = -E1000_ERR_PHY;
536 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
537 * @hw: pointer to the HW structure
539 * Initialize family-specific PHY parameters and function pointers.
541 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
543 struct e1000_phy_info *phy = &hw->phy;
547 DEBUGFUNC("e1000_init_phy_params_ich8lan");
550 phy->reset_delay_us = 100;
552 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
553 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
554 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
555 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
556 phy->ops.read_reg = e1000_read_phy_reg_igp;
557 phy->ops.release = e1000_release_swflag_ich8lan;
558 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
559 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
560 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
561 phy->ops.write_reg = e1000_write_phy_reg_igp;
562 phy->ops.power_up = e1000_power_up_phy_copper;
563 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
565 /* We may need to do this twice - once for IGP and if that fails,
566 * we'll set BM func pointers and try again
568 ret_val = e1000_determine_phy_address(hw);
570 phy->ops.write_reg = e1000_write_phy_reg_bm;
571 phy->ops.read_reg = e1000_read_phy_reg_bm;
572 ret_val = e1000_determine_phy_address(hw);
574 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
580 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
583 ret_val = e1000_get_phy_id(hw);
590 case IGP03E1000_E_PHY_ID:
591 phy->type = e1000_phy_igp_3;
592 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
593 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
594 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
595 phy->ops.get_info = e1000_get_phy_info_igp;
596 phy->ops.check_polarity = e1000_check_polarity_igp;
597 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
600 case IFE_PLUS_E_PHY_ID:
602 phy->type = e1000_phy_ife;
603 phy->autoneg_mask = E1000_ALL_NOT_GIG;
604 phy->ops.get_info = e1000_get_phy_info_ife;
605 phy->ops.check_polarity = e1000_check_polarity_ife;
606 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
608 case BME1000_E_PHY_ID:
609 phy->type = e1000_phy_bm;
610 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
611 phy->ops.read_reg = e1000_read_phy_reg_bm;
612 phy->ops.write_reg = e1000_write_phy_reg_bm;
613 phy->ops.commit = e1000_phy_sw_reset_generic;
614 phy->ops.get_info = e1000_get_phy_info_m88;
615 phy->ops.check_polarity = e1000_check_polarity_m88;
616 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
619 return -E1000_ERR_PHY;
623 return E1000_SUCCESS;
627 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
628 * @hw: pointer to the HW structure
630 * Initialize family-specific NVM parameters and function
633 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
635 struct e1000_nvm_info *nvm = &hw->nvm;
636 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
637 u32 gfpreg, sector_base_addr, sector_end_addr;
641 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
643 nvm->type = e1000_nvm_flash_sw;
645 if (hw->mac.type >= e1000_pch_spt) {
646 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
647 * STRAP register. This is because in SPT the GbE Flash region
648 * is no longer accessed through the flash registers. Instead,
649 * the mechanism has changed, and the Flash region access
650 * registers are now implemented in GbE memory space.
652 nvm->flash_base_addr = 0;
654 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
655 * NVM_SIZE_MULTIPLIER;
656 nvm->flash_bank_size = nvm_size / 2;
657 /* Adjust to word count */
658 nvm->flash_bank_size /= sizeof(u16);
659 /* Set the base address for flash register access */
660 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
662 /* Can't read flash registers if register set isn't mapped. */
663 if (!hw->flash_address) {
664 DEBUGOUT("ERROR: Flash registers not mapped\n");
665 return -E1000_ERR_CONFIG;
668 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
670 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
671 * Add 1 to sector_end_addr since this sector is included in
674 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
675 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
677 /* flash_base_addr is byte-aligned */
678 nvm->flash_base_addr = sector_base_addr
679 << FLASH_SECTOR_ADDR_SHIFT;
681 /* find total size of the NVM, then cut in half since the total
682 * size represents two separate NVM banks.
684 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
685 << FLASH_SECTOR_ADDR_SHIFT);
686 nvm->flash_bank_size /= 2;
687 /* Adjust to word count */
688 nvm->flash_bank_size /= sizeof(u16);
691 nvm->word_size = E1000_SHADOW_RAM_WORDS;
693 /* Clear shadow ram */
694 for (i = 0; i < nvm->word_size; i++) {
695 dev_spec->shadow_ram[i].modified = false;
696 dev_spec->shadow_ram[i].value = 0xFFFF;
699 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
700 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
702 /* Function Pointers */
703 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
704 nvm->ops.release = e1000_release_nvm_ich8lan;
705 if (hw->mac.type >= e1000_pch_spt) {
706 nvm->ops.read = e1000_read_nvm_spt;
707 nvm->ops.update = e1000_update_nvm_checksum_spt;
709 nvm->ops.read = e1000_read_nvm_ich8lan;
710 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
712 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
713 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
714 nvm->ops.write = e1000_write_nvm_ich8lan;
716 return E1000_SUCCESS;
720 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
721 * @hw: pointer to the HW structure
723 * Initialize family-specific MAC parameters and function
726 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
728 struct e1000_mac_info *mac = &hw->mac;
729 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
731 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
733 DEBUGFUNC("e1000_init_mac_params_ich8lan");
735 /* Set media type function pointer */
736 hw->phy.media_type = e1000_media_type_copper;
738 /* Set mta register count */
739 mac->mta_reg_count = 32;
740 /* Set rar entry count */
741 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
742 if (mac->type == e1000_ich8lan)
743 mac->rar_entry_count--;
744 /* Set if part includes ASF firmware */
745 mac->asf_firmware_present = true;
747 mac->has_fwsm = true;
748 /* ARC subsystem not supported */
749 mac->arc_subsystem_valid = false;
750 /* Adaptive IFS supported */
751 mac->adaptive_ifs = true;
753 /* Function pointers */
755 /* bus type/speed/width */
756 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
758 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
760 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
761 /* hw initialization */
762 mac->ops.init_hw = e1000_init_hw_ich8lan;
764 mac->ops.setup_link = e1000_setup_link_ich8lan;
765 /* physical interface setup */
766 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
768 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
770 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
771 /* multicast address update */
772 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
773 /* clear hardware counters */
774 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
776 /* LED and other operations */
781 /* check management mode */
782 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
784 mac->ops.id_led_init = e1000_id_led_init_generic;
786 mac->ops.blink_led = e1000_blink_led_generic;
788 mac->ops.setup_led = e1000_setup_led_generic;
790 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
791 /* turn on/off LED */
792 mac->ops.led_on = e1000_led_on_ich8lan;
793 mac->ops.led_off = e1000_led_off_ich8lan;
796 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
797 mac->ops.rar_set = e1000_rar_set_pch2lan;
801 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
802 /* multicast address update for pch2 */
803 mac->ops.update_mc_addr_list =
804 e1000_update_mc_addr_list_pch2lan;
808 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
809 /* save PCH revision_id */
810 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
811 /* SPT uses full byte for revision ID,
812 * as opposed to previous generations
814 if (hw->mac.type >= e1000_pch_spt)
815 hw->revision_id = (u8)(pci_cfg &= 0x00FF);
817 hw->revision_id = (u8)(pci_cfg &= 0x000F);
818 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
819 /* check management mode */
820 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
822 mac->ops.id_led_init = e1000_id_led_init_pchlan;
824 mac->ops.setup_led = e1000_setup_led_pchlan;
826 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
827 /* turn on/off LED */
828 mac->ops.led_on = e1000_led_on_pchlan;
829 mac->ops.led_off = e1000_led_off_pchlan;
835 if (mac->type >= e1000_pch_lpt) {
836 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
837 mac->ops.rar_set = e1000_rar_set_pch_lpt;
838 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
841 /* Enable PCS Lock-loss workaround for ICH8 */
842 if (mac->type == e1000_ich8lan)
843 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
845 return E1000_SUCCESS;
849 * __e1000_access_emi_reg_locked - Read/write EMI register
850 * @hw: pointer to the HW structure
851 * @addr: EMI address to program
852 * @data: pointer to value to read/write from/to the EMI address
853 * @read: boolean flag to indicate read or write
855 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
857 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
858 u16 *data, bool read)
862 DEBUGFUNC("__e1000_access_emi_reg_locked");
864 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
869 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
872 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
879 * e1000_read_emi_reg_locked - Read Extended Management Interface register
880 * @hw: pointer to the HW structure
881 * @addr: EMI address to program
882 * @data: value to be read from the EMI address
884 * Assumes the SW/FW/HW Semaphore is already acquired.
886 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
888 DEBUGFUNC("e1000_read_emi_reg_locked");
890 return __e1000_access_emi_reg_locked(hw, addr, data, true);
894 * e1000_write_emi_reg_locked - Write Extended Management Interface register
895 * @hw: pointer to the HW structure
896 * @addr: EMI address to program
897 * @data: value to be written to the EMI address
899 * Assumes the SW/FW/HW Semaphore is already acquired.
901 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
903 DEBUGFUNC("e1000_read_emi_reg_locked");
905 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
909 * e1000_set_eee_pchlan - Enable/disable EEE support
910 * @hw: pointer to the HW structure
912 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
913 * the link and the EEE capabilities of the link partner. The LPI Control
914 * register bits will remain set only if/when link is up.
916 * EEE LPI must not be asserted earlier than one second after link is up.
917 * On 82579, EEE LPI should not be enabled until such time otherwise there
918 * can be link issues with some switches. Other devices can have EEE LPI
919 * enabled immediately upon link up since they have a timer in hardware which
920 * prevents LPI from being asserted too early.
922 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
924 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
926 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
928 DEBUGFUNC("e1000_set_eee_pchlan");
930 switch (hw->phy.type) {
931 case e1000_phy_82579:
932 lpa = I82579_EEE_LP_ABILITY;
933 pcs_status = I82579_EEE_PCS_STATUS;
934 adv_addr = I82579_EEE_ADVERTISEMENT;
937 lpa = I217_EEE_LP_ABILITY;
938 pcs_status = I217_EEE_PCS_STATUS;
939 adv_addr = I217_EEE_ADVERTISEMENT;
942 return E1000_SUCCESS;
945 ret_val = hw->phy.ops.acquire(hw);
949 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
953 /* Clear bits that enable EEE in various speeds */
954 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
956 /* Enable EEE if not disabled by user */
957 if (!dev_spec->eee_disable) {
958 /* Save off link partner's EEE ability */
959 ret_val = e1000_read_emi_reg_locked(hw, lpa,
960 &dev_spec->eee_lp_ability);
964 /* Read EEE advertisement */
965 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
969 /* Enable EEE only for speeds in which the link partner is
970 * EEE capable and for which we advertise EEE.
972 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
973 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
975 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
976 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
977 if (data & NWAY_LPAR_100TX_FD_CAPS)
978 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
980 /* EEE is not supported in 100Half, so ignore
981 * partner's EEE in 100 ability if full-duplex
984 dev_spec->eee_lp_ability &=
985 ~I82579_EEE_100_SUPPORTED;
989 if (hw->phy.type == e1000_phy_82579) {
990 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
995 data &= ~I82579_LPI_100_PLL_SHUT;
996 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
1000 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
1001 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
1005 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
1007 hw->phy.ops.release(hw);
1013 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
1014 * @hw: pointer to the HW structure
1015 * @link: link up bool flag
1017 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
1018 * preventing further DMA write requests. Workaround the issue by disabling
1019 * the de-assertion of the clock request when in 1Gpbs mode.
1020 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1021 * speeds in order to avoid Tx hangs.
1023 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1025 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1026 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1027 s32 ret_val = E1000_SUCCESS;
1030 if (link && (status & E1000_STATUS_SPEED_1000)) {
1031 ret_val = hw->phy.ops.acquire(hw);
1036 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1042 e1000_write_kmrn_reg_locked(hw,
1043 E1000_KMRNCTRLSTA_K1_CONFIG,
1045 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1051 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1052 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1055 e1000_write_kmrn_reg_locked(hw,
1056 E1000_KMRNCTRLSTA_K1_CONFIG,
1059 hw->phy.ops.release(hw);
1061 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1062 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1064 if ((hw->phy.revision > 5) || !link ||
1065 ((status & E1000_STATUS_SPEED_100) &&
1066 (status & E1000_STATUS_FD)))
1067 goto update_fextnvm6;
1069 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1073 /* Clear link status transmit timeout */
1074 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1076 if (status & E1000_STATUS_SPEED_100) {
1077 /* Set inband Tx timeout to 5x10us for 100Half */
1078 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1080 /* Do not extend the K1 entry latency for 100Half */
1081 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1083 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1085 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1087 /* Extend the K1 entry latency for 10 Mbps */
1088 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1091 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1096 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1104 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1105 * @hw: pointer to the HW structure
1106 * @to_sx: boolean indicating a system power state transition to Sx
1108 * When link is down, configure ULP mode to significantly reduce the power
1109 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1110 * ME firmware to start the ULP configuration. If not on an ME enabled
1111 * system, configure the ULP mode by software.
1113 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1116 s32 ret_val = E1000_SUCCESS;
1120 if ((hw->mac.type < e1000_pch_lpt) ||
1121 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1122 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1123 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1124 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1125 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1130 /* Poll up to 5 seconds for Cable Disconnected indication */
1131 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1132 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1133 /* Bail if link is re-acquired */
1134 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1135 return -E1000_ERR_PHY;
1141 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1142 (E1000_READ_REG(hw, E1000_FEXT) &
1143 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1145 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1146 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1150 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1151 /* Request ME configure ULP mode in the PHY */
1152 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1153 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1154 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1159 ret_val = hw->phy.ops.acquire(hw);
1163 /* During S0 Idle keep the phy in PCI-E mode */
1164 if (hw->dev_spec.ich8lan.smbus_disable)
1167 /* Force SMBus mode in PHY */
1168 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1171 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1172 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1174 /* Force SMBus mode in MAC */
1175 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1176 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1177 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1179 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1180 * LPLU and disable Gig speed when entering ULP
1182 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1183 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1189 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1191 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1200 /* Change the 'Link Status Change' interrupt to trigger
1201 * on 'Cable Status Change'
1203 ret_val = e1000_read_kmrn_reg_locked(hw,
1204 E1000_KMRNCTRLSTA_OP_MODES,
1208 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1209 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1213 /* Set Inband ULP Exit, Reset to SMBus mode and
1214 * Disable SMBus Release on PERST# in PHY
1216 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1219 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1220 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1222 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1223 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1225 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1227 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1228 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1230 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1231 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1232 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1234 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1236 /* Set Disable SMBus Release on PERST# in MAC */
1237 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1238 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1239 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1241 /* Commit ULP changes in PHY by starting auto ULP configuration */
1242 phy_reg |= I218_ULP_CONFIG1_START;
1243 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1246 /* Disable Tx so that the MAC doesn't send any (buffered)
1247 * packets to the PHY.
1249 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1250 mac_reg &= ~E1000_TCTL_EN;
1251 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1254 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1255 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1256 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1263 hw->phy.ops.release(hw);
1266 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1268 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1274 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1275 * @hw: pointer to the HW structure
1276 * @force: boolean indicating whether or not to force disabling ULP
1278 * Un-configure ULP mode when link is up, the system is transitioned from
1279 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1280 * system, poll for an indication from ME that ULP has been un-configured.
1281 * If not on an ME enabled system, un-configure the ULP mode by software.
1283 * During nominal operation, this function is called when link is acquired
1284 * to disable ULP mode (force=false); otherwise, for example when unloading
1285 * the driver or during Sx->S0 transitions, this is called with force=true
1286 * to forcibly disable ULP.
1288 * When the cable is plugged in while the device is in D0, a Cable Status
1289 * Change interrupt is generated which causes this function to be called
1290 * to partially disable ULP mode and restart autonegotiation. This function
1291 * is then called again due to the resulting Link Status Change interrupt
1292 * to finish cleaning up after the ULP flow.
1294 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1296 s32 ret_val = E1000_SUCCESS;
1301 if ((hw->mac.type < e1000_pch_lpt) ||
1302 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1303 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1304 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1305 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1306 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1309 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1311 /* Request ME un-configure ULP mode in the PHY */
1312 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1313 mac_reg &= ~E1000_H2ME_ULP;
1314 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1315 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1318 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1319 while (E1000_READ_REG(hw, E1000_FWSM) &
1320 E1000_FWSM_ULP_CFG_DONE) {
1322 ret_val = -E1000_ERR_PHY;
1328 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1331 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1332 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1333 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1335 /* Clear H2ME.ULP after ME ULP configuration */
1336 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1337 mac_reg &= ~E1000_H2ME_ULP;
1338 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1340 /* Restore link speed advertisements and restart
1343 if (hw->mac.autoneg) {
1344 ret_val = e1000_phy_setup_autoneg(hw);
1348 ret_val = e1000_setup_copper_link_generic(hw);
1352 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1358 ret_val = hw->phy.ops.acquire(hw);
1362 /* Revert the change to the 'Link Status Change'
1363 * interrupt to trigger on 'Cable Status Change'
1365 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1369 phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1370 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1373 /* Toggle LANPHYPC Value bit */
1374 e1000_toggle_lanphypc_pch_lpt(hw);
1376 /* Unforce SMBus mode in PHY */
1377 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1379 /* The MAC might be in PCIe mode, so temporarily force to
1380 * SMBus mode in order to access the PHY.
1382 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1383 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1384 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1388 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1393 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1394 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1396 /* Unforce SMBus mode in MAC */
1397 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1398 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1399 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1401 /* When ULP mode was previously entered, K1 was disabled by the
1402 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1404 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1407 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1408 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1410 /* Clear ULP enabled configuration */
1411 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1414 /* CSC interrupt received due to ULP Indication */
1415 if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1416 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1417 I218_ULP_CONFIG1_STICKY_ULP |
1418 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1419 I218_ULP_CONFIG1_WOL_HOST |
1420 I218_ULP_CONFIG1_INBAND_EXIT |
1421 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1422 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1423 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1424 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1426 /* Commit ULP changes by starting auto ULP configuration */
1427 phy_reg |= I218_ULP_CONFIG1_START;
1428 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1430 /* Clear Disable SMBus Release on PERST# in MAC */
1431 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1432 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1433 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1436 hw->phy.ops.release(hw);
1438 if (hw->mac.autoneg)
1439 e1000_phy_setup_autoneg(hw);
1441 e1000_setup_copper_link_generic(hw);
1443 e1000_sw_lcd_config_ich8lan(hw);
1445 e1000_oem_bits_config_ich8lan(hw, true);
1447 /* Set ULP state to unknown and return non-zero to
1448 * indicate no link (yet) and re-enter on the next LSC
1449 * to finish disabling ULP flow.
1451 hw->dev_spec.ich8lan.ulp_state =
1452 e1000_ulp_state_unknown;
1459 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1460 mac_reg |= E1000_TCTL_EN;
1461 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1464 hw->phy.ops.release(hw);
1466 hw->phy.ops.reset(hw);
1471 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1473 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1478 #endif /* ULP_SUPPORT */
1482 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1483 * @hw: pointer to the HW structure
1485 * Checks to see of the link status of the hardware has changed. If a
1486 * change in link status has been detected, then we read the PHY registers
1487 * to get the current speed/duplex if link exists.
1489 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1491 struct e1000_mac_info *mac = &hw->mac;
1492 s32 ret_val, tipg_reg = 0;
1493 u16 emi_addr, emi_val = 0;
1497 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1499 /* We only want to go out to the PHY registers to see if Auto-Neg
1500 * has completed and/or if our link status has changed. The
1501 * get_link_status flag is set upon receiving a Link Status
1502 * Change or Rx Sequence Error interrupt.
1504 if (!mac->get_link_status)
1505 return E1000_SUCCESS;
1507 if ((hw->mac.type < e1000_pch_lpt) ||
1508 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1509 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1510 /* First we want to see if the MII Status Register reports
1511 * link. If so, then we want to get the current speed/duplex
1514 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1518 /* Check the MAC's STATUS register to determine link state
1519 * since the PHY could be inaccessible while in ULP mode.
1521 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1523 ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1525 ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1530 if (hw->mac.type == e1000_pchlan) {
1531 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1536 /* When connected at 10Mbps half-duplex, some parts are excessively
1537 * aggressive resulting in many collisions. To avoid this, increase
1538 * the IPG and reduce Rx latency in the PHY.
1540 if ((hw->mac.type >= e1000_pch2lan) && link) {
1543 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1544 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1545 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1547 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1549 /* Reduce Rx latency in analog PHY */
1551 } else if (hw->mac.type >= e1000_pch_spt &&
1552 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1556 /* Roll back the default values */
1561 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1563 ret_val = hw->phy.ops.acquire(hw);
1567 if (hw->mac.type == e1000_pch2lan)
1568 emi_addr = I82579_RX_CONFIG;
1570 emi_addr = I217_RX_CONFIG;
1571 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1574 if (hw->mac.type >= e1000_pch_lpt) {
1577 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1579 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1580 if (speed == SPEED_100 || speed == SPEED_10)
1584 hw->phy.ops.write_reg_locked(hw,
1585 I217_PLL_CLOCK_GATE_REG,
1588 hw->phy.ops.release(hw);
1593 if (hw->mac.type >= e1000_pch_spt) {
1597 if (speed == SPEED_1000) {
1598 ret_val = hw->phy.ops.acquire(hw);
1602 ret_val = hw->phy.ops.read_reg_locked(hw,
1606 hw->phy.ops.release(hw);
1610 ptr_gap = (data & (0x3FF << 2)) >> 2;
1611 if (ptr_gap < 0x18) {
1612 data &= ~(0x3FF << 2);
1613 data |= (0x18 << 2);
1615 hw->phy.ops.write_reg_locked(hw,
1616 PHY_REG(776, 20), data);
1618 hw->phy.ops.release(hw);
1622 ret_val = hw->phy.ops.acquire(hw);
1626 ret_val = hw->phy.ops.write_reg_locked(hw,
1629 hw->phy.ops.release(hw);
1637 /* I217 Packet Loss issue:
1638 * ensure that FEXTNVM4 Beacon Duration is set correctly
1640 * Set the Beacon Duration for I217 to 8 usec
1642 if (hw->mac.type >= e1000_pch_lpt) {
1645 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1646 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1647 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1648 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1651 /* Work-around I218 hang issue */
1652 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1653 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1654 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1655 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1656 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1660 /* Clear link partner's EEE ability */
1661 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1663 /* Configure K0s minimum time */
1664 if (hw->mac.type >= e1000_pch_lpt) {
1665 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1668 if (hw->mac.type >= e1000_pch_lpt) {
1669 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1671 if (hw->mac.type == e1000_pch_spt) {
1672 /* FEXTNVM6 K1-off workaround - for SPT only */
1673 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1675 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1676 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1678 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1681 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1685 return E1000_SUCCESS; /* No link detected */
1687 mac->get_link_status = false;
1689 switch (hw->mac.type) {
1691 ret_val = e1000_k1_workaround_lv(hw);
1696 if (hw->phy.type == e1000_phy_82578) {
1697 ret_val = e1000_link_stall_workaround_hv(hw);
1702 /* Workaround for PCHx parts in half-duplex:
1703 * Set the number of preambles removed from the packet
1704 * when it is passed from the PHY to the MAC to prevent
1705 * the MAC from misinterpreting the packet type.
1707 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1708 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1710 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1712 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1714 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1720 /* Check if there was DownShift, must be checked
1721 * immediately after link-up
1723 e1000_check_downshift_generic(hw);
1725 /* Enable/Disable EEE after link up */
1726 if (hw->phy.type > e1000_phy_82579) {
1727 ret_val = e1000_set_eee_pchlan(hw);
1732 /* If we are forcing speed/duplex, then we simply return since
1733 * we have already determined whether we have link or not.
1736 return -E1000_ERR_CONFIG;
1738 /* Auto-Neg is enabled. Auto Speed Detection takes care
1739 * of MAC speed/duplex configuration. So we only need to
1740 * configure Collision Distance in the MAC.
1742 mac->ops.config_collision_dist(hw);
1744 /* Configure Flow Control now that Auto-Neg has completed.
1745 * First, we need to restore the desired flow control
1746 * settings because we may have had to re-autoneg with a
1747 * different link partner.
1749 ret_val = e1000_config_fc_after_link_up_generic(hw);
1751 DEBUGOUT("Error configuring flow control\n");
1757 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1758 * @hw: pointer to the HW structure
1760 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1762 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1764 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1766 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1767 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1768 switch (hw->mac.type) {
1771 case e1000_ich10lan:
1772 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1778 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1786 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1787 * @hw: pointer to the HW structure
1789 * Acquires the mutex for performing NVM operations.
1791 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1793 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1795 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1797 return E1000_SUCCESS;
1801 * e1000_release_nvm_ich8lan - Release NVM mutex
1802 * @hw: pointer to the HW structure
1804 * Releases the mutex used while performing NVM operations.
1806 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1808 DEBUGFUNC("e1000_release_nvm_ich8lan");
1810 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1816 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1817 * @hw: pointer to the HW structure
1819 * Acquires the software control flag for performing PHY and select
1822 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1824 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1825 s32 ret_val = E1000_SUCCESS;
1827 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1829 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1832 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1833 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1841 DEBUGOUT("SW has already locked the resource.\n");
1842 ret_val = -E1000_ERR_CONFIG;
1846 timeout = SW_FLAG_TIMEOUT;
1848 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1849 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1852 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1853 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1861 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1862 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1863 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1864 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1865 ret_val = -E1000_ERR_CONFIG;
1871 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1877 * e1000_release_swflag_ich8lan - Release software control flag
1878 * @hw: pointer to the HW structure
1880 * Releases the software control flag for performing PHY and select
1883 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1887 DEBUGFUNC("e1000_release_swflag_ich8lan");
1889 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1891 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1892 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1893 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1895 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1898 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1904 * e1000_check_mng_mode_ich8lan - Checks management mode
1905 * @hw: pointer to the HW structure
1907 * This checks if the adapter has any manageability enabled.
1908 * This is a function pointer entry point only called by read/write
1909 * routines for the PHY and NVM parts.
1911 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1915 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1917 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1919 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1920 ((fwsm & E1000_FWSM_MODE_MASK) ==
1921 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1925 * e1000_check_mng_mode_pchlan - Checks management mode
1926 * @hw: pointer to the HW structure
1928 * This checks if the adapter has iAMT enabled.
1929 * This is a function pointer entry point only called by read/write
1930 * routines for the PHY and NVM parts.
1932 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1936 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1938 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1940 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1941 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1945 * e1000_rar_set_pch2lan - Set receive address register
1946 * @hw: pointer to the HW structure
1947 * @addr: pointer to the receive address
1948 * @index: receive address array register
1950 * Sets the receive address array register at index to the address passed
1951 * in by addr. For 82579, RAR[0] is the base address register that is to
1952 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1953 * Use SHRA[0-3] in place of those reserved for ME.
1955 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1957 u32 rar_low, rar_high;
1959 DEBUGFUNC("e1000_rar_set_pch2lan");
1961 /* HW expects these in little endian so we reverse the byte order
1962 * from network order (big endian) to little endian
1964 rar_low = ((u32) addr[0] |
1965 ((u32) addr[1] << 8) |
1966 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1968 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1970 /* If MAC address zero, no need to set the AV bit */
1971 if (rar_low || rar_high)
1972 rar_high |= E1000_RAH_AV;
1975 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1976 E1000_WRITE_FLUSH(hw);
1977 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1978 E1000_WRITE_FLUSH(hw);
1979 return E1000_SUCCESS;
1982 /* RAR[1-6] are owned by manageability. Skip those and program the
1983 * next address into the SHRA register array.
1985 if (index < (u32) (hw->mac.rar_entry_count)) {
1988 ret_val = e1000_acquire_swflag_ich8lan(hw);
1992 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1993 E1000_WRITE_FLUSH(hw);
1994 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1995 E1000_WRITE_FLUSH(hw);
1997 e1000_release_swflag_ich8lan(hw);
1999 /* verify the register updates */
2000 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2001 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2002 return E1000_SUCCESS;
2004 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
2005 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2009 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2010 return -E1000_ERR_CONFIG;
2014 * e1000_rar_set_pch_lpt - Set receive address registers
2015 * @hw: pointer to the HW structure
2016 * @addr: pointer to the receive address
2017 * @index: receive address array register
2019 * Sets the receive address register array at index to the address passed
2020 * in by addr. For LPT, RAR[0] is the base address register that is to
2021 * contain the MAC address. SHRA[0-10] are the shared receive address
2022 * registers that are shared between the Host and manageability engine (ME).
2024 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2026 u32 rar_low, rar_high;
2029 DEBUGFUNC("e1000_rar_set_pch_lpt");
2031 /* HW expects these in little endian so we reverse the byte order
2032 * from network order (big endian) to little endian
2034 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2035 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2037 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2039 /* If MAC address zero, no need to set the AV bit */
2040 if (rar_low || rar_high)
2041 rar_high |= E1000_RAH_AV;
2044 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2045 E1000_WRITE_FLUSH(hw);
2046 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2047 E1000_WRITE_FLUSH(hw);
2048 return E1000_SUCCESS;
2051 /* The manageability engine (ME) can lock certain SHRAR registers that
2052 * it is using - those registers are unavailable for use.
2054 if (index < hw->mac.rar_entry_count) {
2055 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2056 E1000_FWSM_WLOCK_MAC_MASK;
2057 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2059 /* Check if all SHRAR registers are locked */
2063 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2066 ret_val = e1000_acquire_swflag_ich8lan(hw);
2071 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2073 E1000_WRITE_FLUSH(hw);
2074 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2076 E1000_WRITE_FLUSH(hw);
2078 e1000_release_swflag_ich8lan(hw);
2080 /* verify the register updates */
2081 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2082 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2083 return E1000_SUCCESS;
2088 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2089 return -E1000_ERR_CONFIG;
2092 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
2094 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2095 * @hw: pointer to the HW structure
2096 * @mc_addr_list: array of multicast addresses to program
2097 * @mc_addr_count: number of multicast addresses to program
2099 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2100 * The caller must have a packed mc_addr_list of multicast addresses.
2102 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2110 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2112 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2114 ret_val = hw->phy.ops.acquire(hw);
2118 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2122 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2123 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2124 (u16)(hw->mac.mta_shadow[i] &
2126 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2127 (u16)((hw->mac.mta_shadow[i] >> 16) &
2131 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2134 hw->phy.ops.release(hw);
2137 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
2139 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2140 * @hw: pointer to the HW structure
2142 * Checks if firmware is blocking the reset of the PHY.
2143 * This is a function pointer entry point only called by
2146 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2149 bool blocked = false;
2152 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2155 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2156 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2162 } while (blocked && (i++ < 30));
2163 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2167 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2168 * @hw: pointer to the HW structure
2170 * Assumes semaphore already acquired.
2173 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2176 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2177 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2178 E1000_STRAP_SMT_FREQ_SHIFT;
2181 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2183 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2187 phy_data &= ~HV_SMB_ADDR_MASK;
2188 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2189 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2191 if (hw->phy.type == e1000_phy_i217) {
2192 /* Restore SMBus frequency */
2194 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2195 phy_data |= (freq & (1 << 0)) <<
2196 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2197 phy_data |= (freq & (1 << 1)) <<
2198 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2200 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2204 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2208 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2209 * @hw: pointer to the HW structure
2211 * SW should configure the LCD from the NVM extended configuration region
2212 * as a workaround for certain parts.
2214 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2216 struct e1000_phy_info *phy = &hw->phy;
2217 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2218 s32 ret_val = E1000_SUCCESS;
2219 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2221 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2223 /* Initialize the PHY from the NVM on ICH platforms. This
2224 * is needed due to an issue where the NVM configuration is
2225 * not properly autoloaded after power transitions.
2226 * Therefore, after each PHY reset, we will load the
2227 * configuration data out of the NVM manually.
2229 switch (hw->mac.type) {
2231 if (phy->type != e1000_phy_igp_3)
2234 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2235 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2236 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2244 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2250 ret_val = hw->phy.ops.acquire(hw);
2254 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2255 if (!(data & sw_cfg_mask))
2258 /* Make sure HW does not configure LCD from PHY
2259 * extended configuration before SW configuration
2261 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2262 if ((hw->mac.type < e1000_pch2lan) &&
2263 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2266 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2267 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2268 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2272 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2273 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2275 if (((hw->mac.type == e1000_pchlan) &&
2276 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2277 (hw->mac.type > e1000_pchlan)) {
2278 /* HW configures the SMBus address and LEDs when the
2279 * OEM and LCD Write Enable bits are set in the NVM.
2280 * When both NVM bits are cleared, SW will configure
2283 ret_val = e1000_write_smbus_addr(hw);
2287 data = E1000_READ_REG(hw, E1000_LEDCTL);
2288 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2294 /* Configure LCD from extended configuration region. */
2296 /* cnf_base_addr is in DWORD */
2297 word_addr = (u16)(cnf_base_addr << 1);
2299 for (i = 0; i < cnf_size; i++) {
2300 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2305 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2310 /* Save off the PHY page for future writes. */
2311 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2312 phy_page = reg_data;
2316 reg_addr &= PHY_REG_MASK;
2317 reg_addr |= phy_page;
2319 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2326 hw->phy.ops.release(hw);
2331 * e1000_k1_gig_workaround_hv - K1 Si workaround
2332 * @hw: pointer to the HW structure
2333 * @link: link up bool flag
2335 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2336 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2337 * If link is down, the function will restore the default K1 setting located
2340 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2342 s32 ret_val = E1000_SUCCESS;
2344 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2346 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2348 if (hw->mac.type != e1000_pchlan)
2349 return E1000_SUCCESS;
2351 /* Wrap the whole flow with the sw flag */
2352 ret_val = hw->phy.ops.acquire(hw);
2356 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2358 if (hw->phy.type == e1000_phy_82578) {
2359 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2364 status_reg &= (BM_CS_STATUS_LINK_UP |
2365 BM_CS_STATUS_RESOLVED |
2366 BM_CS_STATUS_SPEED_MASK);
2368 if (status_reg == (BM_CS_STATUS_LINK_UP |
2369 BM_CS_STATUS_RESOLVED |
2370 BM_CS_STATUS_SPEED_1000))
2374 if (hw->phy.type == e1000_phy_82577) {
2375 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2380 status_reg &= (HV_M_STATUS_LINK_UP |
2381 HV_M_STATUS_AUTONEG_COMPLETE |
2382 HV_M_STATUS_SPEED_MASK);
2384 if (status_reg == (HV_M_STATUS_LINK_UP |
2385 HV_M_STATUS_AUTONEG_COMPLETE |
2386 HV_M_STATUS_SPEED_1000))
2390 /* Link stall fix for link up */
2391 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2397 /* Link stall fix for link down */
2398 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2404 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2407 hw->phy.ops.release(hw);
2413 * e1000_configure_k1_ich8lan - Configure K1 power state
2414 * @hw: pointer to the HW structure
2415 * @enable: K1 state to configure
2417 * Configure the K1 power state based on the provided parameter.
2418 * Assumes semaphore already acquired.
2420 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2422 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2430 DEBUGFUNC("e1000_configure_k1_ich8lan");
2432 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2438 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2440 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2442 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2448 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2449 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2451 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2452 reg |= E1000_CTRL_FRCSPD;
2453 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2455 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2456 E1000_WRITE_FLUSH(hw);
2458 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2459 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2460 E1000_WRITE_FLUSH(hw);
2463 return E1000_SUCCESS;
2467 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2468 * @hw: pointer to the HW structure
2469 * @d0_state: boolean if entering d0 or d3 device state
2471 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2472 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2473 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2475 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2481 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2483 if (hw->mac.type < e1000_pchlan)
2486 ret_val = hw->phy.ops.acquire(hw);
2490 if (hw->mac.type == e1000_pchlan) {
2491 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2492 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2496 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2497 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2500 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2502 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2506 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2509 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2510 oem_reg |= HV_OEM_BITS_GBE_DIS;
2512 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2513 oem_reg |= HV_OEM_BITS_LPLU;
2515 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2516 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2517 oem_reg |= HV_OEM_BITS_GBE_DIS;
2519 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2520 E1000_PHY_CTRL_NOND0A_LPLU))
2521 oem_reg |= HV_OEM_BITS_LPLU;
2524 /* Set Restart auto-neg to activate the bits */
2525 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2526 !hw->phy.ops.check_reset_block(hw))
2527 oem_reg |= HV_OEM_BITS_RESTART_AN;
2529 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2532 hw->phy.ops.release(hw);
2539 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2540 * @hw: pointer to the HW structure
2542 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2547 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2549 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2553 data |= HV_KMRN_MDIO_SLOW;
2555 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2561 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2562 * done after every PHY reset.
2564 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2566 s32 ret_val = E1000_SUCCESS;
2569 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2571 if (hw->mac.type != e1000_pchlan)
2572 return E1000_SUCCESS;
2574 /* Set MDIO slow mode before any other MDIO access */
2575 if (hw->phy.type == e1000_phy_82577) {
2576 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2581 if (((hw->phy.type == e1000_phy_82577) &&
2582 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2583 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2584 /* Disable generation of early preamble */
2585 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2589 /* Preamble tuning for SSC */
2590 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2596 if (hw->phy.type == e1000_phy_82578) {
2597 /* Return registers to default by doing a soft reset then
2598 * writing 0x3140 to the control register.
2600 if (hw->phy.revision < 2) {
2601 e1000_phy_sw_reset_generic(hw);
2602 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2608 ret_val = hw->phy.ops.acquire(hw);
2613 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2614 hw->phy.ops.release(hw);
2618 /* Configure the K1 Si workaround during phy reset assuming there is
2619 * link so that it disables K1 if link is in 1Gbps.
2621 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2625 /* Workaround for link disconnects on a busy hub in half duplex */
2626 ret_val = hw->phy.ops.acquire(hw);
2629 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2632 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2637 /* set MSE higher to enable link to stay up when noise is high */
2638 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2640 hw->phy.ops.release(hw);
2646 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2647 * @hw: pointer to the HW structure
2649 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2655 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2657 ret_val = hw->phy.ops.acquire(hw);
2660 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2664 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2665 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2666 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2667 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2668 (u16)(mac_reg & 0xFFFF));
2669 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2670 (u16)((mac_reg >> 16) & 0xFFFF));
2672 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2673 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2674 (u16)(mac_reg & 0xFFFF));
2675 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2676 (u16)((mac_reg & E1000_RAH_AV)
2680 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2683 hw->phy.ops.release(hw);
2686 #ifndef CRC32_OS_SUPPORT
2687 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2689 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2690 u32 i, j, mask, crc;
2692 DEBUGFUNC("e1000_calc_rx_da_crc");
2695 for (i = 0; i < 6; i++) {
2697 for (j = 8; j > 0; j--) {
2698 mask = (crc & 1) * (-1);
2699 crc = (crc >> 1) ^ (poly & mask);
2705 #endif /* CRC32_OS_SUPPORT */
2707 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2709 * @hw: pointer to the HW structure
2710 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2712 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2714 s32 ret_val = E1000_SUCCESS;
2719 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2721 if (hw->mac.type < e1000_pch2lan)
2722 return E1000_SUCCESS;
2724 /* disable Rx path while enabling/disabling workaround */
2725 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2726 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2727 phy_reg | (1 << 14));
2732 /* Write Rx addresses (rar_entry_count for RAL/H, and
2733 * SHRAL/H) and initial CRC values to the MAC
2735 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2736 u8 mac_addr[ETH_ADDR_LEN] = {0};
2737 u32 addr_high, addr_low;
2739 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2740 if (!(addr_high & E1000_RAH_AV))
2742 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2743 mac_addr[0] = (addr_low & 0xFF);
2744 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2745 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2746 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2747 mac_addr[4] = (addr_high & 0xFF);
2748 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2750 #ifndef CRC32_OS_SUPPORT
2751 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2752 e1000_calc_rx_da_crc(mac_addr));
2753 #else /* CRC32_OS_SUPPORT */
2754 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2755 E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2756 #endif /* CRC32_OS_SUPPORT */
2759 /* Write Rx addresses to the PHY */
2760 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2762 /* Enable jumbo frame workaround in the MAC */
2763 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2764 mac_reg &= ~(1 << 14);
2765 mac_reg |= (7 << 15);
2766 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2768 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2769 mac_reg |= E1000_RCTL_SECRC;
2770 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2772 ret_val = e1000_read_kmrn_reg_generic(hw,
2773 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2777 ret_val = e1000_write_kmrn_reg_generic(hw,
2778 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2782 ret_val = e1000_read_kmrn_reg_generic(hw,
2783 E1000_KMRNCTRLSTA_HD_CTRL,
2787 data &= ~(0xF << 8);
2789 ret_val = e1000_write_kmrn_reg_generic(hw,
2790 E1000_KMRNCTRLSTA_HD_CTRL,
2795 /* Enable jumbo frame workaround in the PHY */
2796 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2797 data &= ~(0x7F << 5);
2798 data |= (0x37 << 5);
2799 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2802 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2804 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2807 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2808 data &= ~(0x3FF << 2);
2809 data |= (E1000_TX_PTR_GAP << 2);
2810 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2813 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2816 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2817 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2822 /* Write MAC register values back to h/w defaults */
2823 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2824 mac_reg &= ~(0xF << 14);
2825 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2827 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2828 mac_reg &= ~E1000_RCTL_SECRC;
2829 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2831 ret_val = e1000_read_kmrn_reg_generic(hw,
2832 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2836 ret_val = e1000_write_kmrn_reg_generic(hw,
2837 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2841 ret_val = e1000_read_kmrn_reg_generic(hw,
2842 E1000_KMRNCTRLSTA_HD_CTRL,
2846 data &= ~(0xF << 8);
2848 ret_val = e1000_write_kmrn_reg_generic(hw,
2849 E1000_KMRNCTRLSTA_HD_CTRL,
2854 /* Write PHY register values back to h/w defaults */
2855 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2856 data &= ~(0x7F << 5);
2857 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2860 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2862 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2865 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2866 data &= ~(0x3FF << 2);
2868 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2871 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2874 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2875 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2881 /* re-enable Rx path after enabling/disabling workaround */
2882 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2887 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2888 * done after every PHY reset.
2890 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2892 s32 ret_val = E1000_SUCCESS;
2894 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2896 if (hw->mac.type != e1000_pch2lan)
2897 return E1000_SUCCESS;
2899 /* Set MDIO slow mode before any other MDIO access */
2900 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2904 ret_val = hw->phy.ops.acquire(hw);
2907 /* set MSE higher to enable link to stay up when noise is high */
2908 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2911 /* drop link after 5 times MSE threshold was reached */
2912 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2914 hw->phy.ops.release(hw);
2920 * e1000_k1_gig_workaround_lv - K1 Si workaround
2921 * @hw: pointer to the HW structure
2923 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2924 * Disable K1 for 1000 and 100 speeds
2926 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2928 s32 ret_val = E1000_SUCCESS;
2931 DEBUGFUNC("e1000_k1_workaround_lv");
2933 if (hw->mac.type != e1000_pch2lan)
2934 return E1000_SUCCESS;
2936 /* Set K1 beacon duration based on 10Mbs speed */
2937 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2941 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2942 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2944 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2947 /* LV 1G/100 Packet drop issue wa */
2948 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2952 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2953 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2959 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2960 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2961 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2962 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2970 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2971 * @hw: pointer to the HW structure
2972 * @gate: boolean set to true to gate, false to ungate
2974 * Gate/ungate the automatic PHY configuration via hardware; perform
2975 * the configuration via software instead.
2977 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2981 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2983 if (hw->mac.type < e1000_pch2lan)
2986 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2989 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2991 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2993 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2997 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2998 * @hw: pointer to the HW structure
3000 * Check the appropriate indication the MAC has finished configuring the
3001 * PHY after a software reset.
3003 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3005 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3007 DEBUGFUNC("e1000_lan_init_done_ich8lan");
3009 /* Wait for basic configuration completes before proceeding */
3011 data = E1000_READ_REG(hw, E1000_STATUS);
3012 data &= E1000_STATUS_LAN_INIT_DONE;
3014 } while ((!data) && --loop);
3016 /* If basic configuration is incomplete before the above loop
3017 * count reaches 0, loading the configuration from NVM will
3018 * leave the PHY in a bad state possibly resulting in no link.
3021 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3023 /* Clear the Init Done bit for the next init event */
3024 data = E1000_READ_REG(hw, E1000_STATUS);
3025 data &= ~E1000_STATUS_LAN_INIT_DONE;
3026 E1000_WRITE_REG(hw, E1000_STATUS, data);
3030 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3031 * @hw: pointer to the HW structure
3033 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3035 s32 ret_val = E1000_SUCCESS;
3038 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3040 if (hw->phy.ops.check_reset_block(hw))
3041 return E1000_SUCCESS;
3043 /* Allow time for h/w to get to quiescent state after reset */
3046 /* Perform any necessary post-reset workarounds */
3047 switch (hw->mac.type) {
3049 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3054 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3062 /* Clear the host wakeup bit after lcd reset */
3063 if (hw->mac.type >= e1000_pchlan) {
3064 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3065 reg &= ~BM_WUC_HOST_WU_BIT;
3066 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3069 /* Configure the LCD with the extended configuration region in NVM */
3070 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3074 /* Configure the LCD with the OEM bits in NVM */
3075 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3077 if (hw->mac.type == e1000_pch2lan) {
3078 /* Ungate automatic PHY configuration on non-managed 82579 */
3079 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3080 E1000_ICH_FWSM_FW_VALID)) {
3082 e1000_gate_hw_phy_config_ich8lan(hw, false);
3085 /* Set EEE LPI Update Timer to 200usec */
3086 ret_val = hw->phy.ops.acquire(hw);
3089 ret_val = e1000_write_emi_reg_locked(hw,
3090 I82579_LPI_UPDATE_TIMER,
3092 hw->phy.ops.release(hw);
3099 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3100 * @hw: pointer to the HW structure
3103 * This is a function pointer entry point called by drivers
3104 * or other shared routines.
3106 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3108 s32 ret_val = E1000_SUCCESS;
3110 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3112 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3113 if ((hw->mac.type == e1000_pch2lan) &&
3114 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3115 e1000_gate_hw_phy_config_ich8lan(hw, true);
3117 ret_val = e1000_phy_hw_reset_generic(hw);
3121 return e1000_post_phy_reset_ich8lan(hw);
3125 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3126 * @hw: pointer to the HW structure
3127 * @active: true to enable LPLU, false to disable
3129 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3130 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3131 * the phy speed. This function will manually set the LPLU bit and restart
3132 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3133 * since it configures the same bit.
3135 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3140 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3141 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3146 oem_reg |= HV_OEM_BITS_LPLU;
3148 oem_reg &= ~HV_OEM_BITS_LPLU;
3150 if (!hw->phy.ops.check_reset_block(hw))
3151 oem_reg |= HV_OEM_BITS_RESTART_AN;
3153 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3157 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3158 * @hw: pointer to the HW structure
3159 * @active: true to enable LPLU, false to disable
3161 * Sets the LPLU D0 state according to the active flag. When
3162 * activating LPLU this function also disables smart speed
3163 * and vice versa. LPLU will not be activated unless the
3164 * device autonegotiation advertisement meets standards of
3165 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3166 * This is a function pointer entry point only called by
3167 * PHY setup routines.
3169 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3171 struct e1000_phy_info *phy = &hw->phy;
3173 s32 ret_val = E1000_SUCCESS;
3176 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3178 if (phy->type == e1000_phy_ife)
3179 return E1000_SUCCESS;
3181 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3184 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3185 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3187 if (phy->type != e1000_phy_igp_3)
3188 return E1000_SUCCESS;
3190 /* Call gig speed drop workaround on LPLU before accessing
3193 if (hw->mac.type == e1000_ich8lan)
3194 e1000_gig_downshift_workaround_ich8lan(hw);
3196 /* When LPLU is enabled, we should disable SmartSpeed */
3197 ret_val = phy->ops.read_reg(hw,
3198 IGP01E1000_PHY_PORT_CONFIG,
3202 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3203 ret_val = phy->ops.write_reg(hw,
3204 IGP01E1000_PHY_PORT_CONFIG,
3209 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3210 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3212 if (phy->type != e1000_phy_igp_3)
3213 return E1000_SUCCESS;
3215 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3216 * during Dx states where the power conservation is most
3217 * important. During driver activity we should enable
3218 * SmartSpeed, so performance is maintained.
3220 if (phy->smart_speed == e1000_smart_speed_on) {
3221 ret_val = phy->ops.read_reg(hw,
3222 IGP01E1000_PHY_PORT_CONFIG,
3227 data |= IGP01E1000_PSCFR_SMART_SPEED;
3228 ret_val = phy->ops.write_reg(hw,
3229 IGP01E1000_PHY_PORT_CONFIG,
3233 } else if (phy->smart_speed == e1000_smart_speed_off) {
3234 ret_val = phy->ops.read_reg(hw,
3235 IGP01E1000_PHY_PORT_CONFIG,
3240 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3241 ret_val = phy->ops.write_reg(hw,
3242 IGP01E1000_PHY_PORT_CONFIG,
3249 return E1000_SUCCESS;
3253 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3254 * @hw: pointer to the HW structure
3255 * @active: true to enable LPLU, false to disable
3257 * Sets the LPLU D3 state according to the active flag. When
3258 * activating LPLU this function also disables smart speed
3259 * and vice versa. LPLU will not be activated unless the
3260 * device autonegotiation advertisement meets standards of
3261 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3262 * This is a function pointer entry point only called by
3263 * PHY setup routines.
3265 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3267 struct e1000_phy_info *phy = &hw->phy;
3269 s32 ret_val = E1000_SUCCESS;
3272 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3274 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3277 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3278 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3280 if (phy->type != e1000_phy_igp_3)
3281 return E1000_SUCCESS;
3283 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3284 * during Dx states where the power conservation is most
3285 * important. During driver activity we should enable
3286 * SmartSpeed, so performance is maintained.
3288 if (phy->smart_speed == e1000_smart_speed_on) {
3289 ret_val = phy->ops.read_reg(hw,
3290 IGP01E1000_PHY_PORT_CONFIG,
3295 data |= IGP01E1000_PSCFR_SMART_SPEED;
3296 ret_val = phy->ops.write_reg(hw,
3297 IGP01E1000_PHY_PORT_CONFIG,
3301 } else if (phy->smart_speed == e1000_smart_speed_off) {
3302 ret_val = phy->ops.read_reg(hw,
3303 IGP01E1000_PHY_PORT_CONFIG,
3308 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3309 ret_val = phy->ops.write_reg(hw,
3310 IGP01E1000_PHY_PORT_CONFIG,
3315 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3316 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3317 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3318 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3319 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3321 if (phy->type != e1000_phy_igp_3)
3322 return E1000_SUCCESS;
3324 /* Call gig speed drop workaround on LPLU before accessing
3327 if (hw->mac.type == e1000_ich8lan)
3328 e1000_gig_downshift_workaround_ich8lan(hw);
3330 /* When LPLU is enabled, we should disable SmartSpeed */
3331 ret_val = phy->ops.read_reg(hw,
3332 IGP01E1000_PHY_PORT_CONFIG,
3337 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3338 ret_val = phy->ops.write_reg(hw,
3339 IGP01E1000_PHY_PORT_CONFIG,
3347 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3348 * @hw: pointer to the HW structure
3349 * @bank: pointer to the variable that returns the active bank
3351 * Reads signature byte from the NVM using the flash access registers.
3352 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3354 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3357 struct e1000_nvm_info *nvm = &hw->nvm;
3358 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3359 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3364 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3366 switch (hw->mac.type) {
3368 bank1_offset = nvm->flash_bank_size;
3369 act_offset = E1000_ICH_NVM_SIG_WORD;
3371 /* set bank to 0 in case flash read fails */
3375 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3379 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3380 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3381 E1000_ICH_NVM_SIG_VALUE) {
3383 return E1000_SUCCESS;
3387 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3392 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3393 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3394 E1000_ICH_NVM_SIG_VALUE) {
3396 return E1000_SUCCESS;
3399 DEBUGOUT("ERROR: No valid NVM bank present\n");
3400 return -E1000_ERR_NVM;
3403 eecd = E1000_READ_REG(hw, E1000_EECD);
3404 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3405 E1000_EECD_SEC1VAL_VALID_MASK) {
3406 if (eecd & E1000_EECD_SEC1VAL)
3411 return E1000_SUCCESS;
3413 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3416 /* set bank to 0 in case flash read fails */
3420 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3424 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3425 E1000_ICH_NVM_SIG_VALUE) {
3427 return E1000_SUCCESS;
3431 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3436 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3437 E1000_ICH_NVM_SIG_VALUE) {
3439 return E1000_SUCCESS;
3442 DEBUGOUT("ERROR: No valid NVM bank present\n");
3443 return -E1000_ERR_NVM;
3448 * e1000_read_nvm_spt - NVM access for SPT
3449 * @hw: pointer to the HW structure
3450 * @offset: The offset (in bytes) of the word(s) to read.
3451 * @words: Size of data to read in words.
3452 * @data: pointer to the word(s) to read at offset.
3454 * Reads a word(s) from the NVM
3456 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3459 struct e1000_nvm_info *nvm = &hw->nvm;
3460 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3462 s32 ret_val = E1000_SUCCESS;
3468 DEBUGFUNC("e1000_read_nvm_spt");
3470 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3472 DEBUGOUT("nvm parameter(s) out of bounds\n");
3473 ret_val = -E1000_ERR_NVM;
3477 nvm->ops.acquire(hw);
3479 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3480 if (ret_val != E1000_SUCCESS) {
3481 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3485 act_offset = (bank) ? nvm->flash_bank_size : 0;
3486 act_offset += offset;
3488 ret_val = E1000_SUCCESS;
3490 for (i = 0; i < words; i += 2) {
3491 if (words - i == 1) {
3492 if (dev_spec->shadow_ram[offset+i].modified) {
3493 data[i] = dev_spec->shadow_ram[offset+i].value;
3495 offset_to_read = act_offset + i -
3496 ((act_offset + i) % 2);
3498 e1000_read_flash_dword_ich8lan(hw,
3503 if ((act_offset + i) % 2 == 0)
3504 data[i] = (u16)(dword & 0xFFFF);
3506 data[i] = (u16)((dword >> 16) & 0xFFFF);
3509 offset_to_read = act_offset + i;
3510 if (!(dev_spec->shadow_ram[offset+i].modified) ||
3511 !(dev_spec->shadow_ram[offset+i+1].modified)) {
3513 e1000_read_flash_dword_ich8lan(hw,
3519 if (dev_spec->shadow_ram[offset+i].modified)
3520 data[i] = dev_spec->shadow_ram[offset+i].value;
3522 data[i] = (u16) (dword & 0xFFFF);
3523 if (dev_spec->shadow_ram[offset+i].modified)
3525 dev_spec->shadow_ram[offset+i+1].value;
3527 data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3531 nvm->ops.release(hw);
3535 DEBUGOUT1("NVM read error: %d\n", ret_val);
3541 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3542 * @hw: pointer to the HW structure
3543 * @offset: The offset (in bytes) of the word(s) to read.
3544 * @words: Size of data to read in words
3545 * @data: Pointer to the word(s) to read at offset.
3547 * Reads a word(s) from the NVM using the flash access registers.
3549 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3552 struct e1000_nvm_info *nvm = &hw->nvm;
3553 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3555 s32 ret_val = E1000_SUCCESS;
3559 DEBUGFUNC("e1000_read_nvm_ich8lan");
3561 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3563 DEBUGOUT("nvm parameter(s) out of bounds\n");
3564 ret_val = -E1000_ERR_NVM;
3568 nvm->ops.acquire(hw);
3570 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3571 if (ret_val != E1000_SUCCESS) {
3572 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3576 act_offset = (bank) ? nvm->flash_bank_size : 0;
3577 act_offset += offset;
3579 ret_val = E1000_SUCCESS;
3580 for (i = 0; i < words; i++) {
3581 if (dev_spec->shadow_ram[offset+i].modified) {
3582 data[i] = dev_spec->shadow_ram[offset+i].value;
3584 ret_val = e1000_read_flash_word_ich8lan(hw,
3593 nvm->ops.release(hw);
3597 DEBUGOUT1("NVM read error: %d\n", ret_val);
3603 * e1000_flash_cycle_init_ich8lan - Initialize flash
3604 * @hw: pointer to the HW structure
3606 * This function does initial flash setup so that a new read/write/erase cycle
3609 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3611 union ich8_hws_flash_status hsfsts;
3612 s32 ret_val = -E1000_ERR_NVM;
3614 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3616 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3618 /* Check if the flash descriptor is valid */
3619 if (!hsfsts.hsf_status.fldesvalid) {
3620 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3621 return -E1000_ERR_NVM;
3624 /* Clear FCERR and DAEL in hw status by writing 1 */
3625 hsfsts.hsf_status.flcerr = 1;
3626 hsfsts.hsf_status.dael = 1;
3627 if (hw->mac.type >= e1000_pch_spt)
3628 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3629 hsfsts.regval & 0xFFFF);
3631 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3633 /* Either we should have a hardware SPI cycle in progress
3634 * bit to check against, in order to start a new cycle or
3635 * FDONE bit should be changed in the hardware so that it
3636 * is 1 after hardware reset, which can then be used as an
3637 * indication whether a cycle is in progress or has been
3641 if (!hsfsts.hsf_status.flcinprog) {
3642 /* There is no cycle running at present,
3643 * so we can start a cycle.
3644 * Begin by setting Flash Cycle Done.
3646 hsfsts.hsf_status.flcdone = 1;
3647 if (hw->mac.type >= e1000_pch_spt)
3648 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3649 hsfsts.regval & 0xFFFF);
3651 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3653 ret_val = E1000_SUCCESS;
3657 /* Otherwise poll for sometime so the current
3658 * cycle has a chance to end before giving up.
3660 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3661 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3663 if (!hsfsts.hsf_status.flcinprog) {
3664 ret_val = E1000_SUCCESS;
3669 if (ret_val == E1000_SUCCESS) {
3670 /* Successful in waiting for previous cycle to timeout,
3671 * now set the Flash Cycle Done.
3673 hsfsts.hsf_status.flcdone = 1;
3674 if (hw->mac.type >= e1000_pch_spt)
3675 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3676 hsfsts.regval & 0xFFFF);
3678 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3681 DEBUGOUT("Flash controller busy, cannot get access\n");
3689 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3690 * @hw: pointer to the HW structure
3691 * @timeout: maximum time to wait for completion
3693 * This function starts a flash cycle and waits for its completion.
3695 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3697 union ich8_hws_flash_ctrl hsflctl;
3698 union ich8_hws_flash_status hsfsts;
3701 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3703 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3704 if (hw->mac.type >= e1000_pch_spt)
3705 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3707 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3708 hsflctl.hsf_ctrl.flcgo = 1;
3710 if (hw->mac.type >= e1000_pch_spt)
3711 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3712 hsflctl.regval << 16);
3714 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3716 /* wait till FDONE bit is set to 1 */
3718 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3719 if (hsfsts.hsf_status.flcdone)
3722 } while (i++ < timeout);
3724 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3725 return E1000_SUCCESS;
3727 return -E1000_ERR_NVM;
3731 * e1000_read_flash_dword_ich8lan - Read dword from flash
3732 * @hw: pointer to the HW structure
3733 * @offset: offset to data location
3734 * @data: pointer to the location for storing the data
3736 * Reads the flash dword at offset into data. Offset is converted
3737 * to bytes before read.
3739 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3742 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3745 return -E1000_ERR_NVM;
3747 /* Must convert word offset into bytes. */
3750 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3754 * e1000_read_flash_word_ich8lan - Read word from flash
3755 * @hw: pointer to the HW structure
3756 * @offset: offset to data location
3757 * @data: pointer to the location for storing the data
3759 * Reads the flash word at offset into data. Offset is converted
3760 * to bytes before read.
3762 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3765 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3768 return -E1000_ERR_NVM;
3770 /* Must convert offset into bytes. */
3773 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3777 * e1000_read_flash_byte_ich8lan - Read byte from flash
3778 * @hw: pointer to the HW structure
3779 * @offset: The offset of the byte to read.
3780 * @data: Pointer to a byte to store the value read.
3782 * Reads a single byte from the NVM using the flash access registers.
3784 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3790 /* In SPT, only 32 bits access is supported,
3791 * so this function should not be called.
3793 if (hw->mac.type >= e1000_pch_spt)
3794 return -E1000_ERR_NVM;
3796 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3803 return E1000_SUCCESS;
3807 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3808 * @hw: pointer to the HW structure
3809 * @offset: The offset (in bytes) of the byte or word to read.
3810 * @size: Size of data to read, 1=byte 2=word
3811 * @data: Pointer to the word to store the value read.
3813 * Reads a byte or word from the NVM using the flash access registers.
3815 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3818 union ich8_hws_flash_status hsfsts;
3819 union ich8_hws_flash_ctrl hsflctl;
3820 u32 flash_linear_addr;
3822 s32 ret_val = -E1000_ERR_NVM;
3825 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3827 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3828 return -E1000_ERR_NVM;
3829 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3830 hw->nvm.flash_base_addr);
3835 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3836 if (ret_val != E1000_SUCCESS)
3838 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3840 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3841 hsflctl.hsf_ctrl.fldbcount = size - 1;
3842 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3843 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3844 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3846 ret_val = e1000_flash_cycle_ich8lan(hw,
3847 ICH_FLASH_READ_COMMAND_TIMEOUT);
3849 /* Check if FCERR is set to 1, if set to 1, clear it
3850 * and try the whole sequence a few more times, else
3851 * read in (shift in) the Flash Data0, the order is
3852 * least significant byte first msb to lsb
3854 if (ret_val == E1000_SUCCESS) {
3855 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3857 *data = (u8)(flash_data & 0x000000FF);
3859 *data = (u16)(flash_data & 0x0000FFFF);
3862 /* If we've gotten here, then things are probably
3863 * completely hosed, but if the error condition is
3864 * detected, it won't hurt to give it another try...
3865 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3867 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3869 if (hsfsts.hsf_status.flcerr) {
3870 /* Repeat for some time before giving up. */
3872 } else if (!hsfsts.hsf_status.flcdone) {
3873 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3877 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3883 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3884 * @hw: pointer to the HW structure
3885 * @offset: The offset (in bytes) of the dword to read.
3886 * @data: Pointer to the dword to store the value read.
3888 * Reads a byte or word from the NVM using the flash access registers.
3890 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3893 union ich8_hws_flash_status hsfsts;
3894 union ich8_hws_flash_ctrl hsflctl;
3895 u32 flash_linear_addr;
3896 s32 ret_val = -E1000_ERR_NVM;
3899 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3901 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3902 hw->mac.type < e1000_pch_spt)
3903 return -E1000_ERR_NVM;
3904 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3905 hw->nvm.flash_base_addr);
3910 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3911 if (ret_val != E1000_SUCCESS)
3913 /* In SPT, This register is in Lan memory space, not flash.
3914 * Therefore, only 32 bit access is supported
3916 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3918 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3919 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3920 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3921 /* In SPT, This register is in Lan memory space, not flash.
3922 * Therefore, only 32 bit access is supported
3924 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3925 (u32)hsflctl.regval << 16);
3926 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3928 ret_val = e1000_flash_cycle_ich8lan(hw,
3929 ICH_FLASH_READ_COMMAND_TIMEOUT);
3931 /* Check if FCERR is set to 1, if set to 1, clear it
3932 * and try the whole sequence a few more times, else
3933 * read in (shift in) the Flash Data0, the order is
3934 * least significant byte first msb to lsb
3936 if (ret_val == E1000_SUCCESS) {
3937 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3940 /* If we've gotten here, then things are probably
3941 * completely hosed, but if the error condition is
3942 * detected, it won't hurt to give it another try...
3943 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3945 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3947 if (hsfsts.hsf_status.flcerr) {
3948 /* Repeat for some time before giving up. */
3950 } else if (!hsfsts.hsf_status.flcdone) {
3951 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3955 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3961 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3962 * @hw: pointer to the HW structure
3963 * @offset: The offset (in bytes) of the word(s) to write.
3964 * @words: Size of data to write in words
3965 * @data: Pointer to the word(s) to write at offset.
3967 * Writes a byte or word to the NVM using the flash access registers.
3969 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3972 struct e1000_nvm_info *nvm = &hw->nvm;
3973 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3976 DEBUGFUNC("e1000_write_nvm_ich8lan");
3978 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3980 DEBUGOUT("nvm parameter(s) out of bounds\n");
3981 return -E1000_ERR_NVM;
3984 nvm->ops.acquire(hw);
3986 for (i = 0; i < words; i++) {
3987 dev_spec->shadow_ram[offset+i].modified = true;
3988 dev_spec->shadow_ram[offset+i].value = data[i];
3991 nvm->ops.release(hw);
3993 return E1000_SUCCESS;
3997 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3998 * @hw: pointer to the HW structure
4000 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4001 * which writes the checksum to the shadow ram. The changes in the shadow
4002 * ram are then committed to the EEPROM by processing each bank at a time
4003 * checking for the modified bit and writing only the pending changes.
4004 * After a successful commit, the shadow ram is cleared and is ready for
4007 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4009 struct e1000_nvm_info *nvm = &hw->nvm;
4010 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4011 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4015 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4017 ret_val = e1000_update_nvm_checksum_generic(hw);
4021 if (nvm->type != e1000_nvm_flash_sw)
4024 nvm->ops.acquire(hw);
4026 /* We're writing to the opposite bank so if we're on bank 1,
4027 * write to bank 0 etc. We also need to erase the segment that
4028 * is going to be written
4030 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4031 if (ret_val != E1000_SUCCESS) {
4032 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4037 new_bank_offset = nvm->flash_bank_size;
4038 old_bank_offset = 0;
4039 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4043 old_bank_offset = nvm->flash_bank_size;
4044 new_bank_offset = 0;
4045 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4049 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4050 /* Determine whether to write the value stored
4051 * in the other NVM bank or a modified value stored
4054 ret_val = e1000_read_flash_dword_ich8lan(hw,
4055 i + old_bank_offset,
4058 if (dev_spec->shadow_ram[i].modified) {
4059 dword &= 0xffff0000;
4060 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4062 if (dev_spec->shadow_ram[i + 1].modified) {
4063 dword &= 0x0000ffff;
4064 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4070 /* If the word is 0x13, then make sure the signature bits
4071 * (15:14) are 11b until the commit has completed.
4072 * This will allow us to write 10b which indicates the
4073 * signature is valid. We want to do this after the write
4074 * has completed so that we don't mark the segment valid
4075 * while the write is still in progress
4077 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4078 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4080 /* Convert offset to bytes. */
4081 act_offset = (i + new_bank_offset) << 1;
4085 /* Write the data to the new bank. Offset in words*/
4086 act_offset = i + new_bank_offset;
4087 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4093 /* Don't bother writing the segment valid bits if sector
4094 * programming failed.
4097 DEBUGOUT("Flash commit failed.\n");
4101 /* Finally validate the new segment by setting bit 15:14
4102 * to 10b in word 0x13 , this can be done without an
4103 * erase as well since these bits are 11 to start with
4104 * and we need to change bit 14 to 0b
4106 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4108 /*offset in words but we read dword*/
4110 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4115 dword &= 0xBFFFFFFF;
4116 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4121 /* And invalidate the previously valid segment by setting
4122 * its signature word (0x13) high_byte to 0b. This can be
4123 * done without an erase because flash erase sets all bits
4124 * to 1's. We can write 1's to 0's without an erase
4126 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4128 /* offset in words but we read dword*/
4129 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4130 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4135 dword &= 0x00FFFFFF;
4136 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4141 /* Great! Everything worked, we can now clear the cached entries. */
4142 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4143 dev_spec->shadow_ram[i].modified = false;
4144 dev_spec->shadow_ram[i].value = 0xFFFF;
4148 nvm->ops.release(hw);
4150 /* Reload the EEPROM, or else modifications will not appear
4151 * until after the next adapter reset.
4154 nvm->ops.reload(hw);
4160 DEBUGOUT1("NVM update error: %d\n", ret_val);
4166 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4167 * @hw: pointer to the HW structure
4169 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4170 * which writes the checksum to the shadow ram. The changes in the shadow
4171 * ram are then committed to the EEPROM by processing each bank at a time
4172 * checking for the modified bit and writing only the pending changes.
4173 * After a successful commit, the shadow ram is cleared and is ready for
4176 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4178 struct e1000_nvm_info *nvm = &hw->nvm;
4179 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4180 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4184 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4186 ret_val = e1000_update_nvm_checksum_generic(hw);
4190 if (nvm->type != e1000_nvm_flash_sw)
4193 nvm->ops.acquire(hw);
4195 /* We're writing to the opposite bank so if we're on bank 1,
4196 * write to bank 0 etc. We also need to erase the segment that
4197 * is going to be written
4199 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4200 if (ret_val != E1000_SUCCESS) {
4201 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4206 new_bank_offset = nvm->flash_bank_size;
4207 old_bank_offset = 0;
4208 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4212 old_bank_offset = nvm->flash_bank_size;
4213 new_bank_offset = 0;
4214 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4218 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4219 if (dev_spec->shadow_ram[i].modified) {
4220 data = dev_spec->shadow_ram[i].value;
4222 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4228 /* If the word is 0x13, then make sure the signature bits
4229 * (15:14) are 11b until the commit has completed.
4230 * This will allow us to write 10b which indicates the
4231 * signature is valid. We want to do this after the write
4232 * has completed so that we don't mark the segment valid
4233 * while the write is still in progress
4235 if (i == E1000_ICH_NVM_SIG_WORD)
4236 data |= E1000_ICH_NVM_SIG_MASK;
4238 /* Convert offset to bytes. */
4239 act_offset = (i + new_bank_offset) << 1;
4243 /* Write the bytes to the new bank. */
4244 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4251 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4258 /* Don't bother writing the segment valid bits if sector
4259 * programming failed.
4262 DEBUGOUT("Flash commit failed.\n");
4266 /* Finally validate the new segment by setting bit 15:14
4267 * to 10b in word 0x13 , this can be done without an
4268 * erase as well since these bits are 11 to start with
4269 * and we need to change bit 14 to 0b
4271 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4272 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4277 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4282 /* And invalidate the previously valid segment by setting
4283 * its signature word (0x13) high_byte to 0b. This can be
4284 * done without an erase because flash erase sets all bits
4285 * to 1's. We can write 1's to 0's without an erase
4287 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4289 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4294 /* Great! Everything worked, we can now clear the cached entries. */
4295 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4296 dev_spec->shadow_ram[i].modified = false;
4297 dev_spec->shadow_ram[i].value = 0xFFFF;
4301 nvm->ops.release(hw);
4303 /* Reload the EEPROM, or else modifications will not appear
4304 * until after the next adapter reset.
4307 nvm->ops.reload(hw);
4313 DEBUGOUT1("NVM update error: %d\n", ret_val);
4319 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4320 * @hw: pointer to the HW structure
4322 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4323 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4324 * calculated, in which case we need to calculate the checksum and set bit 6.
4326 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4331 u16 valid_csum_mask;
4333 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4335 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4336 * the checksum needs to be fixed. This bit is an indication that
4337 * the NVM was prepared by OEM software and did not calculate
4338 * the checksum...a likely scenario.
4340 switch (hw->mac.type) {
4344 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4347 word = NVM_FUTURE_INIT_WORD1;
4348 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4352 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4356 if (!(data & valid_csum_mask)) {
4357 data |= valid_csum_mask;
4358 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4361 ret_val = hw->nvm.ops.update(hw);
4366 return e1000_validate_nvm_checksum_generic(hw);
4370 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4371 * @hw: pointer to the HW structure
4372 * @offset: The offset (in bytes) of the byte/word to read.
4373 * @size: Size of data to read, 1=byte 2=word
4374 * @data: The byte(s) to write to the NVM.
4376 * Writes one/two bytes to the NVM using the flash access registers.
4378 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4381 union ich8_hws_flash_status hsfsts;
4382 union ich8_hws_flash_ctrl hsflctl;
4383 u32 flash_linear_addr;
4388 DEBUGFUNC("e1000_write_ich8_data");
4390 if (hw->mac.type >= e1000_pch_spt) {
4391 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4392 return -E1000_ERR_NVM;
4394 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4395 return -E1000_ERR_NVM;
4398 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4399 hw->nvm.flash_base_addr);
4404 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4405 if (ret_val != E1000_SUCCESS)
4407 /* In SPT, This register is in Lan memory space, not
4408 * flash. Therefore, only 32 bit access is supported
4410 if (hw->mac.type >= e1000_pch_spt)
4412 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4415 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4417 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4418 hsflctl.hsf_ctrl.fldbcount = size - 1;
4419 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4420 /* In SPT, This register is in Lan memory space,
4421 * not flash. Therefore, only 32 bit access is
4424 if (hw->mac.type >= e1000_pch_spt)
4425 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4426 hsflctl.regval << 16);
4428 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4431 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4434 flash_data = (u32)data & 0x00FF;
4436 flash_data = (u32)data;
4438 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4440 /* check if FCERR is set to 1 , if set to 1, clear it
4441 * and try the whole sequence a few more times else done
4444 e1000_flash_cycle_ich8lan(hw,
4445 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4446 if (ret_val == E1000_SUCCESS)
4449 /* If we're here, then things are most likely
4450 * completely hosed, but if the error condition
4451 * is detected, it won't hurt to give it another
4452 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4454 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4455 if (hsfsts.hsf_status.flcerr)
4456 /* Repeat for some time before giving up. */
4458 if (!hsfsts.hsf_status.flcdone) {
4459 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4462 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4468 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4469 * @hw: pointer to the HW structure
4470 * @offset: The offset (in bytes) of the dwords to read.
4471 * @data: The 4 bytes to write to the NVM.
4473 * Writes one/two/four bytes to the NVM using the flash access registers.
4475 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4478 union ich8_hws_flash_status hsfsts;
4479 union ich8_hws_flash_ctrl hsflctl;
4480 u32 flash_linear_addr;
4484 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4486 if (hw->mac.type >= e1000_pch_spt) {
4487 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4488 return -E1000_ERR_NVM;
4490 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4491 hw->nvm.flash_base_addr);
4495 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4496 if (ret_val != E1000_SUCCESS)
4499 /* In SPT, This register is in Lan memory space, not
4500 * flash. Therefore, only 32 bit access is supported
4502 if (hw->mac.type >= e1000_pch_spt)
4503 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4507 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4510 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4511 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4513 /* In SPT, This register is in Lan memory space,
4514 * not flash. Therefore, only 32 bit access is
4517 if (hw->mac.type >= e1000_pch_spt)
4518 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4519 hsflctl.regval << 16);
4521 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4524 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4526 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4528 /* check if FCERR is set to 1 , if set to 1, clear it
4529 * and try the whole sequence a few more times else done
4531 ret_val = e1000_flash_cycle_ich8lan(hw,
4532 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4534 if (ret_val == E1000_SUCCESS)
4537 /* If we're here, then things are most likely
4538 * completely hosed, but if the error condition
4539 * is detected, it won't hurt to give it another
4540 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4542 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4544 if (hsfsts.hsf_status.flcerr)
4545 /* Repeat for some time before giving up. */
4547 if (!hsfsts.hsf_status.flcdone) {
4548 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4551 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4557 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4558 * @hw: pointer to the HW structure
4559 * @offset: The index of the byte to read.
4560 * @data: The byte to write to the NVM.
4562 * Writes a single byte to the NVM using the flash access registers.
4564 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4567 u16 word = (u16)data;
4569 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4571 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4575 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4576 * @hw: pointer to the HW structure
4577 * @offset: The offset of the word to write.
4578 * @dword: The dword to write to the NVM.
4580 * Writes a single dword to the NVM using the flash access registers.
4581 * Goes through a retry algorithm before giving up.
4583 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4584 u32 offset, u32 dword)
4587 u16 program_retries;
4589 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4591 /* Must convert word offset into bytes. */
4594 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4598 for (program_retries = 0; program_retries < 100; program_retries++) {
4599 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4601 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4602 if (ret_val == E1000_SUCCESS)
4605 if (program_retries == 100)
4606 return -E1000_ERR_NVM;
4608 return E1000_SUCCESS;
4612 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4613 * @hw: pointer to the HW structure
4614 * @offset: The offset of the byte to write.
4615 * @byte: The byte to write to the NVM.
4617 * Writes a single byte to the NVM using the flash access registers.
4618 * Goes through a retry algorithm before giving up.
4620 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4621 u32 offset, u8 byte)
4624 u16 program_retries;
4626 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4628 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4632 for (program_retries = 0; program_retries < 100; program_retries++) {
4633 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4635 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4636 if (ret_val == E1000_SUCCESS)
4639 if (program_retries == 100)
4640 return -E1000_ERR_NVM;
4642 return E1000_SUCCESS;
4646 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4647 * @hw: pointer to the HW structure
4648 * @bank: 0 for first bank, 1 for second bank, etc.
4650 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4651 * bank N is 4096 * N + flash_reg_addr.
4653 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4655 struct e1000_nvm_info *nvm = &hw->nvm;
4656 union ich8_hws_flash_status hsfsts;
4657 union ich8_hws_flash_ctrl hsflctl;
4658 u32 flash_linear_addr;
4659 /* bank size is in 16bit words - adjust to bytes */
4660 u32 flash_bank_size = nvm->flash_bank_size * 2;
4663 s32 j, iteration, sector_size;
4665 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4667 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4669 /* Determine HW Sector size: Read BERASE bits of hw flash status
4671 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4672 * consecutive sectors. The start index for the nth Hw sector
4673 * can be calculated as = bank * 4096 + n * 256
4674 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4675 * The start index for the nth Hw sector can be calculated
4677 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4678 * (ich9 only, otherwise error condition)
4679 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4681 switch (hsfsts.hsf_status.berasesz) {
4683 /* Hw sector size 256 */
4684 sector_size = ICH_FLASH_SEG_SIZE_256;
4685 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4688 sector_size = ICH_FLASH_SEG_SIZE_4K;
4692 sector_size = ICH_FLASH_SEG_SIZE_8K;
4696 sector_size = ICH_FLASH_SEG_SIZE_64K;
4700 return -E1000_ERR_NVM;
4703 /* Start with the base address, then add the sector offset. */
4704 flash_linear_addr = hw->nvm.flash_base_addr;
4705 flash_linear_addr += (bank) ? flash_bank_size : 0;
4707 for (j = 0; j < iteration; j++) {
4709 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4712 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4716 /* Write a value 11 (block Erase) in Flash
4717 * Cycle field in hw flash control
4719 if (hw->mac.type >= e1000_pch_spt)
4721 E1000_READ_FLASH_REG(hw,
4722 ICH_FLASH_HSFSTS)>>16;
4725 E1000_READ_FLASH_REG16(hw,
4728 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4729 if (hw->mac.type >= e1000_pch_spt)
4730 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4731 hsflctl.regval << 16);
4733 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4736 /* Write the last 24 bits of an index within the
4737 * block into Flash Linear address field in Flash
4740 flash_linear_addr += (j * sector_size);
4741 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4744 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4745 if (ret_val == E1000_SUCCESS)
4748 /* Check if FCERR is set to 1. If 1,
4749 * clear it and try the whole sequence
4750 * a few more times else Done
4752 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4754 if (hsfsts.hsf_status.flcerr)
4755 /* repeat for some time before giving up */
4757 else if (!hsfsts.hsf_status.flcdone)
4759 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4762 return E1000_SUCCESS;
4766 * e1000_valid_led_default_ich8lan - Set the default LED settings
4767 * @hw: pointer to the HW structure
4768 * @data: Pointer to the LED settings
4770 * Reads the LED default settings from the NVM to data. If the NVM LED
4771 * settings is all 0's or F's, set the LED default to a valid LED default
4774 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4778 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4780 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4782 DEBUGOUT("NVM Read Error\n");
4786 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4787 *data = ID_LED_DEFAULT_ICH8LAN;
4789 return E1000_SUCCESS;
4793 * e1000_id_led_init_pchlan - store LED configurations
4794 * @hw: pointer to the HW structure
4796 * PCH does not control LEDs via the LEDCTL register, rather it uses
4797 * the PHY LED configuration register.
4799 * PCH also does not have an "always on" or "always off" mode which
4800 * complicates the ID feature. Instead of using the "on" mode to indicate
4801 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4802 * use "link_up" mode. The LEDs will still ID on request if there is no
4803 * link based on logic in e1000_led_[on|off]_pchlan().
4805 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4807 struct e1000_mac_info *mac = &hw->mac;
4809 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4810 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4811 u16 data, i, temp, shift;
4813 DEBUGFUNC("e1000_id_led_init_pchlan");
4815 /* Get default ID LED modes */
4816 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4820 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4821 mac->ledctl_mode1 = mac->ledctl_default;
4822 mac->ledctl_mode2 = mac->ledctl_default;
4824 for (i = 0; i < 4; i++) {
4825 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4828 case ID_LED_ON1_DEF2:
4829 case ID_LED_ON1_ON2:
4830 case ID_LED_ON1_OFF2:
4831 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4832 mac->ledctl_mode1 |= (ledctl_on << shift);
4834 case ID_LED_OFF1_DEF2:
4835 case ID_LED_OFF1_ON2:
4836 case ID_LED_OFF1_OFF2:
4837 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4838 mac->ledctl_mode1 |= (ledctl_off << shift);
4845 case ID_LED_DEF1_ON2:
4846 case ID_LED_ON1_ON2:
4847 case ID_LED_OFF1_ON2:
4848 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4849 mac->ledctl_mode2 |= (ledctl_on << shift);
4851 case ID_LED_DEF1_OFF2:
4852 case ID_LED_ON1_OFF2:
4853 case ID_LED_OFF1_OFF2:
4854 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4855 mac->ledctl_mode2 |= (ledctl_off << shift);
4863 return E1000_SUCCESS;
4867 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4868 * @hw: pointer to the HW structure
4870 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4871 * register, so the the bus width is hard coded.
4873 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4875 struct e1000_bus_info *bus = &hw->bus;
4878 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4880 ret_val = e1000_get_bus_info_pcie_generic(hw);
4882 /* ICH devices are "PCI Express"-ish. They have
4883 * a configuration space, but do not contain
4884 * PCI Express Capability registers, so bus width
4885 * must be hardcoded.
4887 if (bus->width == e1000_bus_width_unknown)
4888 bus->width = e1000_bus_width_pcie_x1;
4894 * e1000_reset_hw_ich8lan - Reset the hardware
4895 * @hw: pointer to the HW structure
4897 * Does a full reset of the hardware which includes a reset of the PHY and
4900 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4902 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4907 DEBUGFUNC("e1000_reset_hw_ich8lan");
4909 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4910 * on the last TLP read/write transaction when MAC is reset.
4912 ret_val = e1000_disable_pcie_master_generic(hw);
4914 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4916 DEBUGOUT("Masking off all interrupts\n");
4917 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4919 /* Disable the Transmit and Receive units. Then delay to allow
4920 * any pending transactions to complete before we hit the MAC
4921 * with the global reset.
4923 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4924 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4925 E1000_WRITE_FLUSH(hw);
4929 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4930 if (hw->mac.type == e1000_ich8lan) {
4931 /* Set Tx and Rx buffer allocation to 8k apiece. */
4932 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4933 /* Set Packet Buffer Size to 16k. */
4934 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4937 if (hw->mac.type == e1000_pchlan) {
4938 /* Save the NVM K1 bit setting*/
4939 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4943 if (kum_cfg & E1000_NVM_K1_ENABLE)
4944 dev_spec->nvm_k1_enabled = true;
4946 dev_spec->nvm_k1_enabled = false;
4949 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4951 if (!hw->phy.ops.check_reset_block(hw)) {
4952 /* Full-chip reset requires MAC and PHY reset at the same
4953 * time to make sure the interface between MAC and the
4954 * external PHY is reset.
4956 ctrl |= E1000_CTRL_PHY_RST;
4958 /* Gate automatic PHY configuration by hardware on
4961 if ((hw->mac.type == e1000_pch2lan) &&
4962 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4963 e1000_gate_hw_phy_config_ich8lan(hw, true);
4965 ret_val = e1000_acquire_swflag_ich8lan(hw);
4966 DEBUGOUT("Issuing a global reset to ich8lan\n");
4967 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4968 /* cannot issue a flush here because it hangs the hardware */
4971 /* Set Phy Config Counter to 50msec */
4972 if (hw->mac.type == e1000_pch2lan) {
4973 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4974 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4975 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4976 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4980 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4982 if (ctrl & E1000_CTRL_PHY_RST) {
4983 ret_val = hw->phy.ops.get_cfg_done(hw);
4987 ret_val = e1000_post_phy_reset_ich8lan(hw);
4992 /* For PCH, this write will make sure that any noise
4993 * will be detected as a CRC error and be dropped rather than show up
4994 * as a bad packet to the DMA engine.
4996 if (hw->mac.type == e1000_pchlan)
4997 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4999 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5000 E1000_READ_REG(hw, E1000_ICR);
5002 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5003 reg |= E1000_KABGTXD_BGSQLBIAS;
5004 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5006 return E1000_SUCCESS;
5010 * e1000_init_hw_ich8lan - Initialize the hardware
5011 * @hw: pointer to the HW structure
5013 * Prepares the hardware for transmit and receive by doing the following:
5014 * - initialize hardware bits
5015 * - initialize LED identification
5016 * - setup receive address registers
5017 * - setup flow control
5018 * - setup transmit descriptors
5019 * - clear statistics
5021 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5023 struct e1000_mac_info *mac = &hw->mac;
5024 u32 ctrl_ext, txdctl, snoop;
5028 DEBUGFUNC("e1000_init_hw_ich8lan");
5030 e1000_initialize_hw_bits_ich8lan(hw);
5032 /* Initialize identification LED */
5033 ret_val = mac->ops.id_led_init(hw);
5034 /* An error is not fatal and we should not stop init due to this */
5036 DEBUGOUT("Error initializing identification LED\n");
5038 /* Setup the receive address. */
5039 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5041 /* Zero out the Multicast HASH table */
5042 DEBUGOUT("Zeroing the MTA\n");
5043 for (i = 0; i < mac->mta_reg_count; i++)
5044 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5046 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5047 * the ME. Disable wakeup by clearing the host wakeup bit.
5048 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5050 if (hw->phy.type == e1000_phy_82578) {
5051 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5052 i &= ~BM_WUC_HOST_WU_BIT;
5053 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5054 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5059 /* Setup link and flow control */
5060 ret_val = mac->ops.setup_link(hw);
5062 /* Set the transmit descriptor write-back policy for both queues */
5063 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5064 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5065 E1000_TXDCTL_FULL_TX_DESC_WB);
5066 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5067 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5068 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5069 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5070 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5071 E1000_TXDCTL_FULL_TX_DESC_WB);
5072 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5073 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5074 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5076 /* ICH8 has opposite polarity of no_snoop bits.
5077 * By default, we should use snoop behavior.
5079 if (mac->type == e1000_ich8lan)
5080 snoop = PCIE_ICH8_SNOOP_ALL;
5082 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5083 e1000_set_pcie_no_snoop_generic(hw, snoop);
5085 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5086 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5087 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5089 /* Clear all of the statistics registers (clear on read). It is
5090 * important that we do this after we have tried to establish link
5091 * because the symbol error count will increment wildly if there
5094 e1000_clear_hw_cntrs_ich8lan(hw);
5100 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5101 * @hw: pointer to the HW structure
5103 * Sets/Clears required hardware bits necessary for correctly setting up the
5104 * hardware for transmit and receive.
5106 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5110 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5112 /* Extended Device Control */
5113 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5115 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5116 if (hw->mac.type >= e1000_pchlan)
5117 reg |= E1000_CTRL_EXT_PHYPDEN;
5118 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5120 /* Transmit Descriptor Control 0 */
5121 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5123 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5125 /* Transmit Descriptor Control 1 */
5126 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5128 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5130 /* Transmit Arbitration Control 0 */
5131 reg = E1000_READ_REG(hw, E1000_TARC(0));
5132 if (hw->mac.type == e1000_ich8lan)
5133 reg |= (1 << 28) | (1 << 29);
5134 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5135 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5137 /* Transmit Arbitration Control 1 */
5138 reg = E1000_READ_REG(hw, E1000_TARC(1));
5139 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5143 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5144 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5147 if (hw->mac.type == e1000_ich8lan) {
5148 reg = E1000_READ_REG(hw, E1000_STATUS);
5150 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5153 /* work-around descriptor data corruption issue during nfs v2 udp
5154 * traffic, just disable the nfs filtering capability
5156 reg = E1000_READ_REG(hw, E1000_RFCTL);
5157 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5159 /* Disable IPv6 extension header parsing because some malformed
5160 * IPv6 headers can hang the Rx.
5162 if (hw->mac.type == e1000_ich8lan)
5163 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5164 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5166 /* Enable ECC on Lynxpoint */
5167 if (hw->mac.type >= e1000_pch_lpt) {
5168 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5169 reg |= E1000_PBECCSTS_ECC_ENABLE;
5170 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5172 reg = E1000_READ_REG(hw, E1000_CTRL);
5173 reg |= E1000_CTRL_MEHE;
5174 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5181 * e1000_setup_link_ich8lan - Setup flow control and link settings
5182 * @hw: pointer to the HW structure
5184 * Determines which flow control settings to use, then configures flow
5185 * control. Calls the appropriate media-specific link configuration
5186 * function. Assuming the adapter has a valid link partner, a valid link
5187 * should be established. Assumes the hardware has previously been reset
5188 * and the transmitter and receiver are not enabled.
5190 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5194 DEBUGFUNC("e1000_setup_link_ich8lan");
5196 if (hw->phy.ops.check_reset_block(hw))
5197 return E1000_SUCCESS;
5199 /* ICH parts do not have a word in the NVM to determine
5200 * the default flow control setting, so we explicitly
5203 if (hw->fc.requested_mode == e1000_fc_default)
5204 hw->fc.requested_mode = e1000_fc_full;
5206 /* Save off the requested flow control mode for use later. Depending
5207 * on the link partner's capabilities, we may or may not use this mode.
5209 hw->fc.current_mode = hw->fc.requested_mode;
5211 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5212 hw->fc.current_mode);
5214 /* Continue to configure the copper link. */
5215 ret_val = hw->mac.ops.setup_physical_interface(hw);
5219 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5220 if ((hw->phy.type == e1000_phy_82578) ||
5221 (hw->phy.type == e1000_phy_82579) ||
5222 (hw->phy.type == e1000_phy_i217) ||
5223 (hw->phy.type == e1000_phy_82577)) {
5224 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5226 ret_val = hw->phy.ops.write_reg(hw,
5227 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5233 return e1000_set_fc_watermarks_generic(hw);
5237 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5238 * @hw: pointer to the HW structure
5240 * Configures the kumeran interface to the PHY to wait the appropriate time
5241 * when polling the PHY, then call the generic setup_copper_link to finish
5242 * configuring the copper link.
5244 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5250 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5252 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5253 ctrl |= E1000_CTRL_SLU;
5254 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5255 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5257 /* Set the mac to wait the maximum time between each iteration
5258 * and increase the max iterations when polling the phy;
5259 * this fixes erroneous timeouts at 10Mbps.
5261 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5265 ret_val = e1000_read_kmrn_reg_generic(hw,
5266 E1000_KMRNCTRLSTA_INBAND_PARAM,
5271 ret_val = e1000_write_kmrn_reg_generic(hw,
5272 E1000_KMRNCTRLSTA_INBAND_PARAM,
5277 switch (hw->phy.type) {
5278 case e1000_phy_igp_3:
5279 ret_val = e1000_copper_link_setup_igp(hw);
5284 case e1000_phy_82578:
5285 ret_val = e1000_copper_link_setup_m88(hw);
5289 case e1000_phy_82577:
5290 case e1000_phy_82579:
5291 ret_val = e1000_copper_link_setup_82577(hw);
5296 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5301 reg_data &= ~IFE_PMC_AUTO_MDIX;
5303 switch (hw->phy.mdix) {
5305 reg_data &= ~IFE_PMC_FORCE_MDIX;
5308 reg_data |= IFE_PMC_FORCE_MDIX;
5312 reg_data |= IFE_PMC_AUTO_MDIX;
5315 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5324 return e1000_setup_copper_link_generic(hw);
5328 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5329 * @hw: pointer to the HW structure
5331 * Calls the PHY specific link setup function and then calls the
5332 * generic setup_copper_link to finish configuring the link for
5333 * Lynxpoint PCH devices
5335 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5340 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5342 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5343 ctrl |= E1000_CTRL_SLU;
5344 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5345 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5347 ret_val = e1000_copper_link_setup_82577(hw);
5351 return e1000_setup_copper_link_generic(hw);
5355 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5356 * @hw: pointer to the HW structure
5357 * @speed: pointer to store current link speed
5358 * @duplex: pointer to store the current link duplex
5360 * Calls the generic get_speed_and_duplex to retrieve the current link
5361 * information and then calls the Kumeran lock loss workaround for links at
5364 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5369 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5371 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5375 if ((hw->mac.type == e1000_ich8lan) &&
5376 (hw->phy.type == e1000_phy_igp_3) &&
5377 (*speed == SPEED_1000)) {
5378 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5385 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5386 * @hw: pointer to the HW structure
5388 * Work-around for 82566 Kumeran PCS lock loss:
5389 * On link status change (i.e. PCI reset, speed change) and link is up and
5391 * 0) if workaround is optionally disabled do nothing
5392 * 1) wait 1ms for Kumeran link to come up
5393 * 2) check Kumeran Diagnostic register PCS lock loss bit
5394 * 3) if not set the link is locked (all is good), otherwise...
5396 * 5) repeat up to 10 times
5397 * Note: this is only called for IGP3 copper when speed is 1gb.
5399 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5401 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5407 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5409 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5410 return E1000_SUCCESS;
5412 /* Make sure link is up before proceeding. If not just return.
5413 * Attempting this while link is negotiating fouled up link
5416 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5418 return E1000_SUCCESS;
5420 for (i = 0; i < 10; i++) {
5421 /* read once to clear */
5422 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5425 /* and again to get new status */
5426 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5430 /* check for PCS lock */
5431 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5432 return E1000_SUCCESS;
5434 /* Issue PHY reset */
5435 hw->phy.ops.reset(hw);
5438 /* Disable GigE link negotiation */
5439 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5440 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5441 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5442 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5444 /* Call gig speed drop workaround on Gig disable before accessing
5447 e1000_gig_downshift_workaround_ich8lan(hw);
5449 /* unable to acquire PCS lock */
5450 return -E1000_ERR_PHY;
5454 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5455 * @hw: pointer to the HW structure
5456 * @state: boolean value used to set the current Kumeran workaround state
5458 * If ICH8, set the current Kumeran workaround state (enabled - true
5459 * /disabled - false).
5461 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5464 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5466 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5468 if (hw->mac.type != e1000_ich8lan) {
5469 DEBUGOUT("Workaround applies to ICH8 only.\n");
5473 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5479 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5480 * @hw: pointer to the HW structure
5482 * Workaround for 82566 power-down on D3 entry:
5483 * 1) disable gigabit link
5484 * 2) write VR power-down enable
5486 * Continue if successful, else issue LCD reset and repeat
5488 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5494 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5496 if (hw->phy.type != e1000_phy_igp_3)
5499 /* Try the workaround twice (if needed) */
5502 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5503 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5504 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5505 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5507 /* Call gig speed drop workaround on Gig disable before
5508 * accessing any PHY registers
5510 if (hw->mac.type == e1000_ich8lan)
5511 e1000_gig_downshift_workaround_ich8lan(hw);
5513 /* Write VR power-down enable */
5514 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5515 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5516 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5517 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5519 /* Read it back and test */
5520 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5521 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5522 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5525 /* Issue PHY reset and repeat at most one more time */
5526 reg = E1000_READ_REG(hw, E1000_CTRL);
5527 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5533 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5534 * @hw: pointer to the HW structure
5536 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5537 * LPLU, Gig disable, MDIC PHY reset):
5538 * 1) Set Kumeran Near-end loopback
5539 * 2) Clear Kumeran Near-end loopback
5540 * Should only be called for ICH8[m] devices with any 1G Phy.
5542 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5547 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5549 if ((hw->mac.type != e1000_ich8lan) ||
5550 (hw->phy.type == e1000_phy_ife))
5553 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5557 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5558 ret_val = e1000_write_kmrn_reg_generic(hw,
5559 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5563 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5564 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5569 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5570 * @hw: pointer to the HW structure
5572 * During S0 to Sx transition, it is possible the link remains at gig
5573 * instead of negotiating to a lower speed. Before going to Sx, set
5574 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5575 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5576 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5577 * needs to be written.
5578 * Parts that support (and are linked to a partner which support) EEE in
5579 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5580 * than 10Mbps w/o EEE.
5582 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5584 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5588 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5590 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5591 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5593 if (hw->phy.type == e1000_phy_i217) {
5594 u16 phy_reg, device_id = hw->device_id;
5596 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5597 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5598 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5599 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5600 (hw->mac.type >= e1000_pch_spt)) {
5601 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5603 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5604 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5607 ret_val = hw->phy.ops.acquire(hw);
5611 if (!dev_spec->eee_disable) {
5615 e1000_read_emi_reg_locked(hw,
5616 I217_EEE_ADVERTISEMENT,
5621 /* Disable LPLU if both link partners support 100BaseT
5622 * EEE and 100Full is advertised on both ends of the
5623 * link, and enable Auto Enable LPI since there will
5624 * be no driver to enable LPI while in Sx.
5626 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5627 (dev_spec->eee_lp_ability &
5628 I82579_EEE_100_SUPPORTED) &&
5629 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5630 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5631 E1000_PHY_CTRL_NOND0A_LPLU);
5633 /* Set Auto Enable LPI after link up */
5634 hw->phy.ops.read_reg_locked(hw,
5637 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5638 hw->phy.ops.write_reg_locked(hw,
5644 /* For i217 Intel Rapid Start Technology support,
5645 * when the system is going into Sx and no manageability engine
5646 * is present, the driver must configure proxy to reset only on
5647 * power good. LPI (Low Power Idle) state must also reset only
5648 * on power good, as well as the MTA (Multicast table array).
5649 * The SMBus release must also be disabled on LCD reset.
5651 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5652 E1000_ICH_FWSM_FW_VALID)) {
5653 /* Enable proxy to reset only on power good. */
5654 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5656 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5657 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5660 /* Set bit enable LPI (EEE) to reset only on
5663 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5664 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5665 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5667 /* Disable the SMB release on LCD reset. */
5668 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5669 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5670 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5673 /* Enable MTA to reset for Intel Rapid Start Technology
5676 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5677 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5678 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5681 hw->phy.ops.release(hw);
5684 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5686 if (hw->mac.type == e1000_ich8lan)
5687 e1000_gig_downshift_workaround_ich8lan(hw);
5689 if (hw->mac.type >= e1000_pchlan) {
5690 e1000_oem_bits_config_ich8lan(hw, false);
5692 /* Reset PHY to activate OEM bits on 82577/8 */
5693 if (hw->mac.type == e1000_pchlan)
5694 e1000_phy_hw_reset_generic(hw);
5696 ret_val = hw->phy.ops.acquire(hw);
5699 e1000_write_smbus_addr(hw);
5700 hw->phy.ops.release(hw);
5707 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5708 * @hw: pointer to the HW structure
5710 * During Sx to S0 transitions on non-managed devices or managed devices
5711 * on which PHY resets are not blocked, if the PHY registers cannot be
5712 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5714 * On i217, setup Intel Rapid Start Technology.
5716 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5720 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5721 if (hw->mac.type < e1000_pch2lan)
5722 return E1000_SUCCESS;
5724 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5726 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5730 /* For i217 Intel Rapid Start Technology support when the system
5731 * is transitioning from Sx and no manageability engine is present
5732 * configure SMBus to restore on reset, disable proxy, and enable
5733 * the reset on MTA (Multicast table array).
5735 if (hw->phy.type == e1000_phy_i217) {
5738 ret_val = hw->phy.ops.acquire(hw);
5740 DEBUGOUT("Failed to setup iRST\n");
5744 /* Clear Auto Enable LPI after link up */
5745 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5746 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5747 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5749 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5750 E1000_ICH_FWSM_FW_VALID)) {
5751 /* Restore clear on SMB if no manageability engine
5754 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5758 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5759 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5762 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5764 /* Enable reset on MTA */
5765 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5769 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5770 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5773 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5774 hw->phy.ops.release(hw);
5777 return E1000_SUCCESS;
5781 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5782 * @hw: pointer to the HW structure
5784 * Return the LED back to the default configuration.
5786 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5788 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5790 if (hw->phy.type == e1000_phy_ife)
5791 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5794 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5795 return E1000_SUCCESS;
5799 * e1000_led_on_ich8lan - Turn LEDs on
5800 * @hw: pointer to the HW structure
5804 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5806 DEBUGFUNC("e1000_led_on_ich8lan");
5808 if (hw->phy.type == e1000_phy_ife)
5809 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5810 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5812 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5813 return E1000_SUCCESS;
5817 * e1000_led_off_ich8lan - Turn LEDs off
5818 * @hw: pointer to the HW structure
5820 * Turn off the LEDs.
5822 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5824 DEBUGFUNC("e1000_led_off_ich8lan");
5826 if (hw->phy.type == e1000_phy_ife)
5827 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5828 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5830 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5831 return E1000_SUCCESS;
5835 * e1000_setup_led_pchlan - Configures SW controllable LED
5836 * @hw: pointer to the HW structure
5838 * This prepares the SW controllable LED for use.
5840 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5842 DEBUGFUNC("e1000_setup_led_pchlan");
5844 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5845 (u16)hw->mac.ledctl_mode1);
5849 * e1000_cleanup_led_pchlan - Restore the default LED operation
5850 * @hw: pointer to the HW structure
5852 * Return the LED back to the default configuration.
5854 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5856 DEBUGFUNC("e1000_cleanup_led_pchlan");
5858 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5859 (u16)hw->mac.ledctl_default);
5863 * e1000_led_on_pchlan - Turn LEDs on
5864 * @hw: pointer to the HW structure
5868 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5870 u16 data = (u16)hw->mac.ledctl_mode2;
5873 DEBUGFUNC("e1000_led_on_pchlan");
5875 /* If no link, then turn LED on by setting the invert bit
5876 * for each LED that's mode is "link_up" in ledctl_mode2.
5878 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5879 for (i = 0; i < 3; i++) {
5880 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5881 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5882 E1000_LEDCTL_MODE_LINK_UP)
5884 if (led & E1000_PHY_LED0_IVRT)
5885 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5887 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5891 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5895 * e1000_led_off_pchlan - Turn LEDs off
5896 * @hw: pointer to the HW structure
5898 * Turn off the LEDs.
5900 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5902 u16 data = (u16)hw->mac.ledctl_mode1;
5905 DEBUGFUNC("e1000_led_off_pchlan");
5907 /* If no link, then turn LED off by clearing the invert bit
5908 * for each LED that's mode is "link_up" in ledctl_mode1.
5910 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5911 for (i = 0; i < 3; i++) {
5912 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5913 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5914 E1000_LEDCTL_MODE_LINK_UP)
5916 if (led & E1000_PHY_LED0_IVRT)
5917 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5919 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5923 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5927 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5928 * @hw: pointer to the HW structure
5930 * Read appropriate register for the config done bit for completion status
5931 * and configure the PHY through s/w for EEPROM-less parts.
5933 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5934 * config done bit, so only an error is logged and continues. If we were
5935 * to return with error, EEPROM-less silicon would not be able to be reset
5938 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5940 s32 ret_val = E1000_SUCCESS;
5944 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5946 e1000_get_cfg_done_generic(hw);
5948 /* Wait for indication from h/w that it has completed basic config */
5949 if (hw->mac.type >= e1000_ich10lan) {
5950 e1000_lan_init_done_ich8lan(hw);
5952 ret_val = e1000_get_auto_rd_done_generic(hw);
5954 /* When auto config read does not complete, do not
5955 * return with an error. This can happen in situations
5956 * where there is no eeprom and prevents getting link.
5958 DEBUGOUT("Auto Read Done did not complete\n");
5959 ret_val = E1000_SUCCESS;
5963 /* Clear PHY Reset Asserted bit */
5964 status = E1000_READ_REG(hw, E1000_STATUS);
5965 if (status & E1000_STATUS_PHYRA)
5966 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5968 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5970 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5971 if (hw->mac.type <= e1000_ich9lan) {
5972 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5973 (hw->phy.type == e1000_phy_igp_3)) {
5974 e1000_phy_init_script_igp3(hw);
5977 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5978 /* Maybe we should do a basic PHY config */
5979 DEBUGOUT("EEPROM not present\n");
5980 ret_val = -E1000_ERR_CONFIG;
5988 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5989 * @hw: pointer to the HW structure
5991 * In the case of a PHY power down to save power, or to turn off link during a
5992 * driver unload, or wake on lan is not enabled, remove the link.
5994 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5996 /* If the management interface is not enabled, then power down */
5997 if (!(hw->mac.ops.check_mng_mode(hw) ||
5998 hw->phy.ops.check_reset_block(hw)))
5999 e1000_power_down_phy_copper(hw);
6005 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6006 * @hw: pointer to the HW structure
6008 * Clears hardware counters specific to the silicon family and calls
6009 * clear_hw_cntrs_generic to clear all general purpose counters.
6011 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6016 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6018 e1000_clear_hw_cntrs_base_generic(hw);
6020 E1000_READ_REG(hw, E1000_ALGNERRC);
6021 E1000_READ_REG(hw, E1000_RXERRC);
6022 E1000_READ_REG(hw, E1000_TNCRS);
6023 E1000_READ_REG(hw, E1000_CEXTERR);
6024 E1000_READ_REG(hw, E1000_TSCTC);
6025 E1000_READ_REG(hw, E1000_TSCTFC);
6027 E1000_READ_REG(hw, E1000_MGTPRC);
6028 E1000_READ_REG(hw, E1000_MGTPDC);
6029 E1000_READ_REG(hw, E1000_MGTPTC);
6031 E1000_READ_REG(hw, E1000_IAC);
6032 E1000_READ_REG(hw, E1000_ICRXOC);
6034 /* Clear PHY statistics registers */
6035 if ((hw->phy.type == e1000_phy_82578) ||
6036 (hw->phy.type == e1000_phy_82579) ||
6037 (hw->phy.type == e1000_phy_i217) ||
6038 (hw->phy.type == e1000_phy_82577)) {
6039 ret_val = hw->phy.ops.acquire(hw);
6042 ret_val = hw->phy.ops.set_page(hw,
6043 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6046 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6047 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6048 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6049 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6050 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6051 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6052 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6053 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6054 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6055 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6056 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6057 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6058 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6059 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6061 hw->phy.ops.release(hw);
6066 * e1000_configure_k0s_lpt - Configure K0s power state
6067 * @hw: pointer to the HW structure
6068 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6069 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6070 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
6071 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6073 * Configure the K1 power state based on the provided parameter.
6074 * Assumes semaphore already acquired.
6076 * Success returns 0, Failure returns:
6077 * -E1000_ERR_PHY (-2) in case of access error
6078 * -E1000_ERR_PARAM (-4) in case of parameters error
6080 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6085 DEBUGFUNC("e1000_configure_k0s_lpt");
6087 if (entry_latency > 3 || min_time > 4)
6088 return -E1000_ERR_PARAM;
6090 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6095 /* for now don't touch the latency */
6096 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6097 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6099 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6104 return E1000_SUCCESS;